Comparison circuit, semiconductor integrated circuit device, and switching power supply device

Abstract

To enable setting of preventing deterioration of output accuracy from being quickly recovered even if being out of the setting of preventing deterioration of output accuracy and to enable a plurality of comparators having different characteristics to be appropriately used.SOLUTION: A comparison circuit (13) includes first and second comparators (131, 132) and a logic part (134). The logic part adjusts a variable reference voltage to make logic switching timing of a second comparison signal outputted from the second comparator come close to logic switching timing of a first comparison signal outputted from the first comparator. The comparison circuit has an up-down counter (133a), divides a counter value of the up-down counter into a higher-order bit side and a lower-order bit side in adjusting the variable reference voltage, changes a value of the higher-order bit side to narrow down the adjustment range of the variable reference voltage, and changes a value of the lower-order bit side within the narrowed-down adjustment range.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a comparator circuit, a semiconductor integrated circuit device, and a switching power supply device. [Background technology]

[0002] The comparison circuit disclosed in Patent Document 1 adjusts the variable reference voltage using the counter value of the up / down counter to bring the logic switching timing of the second comparison signal generated by the second comparator closer to the logic switching timing of the first comparison signal generated by the first comparator. The comparison circuit disclosed in Patent Document 1 having such a configuration can return to a setting that does not reduce output accuracy even if it deviates from the setting that does not reduce output accuracy, and can use multiple comparators with different characteristics. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6467539

[0004] [overview] However, the comparison circuit disclosed in Patent Document 1 is configured to change the counter value of the up / down counter by ±1 for each switching period of the switching power supply device, so if adjustment is started from a state in which the logic switching timing of the second comparison signal and the logic switching timing of the first comparison signal are significantly misaligned, it takes time (e.g., several seconds) to complete the initial logic switching timing adjustment.

[0005] The comparison circuit disclosed in this specification includes a first comparator configured to compare an input signal with a reference voltage to generate a first comparison signal, a second comparator configured to compare the input signal with a variable reference voltage to generate a second comparison signal, a variable reference voltage generation unit configured to generate the variable reference voltage, and a logic unit configured to output one of the first comparison signal and the second comparison signal as a comparison signal. The logic unit is configured to adjust the variable reference voltage to bring the logic switching timing of the second comparison signal closer to the logic switching timing of the first comparison signal. The variable reference voltage generation unit includes an up-down counter and a DAC configured to convert a counter value of the up-down counter into an analog voltage, and outputs the analog voltage or a voltage corresponding to the analog voltage as the variable reference voltage. When adjusting the variable reference voltage, the counter value is divided into a higher-order bit side and a lower-order bit side, the value of the higher-order bit side is changed to narrow the adjustment range of the variable reference voltage, and the value of the lower-order bit side is changed in the narrowed adjustment range.

[0006] The semiconductor integrated circuit device disclosed in this specification includes a ripple injection circuit configured to generate a feedback voltage by superimposing a ripple voltage simulating a coil current on an output voltage or a divided voltage of the output voltage, a reference voltage generation circuit configured to generate a predetermined reference voltage, a main comparator configured to generate a comparison signal by comparing the feedback voltage with the reference voltage, a one-shot pulse generation circuit configured to generate a one-shot pulse in a set signal in response to the comparison signal, an RS flip-flop configured to set an output signal to a first logic level in response to the set signal and to reset the output signal to a second logic level in response to a reset signal, an on-time setting circuit configured to generate a one-shot pulse in the reset signal at a time when a predetermined on-time has elapsed since the output signal was set to the first logic level, a gate driver circuit configured to generate drive signals for an output transistor and a synchronous rectification transistor in response to the output signal, and a backflow detection circuit configured to detect a backflow of the coil current and forcibly turn off the synchronous rectification transistor, and has the comparison circuit configured as the main comparator.

[0007] The switching power supply device disclosed in this specification includes a semiconductor integrated circuit device having the above-described configuration, and a switch output stage that is partially or entirely attached externally to the semiconductor integrated circuit device and configured to generate the output voltage from the input voltage. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing the overall configuration of a switching power supply device. [Diagram 2] FIG. 2 is a timing chart showing the switching operation under heavy load. [Diagram 3] FIG. 3 is a timing chart showing the reverse current blocking operation under a light load. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of the main comparator. [Diagram 5]FIG. 5 is a diagram conceptually showing the counter value of the up / down counter. [Figure 6] FIG. 6 is a diagram conceptually showing the counter value of the up / down counter. [Figure 7] FIG. 7 is a block diagram showing another example of the configuration of the main comparator. [Figure 8] FIG. 8 is a block diagram showing an example of the configuration of a television equipped with a switching power supply device. [Figure 9A] FIG. 9A is a front view of a television equipped with a switching power supply device. [Figure 9B] FIG. 9B is a side view of a television equipped with a switching power supply device. [Figure 9C] FIG. 9C is a rear view of a television equipped with a switching power supply device.

[0009] [Detailed Description] In this specification, a MOS (Metal-Oxide-Semiconductor) field effect transistor refers to a field effect transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon having a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0010] In this specification, the reference voltage means a voltage that is constant under ideal conditions, but in reality, it is a voltage that may fluctuate slightly due to temperature changes and the like.

[0011] <Switching power supply unit> 1 is a block diagram showing the overall configuration of a switching power supply device. The switching power supply device 1 of this configuration example is a step-down DC / DC converter that generates an output voltage Vout from an input voltage Vin by a nonlinear control method (bottom detection fixed on-time method). The switching power supply device 1 has a semiconductor integrated circuit device 10 and a switch output stage 20 formed by various discrete components (N-channel MOS field effect transistors N1 and N2, a coil L1, a capacitor C1, and resistors R1 and R2) externally attached to the semiconductor integrated circuit device 10.

[0012] The semiconductor integrated circuit device 10 is a main body that comprehensively controls the overall operation of the switching power supply device 1. The semiconductor integrated circuit device 10 has external terminals T1 to T7 (upper gate terminal T1, lower gate terminal T2, switch terminal T3, feedback terminal T4, input voltage terminal T5, output voltage terminal T6, and ground terminal T7) as means for establishing electrical connection with the outside of the device.

[0013] The external terminal T1 is connected to the gate of the transistor N1. The external terminal T2 is connected to the gate of the transistor N2. The external terminal T3 is connected to the application terminal of the switch voltage Vsw (the connection node between the source of the transistor N1 and the drain of the transistor N2). The external terminal T4 is connected to the application terminal of the divided voltage Vdiv (the connection node between the resistors R1 and R2). The external terminal T5 is connected to the application terminal of the input voltage Vin. The external terminal T6 is connected to the application terminal of the output voltage Vout. The external terminal T7 is connected to the ground terminal.

[0014] Next, the connection relationship of the discrete components externally attached to the semiconductor integrated circuit device 10 will be described. The drain of the transistor N1 is connected to the application terminal of the input voltage Vin. The source of the transistor N2 is connected to the ground terminal. The source of the transistor N1 and the drain of the transistor N2 are both connected to the first terminal of the coil L1. The second terminal of the coil L1 and the first terminal of the capacitor C1 are both connected to the application terminal of the output voltage Vout. The second terminal of the capacitor C1 is connected to the ground terminal. The resistors R1 and R2 are connected in series between the application terminal of the output voltage Vout and the ground terminal.

[0015] The transistor N1 is an output transistor that is on / off controlled according to a gate signal G1 input from an external terminal T1. The transistor N2 is a synchronous rectification transistor that is on / off controlled according to a gate signal G2 input from an external terminal T2. A diode may be used as the rectification element instead of the transistor N2. The transistors N1 and N2 may be built into the semiconductor integrated circuit device 10. The coil L1 and the capacitor C1 function as a rectification smoothing section that rectifies and smoothes the rectangular wave-shaped switch voltage Vsw that appears at the external terminal T3 to generate the output voltage Vout. The resistors R1 and R2 function as a divided voltage generation section that divides the output voltage Vout to generate the divided voltage Vdiv. However, if the output voltage Vout is within the input dynamic range of the ripple injection circuit 11 (or the main comparator 13), the divided voltage generation section may be omitted.

[0016] Next, a description will be given of the internal configuration of the semiconductor integrated circuit device 10. In the semiconductor integrated circuit device 10, a ripple injection circuit 11, a reference voltage generation circuit 12, a main comparator 13, a one-shot pulse generation circuit 14, an RS flip-flop 15, an on-time setting circuit 16, a gate driver circuit 17, and a backflow detection circuit 18 are integrated.

[0017] The ripple injection circuit 11 generates the feedback voltage Vfb (=Vdiv+Vrpl) by adding the ripple voltage Vrpl (pseudo ripple component simulating the coil current IL flowing through the coil L1) to the divided voltage Vdiv. By introducing such a ripple injection technique, stable switching control can be performed even if the ripple component of the output voltage Vout (and thus the divided voltage Vdiv) is not so large, so it becomes possible to use a multilayer ceramic capacitor with a small ESR as the capacitor C1. However, if the ripple component of the output voltage Vout is sufficiently large, it is also possible to omit the ripple injection circuit 11.

[0018] The reference voltage generating circuit 12 generates a predetermined reference voltage Vref.

[0019] The main comparator 13 compares a feedback voltage Vfb input to a non-inverting input terminal (+) with a reference voltage Vref input to an inverting input terminal (-) to generate a comparison signal S1. The comparison signal S1 goes to a high level when the feedback voltage Vfb is higher than the reference voltage Vref, and goes to a low level when the feedback voltage Vfb is lower than the reference voltage Vref.

[0020] The one-shot pulse generating circuit 14 generates a one-shot pulse (for example, a falling pulse) in the set signal S2 using the falling edge of the comparison signal S1 as a trigger.

[0021] The RS flip-flop 15 sets the output signal S4 to a high level at a pulse edge (e.g., a falling edge) of the set signal S2 input to the set terminal (S), and resets the output signal S4 to a low level at a pulse edge (e.g., a falling edge) of the reset signal S3 input to the reset terminal (R).

[0022] The on-time setting circuit 16 generates a one-shot pulse (e.g., a falling pulse) in the reset signal S3 after a predetermined on-time Ton has elapsed since the inverted output signal S4B (=the logically inverted signal of the output signal S4) of the RS flip-flop 15 is caused to fall to a low level.

[0023] The gate driver circuit 17 generates gate signals G1 and G2 in response to the output signal S4 of the RS flip-flop 15, and switches the transistors N1 and N2 complementarily. Note that the meaning of the term "complementary" used in this specification includes a case where the on / off transition timing of the transistors N1 and N2 is given a delay in order to prevent shoot-through current (a case where a so-called simultaneous off period (dead time) is provided).

[0024] The reverse current detection circuit 18 monitors the reverse current of the coil current IL (the coil current IL flowing from the coil L1 to the ground terminal via the transistor N2) and generates a reverse current detection signal S5. The reverse current detection signal S5 is latched to a high level (a logic level when a reverse current is detected) when a reverse current of the coil current IL is detected, and is reset to a low level (a logic level when a reverse current is not detected) at the rising edge of the gate signal G1 in the next period. Note that, as a method for monitoring the reverse current of the coil current IL, for example, it is sufficient to detect a zero cross point where the switch voltage Vsw switches from negative to positive during the on period of the transistor N2. When the reverse current detection signal S5 is at a high level, the gate driver circuit 17 generates a gate signal G2 to forcibly turn off the transistor N2 regardless of the output signal S4.

[0025] The above-mentioned ripple injection circuit 11, reference voltage generation circuit 12, main comparator 13, one-shot pulse generation circuit 14, RS flip-flop 15, on-time setting circuit 16, gate driver circuit 17, and reverse current detection circuit 18 function as a switching control circuit of a nonlinear control method (a bottom detection fixed on-time method in this configuration example) that generates an output voltage Vout from an input voltage Vin by controlling the on / off of the transistors N1 and N2 in accordance with a comparison result between the feedback voltage Vfb and the reference voltage Vref.

[0026] <Switching operation> FIG. 2 is a timing chart showing the switching operation under heavy load (continuous current mode), and depicts, from the top, a feedback voltage Vfb, a set signal S2, a reset signal S3, and an output signal S4.

[0027] At time t11, when the feedback voltage Vfb drops to the reference voltage Vref, the set signal S2 falls to a low level, and the output signal S4 transitions to a high level, so that the transistor N1 turns on and the feedback voltage Vfb starts to rise.

[0028] After that, when the reset signal S3 falls to the low level at time t12 due to the lapse of the on-time Ton, the output signal S4 transitions to the low level, so that the transistor N1 is turned off and the feedback voltage Vfb starts to decrease again.

[0029] The gate driver circuit 17 generates gate signals G1 and G2 in response to the output signal S4, and uses these signals to control the on / off of the transistors N1 and N2. Specifically, when the output signal S4 is at a high level, the gate signal G1 is basically at a high level to turn on the transistor N1, and the gate signal G2 is at a low level to turn off the transistor N2. Conversely, when the output signal S4 is at a low level, the gate signal G1 is basically at a low level to turn off the transistor N1, and the gate signal G2 is at a high level to turn on the transistor N2.

[0030] By the on / off control of the transistors N1 and N2 described above, a switch voltage Vsw with a rectangular waveform appears at the external terminal T3. The switch voltage Vsw is rectified and smoothed by the coil L1 and the capacitor C1 to generate the output voltage Vout. The output voltage Vout is divided by the resistors R1 and R2 to generate a divided voltage Vdiv (and thus a feedback voltage Vfb). By such output feedback control, the switching power supply device 1 generates a desired output voltage Vout from the input voltage Vin with an extremely simple configuration.

[0031] <Backflow blocking operation> FIG. 3 is a timing chart showing the reverse current blocking operation under a light load (discontinuous current mode), and depicts, from the top, gate signals G1 and G2, a reverse current detection signal S5, a coil current IL, and a switch voltage Vsw.

[0032] Between times t21 and t22, the gate signal G1 is at a high level and the gate signal G2 is at a low level, so that the transistor N1 is on and the transistor N2 is off. Therefore, between times t21 and t22, the switch voltage Vsw rises to almost the input voltage Vin, and the coil current IL increases.

[0033] At time t22, when the gate signal G1 falls to a low level and the gate signal G2 rises to a high level, the transistor N1 turns off and the transistor N2 turns on. Therefore, the switch voltage Vsw falls to a negative voltage (=GND-IL×RN2, where RN2 is the on-resistance value of the transistor N2), and the coil current IL starts to decrease.

[0034] Here, when the output current Iout flowing to the load is sufficiently large, the energy stored in the coil L1 is large, so the coil current IL continues to flow toward the load without falling below zero until time t24 when the gate signal G1 is raised to high level again, and the switch voltage Vsw is maintained at a negative voltage. On the other hand, when the output current Iout flowing to the load is small, the energy stored in the coil L1 is small, so at time t23 the coil current IL falls below zero, a reverse flow of the coil current IL occurs, and the polarity of the switch voltage Vsw switches from negative to positive. In this state, the charge stored in the capacitor C1 is returned to the input side via the coil L1, so the efficiency at the time of light load decreases.

[0035] Therefore, the switching power supply device 1 is configured to detect the reverse flow of the coil current IL (polarity reversal of the switch voltage Vsw) using the reverse flow detection circuit 18, and forcibly turn off the transistor N2 during the high level period (times t23 to t24) of the reverse flow detection signal S5. With this configuration, the reverse flow of the coil current IL can be quickly blocked, and it becomes possible to eliminate the decrease in efficiency under light load.

[0036] <Main comparator> 4 is a block diagram showing a configuration example of the main comparator 13. The main comparator 13 in this configuration example is a comparison circuit that compares a feedback voltage Vfb (corresponding to an input signal) with a reference voltage Vref to generate a comparison signal S1, and includes a first comparator 131, a second comparator 132, a variable reference voltage generation unit 133, and a logic unit 134.

[0037] The first comparator 131 compares a feedback voltage Vfb input to a non-inverting input terminal (+) with a reference voltage Vref input to an inverting input terminal (-) to generate a first comparison signal S131. The first comparison signal S131 goes to a high level when the feedback voltage Vfb is higher than the reference voltage Vref, and goes to a low level when the feedback voltage Vfb is lower than the reference voltage Vref.

[0038] Moreover, the first comparator 131 is controlled as to whether or not it is operable according to an enable signal EN131 input from the logic unit 134. Specifically, the first comparator 131 is in an operating state when the enable signal EN131 is at a first logic level (=logic level when enabled), and is in a stopped state when the enable signal EN131 is at a second logic level (=logic level when disabled). Note that by putting the first comparator 131 in a stopped state, the power consumption thereof can be reduced to almost zero.

[0039] The second comparator 132 compares the feedback voltage Vfb input to the non-inverting input terminal (+) with the variable reference voltage Vref2 input to the inverting input terminal (-) to generate a second comparison signal S132. The second comparison signal S132 goes to a high level when the feedback voltage Vfb is higher than the variable reference voltage Vref2, and goes to a low level when the feedback voltage Vfb is lower than the variable reference voltage Vref2. Unlike the first comparator 131, the second comparator 132 continues to operate at all times after the semiconductor integrated circuit device 10 is started up.

[0040] The response speed of the first comparator 131 is faster than that of the second comparator 132. The power consumption of the second comparator 132 is much smaller than that of the first comparator 131. That is, the first comparator 131 is a high-speed response type that prioritizes improvement of the response speed over reduction of the power consumption, and the second comparator 132 is an ultra-low power consumption type that prioritizes reduction of the power consumption over improvement of the response speed.

[0041] The variable reference voltage generating unit 133 is a circuit unit that generates a variable reference voltage Vref2, and includes an up / down counter 133a and a DAC 133b.

[0042] The up / down counter 133a varies the counter value Scnt in response to a control signal S6 input from the logic unit 134. Then, the up / down counter 133a outputs the counter value Scnt to the DAC 133b.

[0043] The DAC 133b converts the digital counter value Scnt into an analog voltage Vdac and outputs this as the variable reference voltage Vref2. Therefore, when the counter value Scnt increases, the variable reference voltage Vref2 increases, and when the counter value Scnt decreases, the variable reference voltage Vref2 decreases.

[0044] The logic unit 134 outputs one of the first comparison signal S131 and the second comparison signal S132 as the comparison signal S1. While the logic unit 134 is outputting the first comparison signal S131 as the comparison signal S1, the logic unit 134 sets the enable signal EN131 to a first logic level (=logic level when enabled) to operate the first comparator 131. Meanwhile, while the logic unit 134 is outputting the second comparison signal S132 as the comparison signal S1, the logic unit 134 sets the enable signal EN131 to a second logic level (=logic level when disabled) to stop the first comparator 131.

[0045] More specifically, while the backflow detection signal S5 is at a low level, the logic unit 134 operates the first comparator 131 and outputs the first comparison signal S131 as the comparison signal S1. The logic unit 134 also operates the first comparator 131 until a first predetermined time (e.g., 8 μs) has elapsed since the backflow detection signal S5 switched from a low level to a high level, and outputs the first comparison signal S131 as the comparison signal S1. On the other hand, if the high level of the backflow detection signal S5 continues beyond the first predetermined time (e.g., 8 μs) since the backflow detection signal S5 switched from a low level to a high level, the logic unit 134 stops the first comparator 131 and outputs the second comparison signal S132 as the comparison signal S1 until the backflow detection signal S5 switches from a high level to a low level. That is, when the period during which the output voltage Vout is sufficient and both the transistors N1 and N2 are in the off state exceeds a first predetermined time (e.g., 8 μs), the first comparator 131 is stopped for the exceeded period, thereby saving power in the main comparator 13. In this way, the logic unit 134 has a function of selectively using the first comparator 131 for high-speed response and the second comparator 132 for ultra-low power consumption depending on the situation (load state).

[0046] However, if there is a discrepancy between the input offsets of the first comparator 131 and the second comparator 132, the logic switching timing of the comparison signal S1 will differ depending on whether the first comparator 131 or the second comparator 132 is being used, which will result in a decrease in the output accuracy of the main comparator 13 as a whole (and thus the accuracy of the output voltage Vout).

[0047] <Calibration process> Therefore, it is necessary to eliminate the mismatch in the input offsets between the comparators by performing calibration processing. Therefore, the switching power supply device 1 executes a startup calibration processing, a first calibration processing, and a second calibration processing.

[0048] The startup calibration process is executed when the switching power supply device 1 is started. If the startup calibration process is executed alone, there is a possibility that the input offsets of the first and second comparators 131 and 132 may diverge due to changes in the external environment (e.g., power supply voltage, temperature, etc.) after the startup calibration process. Furthermore, if an incorrect calibration is performed in the startup calibration process, the input offsets of the first and second comparators 131 and 132 will remain diverged. Therefore, the switching power supply device 1 also executes the first calibration process and the second calibration process after the startup calibration process is completed.

[0049] The first calibration process is executed before the period when only the second comparator 132 is operating, and when both the first comparator 131 and the second comparator 132 are still operating. That is, the first calibration process is executed when the logic unit 134 sets the enable signal EN131 to the first logic level (=the logic level when enabled). The first comparator 131 is not operated only for the first calibration process, but the first calibration process is executed by utilizing the period when the first comparator 131 is operating based on the original operation of the switching power supply device that is unrelated to the first calibration process. This makes it possible to prevent the consumption current from increasing due to the execution of the first calibration process.

[0050] The second calibration process is executed when the state transitions from one in which only the second comparator 132 is operating to one in which both the first comparator 131 and the second comparator 132 are operating. That is, the second calibration process is executed when the logic unit 134 switches the enable signal EN131 from the second logic level (=the logic level when disabled) to the first logic level (=the logic level when enabled). The first comparator 131 is not operated only for the second calibration process, but the second calibration process is executed by utilizing the period in which the first comparator 131 is operating based on the original operation of the switching power supply device that is unrelated to the second calibration process. This makes it possible to prevent the consumption current from increasing due to the execution of the second calibration process.

[0051] The switching power supply device 1 may execute a calibration process that is executed at a timing different from the above-mentioned startup calibration process, the first calibration process, and the second calibration process.

[0052] Next, the contents of the above-mentioned start-up calibration process, first calibration process, and second calibration process will be described.

[0053] The logic unit 134 determines that the counter value Scnt of the up-down counter 133a is smaller than the target value if, for example, when the feedback voltage Vfb decreases, the first comparison signal S131 switches from high to low before the second comparison signal S132 does. On the other hand, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is larger than the target value if, for example, when the feedback voltage Vfb decreases, the second comparison signal S132 switches from high to low before the first comparison signal S131 does.

[0054] As the counter value Scnt of the up-down counter 133a approaches the target value, the logic switching timing of the second comparison signal S132 approaches the logic switching timing of the first comparison signal S131. When the input offsets of the first comparator 131 and the second comparator 132 are not separated from each other, as the counter value Scnt of the up-down counter 133a approaches the target value, the variable reference voltage Vref2 approaches the reference voltage Vref.

[0055] In the following, an example will be given in which the up-down counter 133a is a 10-bit counter. In this case, the counter value of the up-down counter 133a is 0 (00000_00000) to 1023 (11111_11111). Note that the counter value in parentheses indicates a binary number.

[0056] As shown in Fig. 5, the logic unit 134 divides the counter value of the up-down counter 133a into a higher-order bit side G1 and a lower-order bit side G2. In Fig. 5, the higher-order bit side G1 is the upper 5 bits, and the lower-order bit side G2 is the lower 5 bits, but the number of bits of the higher-order bit side G1 and the lower-order bit side G2 is not limited to this example. In other words, the number of bits of the higher-order bit side G1 and the lower-order bit side G2 may be different from each other.

[0057] Here, a case where the target value is 790 will be taken as an example to explain specific operations of the logic unit 134 when the above-mentioned start-up calibration process, first calibration process, and second calibration process are executed.

[0058] First, the logic unit 134 sets the initial value of the counter value Scnt of the up-down counter 133a to 512 (10000_00000). When the counter value Scnt of the up-down counter 133a is 512, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is equal to or less than the target value, based on the logic switching timings of the first comparison signal S131 and the second comparison signal S132.

[0059] Next, the logic unit 134 confirms the value of the most significant bit from the immediately preceding determination result as 1, and further changes the second most significant bit from 0 to 1. That is, the logic unit 134 changes the counter value Scnt of the up-down counter 133a to 768 (11000_00000). When the counter value Scnt of the up-down counter 133a is 768, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is equal to or less than the target value, based on the logic switching timings of the first comparison signal S131 and the second comparison signal S132.

[0060] Next, the logic unit 134 confirms the value of the second most significant bit from the immediately preceding determination result to be 1, and further changes the third most significant bit from 0 to 1. That is, the logic unit 134 changes the counter value Scnt of the up-down counter 133a to 896 (11100_00000). When the counter value Scnt of the up-down counter 133a is 896, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is equal to or greater than the target value, based on the logic switching timings of the first comparison signal S131 and the second comparison signal S132.

[0061] Next, the logic unit 134 confirms the value of the third most significant bit from the immediately preceding determination result to be 0, and further changes the fourth most significant bit from 0 to 1. That is, the logic unit 134 changes the counter value Scnt of the up-down counter 133a to 832 (11010_00000). When the counter value Scnt of the up-down counter 133a is 832, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is equal to or greater than the target value, based on the logic switching timings of the first comparison signal S131 and the second comparison signal S132.

[0062] Next, the logic unit 134 confirms the value of the fourth most significant bit from the immediately preceding determination result to be 0, and further changes the fifth most significant bit from 0 to 1. That is, the logic unit 134 changes the counter value Scnt of the up-down counter 133a to 800 (11001_00000). When the counter value Scnt of the up-down counter 133a is 800, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is equal to or greater than the target value, based on the logic switching timings of the first comparison signal S131 and the second comparison signal S132.

[0063] By changing the value of the higher-order bit side G1 as described above, the logic unit 134 can narrow the adjustment range of the target value to 768 to 800, thereby narrowing the adjustment range of the variable reference voltage Vref2. If the adjustment range of the target value cannot be narrowed down even if the value of the higher-order bit side G1 is changed (if the upper or lower limit of the adjustment range is unknown), for example, the division shown in Fig. 5 may be changed to the division shown in Fig. 6 to increase the number of bits of the higher-order bit side G1 and decrease the number of bits of the lower-order bit side G2, and then the process of narrowing the adjustment range of the target value by changing the value of the higher-order bit side G1 may be continued.

[0064] The logic unit 134 narrows the adjustment range of the target value to 768 to 800 by changing the value of the most significant bit G1 as described above, and then increases the counter value Scnt of the up-down counter 133a from 768 by one in accordance with the change in the value of the least significant bit G2, thereby bringing the counter value Scnt of the up-down counter 133a closer to the target value.

[0065] By the logic unit 134 performing the above-mentioned operation, the time required for the calibration process can be significantly reduced compared to the case where the counter value Scnt of the up-down counter 133a is incremented as in Patent Document 1. Therefore, according to the main comparator 13, even if the setting does not deviate from the setting where the output accuracy (the accuracy of the comparison signal S1) does not decrease, it is possible to quickly return to the setting where the output accuracy does not decrease, and to selectively use a plurality of comparators (the first comparator 131 and the second comparator 132) with different characteristics.

[0066] In addition, the logic unit 134 may narrow down the adjustment range of the target value to 768 to 800 by changing the value of the most significant bit G1 as described above, and then decrease the counter value Scnt of the up-down counter 133a from 800 by one by changing the value of the least significant bit G2, so as to bring the counter value Scnt of the up-down counter 133a closer to the target value.

[0067] Furthermore, according to the operation of the logic unit 134 described above, the value of the most significant bit side G1 changes by repeatedly changing bits that are 0 to 1 one by one starting from the most significant bit, but the value of the most significant bit side G1 may also change by repeatedly changing bits that are 1 to 0 one by one starting from the most significant bit.

[0068] When changing bits which are 1 to 0 one by one in order from the most significant bit, the logic unit 134 first sets the initial value of the counter value Scnt of the up-down counter 133a to 511 (01111_11111). When the counter value Scnt of the up-down counter 133a is 511, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is equal to or less than the target value of 790, based on the logic switching timings of the first comparison signal S131 and the second comparison signal S132.

[0069] Next, the logic unit 134 confirms the value of the most significant bit from the immediately preceding determination result as 1, and further changes the second most significant bit from 1 to 0. That is, the logic unit 134 changes the counter value Scnt of the up-down counter 133a to 767 (10111_11111). When the counter value Scnt of the up-down counter 133a is 767, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is equal to or less than the target value, based on the logic switching timings of the first comparison signal S131 and the second comparison signal S132.

[0070] Next, the logic unit 134 confirms the value of the second most significant bit from the immediately preceding determination result to be 1, and further changes the third most significant bit from 1 to 0. That is, the logic unit 134 changes the counter value Scnt of the up-down counter 133a to 895 (11011_11111). When the counter value Scnt of the up-down counter 133a is 895, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is equal to or greater than the target value, based on the logic switching timings of the first comparison signal S131 and the second comparison signal S132.

[0071] Next, the logic unit 134 confirms the value of the third most significant bit from the immediately preceding determination result to be 0, and further changes the fourth most significant bit from 1 to 0. That is, the logic unit 134 changes the counter value Scnt of the up-down counter 133a to 831 (11001_11111). When the counter value Scnt of the up-down counter 133a is 831, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is equal to or greater than the target value, based on the respective logic switching timings of the first comparison signal S131 and the second comparison signal S132.

[0072] Next, the logic unit 134 confirms the value of the fourth most significant bit from the immediately preceding determination result to be 0, and further changes the fifth most significant bit from 1 to 0. That is, the logic unit 134 changes the counter value Scnt of the up-down counter 133a to 799 (11000_11111). When the counter value Scnt of the up-down counter 133a is 799, the logic unit 134 determines that the counter value Scnt of the up-down counter 133a is equal to or greater than the target value, based on the respective logic switching timings of the first comparison signal S131 and the second comparison signal S132.

[0073] By changing the value of the higher-order bit side G1 as described above, the logic unit 134 can narrow the adjustment range of the target value to 767 to 799, thereby narrowing the adjustment range of the variable reference voltage Vref2. If the adjustment range of the target value cannot be narrowed down even if the value of the higher-order bit side G1 is changed (if the upper or lower limit of the adjustment range is unknown), for example, the division shown in Fig. 5 may be changed to the division shown in Fig. 6 to increase the number of bits of the higher-order bit side G1 and decrease the number of bits of the lower-order bit side G2, and then the process of narrowing the adjustment range of the target value by changing the value of the higher-order bit side G1 may be continued.

[0074] The logic unit 134 narrows down the adjustment range of the target value to 767 to 799 by changing the value of the most significant bit G1 as described above, and then increases the counter value Scnt of the up-down counter 133a from 767 by one in accordance with the change in the value of the least significant bit G2, thereby bringing the counter value Scnt of the up-down counter 133a closer to the target value.

[0075] In addition, the logic unit 134 may narrow down the adjustment range of the target value to 767 to 799 by changing the value of the most significant bit G1 as described above, and then decrease the counter value Scnt of the up-down counter 133a from 799 by one by changing the value of the least significant bit G2, so as to bring the counter value Scnt of the up-down counter 133a closer to the target value.

[0076] <Modification of the main comparator> Fig. 7 is a circuit diagram showing a modified example of the main comparator 13. The main comparator 13 of this modified example is based on the previous configuration example (Fig. 4) and further includes an adder unit 133c. Therefore, the same circuit elements as those in the previous configuration example are given the same reference numerals as in Fig. 4 to avoid redundant explanations, and the following description will focus on the characteristic parts of the modified example.

[0077] The adder 133c adds the analog voltage Vdac to the reference voltage Vref to generate a variable reference voltage Vref2 (=Vref+Vdac) and outputs it to the inverting input terminal (−) of the second comparator 132.

[0078] That is, the analog voltage Vdac is used as an offset voltage to be added to the reference voltage Vref, not as the variable reference voltage Vref2 itself. Note that the analog output value of the analog voltage Vdac relative to the counter value Scnt is set so that the variable reference voltage Vref2 can take both positive and negative voltage values ​​with respect to the reference voltage Vref.

[0079] With this configuration, it is possible to adjust the offset of the second comparator 132 with the reference voltage Vref input to the first comparator 131 as the center value.

[0080] <Application to TV> Fig. 8 is a block diagram showing an example of the configuration of a television equipped with the above-mentioned switching power supply device. Figs. 9A to 9C are a front view, a side view, and a rear view, respectively, of a television equipped with the above-mentioned switching power supply device. Television A of this example configuration has a tuner unit A1, a decoder unit A2, a display unit A3, a speaker unit A4, an operation unit A5, an interface unit A6, a control unit A7, and a power supply unit A8.

[0081] The tuner unit A1 selects a broadcast signal of a desired channel from a signal received by an antenna A0 externally connected to the television A.

[0082] The decoder unit A2 generates a video signal and an audio signal from the broadcast signal selected by the tuner unit A1, and also has a function of generating a video signal and an audio signal based on an external input signal from the interface unit A6.

[0083] The display unit A3 outputs the video signal generated by the decoder unit A2 as a video.

[0084] The speaker unit A4 outputs the audio signal generated by the decoder unit A2 as sound.

[0085] The operation unit A5 is one of the human interfaces that accepts user operations, and may be a button, a switch, a remote controller, or the like.

[0086] The interface unit A6 is a front end that receives external input signals from external devices (such as an optical disc player or a hard disk drive).

[0087] The control unit A7 generally controls the operations of the above-mentioned units A1 to A6. A CPU (central processing unit) or the like can be used as the control unit A7.

[0088] The power supply unit A8 supplies power to the above-mentioned units A1 to A7. As the power supply unit A8, the above-mentioned switching power supply device 1 can be suitably used.

[0089] <Other Modifications> In the above embodiment, a configuration in which a comparison circuit is applied to a step-down switching power supply device has been described as an example, but the application of the comparison circuit is not limited to this. For example, the output stage of the switching power supply device may be a step-up type, a step-up / step-down type, or an inverting type.

[0090] In addition, in the above embodiment, a fixed on-time type switching power supply device (on-time setting circuit) has been described as an example, but the application of the comparison circuit is not limited to this, and by changing the behavior of the variable reference voltage Vref2 based on the same technical idea as above, it is also possible to apply the comparison circuit to a fixed off-time type switching power supply device.

[0091] In addition, in the above embodiment, a switching power supply device that performs both the first calibration process and the second calibration process has been described as an example, but it is also possible to use a switching power supply device that performs only one of the first calibration process and the second calibration process, although this would result in the calibration process being performed slightly less frequently.

[0092] The embodiments of the present disclosure may be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The various embodiments described above may be combined as appropriate within a range that does not cause inconsistency. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments.

[0093] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0094] A comparison circuit (13) according to a first aspect of the present disclosure includes a first comparator (131) configured to compare an input signal with a reference voltage to generate a first comparison signal, a second comparator (132) configured to compare the input signal with a variable reference voltage to generate a second comparison signal, a variable reference voltage generation unit (133) configured to generate the variable reference voltage, and a logic unit (134) configured to output one of the first comparison signal and the second comparison signal as a comparison signal, and the logic unit adjusts the variable reference voltage to change the logic switching timing of the second comparison signal to the logic switching timing of the first comparison signal. a DAC (133b) configured to convert a counter value of the up-down counter into an analog voltage, and outputs the analog voltage or a voltage corresponding to the analog voltage as the variable reference voltage; and when adjusting the variable reference voltage, the counter value is divided into a higher-order bit side and a lower-order bit side, the value of the higher-order bit side is changed to narrow the adjustment range of the variable reference voltage, and the value of the lower-order bit side is changed within the narrowed adjustment range (first configuration).

[0095] A comparison circuit (13) according to a second aspect of the present disclosure includes a first comparator (131) configured to compare an input signal with a reference voltage to generate a first comparison signal, a second comparator (132) configured to compare the input signal with a variable reference voltage to generate a second comparison signal, a variable reference voltage generation unit (133) configured to generate the variable reference voltage, and a logic unit (134) configured to output one of the first comparison signal and the second comparison signal as a comparison signal, and the logic unit is configured to adjust the variable reference voltage to approach the reference voltage. The variable reference voltage generation unit includes an up-down counter (133a) and a DAC (134b) configured to convert the counter value of the up-down counter into an analog voltage, and outputs the analog voltage or a voltage corresponding to the analog voltage as the variable reference voltage. When adjusting the variable reference voltage, the counter value is divided into a higher bit side and a lower bit side, the value of the higher bit side is changed to narrow the adjustment range of the variable reference voltage, and the value of the lower bit side is changed within the narrowed adjustment range (second configuration).

[0096] According to the comparison circuit of the first or second configuration, it is possible to quickly return to a setting that does not degrade the output accuracy even if the setting deviates from the setting that does not degrade the output accuracy, and it is possible to use a plurality of comparators with different characteristics.

[0097] In the comparison circuit of the first or second configuration, the change in the value of the higher-order bit may be a configuration (third configuration) in which bits that are 0 are repeatedly changed to 1 one by one, starting from the most significant bit.

[0098] In the comparison circuit of the first or second configuration, the change in the value of the higher-order bit may be a configuration (fourth configuration) in which bits that are 1 are repeatedly changed to 0 one by one, starting from the most significant bit.

[0099] In the comparator circuit of any of the first to fourth configurations, the change in the value on the lower-order bit side may be such that the counter value is repeatedly increased by one each time (fifth configuration).

[0100] In the comparator circuit of any of the first to fourth configurations, the change in the value on the lower-order bit side may be such that the counter value is repeatedly decreased by one (sixth configuration).

[0101] In a comparison circuit of any of the first to sixth configurations above, if the adjustment range of the variable reference voltage cannot be narrowed even by changing the value of the more significant bit side, the number of bits on the more significant bit side may be increased and the number of bits on the less significant bit side may be decreased, and then the value of the more significant bit side may be changed to continue the process of narrowing the adjustment range of the variable reference voltage (seventh configuration).

[0102] A semiconductor integrated circuit device (10) of the present disclosure includes a ripple injection circuit (11) configured to generate a feedback voltage by superimposing a ripple voltage simulating a coil current on an output voltage or a divided voltage of the output voltage, a reference voltage generation circuit (12) configured to generate a predetermined reference voltage, a main comparator configured to compare the feedback voltage with the reference voltage to generate a comparison signal, a one-shot pulse generation circuit (14) configured to generate a one-shot pulse in a set signal in response to the comparison signal, and a reset circuit (15) configured to set an output signal to a first logic level in response to the set signal and reset the output signal to a second logic level in response to a reset signal. an RS flip-flop (15) configured to set the output signal to the first logic level, an on-time setting circuit (16) configured to generate a one-shot pulse in the reset signal when a predetermined on-time has elapsed since the output signal was set to the first logic level, a gate driver circuit (17) configured to generate drive signals for an output transistor (N1) and a synchronous rectification transistor (N2) in response to the output signal, and a backflow detection circuit (18) configured to detect a backflow of the coil current and forcibly turn off the synchronous rectification transistor, and a configuration (eighth configuration) having a comparison circuit of any of the first to seventh configurations as the main comparator.

[0103] A switching power supply device (1) of the present disclosure has a configuration (ninth configuration) including a semiconductor integrated circuit device of the eighth configuration described above, and a switch output stage that is partially or entirely attached externally to the semiconductor integrated circuit device and configured to generate the output voltage from the input voltage. [Explanation of symbols]

[0104] 1 Switching power supply 10. Semiconductor integrated circuit device 11 Ripple injection circuit 12 Reference voltage generation circuit 13 Main comparator (comparison circuit) 131 First Comparator 132 Second Comparator 133 Variable reference voltage generator 133a Up / down counter 133b DAC 133c Addition section 134 Logic Section 14 One-shot pulse generator 15 RS Flip-Flop 16 ON time setting circuit 17 Gate driver circuit 18 Reverse current detection circuit 20 Switch output stage N1 N-channel MOS field effect transistor (output transistor) N2 N-channel MOS field effect transistor (synchronous rectification transistor) L1 coil R1, R2 resistance C1 Capacitor T1~T8 External terminals A Television A0 Antenna A1 Tuner section A2 Decoder section A3 display section A4 Speaker section A5 Control section A6 Interface section A7 Control section A8 Power supply section G1 Higher bit side G2 lower bit side

Claims

1. a first comparator configured to compare an input signal with a reference voltage to generate a first comparison signal; a second comparator configured to compare the input signal with a variable reference voltage to generate a second comparison signal; a variable reference voltage generator configured to generate the variable reference voltage; a logic section configured to output one of the first comparison signal and the second comparison signal as a comparison signal; having the logic unit is configured to adjust the variable reference voltage so as to bring a logic switching timing of the second comparison signal closer to a logic switching timing of the first comparison signal; The variable reference voltage generating unit is an up-down counter; and a DAC configured to convert a counter value of the up-down counter into an analog voltage; outputting the analog voltage or a voltage corresponding to the analog voltage as the variable reference voltage; A comparison circuit configured to divide the counter value into upper bit and lower bit sides when adjusting the variable reference voltage, change the value of the upper bit side to narrow the adjustment range of the variable reference voltage, and change the value of the lower bit side within the narrowed adjustment range.

2. 2. The comparison circuit according to claim 1, wherein the change in the value of the most significant bit side is performed by repeatedly changing bits that are 0 to 1 one by one starting from the most significant bit.

3. 2. The comparison circuit according to claim 1, wherein the change in the value of the most significant bit side is performed by repeatedly changing bits that are 1 to 0 one by one in order from the most significant bit.

4. 2. The comparison circuit according to claim 1, wherein the change in the value on the lower bit side repeats incrementing the counter value by one.

5. 2. The comparison circuit according to claim 1, wherein the change in the value on the lower bit side is performed by repeatedly decreasing the counter value by one.

6. 2. The comparison circuit according to claim 1, wherein if the adjustment range of the variable reference voltage cannot be narrowed by changing the value of the more significant bit, the number of bits on the more significant bit side is increased and the number of bits on the less significant bit side is decreased, and then the value of the more significant bit side is changed to continue the process of narrowing the adjustment range of the variable reference voltage.

7. a ripple injection circuit configured to generate a feedback voltage by superimposing a ripple voltage simulating a coil current on an output voltage or a divided voltage of the output voltage; a reference voltage generating circuit configured to generate a predetermined reference voltage; a main comparator configured to compare the feedback voltage with the reference voltage to generate a comparison signal; a one-shot pulse generating circuit configured to generate a one-shot pulse in a set signal in response to the comparison signal; an RS flip-flop configured to set an output signal to a first logic level in response to the set signal and to reset the output signal to a second logic level in response to a reset signal; an on-time setting circuit configured to generate a one-shot pulse in the reset signal when a predetermined on-time has elapsed since the output signal is set to the first logic level; a gate driver circuit configured to generate drive signals for an output transistor and a synchronous rectification transistor in response to the output signal; a reverse current detection circuit configured to detect a reverse current of the coil current and forcibly turn off the synchronous rectification transistor; having 7. A semiconductor integrated circuit device comprising the comparison circuit according to claim 1 as the main comparator.

8. A semiconductor integrated circuit device according to claim 7; a switch output stage that is partly or entirely attached externally to the semiconductor integrated circuit device and configured to generate the output voltage from an input voltage; A switching power supply device comprising:

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