Communication device

Abstract

To provide a communication device capable of reducing EMI noise.SOLUTION: At least one of a master node (1x) and a slave node (1Ax) is a communication device (x) configured to be switchable between a first state in which in response to a feedback input of a bus voltage (VBUS) of a communication line (3), a slew rate of the bus voltage (VBUS) is controlled to a desired value, and a second state in which in response to an input of a predetermined control signal, the slew rate of the bus voltage (VBUS) is controlled to the desired value.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The invention disclosed herein relates to a communication device. [Background technology]

[0002] In recent years, in the field of in-vehicle communications, communication devices (such as CXPI [clock extension peripheral interface] communication devices) that use pulse-width modulated signals as transmission codes between multiple nodes (master node and slave node) connected to a communication line have been put into practical use.

[0003] As an example of the related art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2021 / 085169

[0005] [overview] The communication device disclosed in Patent Document 1 leaves room for further consideration in terms of reducing EMI (electromagnetic interference) noise that occurs during communication.

[0006] The communication device disclosed in this specification is a communication device that uses a pulse width modulation signal as a transmission code between a master node and a slave node connected to a communication line. At least one of the master node and the slave node is configured to be switchable between a first state in which the slew rate of the bus voltage is controlled to a desired value in response to a feedback input of the bus voltage of the communication line, and a second state in which the slew rate of the bus voltage is controlled to a desired value in response to an input of a predetermined control signal. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing the overall configuration of a communication device Y of a comparative example. [Diagram 2] FIG. 2 is a block diagram showing the configuration of the communication device Y. [Diagram 3] FIG. 3 is a timing chart showing the first signal S1, the drive signal G1, and the bus voltage VBUS when the master node 1y transmits data. [Figure 4] FIG. 4 is a timing chart showing the first signal S1, the drive signal G1, the second signal S2, the drive signal G2, and the bus voltage VBUS when the slave node 2Ay transmits data. [Diagram 5] FIG. 5 is a graph comparing the amount of noise generated when the master node 1y transmits data and when the slave node 2Ay transmits data. [Figure 6] FIG. 6 is a block diagram showing a configuration of a communication device X according to the present disclosure. [Figure 7] FIG. 7 is a timing chart showing the first signal S1, the drive signal G1, the current detection signal S3, the second signal S2, the drive signal G2, and the bus voltage VBUS when the slave node 2Ax transmits data. [Figure 8] FIG. 8 is a timing chart showing the first signal S1, the drive signal G1, the second signal S2, the drive signal G2, and the bus voltage VBUS when the slave node 2Ax transmits data. [Figure 9] FIG. 9 is a block diagram showing a configuration of a communication device X according to the second embodiment of the present disclosure. [Figure 10] FIG. 10 is a timing chart showing the first signal S1, the detection signal S4, the second signal S2, the drive signal G2, and the bus voltage VBUS when the slave node 2Ax according to the second embodiment of the present disclosure transmits data. [Figure 11] FIG. 11 is a block diagram showing an example of a waveform shaping circuit 15x.

[0008] [Detailed Description] <Communication device of comparative example> First, a communication device Y will be described as a comparative example (= a configuration to be compared with an embodiment of the present disclosure described later) of the communication device X of the present disclosure, with reference to Fig. 1. Fig. 1 is a block diagram showing the overall configuration of the communication device Y of the comparative example.

[0009] The communication device Y is mounted on a vehicle as a means for constructing an in-vehicle LAN [local area network], and includes a master node 1y, multiple slave nodes (slave nodes 2Ay and 2By in this diagram), and a communication line 3. The communication device Y complies with the CXPI protocol, and uses a pulse width modulation signal PWM as a transmission code between multiple nodes connected to the communication line 3.

[0010] The master node 1y is, for example, a body control module (BCM) (or an electronic control unit (ECU) mounted thereon) that comprehensively controls wipers, interior lights, etc. The master node 1y includes a CXPI transceiver 4, a microcomputer 5, and an oscillator 6.

[0011] The slave node 2Ay is, for example, a wiper (or an ECU mounted thereon). The slave node 2Ay includes a CXPI transceiver 7A and a microcomputer 8.

[0012] The slave node 2By is, for example, an interior light (or an ECU mounted thereon). The slave node 2By includes a microcomputer-less CXPI transceiver 7B. The microcomputer-less CXPI transceiver 7B includes, for example, a CXPI physical layer, a sequencer, and an interface (driver, etc.).

[0013] The communication line 3 is a so-called harness (wire harness) that is laid out in various parts of the vehicle. Note that various in-vehicle devices such as air conditioners and door mirrors, in addition to the above-mentioned wipers and interior lights, are assumed to be slave nodes connected to the communication line 3.

[0014] The features of the CXPI protocol are briefly described below. First, the microcomputers 5 and 8 can communicate with each other using a general-purpose UART [universal asynchronous receiver / transmitter] interface. Second, bidirectional communication is performed between the CXPI transceiver 4 and the CXPI transceivers 7A and 7B using a pulse-width modulation signal PWM in which data is superimposed on the communication clock CLK. Third, the slave nodes 2Ay and 2By can extract the communication clock CLK from the pulse-width modulation signal PWM, so there is no need to provide individual oscillators. Fourth, the communication device Y can perform bidirectional communication between multiple nodes in synchronization with the communication clock CLK generated by the oscillator 6 of the master node 1y.

[0015] Next, bidirectional communication using the pulse width modulation signal PWM will be described. The logical value of the data superimposed on the pulse width modulation signal PWM is determined according to the length of the period during which the pulse width modulation signal PWM is at a low level (dominant level) (=pulse width WL).

[0016] Specifically, when the pulse width WL is shorter than a predetermined logical decision value, the logical value of the data is determined to be [1]. On the other hand, when the pulse width WL is longer than the logical decision value, the logical value of the data is determined to be [0].

[0017] When transmitting data [1] from the master node 1y, the CXPI transceiver 4 sets the low-level period (=pulse width WL) of the pulse-width modulation signal PWM to be shorter than the logical decision value. On the other hand, when transmitting data [0] from the master node 1y, the CXPI transceiver 4 sets the low-level period (=pulse width WL) of the pulse-width modulation signal PWM to be longer than the logical decision value.

[0018] In addition, during the data transmission period of the slave node 2Ay or 2By (= the data reception period of the master node 1y), the master node 1y is always in a state of transmitting data [1], i.e., transmitting the communication clock CLK for synchronization to the slave nodes 2Ay and 2By.

[0019] At this time, the CXPI transceiver 7A or 7B determines whether or not to extend the low level period (=pulse width WL) of the pulse width modulation signal PWM, depending on the data to be transmitted from the slave node 2Ay or 2By.

[0020] More specifically, when data [0] is transmitted from the slave node 2Ay or 2By, the low-level period of the pulse-width modulation signal PWM is extended, and the pulse width WL becomes longer than the logical decision value. On the other hand, when data [1] is transmitted from the slave node 2Ay or 2By, the low-level period of the pulse-width modulation signal PWM is not extended, and the pulse width WL remains shorter than the logical decision value.

[0021] The communication device Y conforming to the CXPI protocol is configured so that the low level (dominant level) of the pulse width modulation signal PWM prevails over the high level (recessive level). Therefore, when data (master side transmission signal and slave side transmission signal) transmitted from the master node 1y and the slave nodes 2Ay and 2By collide, the node that transmits the low level (dominant level) for a longer period prevails in arbitration. The above-mentioned parts of the configuration of the communication device Y are configured similarly in the communication device X described later.

[0022] Next, the master node 1y and the slave node 2Ay will be described in more detail. The slave node 2By has a basic configuration in common with the slave node 2Ay. Therefore, only the slave node 2Ay will be described here, and the description of the slave node 2By will be omitted.

[0023] Fig. 2 is a block diagram showing the configuration of a communication device Y. As shown in Fig. 2, the master node 1y has an external terminal N1 as a means for establishing an electrical connection with the outside. The slave node 2Ay has an external terminal N2 as a means for establishing an electrical connection with the outside. A first end of a communication line 3 is connected to the external terminal N1. A second end of the communication line 3 is connected to the external terminal N2. First, the master node 1y will be described, and then the slave node 2Ay will be described.

[0024] The master node 1y includes a diode D1a, a diode D1b, a terminating resistor R1, a receiving circuit 9, a communication circuit 10, and a waveform shaping circuit 11y.

[0025] The anode of the diode D1a is connected to the power supply terminal P1. The cathode of the diode D1a is connected to a first terminal of the termination resistor R1. The second terminal of the termination resistor R1 is connected to the external terminal N1. The anode of the diode D1b is connected to the second terminal of the termination resistor R1. The cathode of the diode D1b is connected to the drain of a master-side transistor T1, which will be described later.

[0026] The receiving circuit 9 detects the pulse width WL of the bus voltage VBUS (=pulse width modulation signal PWM) appearing on the communication line 3, and outputs the detection result to the communication circuit 10. As the receiving circuit 9, a comparator that compares the bus voltage VBUS with a predetermined logical determination value can be suitably used.

[0027] The communication circuit 10 receives the data (slave-side transmission signal) transmitted from the slave node 2Ay by receiving the output of the receiving circuit 9. The communication circuit 10 also outputs a first signal S1, in which data is superimposed on a communication clock, to a waveform shaping circuit 11y (more specifically, a master-side drive control circuit 12y, which will be described later).

[0028] The waveform shaping circuit 11y transmits data (master side transmission signal) to the slave node 2Ay based on the first signal S1 and the bus voltage VBUS.

[0029] Specifically, the waveform shaping circuit 11y includes a master side drive control circuit 12y and a master side transistor T1. The master side drive control circuit 12y generates a drive signal G1 based on a first signal S1 input from the communication circuit 10 and a bus voltage VBUS. The master side drive control circuit 12y generates the drive signal G1 so that the period of the drive signal G1 is the same as that of the first signal S1.

[0030] The master-side drive control circuit 12y controls the slew rate of the drive signal G1 based on the first signal S1 and the bus voltage VBUS. Specifically, a predetermined slew rate (slope) is added to the rising / falling edge of the drive signal G1 at the timing when the logic level of the first signal S1 is switched.

[0031] The master-side transistor T1 is an NMOSFET [N-channel type metal oxide semiconductor field effect transistor]. The source of the master-side transistor T1 is connected to the ground terminal. The gate of the master-side transistor T1 is connected to the application terminal of the drive signal G1 (= the output terminal of the master-side drive control circuit 12y). The drain of the master-side transistor T1 is connected to the communication line 3 (more specifically, the external terminal N1) via the diode D1b.

[0032] The master transistor T1 is turned on when the drive signal G1 is at a high level, and is turned off when the drive signal G1 is at a low level.

[0033] The slave node 2Ay includes a diode D2a, a diode D2b, a receiving circuit 13, a communication circuit 14, a waveform shaping circuit 15y, and a termination resistor R2.

[0034] The anode of the diode D2a is connected to the power supply terminal P2. The cathode of the diode D2a is connected to a first terminal of the termination resistor R2. The second terminal of the termination resistor R2 is connected to the external terminal N2. The resistance value of the termination resistor R2 is greater than the resistance value of the termination resistor R1. For example, the resistance value of the termination resistor R1 can be 1 kΩ, and the resistance value of the termination resistor R2 can be 30 kΩ.

[0035] The anode of the diode D2b is connected to the second end of the termination resistor R2. The cathode of the diode D2b is connected to the drain of the slave transistor T2, which will be described later.

[0036] The receiving circuit 13 detects the pulse width WL of the bus voltage VBUS (=pulse width modulation signal PWM) appearing on the communication line 3, and outputs the detection result to the communication circuit 14. A comparator that compares the bus voltage VBUS with a predetermined logical determination value can be suitably used as the receiving circuit 13. The slave node 2Ay is configured to be able to record the length of the pulse width WL of the bus voltage VBUS.

[0037] The communication circuit 14 receives data (master-side transmission signal) transmitted from the master node 1y by receiving the output of the receiving circuit 13. The communication circuit 14 can detect the communication clock used to generate the first signal S1, i.e., the timing at which the logic level of the first signal S1 switches (in other words, the timing at which the logic level of the drive signal G1 switches), from the output of the receiving circuit 13. The communication circuit 14 outputs a second signal S2, in which data is superimposed on the communication clock detected from the output of the receiving circuit 13, to the waveform shaping circuit 15y (more specifically, to the slave-side drive control circuit 16y described later).

[0038] The waveform shaping circuit 15y transmits data (slave-side transmission signal) to the master node 1y based on the second signal S2 and the bus voltage VBUS.

[0039] Specifically, the waveform shaping circuit 15y includes a slave-side drive control circuit 16y and a slave-side transistor T2. The slave-side drive control circuit 16y generates a drive signal G2 based on the second signal S2 input from the communication circuit 14 and the bus voltage VBUS. The slave-side drive control circuit 16y generates the drive signal G2 so that the period of the drive signal G2 is the same as that of the second signal S2.

[0040] The slave side drive control circuit 16y controls the slew rate of the drive signal G2 based on the second signal S2 and the bus voltage V. Specifically, a predetermined slew rate is added to the rising / falling edge of the drive signal G2 at the timing when the logic level of the second signal S2 is switched.

[0041] The slave side transistor T2 is an NMOSFET. The source of the slave side transistor T2 is connected to the ground terminal. The gate of the slave side transistor T2 is connected to the application terminal of the drive signal G2 (= the output terminal of the slave side drive control circuit 16y). The drain of the slave side transistor T2 is connected to the communication line 3 (more specifically, the external terminal N2) via the diode D2b.

[0042] The slave transistor T2 is turned on when the drive signal G2 is at a high level, and turned off when the drive signal G2 is at a low level. Hereinafter, the bus voltage VBUS when the master transistor T1 and the slave transistor T2 are both off is referred to as a first voltage V1. The first voltage V1 is about 12V.

[0043] When the master transistor T1 is on and the slave transistor T2 is off, a small current flows in the communication line 3 in the direction from the slave node 2Ay to the master node 1y. More specifically, a current flows from the power supply terminal P2 through the communication line 3, via the diode D1b and the master transistor T1 to the ground terminal. This current flows through the high resistance termination resistor R2, so the current value is small. Also, in this state, a current flows from the power supply terminal P1 to the ground terminal through the diode D1b and the master transistor T1. This current does not flow in the communication line 3.

[0044] The bus voltage VBUS in this state (= the state in which the master transistor T1 is on and the slave transistor T2 is off) is defined as the second voltage V2. The voltage value of the second voltage V2 corresponds to the forward drop voltage of the diode D1b, and is about 0.7 to 0.8 V.

[0045] Furthermore, when both the master-side transistor T1 and the slave-side transistor T2 are on, a current flows in the direction from the master node 1y to the slave node 2Ay in the communication line 3. This current is approximately equal to the current flowing from the power supply terminal P1 via the low-resistance terminating resistor R1 (for example, 1 kΩ) minus the current flowing toward the ground terminal via the master-side transistor T1.

[0046] The bus voltage VBUS in this state (=the state in which the master-side transistor T1 and the slave-side transistor T2 are both on) is defined as a third voltage V3. The voltage value of the third voltage V3 is the forward drop voltage of each of the diodes D1b and D2b, and is about 0.6 V.

[0047] When both the master transistor T1 and the slave transistor T2 are on, the current flowing from the power supply terminal P1 is divided into two parts: one that flows to the ground terminal via the diode D1b, and the other that flows to the ground terminal via the communication line 3 and the diode D2b. Therefore, the value of the current flowing through the diode D1b is smaller than when the master transistor T1 is on and the slave transistor T2 is off, and the forward drop voltage of the diode D1b is reduced. Therefore, the third voltage V3 is smaller than the second voltage V2. The forward drop voltage of the diode D2b is also reduced in the same manner.

[0048] When the master transistor T1 is off and the slave transistor T2 is on, a current flows in the communication line 3 in the direction from the master node 1y to the slave node 2Ay. This current corresponds to almost the entire amount of the large current flowing through the low-resistance termination resistor R1. Therefore, the current value increases compared to when both the master transistor T1 and the slave transistor T2 are on. Therefore, the bus voltage VBUS in this state (= the state in which the master transistor T1 is off and the slave transistor T2 is on) is higher than the bus voltage VBUS in the state in which both the master transistor T1 and the slave transistor T2 are on. The bus voltage VBUS in this state is approximately the same as the second voltage V2.

[0049] <About data transmission between nodes> Next, data transmission between the master node 1y and the slave node 2Ay will be described in detail using a timing chart. As described above, a communication method is adopted between the master node 1y and the slave node 2Ay in the communication device Y, which distinguishes between logical values ​​(=data [0] or [1]) depending on whether the pulse width WL (=length of the low level period) of the pulse width modulation signal PWM exceeds a predetermined logical determination value. Specifically, it is as follows.

[0050] First, a case where the master node 1y transmits data to the slave node 2Ay will be described. Fig. 3 is a timing chart showing the first signal S1, the drive signal G1, and the bus voltage VBUS when the master node 1y transmits data.

[0051] During the data transmission period of the master node 1y, the master node 1y is basically in a state of outputting data [1] to the communication line 3. In terms of Fig. 3, this state corresponds to the period from time t11 to time t13. At this time, the drive signal G1 is pulse-driven with an on-duty (=Ton / T, where T is the switching period and Ton is the on-period) such that the pulse width WL (=length of the low-level period) of the pulse-width modulation signal PWM falls below the logical decision value.

[0052] During the data transmission period of the master node 1y, when the master node 1y outputs data [0] to the communication line 3, the drive signal G1 is pulse-driven with an on-duty such that the pulse width WL (=length of the low-level period) of the pulse-width modulation signal PWM exceeds the logical decision value. This state corresponds to the period from time t13 to time t15 in FIG. 3.

[0053] As described above, the master-side drive control circuit 12y adds a slew rate to the rising / falling edges of the drive signal G1 at the timing when the logic level of the first signal S1 switches. Referring to Fig. 3, a predetermined slew rate (slope) is added to the drive signal G1 at times t11, t13, and t15, and at times t12, t14, and t16.

[0054] By adding a slew rate to the rise / fall of the drive signal G1, the bus voltage VBUS changes at a predetermined slew rate when changing between the first voltage V1 and the second voltage V2.

[0055] Next, a case where data is transmitted from the slave node 2Ay to the master node 1y will be described. Fig. 4 is a timing chart showing the first signal S1, the drive signal G1, the second signal S2, the drive signal G2, and the bus voltage VBUS when the slave node 2Ay transmits data.

[0056] Even during the data transmission period of the slave node 2Ay, the master node 1y is basically in a state of outputting data [1] onto the communication line 3.

[0057] During the period when data [1] is transmitted from the slave node 2Ay (times t21 to t23 in FIG. 4), the drive signal G2 is maintained at a low level, and the slave-side transistor T2 remains off. As a result, the low-level period of the pulse-width modulation signal PWM is not extended, and the pulse width WL remains shorter than the logical determination value.

[0058] On the other hand, during the period in which the slave node 2Ay transmits data [0] to the master node 1y (the period from time t23 to time t27 in accordance with FIG. 4), the pulse width WL is expanded so as to exceed the logical decision value.

[0059] Specifically, the slave node 2Ay drops the second signal S2 to a low level after receiving the falling edge of the first signal S1 (=the falling edge of the bus voltage VBUS voltage) via the communication line 3. At this time, the data output from the master node 1y (master side transmission signal) and the data output from the slave node 2Ay (slave side transmission signal) collide. As a result, the data output from the slave node 2Ay becomes dominant, and the pulse width WL is extended until the second signal S2 switches from a low level to a high level.

[0060] More specifically, with reference to FIG. 4, at time t23, the drive signal G1 rises to the high level, and as the voltage of the bus voltage VBUS decreases, the slave node 2Ay detects the falling timing of the first signal S1. Then, at time t24 after a predetermined time, the slave node 2Ay raises the drive signal G2 to the high level.

[0061] At time t25, the drive signal G1 falls to the low level. The slave node 2Ay lowers the drive signal G2 to the low level at time 26 when the low level becomes longer than the pulse width WL recorded in the section from t21 to t23. In this way, by adjusting the timing at which the slave node 2Ay lowers the drive signal G2 to the low level, the pulse width WL is made longer than the logical determination value, and the data [1] is transmitted from the slave node 2Ay to the master node 1y.

[0062] <Consideration of EMI Noise> By the way, if there is a steep change in the bus voltage VBUS, there is a possibility that EMI noise may occur. Hereinafter, the generation of EMI noise will be described.

[0063] In the communication device Y, as described above, the master-side drive control circuit 12y adds a slew rate to the drive signal G1 at the switching timing of the logical level of the first signal S1 (when described with reference to FIG. 4, times t21, t22, t23, t27, and time 28). Also, the slave-side drive control circuit 16y adds a slew rate to the drive signal G2 at the switching timing of the logical level of the second signal S2 (when described with reference to FIG. 4, time 26).

[0064] The speed of the transition of the on / off state of the master transistor T1 changes according to the slew rate of the drive signal G1. Also, the speed of the transition of the on / off state of the slave transistor T2 changes according to the slew rate of the drive signal G2. Then, when the bus voltage VBUS changes between the above-mentioned first voltage V1 and second voltage V2, a slew rate is also applied to the bus voltage VBUS according to the slew rates of the drive signals G1 and G2.

[0065] Therefore, at the timing when the logic level of the first signal S1 switches and at the timing when the logic level of the second signal S2 switches, the bus voltage VBUS is given a slew rate and changes relatively gently, thereby suppressing the generation of EMI noise.

[0066] As described above, the slew rates of the drive signals G1 and G2 are controlled based on the bus voltage V. That is, the slew rate of the bus voltage V is feedback-controlled to a desired value in response to a feedback input of the bus voltage V.

[0067] However, even when the logic level of the second signal S2 is switched, if the slave transistor T2 is turned on while the master transistor T1 is on, EMI noise may occur for the following reasons.

[0068] As described above, in a state in which the master-side transistor T1 is on and the slave-side transistor T2 is off (the state immediately before time t24 in FIG. 4), the voltage value of the bus voltage VBUS is the second voltage V2. When the slave-side transistor T2 is turned on in this state, the bus voltage VBUS drops from the second voltage V2 to the third voltage V3. The potential difference between the second voltage V2 and the third voltage V3 (approximately 0.1 V) is much smaller than the potential difference between the first voltage V1 and the second voltage V2 (approximately 11 V).

[0069] Here, the slew rate applied to the bus voltage VBUS is feedback-controlled so as to be a desired value set as a value to be applied when the bus voltage VBUS changes between the first voltage V1 and the second voltage V2 (when the voltage value of the bus voltage VBUS changes between about 12V and about 0.7V). In contrast, when the bus voltage VBUS changes between the second voltage V2 (=about 0.7V) and the third voltage V3 (=about 0.6V), the potential difference (=about 0.1V) is relatively small as described above. Then, when the bus voltage VBUS drops from the second voltage V2 to the third voltage V3, it is difficult to make the slew rate of the bus voltage VBUS a desired value by the feedback control as described above. For this reason, when the bus voltage VBUS drops from the second voltage V2 to the third voltage V3 (when the slave-side transistor T2 is turned on while the master-side transistor T1 is on), the bus voltage VBUS changes abruptly, causing EMI noise.

[0070] Similarly, even when the logic level of the first signal S1 is switched, if the master transistor T1 is turned off while the slave transistor T2 is on, EMI noise may occur for the following reasons.

[0071] As described above, when the master-side transistor T1 and the slave-side transistor T2 are both on (in the state from time t24 to time t25 in FIG. 4), the voltage value of the bus voltage VBUS is the third voltage V3. When the master-side transistor T1 is turned off in this state, the bus voltage VBUS rises from the third voltage V3 to the second voltage V2. The potential difference between the second voltage V2 and the third voltage V3 (=about 0.1 V) is much smaller than the potential difference between the first voltage V1 and the second voltage V2 (about 11 V). Then, when the master-side transistor T1 is turned off while the slave-side transistor T2 is on, it is difficult to make the slew rate of the bus voltage VBUS a desired value by the feedback control as described above. For this reason, when the bus voltage VBUS rises from the third voltage V3 to the second voltage V2 (when the master-side transistor T1 is turned off while the slave-side transistor T2 is on), the bus voltage VBUS changes abruptly, causing EMI noise.

[0072] Fig. 5 is a graph comparing the amount of noise generated when the master node 1y transmits data and when the slave node 2Ay transmits data. In Fig. 5, the graph when the master node 1y transmits data is shown by a dashed line, and the graph when the slave node 2Ay transmits data is shown by a solid line.

[0073] In general, EMI noise is a type of noise that occurs in a relatively high frequency band among various types of noise. As shown in Fig. 5, in a band below a certain frequency a [Hz], the amount of noise is equal between the slave node 2Ay and the master node 1y when transmitting data. However, in a relatively high frequency band exceeding the frequency a [Hz], the amount of noise is greater when the slave node 2Ay transmits data than when the master node 1y transmits data. This is because, as described above, EMI noise occurs during the data transmission period of the slave node 2Ay when transmitting data [0] (the period from time t23 to time t26 in accordance with Fig. 4).

[0074] Note that the change in the bus voltage VBUS and EMI noise have been explained here with a focus on the diodes D1a to D2b. However, even when focusing on the current (bus current) flowing through the communication line 3, the same problem as described above can be explained in that a sudden change in the bus voltage VBUS causes a sudden change in the bus current, which generates EMI noise.

[0075] In response to the above-mentioned problems, the communication device X according to the embodiment of the present disclosure is capable of suppressing the generation of EMI noise. The communication device X according to the first embodiment of the present disclosure will be described in detail below. Note that the communication device X according to the embodiment of the present disclosure includes configurations in common with the above-mentioned communication device Y. For this reason, the same reference numerals are used for the common configurations, and description thereof will be omitted.

[0076] <Communication device according to the present disclosure> The communication device X according to the first embodiment of the present disclosure is mounted on a vehicle as a means for constructing an in-vehicle LAN (local area network), similar to the above-mentioned communication device Y. The communication device X complies with the CXPI protocol and uses a pulse width modulation signal PWM as a transmission code between multiple nodes.

[0077] Fig. 6 is a block diagram showing a configuration of a communication device X of the present disclosure. As shown in Fig. 6, the communication device X includes a master node 1x, a slave node 2Ax, and a communication line 3. The master node 1x has an external terminal N1 as a means for establishing an electrical connection with the outside. The slave node 2Ax has an external terminal N2 as a means for establishing an electrical connection with the outside.

[0078] At least one of the master node 1x and the slave node 2Ax is configured to be switchable between a first state and a second state. The first state is a state in which at least one of the master node 1x and the slave node 2Ax receives a feedback input of the bus voltage VBUS and feedback controls the slew rate of the bus voltage VBUS to a desired value. The second state is a state in which at least one of the master node 1x and the slave node 2Ax receives an input of a predetermined internal signal and controls the slew rate of the bus voltage VBUS to a desired value. The specific configurations of the master node 1x and the slave node 2Ax will be described below.

[0079] The master node 1x includes a diode D1a, a diode D1b, a terminating resistor R1, a receiving circuit 9, a communication circuit 10, a control circuit 17, a selector 18, a waveform shaping circuit 11x, and a detection circuit 19.

[0080] The communication circuit 10 receives the output of the receiving circuit 9, thereby receiving the data transmitted from the slave node 2Ax.

[0081] The detection circuit 19 is connected on the current path through the master transistor T1 (between the source of the master transistor T1 and the ground terminal in FIG. 6). The detection circuit 19 detects a change in current (= a decrease in the sink current flowing through the master transistor T1) during the on-period Ton of the master transistor T1, and inputs the detection result to the selector 18 as a current detection signal S3.

[0082] The control circuit 17 outputs a predetermined control signal. The selector 18 receives the output of the control circuit 17 and the bus voltage VBUS, selects either the output of the control circuit 17 or the bus voltage VBUS in response to the current detection signal S3, and inputs the selected output to the waveform shaping circuit 11x (more specifically, the master side drive control circuit 12x).

[0083] The waveform shaping circuit 11x receives the first signal S1 and the output of the selector 18, and transmits data to the slave node 2Ax while controlling the slew rate of the bus voltage VBUS.

[0084] When the output of the selector 18 is the bus voltage VBUS, the waveform shaping circuit 11x receives the bus voltage VBUS as a feedback input and performs feedback control so that the slew rate of the bus voltage VBUS becomes a desired value. This state is the first state described above. When the output of the selector 18 is the output of the control circuit 17, the waveform shaping circuit 11x receives the control signal (internal signal) output by the control circuit 17 as an input and controls the slew rate of the bus voltage VBUS to become a desired value. This state is the second state described above.

[0085] Specifically, the waveform shaping circuit 11x includes a master side drive control circuit 12x and a master side transistor T1. The master side drive control circuit 12x generates a drive signal G1 in response to the first signal S1 and the output of the selector 18. More specifically, the master side drive control circuit 12x generates the drive signal G1 so that the period of the drive signal G1 is the same as that of the first signal S1.

[0086] The master-side drive control circuit 12x controls the slew rate of the drive signal G1 based on the first signal S1 and the output of the selector 18. Specifically, the master-side drive control circuit 12x adds either a slew rate based on the bus voltage VBUS or a slew rate based on the output of the control circuit 17 to the drive signal G1 at the timing when the logic level of the first signal S1 switches.

[0087] The slave node 2Ax includes a diode D2a, a diode D2b, a receiving circuit 13, a communication circuit 14, a waveform shaping circuit 15x, and a termination resistor R2.

[0088] The communication circuit 14 receives the data transmitted from the master node 1x by receiving the output of the receiving circuit 13. The communication circuit 14 also outputs a second signal S2, in which data is superimposed on a communication clock extracted from the output of the receiving circuit 13, to a waveform shaping circuit 15x (more specifically, a slave side drive control circuit 16x, described later), thereby transmitting data to the master node 1x.

[0089] The control circuit 20 outputs a predetermined control signal. The selector 21 receives the output of the control circuit 20 and the bus voltage VBUS, and inputs either the output of the control circuit 20 or the bus voltage VBUS to the waveform shaping circuit 15x (more specifically, the slave side drive control circuit 16x) under a predetermined condition. In other words, the communication circuit 14 switches the output of the selector 21 to either the output of the control circuit 20 or the bus voltage VBUS in synchronization with the switching timing of the logic level of the second signal S2.

[0090] The waveform shaping circuit 15x receives the second signal S2 and the output of the selector 21, and transmits data to the master node 1x while controlling the slew rate of the bus voltage VBUS.

[0091] When the output of the selector 21 is the bus voltage VBUS, the waveform shaping circuit 15x receives the bus voltage VBUS as a feedback input and performs feedback control so that the slew rate of the bus voltage VBUS becomes a desired value. This state is the first state described above. When the output of the selector 21 is the output of the control circuit 20, the waveform shaping circuit 15x receives the control signal (internal signal) output by the control circuit 20 as an input and controls the slew rate of the bus voltage VBUS to become a desired value. This state is the second state described above.

[0092] Specifically, the waveform shaping circuit 15x includes a slave-side drive control circuit 16x and a slave-side transistor T2. The slave-side drive control circuit 16x generates a drive signal G1 in response to the second signal S2 and the output of the selector 21. More specifically, the slave-side drive control circuit 16x generates a drive signal G2 so that the drive signal G2 has the same period as that of the second signal S2.

[0093] The slave-side drive control circuit 16x controls the slew rate of the drive signal G2 based on the second signal S2 and the output of the selector 21. Specifically, the slave-side drive control circuit 16x applies, to the drive signal G2, either a slew rate based on the bus voltage VBUS or a slew rate based on the output of the control circuit 20 at the timing when the logic level of the second signal S2 switches.

[0094] The slew rate control of the bus voltage VBUS by the communication device X according to this embodiment will be described in more detail below.

[0095] FIG. 7 is a timing chart showing the first signal S1, the drive signal G1, the current detection signal S3, the second signal S2, the drive signal G2, and the bus voltage VBUS when the slave node 2Ax transmits data.

[0096] The slave node 2Ax switches to the second state at the first timing. The first timing is the timing when the logic level of the second signal S2 switches from a high level (= recessive level) to a low level (= dominant level). In reference to FIG. 7, the first timing is time t34.

[0097] On the other hand, the master node 1x switches to the second state at the second timing. The second timing is the timing when the logic level of the first signal S1 switches while the slave node 2Ax sets the second signal S2 to a low level (=dominant level). In reference to FIG. 7, the second timing is time t35.

[0098] Moreover, the master node 1x switches to the first state at the third timing. The third timing is the timing at which the logic level of the first signal S1 switches while the slave node 2Ax sets the second signal S2 to a high level (=recessive level). In reference to FIG. 7, the third timings are t31, t32, t33, t37, and t38.

[0099] The master node 1x determines, based on the current detection signal S3 output by the detection circuit 19, whether the timing at which the logic level of the first signal S1 switches is the second timing or the third timing.

[0100] The slave node 2Ax switches to the first state at the fourth timing. The fourth timing is the timing when the logic level of the second signal S2 switches from a low level (=dominant level) to a high level (=recessive level). In reference to FIG. 7, the fourth timing is t36.

[0101] A more detailed explanation will be given with reference to Fig. 7. At times t31, t33, and t37 (=third timing), the first signal S1 falls to a low level, and the drive signal G1 rises to a high level. As a result, the slave side transistor T2 remains off, and the master side transistor T1 turns on. This causes the bus voltage VBUS to drop from the first voltage V1 to the second voltage V2.

[0102] At time t31 and time t33, the detection circuit 19 outputs a low-level current detection signal S3. At time t37, the detection circuit 19 detects that the bus voltage VBUS is the first voltage V1 and drops the current detection signal S3 to a low level. In response to the low-level current detection signal S3, the selector 18 selects the bus voltage VBUS and inputs it to the master-side drive control circuit 12x. Then, a slew rate based on the bus voltage VBUS is added to the drive signal G1, and the drive signal G1 rises from a low level to a high level. As a result, a slew rate (more specifically, a slew rate feedback-controlled to a desired value in response to a feedback input of the bus voltage VBUS) is added to the bus voltage VBUS at time t31, time t33, and time t37 (=third timing).

[0103] At times t32 and t38 (=third timing), the first signal S1 rises from low level to high level, the drive signal G1 falls to low level, and both the master transistor T1 and the slave transistor T2 are turned off. As a result, the bus voltage VBUS rises from the second voltage V2 to the first voltage V1.

[0104] At this time, the detection circuit 19 outputs a low-level current detection signal S3. Therefore, upon receiving the low-level current detection signal S3, the selector 18 selects the bus voltage VBUS and inputs it to the master-side drive control circuit 12x. As a result, the drive signal G1 is given the above-mentioned second slew rate and falls from a high level to a low level. Therefore, at time t32 and time t38 (=third timing), a slew rate (more specifically, a slew rate feedback-controlled to a desired value in response to a feedback input of the bus voltage VBUS) is added to the bus voltage VBUS.

[0105] At time t34 (=first timing), the first signal S1 is at a low level and the second signal S2 rises to a high level. At this time, the master transistor T1 is on and the slave transistor T2 is on, and the bus voltage VBUS drops from the second voltage V2 to the third voltage V3.

[0106] At this time, the selector 21 selects the output of the control circuit 20 and outputs it to the slave side drive control circuit 16x. Therefore, the drive signal G2 rises from a low level to a high level with a slew rate based on the output of the control circuit 20 being added. As a result, at time t34, a slew rate (more specifically, a slew rate controlled to a desired value in response to an internal signal (= the output signal of the control circuit 20)) is added to the bus voltage VBUS.

[0107] After time t34 and before time t35, the detection circuit 19 detects a current change during the on-period Ton of the master-side transistor T1 and raises the logic level of the current detection signal S3 from low to high. Then, the selector 18 selects the output of the control circuit 17 based on the current detection signal S3 and outputs it to the master-side drive control circuit 12x.

[0108] At time t35 (second timing), the first signal S1 rises from a state in which both the first signal S1 and the second signal S2 are at a low level to a high level. At this time, the master-side transistor T1 and the slave-side transistor are both on, and only the master-side transistor T1 turns off. Then, the bus voltage VBUS rises from the third voltage V3 to the second voltage V2.

[0109] At this time, as described above, the logic level of the current detection signal S3 is high, and the selector 18 receives the high-level current detection signal S3, selects the output of the control circuit 17, and outputs it to the master-side drive control circuit 12x. As a result, the drive signal G1 is given the second slew rate described above and falls from high to low. As a result, at time t35, a slew rate (more specifically, a slew rate controlled to a desired value in response to an internal signal (= the output signal of the control circuit 17)) is added to the bus voltage VBUS.

[0110] At time t36 (=fourth timing), the second signal S2 rises from low level to high level, the drive signal G2 falls from high level to low level, and both the master transistor T1 and the slave transistor T2 are turned off. As a result, the bus voltage VBUS rises from the second voltage V2 to the first voltage V1.

[0111] At this time, the selector 21 selects the bus voltage VBUS and outputs it to the slave-side drive control circuit 16x. Therefore, a slew rate based on the bus voltage VBUS is added to the drive signal G2, and the drive signal G2 falls from high to low. As a result, at time t36 (=fourth timing), a slew rate (a slew rate that is feedback-controlled to a desired value in response to the feedback input of the bus voltage VBUS) is added to the bus voltage VBUS.

[0112] As described above, by switching to either the first state or the second state, a desired slew rate can be applied to the bus voltage VBUS when the slave transistor T2 is turned on while the master transistor T1 is on, and when the master transistor T1 is turned off while the slave transistor T2 is on, thereby suppressing EMI noise.

[0113] <Considerations on Glitches> However, even if the low-level pulse width of the first signal S1 is a value that can be adopted in the communication standard (= CXPI protocol), if it is relatively small (for example, if it is the minimum value in the range that complies with the communication standard), a so-called glitch that is not permitted by the communication standard may occur due to the above-mentioned slew rate control. If a glitch occurs, the bidirectional communication between the master node 1x and the slave node 2Ax may become unstable (or may not be established). The occurrence of a glitch will be specifically described below with reference to FIG. 8.

[0114] FIG. 8 is a timing chart showing the first signal S1, the drive signal G1, the second signal S2, the drive signal G2, and the bus voltage VBUS when the slave node 2Ax transmits data.

[0115] As described above, a slew rate is applied to the drive signal G2 when it rises from a low level to a high level. If the low-level pulse width of the first signal S1 is the minimum width that satisfies the communication standard, then at time t41, while the drive signal G2 is rising to a high level, the drive signal G1 may fall to a low level, causing a momentary rise in the bus voltage VBUS, a so-called glitch (see the dashed line frame in the figure).

[0116] To address such problems, the occurrence of glitches can be suppressed by a communication device X according to a second embodiment of the present disclosure. The second embodiment of the communication device X will be described below. Note that, in the following, differences from the first embodiment will be described, and configurations similar to those in the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.

[0117] 9 is a block diagram showing a configuration of a communication device X according to a second embodiment of the present disclosure. As shown in FIG. 9, a waveform shaping circuit 15x according to the communication device X of the second embodiment includes a slave side drive control circuit 16x, a selector 21, a pulse width detection circuit 22, a selector 23, and control circuits 24 and 25.

[0118] The pulse width detection circuit 22 detects the pulse width WL of the bus voltage VBUS (=pulse width modulation signal PWM) and outputs a detection signal S4 according to the pulse width WL to the selector 23. More specifically, the pulse width detection circuit 22 detects whether the pulse width WL of the bus voltage VBUS is equal to or greater than a predetermined threshold value TH, and outputs a detection signal S4 reflecting the detection result.

[0119] The selector 23 receives the output of the control circuit 24 and the output of the control circuit 25, and selects one of the output of the control circuit 24 and the output of the control circuit 25 in accordance with the detection signal S4, and outputs the selected output to the selector 21.

[0120] The selector 21 receives the output of the selector 23 and the bus voltage VBUS, and selects either the output of the selector 23 or the bus voltage VBUS under predetermined conditions, and inputs it to the waveform shaping circuit 15x (more specifically, the slave side drive control circuit 16x).

[0121] Specifically, when the relationship of pulse width WL≧threshold value TH is established, the selector 23 selects the output of the control circuit 24 in response to the detection signal S4 and inputs it to the selector 21. When the output of the control circuit 24 is input to the slave side drive control circuit 16x by the selector 21, a relatively gentle slew rate is added to the rise / fall of the drive signal G2. The slew rate added to the bus voltage VBUS at this time is referred to as the first slew rate.

[0122] On the other hand, when the relationship of pulse width WL<threshold TH holds, the selector 23 selects the output of the control circuit 25 in response to the detection signal S4 and inputs it to the selector 21. When the output of the control circuit 25 is input to the slave-side drive control circuit 16x by the selector 21, a relatively steep slew rate (steeper than when the output of the control circuit 24 is input to the slave-side drive control circuit 16x) is added to the rise / fall of the drive signal G2. The slew rate added to the bus voltage VBUS at this time is referred to as the second slew rate.

[0123] 10 is a timing chart showing the first signal S1, the detection signal S4, the second signal S2, the drive signal G2, and the bus voltage VBUS during data transmission by the slave node 2Ax according to the second embodiment of the present disclosure. Referring to FIG. 10, at time t51, the first signal S1 falls to a low level. At time t52, the first signal S1 rises to a high level. At this time, the pulse width detection circuit 22 detects whether the pulse width WL is equal to or greater than a predetermined threshold value TH.

[0124] As shown in FIG. 10, when the pulse width WL is less than the threshold value TH, at time t53, the pulse width detection circuit 22 raises the detection signal S4 from a low level to a high level. After the first signal S1 falls to a low level at time t54, when the second signal S2 falls to a low level at time t55, the slave side drive control circuit 16x abruptly raises the drive signal G2. Specifically, upon receiving the detection signal S4, the selector 23 selects the output of the control circuit 25 and inputs it to the selector 21. The selector 21 selects the input control circuit 25 and inputs it to the slave side drive control circuit 16x. In response to this, the slave side drive control circuit 16x abruptly raises the drive signal G2. As a result, when the first signal falls to a low level at time t55, the slave side transistor T2 transitions to an on state before the above-mentioned glitch occurs. This makes it possible to suppress the occurrence of a glitch.

[0125] Here, the pulse width detection circuit 22 always detects the previous pulse width WL and outputs a detection signal S4 according to the detection result. If the pulse width WL is changed from less than the threshold value TH to equal to or greater than the threshold value TH, the pulse width detection circuit 22 detects the pulse width WL and drops the detection signal S4 to a low level before the falling edge timing of the first signal S1 immediately after the change arrives. Therefore, the drive signal G2 is given a relatively gentle slew rate and rises to a high level. In this way, the magnitude of the slew rate of the drive signal G2 is always changed according to the pulse width WL at the falling edge timing of the first signal S1 immediately before.

[0126] <Waveform shaper> The configuration of the waveform shaping circuit 15x will be described in more detail below. Fig. 11 is a block diagram showing an example of the waveform shaping circuit 15x. The waveform shaping circuit 15x includes current sources CS1 to CS4.

[0127] The current sources CS1 to CS3 are connected in parallel between the power supply terminal and the gate of the slave transistor T2 (=the application terminal of the drive signal G2), and generate on-currents IH1 to IH3 for switching the drive signal G2 to a high level (=the logic level when on), respectively. Note that the on-currents IH1 to IH3 may have the same current value or different current values.

[0128] The current source CS4 is connected between the gate of the slave transistor T2 (=the application terminal of the drive signal G2) and the ground terminal, and generates an off current IL for switching the drive signal G2 to a low level (=the logic level when off).

[0129] When the drive signal G2 is at high level, the communication circuit 14 turns on at least one of the current sources CS1 to CS3 and turns off the current source CS4. On the other hand, when the drive signal G2 is at low level, the communication circuit 14 turns off all of the current sources CS1 to CS3 and turns on the current source CS4.

[0130] In addition, the communication circuit 14 has a function of individually turning on / off each of the current sources CS1 to CS3 (and thus the on-currents IH1 to IH3) in response to the output of the pulse width detection circuit 22 when the drive signal G2 rises from a low level to a high level, in other words, a function of controlling the magnitude of the on-current IH flowing into the gate capacitance of the slave-side transistor T2.

[0131] For example, when the current source CS1 is turned on and the current sources CS2 and CS3 are turned off, IH=IH1. Also, when the current sources CS1 and CS2 are turned on and the current source CS3 is turned off, IH=IH1+IH2. Also, when all the current sources CS1 to CS3 are turned on, IH=IH1+IH2+IH3.

[0132] In addition, the smaller the on-current IH, the more gradually the drive signal G2 rises, so the current that flows when the slave transistor T2 turns on is limited and the bus voltage VBUS falls more gradually. Conversely, the larger the on-current IH, the more steeply the drive signal G2 rises, so the bus voltage VBUS rises more steeply.

[0133] Therefore, for example, when the pulse width WL of the pulse width modulation signal PWM is larger than the threshold value TH, it is possible to suppress EMI noise by reducing the on-current IH without turning on all of the current sources CS1 to CS3.

[0134] On the other hand, when the pulse width WL of the pulse width modulation signal PWM is smaller than the threshold value TH, all of the current sources CS1 to CS3 are turned on to cause a larger amount of the on-current IH to flow, thereby making it possible to improve the stability of communication.

[0135] <Other Modifications> In addition to the above-mentioned embodiment, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-mentioned embodiment, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0136] For example, in the above embodiment, an in-vehicle communication system conforming to the CXPI protocol is given as an example, but the application of the present invention is in no way limited to this, and it can be applied to any communication system that employs a similar operating principle to that described above, that is, a pulse width modulated signal is used as a transmission code between multiple nodes, and in the event of a collision between the transmission signals of each node, the node that has been transmitting a dominant level for a longer period of time will prevail in arbitration.

[0137] Moreover, the master transistor T1 and the slave transistor T2 have been described as NMOSFETs, but they may be npn-type bipolar transistors or N-channel IGBTs (insulated gate bipolar transistors).

[0138] <Additional Notes> The communication device (x) disclosed in the specification is a communication device (x) that uses a pulse width modulation signal (PWM) as a transmission code between a master node (1x) and a slave node (1Ax) connected to a communication line (3), and at least one of the master node (1x) and the slave node (1Ax) is configured to be switchable between a first state in which a feedback input of a bus voltage (VBUS) of the communication line (3) is received to control the slew rate of the bus voltage (VBUS) to a desired value, and a second state in which a predetermined control signal is received to control the slew rate of the bus voltage (VBUS) to a desired value (first configuration).

[0139] In the communication device (x) having the first configuration, the master node (1x) is configured to generate a master side transmission signal (S1) whose logical level is variable between a dominant level and a recessive level, and to be able to transmit the signal to the slave node (1Ax) via the communication line (3), and the slave node (1Ax) is configured to generate a slave side transmission signal (S2) whose logical level is variable between a dominant level and a recessive level, and to be able to transmit the signal to the master node (1x) via the communication line (3), and when the master side transmission signal (S1) and the slave side transmission signal (S2) collide on the communication line (3), It is preferable to configure the slave node (1Ax) to switch to the second state at a first timing when the logical level of the slave side transmission signal (S2) switches from a recessive level to a dominant level, and the master node (1x) to switch to the second state at a second timing when the logical level of the master side transmission signal (S1) switches while the slave node (1Ax) has the slave side transmission signal (S2) at the dominant level (second configuration).

[0140] Furthermore, in a communication device (x) having the second configuration, the master node (1x) may be configured to switch to the first state at a third timing when the logic level of the master side transmission signal (S1) switches while the slave node (1Ax) has the slave side transmission signal (S2) at a recessive level, and the slave node (1Ax) may be configured to switch to the first state at a fourth timing when the logic level of the slave side transmission signal (S2) switches from the dominant level to the recessive level (third configuration).

[0141] In addition, in a communication device (x) having the second or third configuration, the master node (1x) includes a master side transistor (T1) connected to the communication line (3) and a master side drive control circuit (12x) configured to control a first drive signal (G1) of the master side transistor (T1), and the slave node (1Ax) includes a slave side transistor (T2) connected to the communication line (3) and a slave side drive control circuit (16x) configured to control a second drive signal (G2) of the slave side transistor (T2), and the master node (1x) and the slave node (1Ax) may be configured to control the on / off state of the first transistor and the second transistor to change the bus voltage (VBUS) (fourth configuration).

[0142] Furthermore, in the communication device (x) described in any of the second to fourth configurations, the master node (1x) includes a detection circuit (19) configured to be able to detect whether the switching timing of the logic level of the incoming master side transmission signal (S1) is the second timing or the third timing based on the bus voltage (VBUS), and the master side drive control circuit (12x) is configured to control the first drive signal (G1) depending on the detection result of the detection circuit (19) (fifth configuration).

[0143] A communication device (x) described in any of the second to fifth configurations may be configured such that, in the second state, the slew rate of the bus voltage is controlled to a predetermined first slew rate or a second slew rate steeper than the first slew rate as a desired value, and the slave node (1Ax) is provided with a pulse width detection circuit (22) configured to be able to detect a pulse width from the timing at which the logical level of the master side transmission signal (S1) switches from a recessive level to a dominant level to the timing at which the logical level of the master side transmission signal (S1) next switches, and when, at the second timing, the pulse width is equal to or less than the interval between the second timing and the immediately preceding third timing, the slew rate of the bus voltage (VBUS) is switched to the second slew rate (sixth configuration).

[0144] A communication device (x) according to any one of the first to sixth configurations, which is compliant with the CXPI protocol (seventh configuration).

[0145] According to the communication device (x) of the first configuration, even if it is difficult to control the slew rate of the bus voltage (VBUS) to a desired value in the first state, the slew rate of the bus voltage (VBUS) can be controlled by switching to the second state. This makes it possible to suppress abrupt changes in the bus voltage (VBUS) and suppress the generation of EMI noise.

[0146] Furthermore, in the communication device (x) according to the second configuration, even if it is difficult to control the slew rate of the bus voltage (VBUS) to a desired value in the first state at the first timing and the second timing, the slew rate of the bus voltage (VBUS) can be controlled by switching to the second state. This makes it possible to more suitably suppress abrupt changes in the bus voltage (VBUS) and suppress the generation of EMI noise.

[0147] Furthermore, in the communication device (x) according to the third configuration, by switching to the first state at the third timing and the fourth timing, it becomes possible to more suitably control the slew rate of the bus voltage (VBUS) by feedback control.

[0148] Furthermore, according to the communication device (x) of the fourth configuration, the bus voltage (VBUS) can be controlled more suitably.

[0149] Furthermore, in the communication device (x) according to the fifth configuration, it becomes possible to more appropriately select the timing for performing the slew rate control of the bus voltage (VBUS).

[0150] Furthermore, in the communication device (x) according to the sixth configuration, even if the pulse width at the second timing is equal to or less than the interval between the second timing and the immediately preceding third timing, the bus voltage (VBUS) rises at the second slew rate, so that the bus voltage (VBUS) can be prevented from rising before the timing at which the logic level of the master side transmission signal (S1) switches arrives, thereby preventing the occurrence of glitches.

[0151] Furthermore, according to the communication device (x) of the seventh configuration, in the communication device (x) conforming to the CXPI protocol, it becomes possible to more suitably suppress the occurrence of EMI noise. [Explanation of symbols]

[0152] 1x, 1y Masternodes 2Ax, 2Ay, 2By slave nodes 3. Communication lines 4 CXPI Transceivers 5. Microcomputer 6 Transducers 7A CXPI Transceiver 7B CXPI Transceiver 8. Microcomputer 9 Receiving circuit 10. Communication Circuits 11x11,y waveform shaping circuit 12x, 12y Master side drive control circuit 13 Receiving circuit 14 Communication Circuits 15x, 15y waveform shaping circuit 16x, 16y slave side drive control circuit 17 Control circuit 18 Selector 19 Detection circuit 20 Control circuit 21 Selector 22 Pulse width detection circuit 23 Selector 24 Control circuit 25 Control circuit CLK Communication clock CS1~CS4 current source G1 drive signal G2 drive signal IH1~IH3 ON current IL off-state current N1 external terminal N2 external terminal P1 power end P2 power end PW Pulse width PWM Pulse Width Modulation Signal R1 terminating resistor R2 terminating resistor S1 1st signal S2 2nd signal S3 Current detection signal S4 detection signal T1 Master side transistor T2 Slave side transistor TH Threshold V1 First voltage V2 Second voltage V3 Third voltage VBUS bus voltage WL Pulse width X communication device Y Communication Equipment D1a Diode D1b Diode D2a Diode D2b Diode

Claims

1. A communication device using a pulse width modulation signal as a transmission code between a master node and a slave node connected to a communication line, At least one of the master node and the slave node, a first state in which a slew rate of the bus voltage of the communication line is controlled to a desired value in response to a feedback input of the bus voltage of the communication line; a second state in which a slew rate of the bus voltage is controlled to a desired value in response to an input of a predetermined control signal; A communication device configured to be switchable between the above and the above.

2. The master node is configured to generate a master side transmission signal that is variable between a dominant level and a recessive level, and to transmit the master side transmission signal to the slave node via the communication line; the slave node is configured to generate a slave-side transmission signal that is variable between a dominant level and a recessive level, and to transmit the signal to the master node via the communication line; When the master side transmission signal and the slave side transmission signal collide with each other on the communication line, one of the master side transmission signal and the slave side transmission signal which maintains a dominant level for a longer period of time is transmitted predominantly, 2. The communication device according to claim 1, wherein the slave node switches to the second state at a first timing when a logical level of the slave side transmission signal switches from a recessive level to a dominant level, and the master node switches to the second state at a second timing when a logical level of the master side transmission signal switches while the slave node has the slave side transmission signal at the dominant level.

3. 3. The communication device according to claim 2, wherein the master node switches to the first state at a third timing when the logical level of the master side transmission signal switches while the slave node has the slave side transmission signal at a recessive level, and the slave node switches to the first state at a fourth timing when the logical level of the slave side transmission signal switches from a dominant level to a recessive level.

4. The master node is A master side transistor connected to the communication line; a master-side drive control circuit configured to control a first drive signal of the master-side transistor; Equipped with The slave node is a slave side transistor connected to the communication line; a slave-side drive control circuit configured to control a second drive signal of the slave-side transistor; Equipped with 4. The communication device according to claim 3, wherein the master node and the slave node are configured to control an on / off state of the first transistor and the second transistor to vary the bus voltage.

5. the master node includes a detection circuit configured to be able to detect, based on the bus voltage, whether a switching timing of a logic level of the incoming master side transmission signal is the second timing or the third timing; The communication device according to claim 4 , wherein the master side drive control circuit controls the first drive signal in response to a detection result of the detection circuit.

6. In the second state, a slew rate of the bus voltage is controlled to a predetermined first slew rate or a second slew rate steeper than the first slew rate as a desired value; The slave node is a pulse width detection circuit configured to detect a pulse width from a timing when a logic level of the master side transmission signal switches from a recessive level to a dominant level to a timing when the logic level of the master side transmission signal switches next; 6. The communication device according to claim 2, wherein, at the second timing, when the pulse width is equal to or less than the interval between the second timing and the immediately preceding third timing, the slew rate of the bus voltage is switched to the second slew rate.

7. 2. The communication device of claim 1, which is compliant with the CXPI protocol.

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