Semiconductor element, and semiconductor device

Abstract

To improve adhesion between an electrode terminal and a sealing resin.SOLUTION: A semiconductor element 30 includes an element surface 31, an electrode 47 formed on the element surface 31, an insulation layer 48 formed on the element surface 31 to include an opening part 481 for exposing a portion of the electrode 47, and an electrode terminal 50 coming into contact with the electrode 47 through the opening part 481 and partially overlapping the insulation layer 48 when viewed from a Z direction. The electrode terminal 50 includes a terminal rear surface 50B facing the electrode 47, a terminal surface 50A facing the same direction as the element surface 31, and terminal side surfaces 50C facing a direction crossing a thickness direction, and the terminal side surfaces 50C include a recess 53.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor element and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor element and a wiring portion in which the semiconductor element is bonded to the wiring portion by flip-chip bonding, and a sealing resin that seals the semiconductor element and the wiring portion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-161149 A

[0004] [overview] However, in a semiconductor device, peeling of the sealing resin from the semiconductor element may occur, and therefore there is room for improvement regarding the semiconductor element.

[0005] A semiconductor element according to one embodiment of the present disclosure comprises an element front surface and an element back surface facing opposite each other in a thickness direction, an electrode formed on the element front surface, an insulating layer formed on the element front surface and including an opening exposing a portion of the electrode, and an electrode terminal contacting the electrode through the opening and partially overlapping the insulating layer when viewed from the thickness direction, wherein the electrode terminal includes a terminal back surface facing the electrode, a terminal front surface facing the same direction as the element front surface, and a terminal side surface facing a direction intersecting the thickness direction, and the terminal side surface includes a recess.

[0006] Moreover, a semiconductor device according to one aspect of the present disclosure includes a semiconductor element, a plurality of connection terminals electrically connected to the electrode terminals of the semiconductor element, and a sealing resin that seals the semiconductor element and the plurality of connection terminals. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a perspective view illustrating an example of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing the internal structure of the semiconductor device of FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an enlargement of the electrode terminal and its periphery in FIG. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing the electrode terminal and its peripheral members taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing the configuration of an electrode terminal of the semiconductor element shown in FIG. [Figure 7] 7A to 7C are schematic cross-sectional views illustrating an exemplary manufacturing process for the electrode terminal shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 14] FIG. 14 is a schematic plan view showing the mask and the opening shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view illustrating an example of the semiconductor device according to the second embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view showing an enlargement of the electrode terminal and its periphery in FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing an electrode terminal and its peripheral members taken along line F20-F20 in FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view showing the configuration of an electrode terminal of the semiconductor element shown in FIG. [Figure 22] 22A to 22C are schematic cross-sectional views illustrating an exemplary manufacturing process for the electrode terminal shown in FIG. [Diagram 23] FIG. 23 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Diagram 25] FIG. 25 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 27] FIG. 27 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 28] FIG. 28 is a schematic cross-sectional view showing a manufacturing process following FIG. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a manufacturing process following FIG. [Diagram 30] FIG. 30 is a schematic cross-sectional view showing an electrode terminal of a semiconductor element according to a modified example. [Diagram 31] FIG. 31 is a schematic cross-sectional view showing an electrode terminal and its peripheral members taken along line F31-F31 in FIG. [Diagram 32] FIG. 32 is a schematic cross-sectional view showing an electrode terminal of a semiconductor element according to a modified example. [Diagram 33] FIG. 33 is a schematic cross-sectional view showing an electrode terminal of a semiconductor element according to a modified example. [Diagram 34] FIG. 34 is a schematic cross-sectional view showing an electrode terminal of a semiconductor element according to a modified example. [Diagram 35] FIG. 35 is a schematic cross-sectional view showing an electrode terminal of a semiconductor element according to a modified example. [Diagram 36]FIG. 36 is a schematic cross-sectional view showing an electrode terminal of a semiconductor element according to a modified example. [Figure 37] FIG. 37 is a schematic cross-sectional view showing a semiconductor element according to a modified example. [Figure 38] FIG. 38 is a schematic cross-sectional view showing a semiconductor element according to a modified example. [Figure 39] FIG. 39 is a schematic cross-sectional view showing a semiconductor device according to a modified example.

[0008] [Detailed Description] Hereinafter, some embodiments of the semiconductor element and semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] (First embodiment) A semiconductor device 10 according to a first embodiment will be described with reference to FIGS. FIG. 1 shows a perspective structure of the semiconductor device 10 of the first embodiment. FIG. 2 shows a planar structure of the semiconductor device 10 of FIG. 1 with a sealing resin 80, which will be described later, removed. FIG. 3 shows a schematic cross-sectional structure of the semiconductor device 10 cut along the line F3-F3 in FIG. 2. FIG. 4 is a schematic cross-sectional view of a part of the semiconductor device 10 of FIG. 3, and is a schematic cross-sectional view of an electrode terminal 50 and its periphery. FIG. 5 is a schematic cross-sectional view of the electrode terminal and its peripheral members cut along the line F5-F5 in FIG. 4. FIG. 6 is a schematic cross-sectional view showing the configuration of the electrode terminal 50 before bonding to the semiconductor element 30 shown in FIG. 3. The term "planar view" used in the present disclosure refers to viewing the semiconductor device 10 in the Z direction of the mutually orthogonal XYZ axes shown in FIG. 1. Here, the X direction is an example of the "first direction", and the Y direction is an example of the "second direction".

[0011] In Fig. 2, the sealing resin 80 is indicated by a two-dot chain line to show the state of the semiconductor element 30 and the leads 20. Fig. 4 shows a state in which the element surface 31 of the semiconductor element 30 faces downward. Fig. 6 shows a state in which the element surface 31 of the semiconductor element 30 faces upward. Fig. 6 shows the structure of the electrode terminal 50 before being joined to the lead 20.

[0012] (Schematic configuration of semiconductor device) As shown in FIG. 1, the semiconductor device 10 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. The semiconductor device 10 has a device front surface 11 and a device back surface 12 facing opposite sides to each other in the Z direction, and four device side surfaces 13 to 16 connecting the device front surface 11 and the device back surface 12 in the Z direction. The device side surfaces 13 and 14 constitute both end surfaces of the semiconductor device 10 in the X direction, and the device side surfaces 15 and 16 constitute both end surfaces of the semiconductor device 10 in the Y direction. In the example shown in FIG. 1, the semiconductor device 10 is formed in a square shape in a plan view. The semiconductor device 10 is a surface mount type package format in which the device back surface 12 becomes a mounting surface when mounted on, for example, a circuit board (not shown). In the example shown in FIG. 1, the package format of the semiconductor device 10 is a QFN (Quad Flat Non-leaded Package) type. Note that the shape of the semiconductor device 10 in a plan view is not limited to a square shape and can be arbitrarily changed. The dimensions of the semiconductor device 10 in the X direction, Y direction, and Z direction can be arbitrarily changed. Furthermore, the package format of the semiconductor device 10 is not limited to QFN, but can be changed arbitrarily.

[0013] As shown in FIG. 2, the semiconductor device 10 includes a lead 20, a semiconductor element 30, and a sealing resin 80. The lead 20 corresponds to a "connection terminal". The semiconductor device 10 may include a plurality of leads 20. The lead 20 may include a first lead 21 and a second lead 22. In one example, the semiconductor device 10 includes a plurality of first leads 21 (three in FIG. 2). In one example, the semiconductor device 10 includes a plurality of second leads 22 (four in FIG. 2). The semiconductor element 30 is disposed on the plurality of first leads 21 and the plurality of second leads 22. The sealing resin 80 seals the plurality of first leads 21, the plurality of second leads 22, and the semiconductor element 30. The first lead 21 and the second lead 22 include portions exposed from the sealing resin 80. In FIG. 1, the portions of the first lead 21 and the second lead 22 exposed from the sealing resin 80 are marked with dots.

[0014] The first lead 21 and the second lead 22 are examples of the lead 20. The lead 20 may include only the first lead 21. The lead 20 may include only the second lead 22. The lead 20 may include the first lead 21 and the second lead 22, and leads other than the first and second leads 21 and 22.

[0015] As shown in FIG. 1, the sealing resin 80 constitutes the external structure of the semiconductor device 10. More specifically, the sealing resin 80 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. The sealing resin 80 has a sealing front surface 81 and a sealing back surface 82 facing opposite sides to each other in the Z direction, and four sealing side surfaces 83 to 86 connecting the sealing front surface 81 and the sealing back surface 82 in the Z direction. The sealing front surface 81 constitutes the device front surface 11, and the sealing back surface 82 constitutes the device back surface 12. The sealing side surface 83 constitutes the device side surface 13, the sealing side surface 84 constitutes the device side surface 14, the sealing side surface 85 constitutes the device side surface 15, and the sealing side surface 86 constitutes the device side surface 16. The sealing resin 80 also supports a plurality of first leads 21 and a plurality of second leads 22.

[0016] As shown in Figs. 2 and 3, the lead 20 is made of a conductive material. For example, a material containing one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au (gold), Ag (silver), Cu (copper), Al (aluminum), and W (tungsten) is used as the conductive material. The lead 20 is formed, for example, by subjecting a plate material made of a conductive material to an etching process. The method of forming the lead 20 can be changed as desired. In one example, the lead 20 may be formed by subjecting a plate material to a punching process, a bending process, or the like.

[0017] 3, the multiple leads 20 include a lead front surface 20S and a lead back surface 20R that face opposite to each other in the Z direction. The lead front surface 20S faces the same side as the sealing front surface 81, and the lead back surface 20R faces the same side as the sealing back surface 82. The lead front surface 20S is covered with the sealing resin 80. On the other hand, the lead back surface 20R is exposed from the sealing back surface 82.

[0018] The multiple first leads 21 are arranged spaced apart from each other in the X direction in a plan view. The multiple second leads 22 are formed in a band shape extending in the Y direction in a plan view. The multiple first leads 21 include portions exposed to the sealing side surfaces 85, 86. Of the multiple first leads 21, the first leads 21 arranged closer to the sealing side surface 84 include portions exposed from the sealing side surface 84.

[0019] The multiple second leads 22 are arranged closer to the sealing side surface 83 than the first leads 21. The multiple second leads 22 are arranged close to each other in the Y direction. The second leads 22 include portions exposed from the sealing back surface 82 of the sealing resin 80. Of the multiple second leads 22, the second leads 22 arranged closer to the sealing side surfaces 85, 86 include portions exposed from the sealing side surfaces 85, 86.

[0020] A conductive film may be formed on the surface of the lead 20 exposed from the sealing resin 80. The conductive film may be a plating film containing Sn (tin), for example. Note that the conductive film may be composed of a plurality of plating films stacked in the order of Ni (nickel), Pd (palladium), and Au (gold).

[0021] (Schematic configuration of semiconductor element) As shown in FIG. 2, the semiconductor element 30 is disposed in the center of the semiconductor device 10 in a plan view. The semiconductor element 30 is formed in a rectangular flat plate shape with the Z direction as the thickness direction. As shown in FIG. 2 and FIG. 3, the semiconductor element 30 includes an element front surface 31, an element back surface 32 facing the opposite side to the element front surface 31, and element side surfaces 33 to 36 connecting the element front surface 31 and the element back surface 32 in the Z direction. The element front surface 31 faces the same side as the sealing back surface 82, and the element back surface 32 faces the same side as the sealing surface 81. Therefore, the element front surface 31 faces the lead surface 20S of the lead 20 in the Z direction. The element side surface 33 faces the same side as the sealing side surface 83, the element side surface 34 faces the same side as the sealing side surface 84, the element side surface 35 faces the same side as the sealing side surface 85, and the element side surface 36 faces the same side as the sealing side surface 86.

[0022] As shown in FIG. 3, the semiconductor element 30 includes a semiconductor substrate 41, a semiconductor layer 42, and a plurality of electrode terminals 50. The semiconductor substrate 41 is formed in a rectangular plate shape with the thickness direction being in the Z direction. The semiconductor substrate 41 is formed of a material containing, for example, Si (silicon) or SiC (silicon carbide). The semiconductor substrate 41 includes a substrate front surface 41A and a substrate back surface 41B that face opposite each other in the Z direction. The substrate front surface 41A faces the same side as the element front surface 31, and the substrate back surface 41B faces the same side as the element back surface 32. In one example, the substrate back surface 41B constitutes the element back surface 32.

[0023] The semiconductor layer 42 is formed on the substrate surface 41A. The semiconductor layer 42 includes a plurality of types of p-type semiconductors and n-type semiconductors based on differences in the amount of elements to be doped. In one example, the semiconductor element 30 may include a first element region 42A and a second element region 42B formed in the semiconductor layer 42. In one example, the first element region 42A may include a switching element, and the second element region 42B may include various elements constituting a control circuit that controls the switching element. The semiconductor device 10 including such a semiconductor element 30 may be configured as a power conversion device such as a DC / DC converter or an AC / DC converter. The first element region 42A and the second element region 42B are examples of element regions included in the semiconductor layer 42. The semiconductor layer 42 may include one element region or three or more element regions.

[0024] The semiconductor element 30 is a flip-chip type LSI (Large Scale Integration). The semiconductor element 30 includes a plurality of electrode terminals 50 formed on an element surface 31. The semiconductor element 30 is mounted with the electrode terminals 50 facing the first lead 21 and the second lead 22.

[0025] (Details of the electrode terminal and its surroundings) 4 to 6, the semiconductor element 30 includes an interlayer insulating film 43, a wiring layer 44, and a passivation film 45. The interlayer insulating film 43 is formed on the semiconductor layer 42 shown in FIG. 3. The wiring layer 44 is formed on the interlayer insulating film 43. The wiring layer 44 may be an electrode of an element formed on the semiconductor layer 42. The wiring layer 44 may be electrically connected to an element formed on the semiconductor layer 42. The semiconductor element 30 may include a plurality of interlayer insulating films 43 and wiring layers 44.

[0026] The passivation film 45 is formed on the interlayer insulating film 43 so as to cover the wiring layer 44. In one example, the surface of the passivation film 45 opposite the wiring layer 44 constitutes the element surface 31 of the semiconductor element 30. In one example, the passivation film 45 is formed of a laminated structure of a SiO2 (silicon oxide) film and a SiN (silicon nitride) film.

[0027] The semiconductor element 30 includes an electrode 47 formed on an upper surface 45A of a passivation film 45. The upper surface 45A of the passivation film 45 constitutes the element surface 31. Therefore, it can be said that the electrode 47 is formed on the element surface 31.

[0028] The electrode 47 is electrically connected to the wiring layer 44 by a plurality of via wirings 46 that penetrate the passivation film 45. The via wirings 46 are made of a material containing at least one of Ti, TiN, Al, Cu, and W.

[0029] The electrode 47 is composed of a plurality of metal layers arranged on the passivation film 45 toward the opposite side to the wiring layer 44. In one example, the electrode 47 includes a first metal layer 471, a second metal layer 472, and a third metal layer 473. The first metal layer 471 is in contact with the upper surface 45A of the passivation film 45. The first metal layer 471 is formed of a material containing Cu, for example. The first metal layer 471 may be a seed layer. The seed layer is provided to form the second metal layer 472 and the third metal layer 473. The second metal layer 472 is laminated on the first metal layer 471. The second metal layer 472 is formed of a material containing Cu, for example. The third metal layer 473 is laminated on the second metal layer 472. The third metal layer 473 is formed of a material containing Pd and Ni, for example. In one example, the third metal layer 473 may be composed of a laminated film of a Ni layer formed on the upper surface of the second metal layer 472 and a Pd layer formed on the Ni layer. Note that the configuration and material of the electrode 47 can each be changed as desired.

[0030] The insulating layer 48 covers an upper surface 45A of the passivation film 45 and a part of the electrode 47. The insulating layer 48 is made of an insulating material such as a phenol resin or a polyimide resin.

[0031] The insulating layer 48 includes an opening 481 that exposes a part of the electrode 47. The opening 481 is formed in a circular shape in a plan view. In one example, as shown in Fig. 4, the opening 481 of the insulating layer 48 may be formed at a position that does not overlap with a region in which the multiple via wirings 46 connected to the electrode 47 are arranged in a plan view.

[0032] The electrode terminal 50 is electrically connected to the electrode 47 exposed from the opening 481 of the insulating layer 48 . The electrode terminal 50 protrudes in the Z direction from the upper surface 47A of the electrode 47. The electrode terminal 50 is formed in a columnar shape. In one example, the electrode terminal 50 is formed in a cylindrical shape.

[0033] The electrode terminal 50 includes a terminal back surface 50B facing the electrode 47, a terminal front surface 50A facing in the same direction as the element front surface 31, and a terminal side surface 50C facing in a direction intersecting the Z direction. The electrode terminal 50 includes a first portion 501 embedded in the opening 481 of the insulating layer 48, and a second portion 502 protruding from the insulating layer 48. The second portion 502 is formed larger than the first portion 501 in a plan view. The second portion 502 includes a portion that overlaps with the insulating layer 48 on the periphery of the opening 481 of the insulating layer 48. The electrode terminal 50 may include a recess 56 recessed from the terminal surface 50A toward the electrode 47 at the center of the terminal surface 50A.

[0034] The electrode terminal 50 includes a first conductive layer 51 and a second conductive layer 52 . The first conductive layer 51 contacts the electrode 47 exposed through the opening 481 of the insulating layer 48, and the insulating layer 48 on the periphery of the opening 481. In one example, the first conductive layer 51 is formed of a material containing Cu. The first conductive layer 51 may be composed of a laminated film of a Ni layer formed on the upper surfaces of the insulating layer 48 and the electrode 47, and a Pd layer formed on the Ni layer. The first conductive layer 51 may be a seed layer.

[0035] The second conductive layer 52 is formed on the first conductive layer 51. The second conductive layer 52 is in contact with the first conductive layer 51. In one example, the second conductive layer 52 is formed of a material containing Cu. The thickness of the second conductive layer 52 in the Z direction is greater than the thickness of the first conductive layer 51.

[0036] The second conductive layer 52 includes a back surface 52B facing the first conductive layer 51, a front surface 52A facing the same direction as the element front surface 31, and a side surface 52C facing a direction intersecting the Z direction. The back surface 52B of the second conductive layer 52 is in contact with the first conductive layer 51 and the insulating layer 48. The front surface 52A of the second conductive layer 52 constitutes a terminal front surface 50A of the electrode terminal 50.

[0037] As shown in FIG. 4 and FIG. 5, the terminal side surface 50C of the electrode terminal 50 includes a recess 53. The electrode terminal 50 includes a first conductive layer 51 and a second conductive layer 52. In one example, the first conductive layer 51 and the second conductive layer 52 can be said to include the recess 53. The side surface 52C of the second conductive layer 52 may include the recess 53. In one example, the side surface 52C of the second conductive layer 52 includes a plurality of recesses 53. As shown in FIG. 4, the recess 53 extends in the Z direction. The second conductive layer 52 can be said to include a plurality of vertical grooves extending in the Z direction. The electrode terminal 50 can be said to include a plurality of vertical grooves extending in the Z direction.

[0038] The recess 53 extends from the front surface 52A to the back surface 52B of the second conductive layer 52. As shown in FIG. 5, the recesses 53 are arranged in the circumferential direction along the side surface 52C of the second conductive layer 52. Each recess 53 may include two recess side surfaces 531 aligned in the circumferential direction of the electrode terminal 50. In plan view, each recess 53 may be formed such that the circumferential distance between the two recess side surfaces 531 gradually decreases toward the center of the electrode terminal 50. The shape of the recess 53 in plan view may be changed arbitrarily. For example, the recess 53 may be formed in a trapezoidal shape, an arc shape, or the like.

[0039] 5, the first conductive layer 51 of the electrode terminal 50 may include a protruding portion 511 that protrudes outward from the electrode terminal 50 further than the second conductive layer 52 of the electrode terminal 50. The protruding portion 511 of the first conductive layer 51 may include a recess 512 along the recess 53 of the side surface 52C of the second conductive layer 52. The first conductive layer 51 may include a side surface formed flush with the side surface 52C of the second conductive layer 52, and may not include the protruding portion 511.

[0040] (Joining layer) The semiconductor element 30 may include a bonding layer 60 formed on the electrode terminals 50. The bonding layer 60 is used for external connection. In the semiconductor element 30 of the first embodiment, the bonding layer 60 is used for bonding to the leads 20.

[0041] The bonding layer 60 may include a first layer 61 and a second layer 62. The first layer 61 is formed on the terminal surface 50A of the electrode terminal 50, and the first layer 61 of the bonding layer 60 is formed so as to cover the terminal surface 50A of the electrode terminal 50. The first layer 61 of the bonding layer 60 is in contact with the terminal surface 50A of the electrode terminal 50. In one example, the first layer 61 of the bonding layer 60 is formed of a material containing Ni and Fe. The first layer 61 may be a barrier layer.

[0042] The second layer 62 is formed on the first layer 61. It can be said that the bonding layer 60 has a laminated structure including the first layer 61 and the second layer 62 formed on the first layer 61. The second layer 62 is in contact with the first layer 61. The second layer 62 is formed of a solder containing Sn. In one example, the second layer 62 may contain SnAg. As shown in FIG. 6, before the electrode terminal 50 is bonded to the lead 20, the surface of the second layer 62 is formed in a hemispherical shape.

[0043] The first layer 61 of the bonding layer 60 is interposed between the second layer 62 of the bonding layer 60 and the second conductive layer 52 of the electrode terminal 50. The second layer 62 is formed of solder, and the second conductive layer 52 is formed of a material containing Cu. The first layer 61 of the bonding layer 60 may be formed of a metal material that suppresses a chemical reaction between the second layer 62 of the bonding layer 60 and the second conductive layer 52 of the electrode terminal 50. In one example, the second conductive layer 52 contains Cu and the second layer 62 contains Sn, while the first layer 61 may be formed of a material containing Ni.

[0044] (Explanation of the joint between the electrode terminal and the lead) As shown in FIG. 4, a plating layer 70 is formed on the lead surface 20S of the lead 20. The plating layer 70 is interposed between the bonding layer 60 and the lead 20. The plating layer 70 electrically connects the bonding layer 60 and the lead 20. The plating layer 70 may have a function of suppressing a chemical reaction between the lead 20 and the second layer 62 of the bonding layer 60. A metal material capable of suppressing a chemical reaction may be appropriately selected as a material constituting the plating layer 70. For example, Ni, Fe, etc. may be used as the metal material. In one example, the plating layer 70 is provided so as to cover a part of the lead surface 20S. The plating layer 70 may be provided so as to cover the entire lead surface 20S.

[0045] In one example, the plating layer 70 may include a first layer 71, a second layer 72, and a third layer 73. It can be said that the plating layer 70 has a laminated structure including the first to third layers 71 to 73. The first layer 71 is formed on the lead surface 20S of the lead 20. In one example, the first layer 71 may be formed of a material containing Ni. The second layer 72 is formed on the first layer 71. The second layer 72 may be formed of a material containing Pd, for example. The third layer 73 is formed on the second layer 72. The third layer 73 may be formed of a material containing Au, for example. The materials forming the first to third layers 71 to 73 may be changed arbitrarily. The layer configuration of the plating layer 70 may be changed as appropriate. Furthermore, the plating layer 70 may be omitted.

[0046] (Sealing resin) 2 and 3, the sealing resin 80 covers the semiconductor element 30. The sealing resin 80 is formed of an insulating material such as epoxy resin. The sealing resin 80 may be colored black or the like. The sealing resin 80 covers the entire semiconductor element 30 and parts of the first lead 21 and the second lead 22.

[0047] 4, the sealing resin 80 covers the upper surface 45A of the passivation film 45, the terminal side surface 50C of the electrode terminal 50, and the surface of the bonding layer 60. The sealing resin 80 is in contact with the terminal side surface 50C of the electrode terminal 50. The sealing resin 80 is also in contact with the surface of the bonding layer 60.

[0048] The terminal side surface 50C of the electrode terminal 50 includes a recess 53. Therefore, in the semiconductor device 10, the sealing resin 80 penetrates toward the center of the electrode terminal 50, compared to the terminal side surface of an electrode terminal that does not include the recess 53. Also, the contact area between the sealing resin 80 and the electrode terminal 50 is larger than that of an electrode terminal that does not include the recess 53.

[0049] (Method of manufacturing semiconductor device) Next, a description will be given of an example of a method for manufacturing the semiconductor element 30. Hereinafter, a description will be given of an example of a method for manufacturing the electrode terminal 50 of the first embodiment.

[0050] Figures 7 to 17 are cross-sectional views showing an example of a manufacturing process for the electrode terminal 50 shown in Figures 4 to 6. Figures 7 to 13 and Figures 15 to 17 are cross-sectional views corresponding to the cut surfaces of Figures 4 and 6. Figure 14 is a schematic plan view showing an opening 905A of a plating mask 905. For ease of understanding, in Figures 7 to 17, the same components as those in Figure 4 are denoted by the same reference numerals.

[0051] As shown in FIGS. 7 to 9, the method for manufacturing the semiconductor device 30 includes a step of forming an electrode 47. 7, a seed layer 901 is formed on the upper surface of the passivation film 45. In one example, the seed layer 901 is formed by a sputtering method. Note that the seed layer 901 may also be formed by an electroless plating method or the like.

[0052] Thereafter, a mask 902 including an opening 902A in a region where the electrode 47 is to be formed is formed on the upper surface 901A of the seed layer 901 by photolithography. In one example, the mask 902 is obtained by attaching a photosensitive sheet-like resist film onto the seed layer 901 and forming the opening 902A in the resist film by photolithography.

[0053] 8, a first metal layer 471 is formed by plating on the upper surface of the seed layer 901. Next, a second metal layer 472 is formed by plating on the upper surface of the first metal layer 471. Thereafter, the mask 902 is removed.

[0054] 9, the seed layer 901 exposed from the second metal layer 472 is removed by, for example, etching to form the first metal layer 471. In this manner, the electrode 47 is formed.

[0055] As shown in FIGS. 10 to 17, the method for manufacturing the semiconductor element 30 includes the steps of forming the electrode terminals 50 and the bonding layer 60. 10, an insulating layer 48 is formed on the passivation film 45 so as to cover an upper surface 45A of the passivation film 45 and the electrodes 47. The insulating layer 48 can be formed, for example, by using a photosensitive resin.

[0056] Next, the opening 481 is formed in the insulating layer 48. In one example, the opening 481 can be formed by performing photolithography and curing on the insulating layer 48. 11, a seed layer 903 is formed on an upper surface 48A of an insulating layer 48. In one example, the seed layer 903 is formed by a sputtering method. Note that the seed layer 903 may also be formed by an electroless plating method or the like.

[0057] 12 to 14, a plating mask 905 including an opening 905A is formed on the seed layer 903. In one example, the plating mask 905 is obtained by forming the opening 905A in a sheet-like photosensitive resist film by photolithography.

[0058] 12, a resist film 904 is formed. In one example, the resist film 904 is formed by attaching a film-like photosensitive resin material onto a seed layer 903. Next, a portion 904A formed by exposing the resist film 904 is removed by development to form a plating mask 905 including an opening 905A, as shown in FIG. 13. As shown in FIG. 14, the plating mask 905 includes an opening 905A formed by an inner surface 905B of the plating mask 905. The opening 905A is approximately circular in plan view. The inner surface 905B of the plating mask 905 includes a protrusion 905C protruding toward the center. The opening 905A exposes a portion of the seed layer 903.

[0059] As shown in Fig. 15, the second conductive layer 52 is formed. In one example, the second conductive layer 52 is formed on the exposed seed layer 903 by an electrolytic plating method using the seed layer 903 as a power supply path. The second conductive layer 52 is formed in the opening 905A of the plating mask 905 shown in Fig. 14. Therefore, the second conductive layer 52 includes a recess 53 on the side surface 52C.

[0060] Next, the bonding layer 60 is formed. The bonding layer 60 includes a first layer 61 and a second layer 62. First, the first layer 61 is formed on the second conductive layer 52. In one example, the first layer 61 is formed on the second conductive layer 52 in the opening 905A of the plating mask 905 by electrolytic plating using the seed layer 903 and the second conductive layer 52 as a power supply path. The first layer 61 is formed in the opening 905A of the plating mask 905 shown in FIG. 14. Therefore, the first layer 61 includes a recess 61D on the side surface 61C.

[0061] Next, the second layer 62 is formed on the first layer 61. In one example, the second layer 62 is formed on the first layer 61 in the opening 905A of the plating mask 905 by electrolytic plating using the seed layer 903, the second conductive layer 52, and the first layer 61 as a power supply path. Thereafter, the plating mask 905 is removed.

[0062] 16, the seed layer 903 exposed from the second conductive layer 52 is removed by, for example, etching to form the first conductive layer 51. The first conductive layer 51 is formed by removing the exposed seed layer 903. Therefore, the first conductive layer 51 is formed according to the shape of the second conductive layer 52 covering the seed layer 903. Therefore, the first conductive layer 51 includes a recess in the peripheral portion.

[0063] Furthermore, the etching for removing the exposed seed layer 903 causes side etching of a part of the second conductive layer 52. Therefore, the side surface 52C of the second conductive layer 52 is formed so as to be located inward from the side surface 61C of the first layer 61 of the bonding layer 60.

[0064] 17, for example, by a reflow process, the surface of the second layer 62 of the bonding layer 60 is formed into a spherical shape. Through the above steps, the electrode terminal 50 is formed. Note that the reflow process may be performed before the step of removing the exposed seed layer 903.

[0065] (action) Next, the operation of the semiconductor element 30 and the semiconductor device 10 of the first embodiment will be described. The semiconductor element 30 includes an element front surface 31 and an element back surface 32 facing opposite each other in the Z direction, an electrode 47 formed on the element front surface 31, an insulating layer 48 formed on the element front surface 31 and including an opening 481 exposing a portion of the electrode 47, and an electrode terminal 50 that contacts the electrode 47 through the opening 481 and partially overlaps the insulating layer 48 when viewed from the Z direction. The electrode terminal 50 includes a terminal back surface 50B facing the electrode 47, a terminal front surface 50A facing the same direction as the element front surface 31, and a terminal side surface 50C facing a direction intersecting the thickness direction, and the terminal side surface 50C includes a recess 53.

[0066] The semiconductor element 30 is sealed with the sealing resin 80 to constitute the semiconductor device 10. The terminal side surface 50C is in contact with the sealing resin 80. The terminal side surface 50C includes a recess 53. Therefore, in the semiconductor device 10, the sealing resin 80 penetrates toward the center of the electrode terminal 50, compared to the terminal side surface of an electrode terminal that does not include the recess 53. Therefore, the anchor effect of the sealing resin 80 on the terminal side surface 50C of the electrode terminal 50 can improve the adhesion of the sealing resin 80 to the terminal side surface 50C of the electrode terminal 50. Furthermore, peeling of the sealing resin 80 from the terminal side surface 50C of the electrode terminal 50 can be suppressed.

[0067] When the electrode terminals are formed in a rectangular column shape, stress remaining during the manufacturing process or temperature changes in the sealing resin 80 may concentrate at the corners. Stress concentration at the corners can cause cracks to occur in the sealing resin 80. In contrast, in the semiconductor device 10 of the first embodiment, the electrode terminals 50 of the semiconductor element 30 are formed in a cylindrical shape. This makes it possible to suppress stress concentration on the electrode terminals 50.

[0068] (effect) As described above, according to this embodiment, the following effects are achieved. (1-1) The semiconductor element 30 includes an element front surface 31 and an element back surface 32 facing opposite each other in the Z direction, an electrode 47 formed on the element front surface 31, an insulating layer 48 formed on the element front surface 31 and including an opening 481 exposing a part of the electrode 47, and an electrode terminal 50 that contacts the electrode 47 through the opening 481 and partially overlaps the insulating layer 48 when viewed from the Z direction. The electrode terminal 50 includes a terminal back surface 50B facing the electrode 47, a terminal front surface 50A facing the same direction as the element front surface 31, and a terminal side surface 50C facing a direction intersecting the thickness direction, and the terminal side surface 50C includes a recess 53. The recess 53 of the terminal side surface 50C can improve the adhesion of the sealing resin 80 to the terminal side surface 50C of the electrode terminal 50. Also, peeling of the sealing resin 80 from the terminal side surface 50C of the electrode terminal 50 can be suppressed.

[0069] (2-2) The electrode terminal 50 is formed in a cylindrical shape, which can reduce stress concentration in the sealing resin 80. Second embodiment A semiconductor device 110 according to a second embodiment will be described with reference to FIGS.

[0070] The semiconductor device 110 of the second embodiment is different from the semiconductor device 10 of the first embodiment in the configuration of the electrode terminals 150 of the semiconductor element 130. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and some or all of the description thereof will be omitted.

[0071] (Schematic configuration of semiconductor device) Fig. 18 is a schematic cross-sectional view of the semiconductor device 110 of the second embodiment. Fig. 19 is a schematic cross-sectional view of an enlarged portion of the semiconductor device 110, showing an electrode terminal 150 and its periphery. Fig. 20 is a schematic cross-sectional view showing the electrode terminal and its peripheral members cut along line F20-F20 in Fig. 19. Fig. 21 is a schematic cross-sectional view showing the configuration of the electrode terminal 150 before bonding to the semiconductor element 130 shown in Fig. 18.

[0072] 18, the semiconductor device 110 includes leads 20 (a first lead 21, a second lead 22), a semiconductor element 130, and a sealing resin 80. The semiconductor element 130 is disposed on the multiple leads 20. The semiconductor element 130 includes a semiconductor substrate 41, a semiconductor layer 42, and multiple electrode terminals 150. The sealing resin 80 seals the multiple leads 20 and the semiconductor element 130.

[0073] (Electrode terminal details) 19 to 21, the electrode terminal 150 protrudes in the Z direction from an upper surface 47A of the electrode 47. The electrode terminal 150 is formed in a columnar shape. In one example, the electrode terminal 150 is formed in a cylindrical shape.

[0074] The electrode terminal 150 includes a terminal back surface 150B facing the electrode 47, a terminal front surface 150A facing in the same direction as the element front surface 131, and a terminal side surface 150C facing in a direction intersecting the Z direction.

[0075] The electrode terminal 150 includes a first conductive layer 151 and a second conductive layer 152 . The first conductive layer 151 contacts the electrode 47 exposed through the opening 481 of the insulating layer 48, and the insulating layer 48 on the periphery of the opening 481. In one example, the first conductive layer 151 is formed of a material containing Cu. The first conductive layer 151 may be composed of a laminated film of a Ni layer formed on the upper surfaces of the insulating layer 48 and the electrode 47, and a Pd layer formed on the Ni layer. The first conductive layer 151 may be a seed layer.

[0076] The second conductive layer 152 is formed on the first conductive layer 151. The second conductive layer 152 is in contact with the first conductive layer 151. In one example, the second conductive layer 152 is formed of a material containing Cu. The thickness of the second conductive layer 152 in the Z direction is greater than the thickness of the first conductive layer 151.

[0077] The second conductive layer 152 includes a back surface 152B facing the first conductive layer 151, a front surface 152A facing the same direction as the element front surface 131, and a side surface 152C facing a direction intersecting the Z direction. The back surface 152B of the second conductive layer 152 contacts the first conductive layer 151 and the insulating layer 48. The front surface 152A of the second conductive layer 152 constitutes a terminal front surface 150A of the electrode terminal 150.

[0078] The terminal side surface 150C of the electrode terminal 150 includes a recess 153. The electrode terminal 150 includes a first conductive layer 151 and a second conductive layer 152. In one example, the side surface 152C of the second conductive layer 152 may include a recess 153. In one example, the side surface 152C of the second conductive layer 152 includes two recesses 153. The two recesses 153 are arranged side by side in the Z direction. The recesses 153 can be said to be peripheral recesses extending in the circumferential direction of the side surface 152C of the second conductive layer 152. The second conductive layer 152 can be said to include a peripheral recess extending in the circumferential direction of the side surface 152C. The electrode terminal 150 can be said to include a peripheral recess extending in the circumferential direction of the terminal side surface 150C.

[0079] 20 , the recesses 153 are formed over the entire circumferential direction of the second conductive layer 152. The multiple recesses 153 may include two recess side surfaces 1531, 1532 facing each other in the Z direction and a recess bottom surface 1533 facing the outside of the second conductive layer 152.

[0080] 21, the recesses 153 are formed so that the distance L1 between the two recesses 153 is equal to the width W1 of the recesses 153, which is the distance between the two recess side surfaces 1531, 1532 facing each other in the Z direction. Note that the distance L1 may be greater than the width W1, or the distance L1 may be smaller than the width W1.

[0081] 20, the first conductive layer 151 of the electrode terminal 150 may include a protruding portion 1511 that protrudes outward from the electrode terminal 150 further than the second conductive layer 152 of the electrode terminal 150. The protruding portion 1511 of the first conductive layer 151 is formed in a circular ring shape and is outward from the side surface 152C of the second conductive layer 152. The first conductive layer 151 may include a side surface formed flush with the side surface 152C of the second conductive layer 152, and may not include the protruding portion 1511.

[0082] (Method of manufacturing semiconductor device) Next, a description will be given of an example of a method for manufacturing the semiconductor element 130. Hereinafter, a description will be given of an example of a method for manufacturing the electrode terminal 150 of the second embodiment.

[0083] Figures 22 to 29 are cross-sectional views showing an example of a manufacturing process for the electrode terminal 150 shown in Figures 19 to 21. Figures 22 to 29 are cross-sectional views corresponding to the cut surfaces of Figures 19 and 21. For ease of understanding, in Figures 22 to 29, the same components as those in Figures 19 and 21 are denoted by the same reference numerals.

[0084] 22, a seed layer 903 is formed on an upper surface of an insulating layer 48. In the manufacturing process of a semiconductor element 130 of the second embodiment, the formation of an electrode 47 and an insulating layer 48, and the formation of a seed layer 903 (first conductive layer 151) are similar to those of the first embodiment, and therefore drawings and descriptions thereof will be omitted.

[0085] 23 to 25, a plating mask 920 including an opening 920A is formed on the seed layer 903. In one example, the plating mask 920 is obtained by forming the opening 920A in a photosensitive resist film by photolithography.

[0086] First, as shown in FIG. 23, a first mask layer 911 is formed. In one example, the first mask layer 911 is formed by attaching a film-like photosensitive resin material onto a seed layer 903. Then, the first mask layer 911 is exposed to light to form a removed portion 911A corresponding to the location where the second conductive layer 152 in FIG. 19 and FIG. 21 is to be formed. This removed portion 911A of the first mask layer 911 is a portion that is removed by development. In one example, the removed portion 911A of the first mask layer 911 is circular when viewed from the Z direction. Note that, 24, a second mask layer 912 is formed to cover the first mask layer 911. In one example, the second mask layer 912 is formed by attaching a film-like photosensitive resin material onto the first mask layer 911. Then, a removal portion 912A of the second mask layer 912, which corresponds to a location where the second conductive layer 152 is to be formed, is exposed to light. The removal portion 912A of the second mask layer 912 overlaps with the removal portion 911A of the first mask layer 911 in the Z direction, and is smaller than the removal portion 911A of the first mask layer 911 when viewed from the Z direction.

[0087] As shown in FIG. 25, a third mask layer 913, a fourth mask layer 914, and a fifth mask layer 915 are formed. The third, fourth, and fifth mask layers 913, 914, and 915 include removed portions 913A, 914A, and 914A. In one example, the third and fifth mask layers 913 and 915 include removed portions 913A and 915A having the same size as the removed portion 911A of the first mask layer 911 when viewed from the Z direction. The fourth mask layer 914 includes a removed portion 914A having the same size as the removed portion 912A of the second mask layer 912 when viewed from the Z direction. In one example, the second to fourth mask layers 912 to 914 may have the same film thickness. At least one mask layer among the second to fourth mask layers 912 to 914 may have a different film thickness from the other mask layers. In the first to fifth mask layers 911 to 915, the sizes of the removed portions 911A to 915A as viewed from the Z direction may be changed as appropriate.

[0088] As shown in FIG. 26, the first to fifth mask layers 911 to 915 are developed, and the removal portions 911A to 915A of the first to fifth mask layers 911 to 915 are removed all at once. This results in a plating mask 920 including a protruding portion 920C on an inner surface 920B of an opening 920A. The opening 920A of the plating mask 920 exposes a part of the seed layer 903. The opening 920A of the plating mask 920 is circular when viewed from the Z direction, and the protruding portion 920C extends over the entire inner surface 920B along the circumferential direction. The number of mask layers may be changed as appropriate.

[0089] The plating mask 920 may be formed by performing exposure and development on each of the first to fifth mask layers 911-915. For example, the first mask layer 911 is exposed to light to form a removed portion 911A, and the removed portion 911A is removed by development. Next, the second mask layer 912 is exposed to light to form a removed portion 912A, and the removed portion 912A is removed by development. Similarly, the third to fifth mask layers 913-915 are exposed to light and developed to remove the removed portions 913A-913A.

[0090] As shown in Fig. 27, the second conductive layer 152 is formed. In one example, the second conductive layer 152 is formed on the exposed seed layer 903 by an electrolytic plating method using the seed layer 903 as a power supply path. The second conductive layer 152 is formed in the opening 920A of the plating mask 920 shown in Fig. 26. Therefore, the second conductive layer 152 includes a recess 153 on a side surface 152C.

[0091] Next, the bonding layer 60 is formed. The bonding layer 60 includes a first layer 61 and a second layer 62. First, the first layer 61 is formed on the second conductive layer 152. In one example, the first layer 61 is formed on the second conductive layer 152 in the opening 920A of the plating mask 920 by an electrolytic plating method using the seed layer 903 and the second conductive layer 152 as a power supply path.

[0092] Next, the second layer 62 is formed on the first layer 61. In one example, the second layer 62 is formed on the first layer 61 in the opening 920A of the plating mask 920 by electrolytic plating using the seed layer 903, the second conductive layer 152, and the first layer 61 as a power supply path. Then, the plating mask 920 is removed.

[0093] 28, the seed layer 903 exposed from the second conductive layer 152 is removed by, for example, etching to form the first conductive layer 151. The first conductive layer 151 is formed by removing the exposed seed layer 903.

[0094] Furthermore, the etching for removing the exposed seed layer 903 causes side etching of a part of the second conductive layer 152. Therefore, the side surface 152C of the second conductive layer 152 is formed so as to be located inward from the side surface 61C of the first layer 61 of the bonding layer 60.

[0095] 29, the surface of the second layer 62 of the bonding layer 60 is formed into a spherical shape by, for example, a reflow process. Through the above steps, the electrode terminal 150 is formed. Note that the reflow process may be performed before the step of removing the exposed seed layer 903.

[0096] (action) Next, the operation of the semiconductor element 130 and the semiconductor device 110 of the second embodiment will be described. The semiconductor element 130 includes an element front surface 131 and an element back surface 132 facing opposite each other in the Z direction, an electrode 47 formed on the element front surface 131, an insulating layer 48 formed on the element front surface 131 and including an opening 481 exposing a portion of the electrode 47, and an electrode terminal 150 that contacts the electrode 47 through the opening 481 and partially overlaps the insulating layer 48 when viewed from the Z direction. The electrode terminal 150 includes a terminal back surface 150B facing the electrode 47, a terminal front surface 150A facing the same direction as the element front surface 131, and a terminal side surface 150C facing a direction intersecting the thickness direction, and the terminal side surface 150C includes a recess 153.

[0097] The semiconductor element 130 is sealed with the sealing resin 80 to constitute the semiconductor device 110. The terminal side surface 150C is in contact with the sealing resin 80. The terminal side surface 150C includes a recess 153. Therefore, in the semiconductor device 110, the sealing resin 80 penetrates toward the center of the electrode terminal 150, compared to the terminal side surface of the electrode terminal that does not include the recess 153. Therefore, the anchor effect of the sealing resin 80 on the terminal side surface 150C of the electrode terminal 150 can improve the adhesion of the sealing resin 80 to the terminal side surface 150C of the electrode terminal 150. Furthermore, peeling of the sealing resin 80 from the terminal side surface 150C of the electrode terminal 150 can be suppressed.

[0098] When the electrode terminals are formed in a rectangular column shape, stress remaining due to temperature changes in the sealing resin 80 or during the manufacturing process may concentrate at the corners. Stress concentration at the corners can cause cracks to occur in the sealing resin 80. In contrast, in the semiconductor device 110, the electrode terminals 150 of the semiconductor element 130 are formed in a cylindrical shape. Therefore, stress concentration at the electrode terminals 150 can be suppressed.

[0099] (effect) As described above, the semiconductor device 110 of the second embodiment provides the following advantages.

[0100] (2-1) The semiconductor element 130 includes an element front surface 131 and an element back surface 132 facing opposite directions in the Z direction, an electrode 47 formed on the element front surface 131, an insulating layer 48 formed on the element front surface 131 and including an opening 481 exposing a part of the electrode 47, and an electrode terminal 150 that contacts the electrode 47 through the opening 481 and partially overlaps the insulating layer 48 when viewed from the Z direction. The electrode terminal 150 includes a terminal back surface 150B facing the electrode 47, a terminal front surface 150A facing the same direction as the element front surface 131, and a terminal side surface 150C facing a direction intersecting the thickness direction, and the terminal side surface 150C includes a recess 153. The recess 153 of the terminal side surface 150C can improve the adhesion of the sealing resin 80 to the terminal side surface 150C of the electrode terminal 150. Also, peeling of the sealing resin 80 from the terminal side surface 150C of the electrode terminal 150 can be suppressed.

[0101] (Example of change) The above embodiment can be modified, for example, as follows. The above embodiment and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, the same reference numerals as in the above embodiment are used for the parts common to the above embodiment, and the description thereof will be omitted.

[0102] The shape of the electrode terminals 50, 150 may be changed as appropriate. The electrode terminal 50 of the semiconductor element 200 shown in FIG. 30 and FIG. 31 has a terminal side surface 50C that is a rough surface compared to the electrode terminal 50 of the first embodiment. The electrode terminal 50 includes a first conductive layer 51 and a second conductive layer 52. The second conductive layer 52 includes a back surface 52B that contacts the first conductive layer 51, a front surface 52A that contacts the first layer 61 of the bonding layer 60, and a side surface 52C that faces outward. The side surface 52C of the second conductive layer 52 is a rough surface having a surface roughness greater than that of the back surface 52B of the second conductive layer 52. As shown in FIG. 31, the surface of the first conductive layer 51 exposed from the second conductive layer 52 is a rough surface having a surface roughness greater than that of the contact surface that contacts the second conductive layer 52. This can further improve the adhesion between the terminal side surface of the electrode terminal 50 and the sealing resin 80. In addition, it is possible to suppress peeling of the sealing resin 80 from the terminal side surface 50C of the electrode terminal 50.

[0103] 30 and 31, the method for manufacturing the semiconductor element 200 includes a step of roughening the terminal side surface 50C of the electrode terminal 50. In the step of roughening the surface, the semiconductor element 200 is immersed in a roughening liquid. The roughening liquid may be a solution that reacts well with Cu constituting the electrode terminal 50 and does not react easily with metals other than Cu, such as Ti, Ni, Sn, and Ag. The roughening liquid may be an alkaline solution, for example.

[0104] The recess 53 of the electrode terminal 50 in the first embodiment may be modified as appropriate. 32, the recess 53 may include a recess 212 closer to the front surface 52A of the second conductive layer 52 and a recess 213 closer to the back surface 52B of the second conductive layer 52. The electrode terminal 211 thus formed can further improve the adhesion with the sealing resin 80.

[0105] 33, the recess 53 may be formed closer to the back surface 52B of the second conductive layer 52 and spaced apart from the front surface 52A. The electrode terminal 221 thus formed can further improve the adhesion with the sealing resin 80.

[0106] 34, the recesses 53 may be formed apart from the front surface 52A and the back surface 52B of the second conductive layer 52. The electrode terminals 231 thus formed can have improved adhesion to the sealing resin 80.

[0107] 35, the recess 53 may be formed closer to the front surface 52A of the second conductive layer 52 and spaced apart from the back surface 52B. The electrode terminal 241 thus formed can further improve the adhesion with the sealing resin 80.

[0108] The recess 153 of the electrode terminal 150 in the second embodiment may be modified as appropriate. 36 includes a plurality of recesses 253 arranged in the circumferential direction. The plurality of recesses 253 extend in the circumferential direction of the electrode terminal 251. That is, the electrode terminal 251 includes a plurality of recesses 253 formed in a terminal side surface 251C at intervals in the circumferential direction. A plurality of recesses 253 may be formed in the terminal side surface 251C of the electrode terminal 251 in the Z direction. The plurality of recesses 253 arranged in the Z direction may be arranged in the same position in the circumferential direction, or may be arranged in different positions in the circumferential direction. The electrode terminal 251 formed in this manner can further improve adhesion with the sealing resin 80.

[0109] In each embodiment, the configuration of the semiconductor elements 30 and 130 may be changed as appropriate. 37, a plurality of via wirings 46 electrically connecting the wiring layer 44 and the electrodes 47 are disposed at positions overlapping the electrode terminals 50 when viewed from the Z direction. That is, in this semiconductor element 260, a plurality of via wirings 46, the electrodes 47, the electrode terminals 50, and the bonding layer 60 are disposed side by side in the Z direction.

[0110] In each embodiment, the configuration of the electrode 47 may be changed as appropriate. An electrode 271 of a semiconductor element 270 shown in Fig. 38 includes a first metal layer 471 and a second metal layer 472, but does not include the third metal layer 473 shown in Fig. 4. The first metal layer 471 and the second metal layer 472 are formed of a material containing Cu.

[0111] In each embodiment, the configuration for supporting the semiconductor element 30 may be changed as appropriate. The semiconductor device 300 shown in FIG. 39 includes a substrate 310 instead of the leads 20 . The substrate 310 is formed in a rectangular flat plate shape with the thickness direction being in the Z direction. The substrate 310 includes a substrate front surface 311 and a substrate back surface 312 which face opposite each other in the Z direction. The substrate front surface 311 faces the same side as the device front surface 11, and the substrate back surface 312 faces the same side as the device back surface 12. The substrate back surface 312 constitutes the device back surface 12. The substrate 310 is formed of an insulating material. An example of the insulating material is epoxy resin.

[0112] The semiconductor device 10 includes a plurality of surface wirings 321 formed on the substrate surface 311. The surface wirings 321 correspond to "connection terminals." The surface wirings 321 are formed of a metal layer formed on the substrate surface 311. The metal layer is formed of a material including at least one of Cu, Al, Ag, Au, Ni, and Ti, for example. The plurality of surface wirings 321 are individually and electrically connected to a plurality of electrode terminals 50 of the semiconductor element 30. The plurality of surface wirings 321 may be provided corresponding to the electrode terminals 50.

[0113] The semiconductor device 10 includes a plurality of back surface wirings 322 formed on the back surface 312 of the substrate, and a plurality of through wirings 323 penetrating the substrate 310 in the Z direction. The back surface wirings 322 and the through wirings 323 are formed of a material including at least one of Cu, Al, Ag, Au, Ni, and Ti, for example. The plurality of back surface wirings 322 are electrically connected to the plurality of front surface wirings 321 via the plurality of through wirings 323. Therefore, the plurality of back surface wirings 322 are electrically connected to the electrode terminals 50 individually.

[0114] The sealing resin 80 is provided on the substrate surface 311 of the substrate 310. The sealing resin 80 seals the semiconductor element 30 and the plurality of surface wirings 321. According to the semiconductor device 10 shown in FIG. 39, the same effects as those of the first embodiment can be obtained. Note that, in the modified example shown in FIG. 39, the semiconductor element 130 of the second embodiment can also be applied. Also, in the modified example shown in FIG. 39, the sealing resin 80 may be omitted from the semiconductor device 10.

[0115] The terms "first", "second", "third", etc. in this disclosure are used merely to distinguish objects and do not rank the objects. The term "at least one" as used herein means "one or more" of the desired options. As an example, the term "at least one" as used herein means "only one option" or "both of two options" if the number of options is two. As another example, the term "at least one" as used herein means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0116] The term "on" as used in this disclosure includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which another layer is formed between the first layer and the second layer.

[0117] The Z-axis direction used in the present disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to the present disclosure (for example, the structure shown in FIG. 1) are not limited to the "up" and "down" of the Z-axis direction described in this specification being "up" and "down" of the vertical direction. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.

[0118] (Additional Note) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples for the purpose of aiding understanding, and the components described in each appendix should not be limited to the components indicated by the reference symbols.

[0119] (Appendix 1) An element front surface (31) and an element back surface (32) facing in opposite directions in a thickness direction; An electrode (47) formed on the element surface (31); an insulating layer (48) formed on the element surface (31) and including an opening (481) exposing a portion of the electrode (47); an electrode terminal (50, 150) that contacts the electrode (47) through the opening (481) and partially overlaps the insulating layer (48) when viewed from the thickness direction; Including, the electrode terminal (50, 150) includes a terminal back surface (50B, 150B) facing the electrode (47), a terminal front surface (50A, 150A) facing the same direction as the element front surface (31), and a terminal side surface (50C, 150C) facing a direction intersecting the thickness direction, The terminal side surface (50C, 150C) includes a recess (53, 153), Semiconductor element.

[0120] (Appendix 2) The semiconductor element according to claim 1, wherein the electrode terminal (50, 150) is cylindrical. (Appendix 3) 3. The semiconductor element according to claim 1, wherein the recess (53) includes a plurality of longitudinal grooves extending in the thickness direction.

[0121] (Appendix 4) 4. The semiconductor element according to claim 3, wherein the plurality of vertical grooves extend from the terminal front surface (50A) toward the terminal back surface (50B).

[0122] (Appendix 5) 4. The semiconductor element according to claim 3, wherein the plurality of vertical grooves extend from the terminal front surface (50A) to a midpoint on the terminal back surface (50B).

[0123] (Appendix 6) 4. The semiconductor element according to claim 3, wherein the plurality of vertical grooves are spaced apart from both the terminal front surface (50A) and the terminal back surface (50B).

[0124] (Appendix 7) 7. The semiconductor element according to claim 1, wherein the recess (153) includes a circumferential recess extending in a circumferential direction of the terminal side surface (150C).

[0125] (Appendix 8) 8. The semiconductor element according to claim 7, wherein the circumferential recess is formed over the entire electrode terminal.

[0126] (Appendix 9) The semiconductor element according to claim 7 or 8, wherein a plurality of the peripheral recesses are provided in the thickness direction.

[0127] (Appendix 10) 10. The semiconductor element according to claim 1, wherein the terminal side surface (50C) has a surface roughness greater than that of the terminal back surface (50B).

[0128] (Appendix 11) The electrode terminal (50, 150) includes a first conductive layer (51, 151) in contact with the electrode (47), and a second conductive layer (52, 152) formed on the first conductive layer (51, 151). 11. A semiconductor device according to any one of claims 1 to 10.

[0129] (Appendix 12) A bonding layer (60) provided on the terminal surface (50A), 12. A semiconductor device according to any one of claims 1 to 11.

[0130] (Appendix 13) In a plan view, the terminal side surface (50C) of the electrode terminal (50, 150) is located closer to the center of the electrode terminal (50) than the side surface of the bonding layer (60). 13. The semiconductor device of claim 12.

[0131] (Appendix 14) The bonding layer (60) is a first layer formed on the terminal surface (50A) of the electrode terminal (50, 150); a second layer formed on the first layer; Including, 14. The semiconductor device according to claim 12 or 13.

[0132] (Appendix 15) A semiconductor device according to any one of claims 1 to 14, a plurality of external connection terminals electrically connected to the electrode terminals (50) of the semiconductor element; a sealing resin that seals the semiconductor element and the plurality of external connection terminals; 13. A semiconductor device comprising:

[0133] (Appendix 16) forming an insulating layer (48) including an opening (481) exposing a portion of an electrode; forming a mask covering the insulating layer (48) and including a mask through-hole overlapping the opening (481) of the insulating layer (48), the mask through-hole including a protrusion; forming an electrode terminal (50) in the mask through hole; A method for manufacturing a semiconductor device, comprising:

[0134] (Appendix 17) The mask through-hole has a circular shape when viewed in the thickness direction of the mask. 17. A method for manufacturing a semiconductor device according to claim 16.

[0135] (Appendix 18) The protrusion extends in a thickness direction of the mask. 18. A method for manufacturing a semiconductor device according to claim 16 or 17.

[0136] (Appendix 19) the mask includes a plurality of mask layers; The mask through-hole includes the protrusion extending in a circumferential direction by the plurality of mask layers. 19. A method for manufacturing a semiconductor device according to any one of claims 16 to 18.

[0137] (Appendix 20) forming an insulating layer (48) including an opening (481) exposing a portion of an electrode; forming a mask including a plurality of mask layers covering the insulating layer (48), the mask including a mask through hole including a protrusion that overlaps with the opening (481) of the insulating layer (48) and extends in a circumferential direction through the plurality of mask layers; forming an electrode terminal (50) in the mask through hole; A method for manufacturing a semiconductor device, comprising:

[0138] (Appendix 21) forming a seed layer covering the electrode (47) and the insulating layer (48) exposed by the opening (481) of the insulating layer (48); the mask is formed on the seed layer; 21. A method for manufacturing a semiconductor device according to any one of claims 16 to 20.

[0139] (Appendix 22) The electrode terminal (50) includes a second conductive layer (52, 152) on the seed layer. 22. A method for manufacturing a semiconductor device according to claim 21.

[0140] (Appendix 23) removing the mask; and removing the seed layer exposed from the second conductive layer (52, 152) to form a first conductive layer (51, 151); Including, 23. A method for manufacturing a semiconductor device according to claim 22.

[0141] (Appendix 24) The side surface of the second conductive layer (52, 152) is rougher than the lower surface of the second conductive layer (52, 152). 24. A method for manufacturing a semiconductor device according to claim 22 or 23.

[0142] (Appendix 25) A bonding layer (60) formed on the electrode terminal (50), 25. A method for manufacturing a semiconductor device according to any one of claims 16 to 24.

[0143] (Appendix 26) The bonding layer (60) includes a first layer on the electrode terminal (50) and a second layer on the first layer. 26. A method for manufacturing a semiconductor device according to claim 25.

[0144] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0145] 10 Semiconductor device 11 Device surface 12 Back of the device 13~16 Side of device 20 Lead 20R Reed back 20S Reed Surface 21 1st Lead 22 2nd Lead 30 Semiconductor elements 31 Element surface 32 Back side of element 33~36 Side of element 41 Semiconductor Substrate 41A Board surface 41B Back side of board 42 Semiconductor layer 42A First element area 42B Second element region 43 Interlayer insulating film 44 Wiring layer 45 Passivation film 45A top 46 Via wiring 47 electrode 47A Top 471 1st metal layer 472 2nd metal layer 473 Third metal layer 48 Insulating Layer 481 Opening 50 electrode terminal 50A Terminal Surface 50B Terminal back side 50C terminal side 51 First conductive layer 52 Second conductive layer 52A surface 52B Back 52C side 53 Recess 56 Recess 60 Bonding layer 61 1st layer 61C Side 61D Recess 62 2nd layer 70 Plating layer 71 1st layer 72 2nd layer 73 3rd layer 80 Sealing resin 81 Sealing surface 82 Sealing back side 83~86 Sealing side 110 Semiconductor device 130 Semiconductor elements 131 Element surface 132 Back side of element 150 Electrode terminal 150A terminal surface 150B Terminal back side 150C terminal side 151 First conductive layer 152 Second conductive layer 152A surface 152B back side 152C side 153 Recess 200 Semiconductor elements 210 Semiconductor elements 211 Electrode terminal 212 Recess 213 Recess 220 Semiconductor Devices 221 Electrode terminal 230 Semiconductor Devices 231 Electrode terminal 240 Semiconductor Devices 241 Electrode terminal 250 Semiconductor Devices 251 Electrode terminal 251C terminal side 253 Recess 260 Semiconductor Devices 270 Semiconductor Devices 271 Electrode 300 Semiconductor device 310 Substrate 311 Substrate surface 312 Back side of board 321 Surface wiring 322 Back wiring 323 Through Wiring 501 Part 1 502 Part 2 511 Overhang 512 Recess 531 Recess side 901 Seed Layer 901A top side 902 Mask 902A Aperture 903 Seed Layer 904 Resist film 904A part 905 Mask 905A Aperture 905B Inner surface 905C Convex 911~915 1st~5th mask layers 911A~915A removed part 920 Mask 920A opening 920B Inner surface 920C convex part 1511 Overhang 1531 Recess side 1532 Recess side 1533 Bottom of recess L1 distance W1 width

Claims

1. a front surface and a back surface of the element facing opposite directions in a thickness direction; An electrode formed on the surface of the element; an insulating layer formed on a surface of the element and including an opening through which a portion of the electrode is exposed; an electrode terminal that contacts the electrode through the opening and that partially overlaps the insulating layer when viewed from the thickness direction; Including, the electrode terminal includes a terminal back surface facing the electrode, a terminal front surface facing the same direction as the element front surface, and a terminal side surface facing a direction intersecting the thickness direction, The terminal side surface includes a recess. Semiconductor element.

2. The semiconductor device according to claim 1 , wherein the electrode terminal is cylindrical.

3. The semiconductor device according to claim 1 , wherein the recess includes a plurality of longitudinal grooves extending in the thickness direction.

4. The semiconductor element according to claim 3 , wherein the plurality of longitudinal grooves extend from the front surface of the terminal toward the back surface of the terminal.

5. The semiconductor element according to claim 3 , wherein the plurality of vertical grooves extend from the front surface of the terminal to a midpoint on the rear surface of the terminal.

6. The semiconductor device according to claim 3 , wherein the plurality of longitudinal grooves are spaced apart from both the front surface of the terminals and the back surface of the terminals.

7. The semiconductor element according to claim 1 , wherein the recess includes a circumferential recess extending in a circumferential direction of the terminal side surface.

8. The semiconductor element according to claim 7 , wherein the peripheral recess is formed over the entire electrode terminal.

9. The semiconductor element according to claim 7 , wherein the peripheral recess is provided in a plurality of portions in the thickness direction.

10. The semiconductor element according to claim 1 , wherein the side surface of the terminal has a surface roughness greater than that of the rear surface of the terminal.

11. The electrode terminal includes a first conductive layer in contact with the electrode, and a second conductive layer formed on the first conductive layer. The semiconductor device according to claim 1 .

12. A bonding layer provided on the terminal surface, The semiconductor device according to claim 1 .

13. In a plan view, the terminal side surface of the electrode terminal is located closer to a center of the electrode terminal than a side surface of the bonding layer. The semiconductor device of claim 12.

14. The bonding layer is a first layer formed on the terminal surface of the electrode terminal; a second layer formed on the first layer; Including, The semiconductor device of claim 12.

15. A semiconductor element according to any one of claims 1 to 14; a plurality of external connection terminals electrically connected to the electrode terminals of the semiconductor element; a sealing resin that seals the semiconductor element and the plurality of external connection terminals; 13. A semiconductor device comprising:

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