Semiconductor device

Abstract

To provide a semiconductor device that enables a connection destination of a back gate contact region to be switched between a source region and a drain region.SOLUTION: A semiconductor device 1 includes: a semiconductor chip 2; an n-type first drain region 21 formed on a surface layer part of a fist main face 3; a p-type back gate region 16 formed away from the first drain region 21 on the surface layer part of the first main face 3; an n-type source region 23 formed inwardly away from circumferences 61 to 64 of the back gate region 16 on the surface layer part of the back gate region 16; a p-type back gate contact region 24 formed electrically away from the source region 23 on the surface layer part of the back gate region 16; and a gate electrode 20 opposite to a channel region 53 formed between the circumferences 61 to 64 of the back gate region 16 and the source region 23.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a p-type silicon substrate and an n-channel LDMOS formed on the silicon substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-017388 A

[0004] [overview] An embodiment of the present disclosure provides a semiconductor device in which a back gate contact region can be switched between a source region and a drain region.

[0005] One embodiment of the present disclosure provides a semiconductor device including a semiconductor chip having a first main surface and a second main surface opposite thereto, a first drain region of a first conductivity type formed in a surface portion of the first main surface, a backgate region of a second conductivity type formed in the surface portion of the first main surface and spaced apart from the first drain region, a source region of a first conductivity type formed in the surface portion of the backgate region and spaced inward from a periphery of the backgate region, a backgate contact region of a second conductivity type formed in the surface portion of the backgate region and electrically isolated from the source region, and a gate electrode facing a channel region formed in the backgate region between the periphery of the backgate region and the source region. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. [Diagram 2]FIG. 2 is a diagram showing an example of a planar layout of impurity diffusion regions in the LDMOS region. [Diagram 3] FIG. 3 is a diagram showing an example of a planar shape of a field insulating film in the LDMOS region. [Figure 4] FIG. 4 is an enlarged view of a portion surrounded by a dashed line IV in FIG. [Diagram 5] FIG. 5 is a diagram showing an example of a planar shape of a gate electrode in the LDMOS region. [Figure 6] FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG. [Figure 7] FIG. 7 is an enlarged view of a portion surrounded by a dashed line VII in FIG. [Figure 8] FIG. 8 is a circuit diagram of the semiconductor device. [Figure 9] FIG. 9 is a graph showing the relationship between the fourth width in the second direction of the back gate contact region and the on-breakdown voltage of the semiconductor device. [Figure 10A] FIG. 10A is a diagram showing a part of the manufacturing process of the semiconductor device, and corresponds to FIG. [Figure 10B] FIG. 10B is a diagram showing the next step of FIG. 10A. [Figure 10C] FIG. 10C is a diagram showing the next step of FIG. 10B. [Figure 10D] FIG. 10D is a diagram showing the next step of FIG. 10C. [Figure 10E] FIG. 10E is a diagram showing the next step of FIG. 10D. [Figure 10F] FIG. 10F is a diagram showing the next step of FIG. 10E. [Figure 10G] FIG. 10G shows the next step of FIG. 10F. [Figure 10H] FIG. 10H is a diagram showing the next step of FIG. 10G. [Figure 10I] FIG. 10I is a diagram showing the next step of FIG. 10H. [Figure 10J] FIG. 10J is a diagram showing the next step of FIG. 10I. [Figure 10K]FIG. 10K is a diagram showing the next step of FIG. 10J. [Figure 10L] FIG. 10L shows the next step of FIG. 10K. [Figure 10M] FIG. 10M is a diagram showing the next step of FIG. 10L. [Figure 10N] FIG. 10N is a diagram showing the next step of FIG. 10M. [Figure 11] FIG. 11 shows a first modification of the planar structure of the semiconductor device, and corresponds to the portion surrounded by the dashed dotted line XI in FIG. [Figure 12] FIG. 12 shows a second modification of the planar structure of the semiconductor device, and corresponds to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure, and corresponds to FIG.

[0007] [Detailed Description] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] FIG. 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present disclosure.

[0009] The semiconductor device 1 includes a semiconductor chip 2 formed in a rectangular parallelepiped shape. The semiconductor chip 2 forms the outer shape of the semiconductor device 1, and is, for example, a structure in which a single crystal semiconductor material is formed in a chip shape (rectangular parallelepiped shape). The semiconductor chip 2 is formed of a semiconductor material such as Si or SiC. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5 to 8 connecting the first main surface 3 and the second main surface 4. The first to fourth side surfaces 5 to 8 include a first side surface 5, a second side surface 6, a third side surface 7, and a fourth side surface 8. The third side surface 7 and the fourth side surface 8 extend in a first direction X and face a second direction Y perpendicular to the first direction X. The first side surface 5 and the second side surface 6 extend in the second direction Y and face the first direction X.

[0010] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") seen from the third direction Z (the normal direction of the first main surface 3 and the second main surface 4). The first main surface 3 may be referred to as a device surface on which functional devices are formed. The second main surface 4 may be referred to as a non-device surface on which no functional devices are formed. A plurality of device regions 9 are formed on the first main surface 3. The number and arrangement of the plurality of device regions 9 are arbitrary. The plurality of device regions 9 may include functional devices formed by utilizing a surface layer portion of the first main surface 3. The functional devices may include, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional devices may include, for example, a circuit network in which at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device are combined.

[0011] The semiconductor switching device may include, for example, at least one of a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET). The semiconductor rectifying device may include, for example, at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include, for example, at least one of a resistor, a capacitor, and an inductor.

[0012] FIG. 2 is a diagram showing an example of a planar layout of an impurity diffusion region in the LDMOS region 11. FIG. 3 is a diagram showing an example of a planar shape of a field insulating film 19 in the LDMOS region 11. FIG. 4 is an enlarged view of a portion surrounded by a dashed line IV in FIG. 3. FIG. 5 is a diagram showing an example of a planar shape of a gate electrode 20 in the LDMOS region 11. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 5. FIG. 7 is an enlarged view of a portion surrounded by a dashed line VII in FIG. 6. With reference to FIGS. 1 to 7, a structure of an LDMOS region 11 in which an LDMOSFET 10 (Lateral Double Diffused MOSFET) is formed as an example of a functional device among a plurality of device regions 9 will be specifically described.

[0013] The LDMOSFET 10 includes a first p-type region 12, a second p-type region 13, a buried region 14, a first well region (well region) 15, a back-gate region 16, a drift region 17, a second well region 18, a field insulating film 19, a gate electrode 20, a first drain region 21, a second drain region 22, a source region 23, a back-gate contact region 24, a first impurity region 25, a second impurity region 26, an interlayer insulating film 27, a drain wiring 28, a first drain contact 29, a second drain contact 30, a source wiring 31, a source contact 32, a back-gate wiring 33, and a back-gate contact 34.

[0014] 6 and 7, the first p-type region 12 is formed in a surface layer portion of the second main surface 4 of the semiconductor chip 2. The first p-type region 12 is a p-type (second conductivity type) impurity region. The first p-type region 12 is formed in the entire surface layer portion of the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5 to 8 (see FIG. 1).

[0015] The p-type impurity concentration of the first p-type region 12 is 1.0×10 13 cm -3 Above 1.0×10 15 cm -3The thickness of the first p-type region 12 may be 100 μm or more and 500 μm or less. The first p-type region 12 may be configured by laminating a p-type epitaxial layer (Si epitaxial layer) on a p-type semiconductor substrate formed on the second main surface 4 side. The first p-type region 12 may be a p-type semiconductor substrate. The first p-type region 12 has a relatively low impurity concentration, and therefore, - This may also be referred to as the area of ​​the mold.

[0016] 6 and 7, the second p-type region 13 is formed in a surface layer portion of the first main surface 3 of the semiconductor chip 2. The second p-type region 13 is a p-type impurity region. The second p-type region 13 is formed in the entire surface layer portion of the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5 to 8 (see FIG. 1). The thickness of the second p-type region 13 is, for example, smaller than the thickness of the first p-type region 12. The thickness of the second p-type region 13 may be 5 μm or more and 20 μm or less. In this embodiment, the second p-type region 13 may be a p-type epitaxial layer. The p-type impurity concentration of the second p-type region 13 may be the same as the p-type impurity concentration of the first p-type region 12. The p-type impurity concentration of the second p-type region 13 may be 1.0×10 13 cm -3 Above 1.0×10 15 cm -3 Since the second p-type region 13 has a relatively low impurity concentration, - This may also be referred to as the area of ​​the mold.

[0017] The second p-type region 13 is insulated and separated into a plurality of regions by an element isolation structure (not shown, for example, an element isolation well, DTI (Deep Trench Isolation), STI (Shallow Trench Isolation), etc.). The element isolation structure divides the semiconductor chip 2 into a plurality of device regions 9. FIGS. 2 to 7 show the second p-type region 13 that forms the LDMOS region 11, out of the plurality of separated second p-type regions 13.

[0018] 2, the second p-type region 13 includes a p-type inner region 13A and an annular p-type outer region 13B that surrounds the sides of the p-type inner region 13A and contacts the element isolation structure. A back gate region 16, a drift region 17, and the like are formed in the p-type inner region 13A.

[0019] 6 and 7, the buried region 14 is an n-type (first conductivity type) region (B / L layer) buried between the first p-type region 12 and the p-type inner region 13A. Specifically, the buried region 14 extends in a layered manner along the first main surface 3 so as to straddle the boundary between the first p-type region 12 and the p-type inner region 13A (i.e., the second p-type region 13). Although not shown, the buried region 14 is quadrangular in plan view. The buried region 14 is electrically connected to the first p-type region 12 and the second p-type region 13. The thickness of the buried region 14 may be 0.1 μm or more and 5 μm or less. The n-type impurity concentration of the buried region 14 is 1.0×10 16 cm -3 Above 1.0×10 20 cm -3 The n-type impurity concentration of the buried region 14 may be higher than the n-type impurity concentration of the drift region 17. The n-type impurity concentration of the buried region 14 may be the same as the n-type impurity concentration of the drift region 17.

[0020] 2, 6 and 7, the first well region 15 is an n-type impurity region formed in a surface layer portion of the second p-type region 13. The first well region 15 is formed in an annular shape in a plan view. With reference to FIG. 2, the first well region 15 may be formed in a rectangular annular shape extending long in the first direction X in a plan view. The first well region 15 overlaps the peripheral portion of the buried region 14 in a plan view. The bottom of the first well region 15 reaches the buried region 14. The depth of the first well region 15 is the same over the entire circumferential area. The peripheral portion of the buried region 14 contacts the first well region 15 from below over the entire circumferential area of ​​the first well region 15.

[0021] The n-type impurity concentration of the first well region 15 is 1.0×10 16cm -3 Above 1.0×10 20 cm -3 The n-type impurity concentration of the first well region 15 may be higher than the n-type impurity concentration of the drift region 17. The n-type impurity concentration of the first well region 15 may be the same as the n-type impurity concentration of the drift region 17.

[0022] 2, 6 and 7, the annular first well region 15 surrounds the sides of the p-type inner region 13A in the second p-type region 13. Since the bottom of the first well region 15 reaches the buried region 14, the p-type inner region 13A is surrounded in the first direction X, the second direction Y and the third direction Z by the n-type region including the buried region 14 and the first well region 15. As a result, the p-type inner region 13A is electrically isolated from the p-type outer region 13B and the first p-type region 12 by the n-type region including the buried region 14 and the first well region 15.

[0023] 6 and 7, the back-gate region 16 is a region in the LDMOS region 11 to which a back-gate voltage of the LDMOSFET 10 is applied. The back-gate region 16 is a p-type back-gate region, and is formed in a surface layer portion of the p-type inner region 13A. The depth of the bottom of the back-gate region 16 is shallower than the bottom of the first well region 15. The depth of the bottom of the back-gate region 16 is shallower than the bottom of the drift region 17.

[0024] 2, 3, and 6, the back gate region 16 is formed in an elliptical shape extending long in the first direction X in a plan view. The back gate region 16 has a first periphery 61 and a second periphery 62 extending linearly with a gap therebetween along the first direction X. The back gate region 16 has a third periphery 63 and a fourth periphery 64 connecting the first periphery 61 and the second periphery 62. The third periphery 63 and the fourth periphery 64 face each other in the first direction X. The third periphery 63 and the fourth periphery 64 are formed in an arc shape bulging outward in the first direction X.

[0025] 6 and 7, the back gate region 16 includes a low concentration portion (second portion) 36 formed in the peripheral portion of the back gate region 16. The low concentration portion 36 is formed over the entire circumferential area of ​​the back gate region 16. The low concentration portion 36 is formed in the peripheral portion of the back gate region 16 excluding the vicinity of the bottom. The low concentration portion 36 is formed in an elliptical ring shape along the peripheral area (first peripheral area 61 to fourth peripheral area 64) of the back gate region 16. The outer periphery of the low concentration portion 36 is in contact with the drift region 17 over the entire circumferential area of ​​the back gate region 16. The p-type impurity concentration of the back gate region 16 is, for example, 1.0×10 15 cm -3 Above 5.0×10 16 cm -3 The depth of the bottom of the low concentration portion 36 is the same as the bottom of the drift region 17 described next.

[0026] 6 and 7, the portion of the back gate region 16 excluding the low concentration portion 36 is a high concentration portion (first portion) 35. The p-type impurity concentration of the high concentration portion 35 is, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 It may be the following.

[0027] 6 and 7, drift region 17 is formed in a surface layer portion of p-type inner region 13A. Drift region 17 is an n-type drift region. The n-type impurity concentration of drift region 17 is, for example, 5.0×10 15 cm -3 Above 5.0×10 17 cm -3 or less. The depth of the bottom of the drift region 17 is shallower than the bottom of the first well region 15. The depth of the bottom of the drift region 17 is deeper than the bottom of the back gate region 16. The second width W2 of the drift region 17 is narrower than the first width W1 of the back gate region 16.

[0028] 2, drift region 17 surrounds back gate region 16 in plan view. Drift region 17 may be formed in an elliptical ring shape extending long in first direction X in plan view. An inner periphery 17A of drift region 17 contacts the periphery (first periphery 61 to fourth periphery 64) of back gate region 16 over the entire circumferential area.

[0029] 6 and 7, second well region 18 is a p-type impurity region formed in a surface layer portion of second p-type region 13. The p-type impurity concentration of second well region 18 is, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 The p-type impurity concentration of the second well region 18 may be equal to or lower than the p-type impurity concentration of the high concentration portion 35 of the second well region 18. The p-type impurity concentration of the second well region 18 may be higher than the p-type impurity concentration of the high concentration portion 35. The p-type impurity concentration of the second well region 18 may be lower than the p-type impurity concentration of the high concentration portion 35.

[0030] 2, the second well region 18 may be formed in a rectangular ring shape extending long in the first direction X in a plan view. The second well region 18 surrounds the drift region 17 in a plan view. The second well region 18 is formed with a gap from the drift region 17 in both the first direction X and the second direction Y in a plan view. The second well region 18 is surrounded by the first well region 15 in a plan view. The second well region 18 is formed with a gap from the first well region 15 in both the first direction X and the second direction Y in a plan view. Although not shown, the second well region 18 may be formed in an elliptical ring shape extending long in the first direction X in a plan view.

[0031] 2 and 3, the field insulating film 19 is formed on the first main surface 3 of the semiconductor chip 2. The field insulating film 19 covers the first main surface 3. For clarity, the field insulating film 19 is shown hatched in FIG. 3. The non-hatched regions in FIG. 3 are regions not covered with the field insulating film 19. The field insulating film 19 may be, for example, a LOCOS oxide film formed by selectively oxidizing the surface (first main surface 3) of the second p-type region 13.

[0032] 3, the field insulating film 19 has a first opening 41, a second opening 42, a third opening 43, and a fourth opening 44. The first opening 41 is formed in an elliptical shape extending long in the first direction X in a plan view. The first opening 41 exposes a part of the drift region 17 (first drain region 21). The second opening 42 is formed in an elliptical shape extending long in the first direction X in a plan view. The second opening 42 exposes a part of the first well region 15 (second drain region 22).

[0033] 3, the third opening 43 is formed in an elliptical shape. The third opening 43 exposes a part of the back gate region 16 (the back gate contact region 24). The fourth opening 44 extends long in the first direction X in a plan view and is formed in an elliptical ring shape surrounding the periphery of the third opening 43 in a plan view. The fourth opening 44 exposes the back gate region 16 and the drift region 17. The opening width of the elliptical ring-shaped fourth opening 44 is wider than the opening width of the elliptical third opening 43.

[0034] 3, the first opening 41 may be formed as a pair to sandwich the third opening 43 and the fourth opening 44 in the second direction Y. The second opening 42 may be formed as a pair to sandwich the first opening 41, the third opening 43, and the fourth opening 44 in the second direction Y. The first opening 41, the second opening 42, and the third opening 43 may be formed in a quadrangle shape extending long in the first direction X in a plan view.

[0035] 6 and 7, the first drain region 21 is formed in a surface layer portion of the drift region 17. The first drain region 21 may have a higher n-type impurity concentration than the drift region 17. The n-type impurity concentration of the first drain region 21 is, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 It may be the following.

[0036] 4, the first drain region 21 is exposed from the field insulating film 19 at the first opening 41. The first drain region 21 has a first side portion 21A and a second side portion 21B extending at an interval along the first direction X. The first drain region 21 has a third side portion 21C and a fourth side portion 21D (see FIG. 3) connecting the first side portion 21A and the second side portion 21B. The third side portion 21C and the fourth side portion 21D are formed in an arc shape that bulges outward in the first direction X. Any of the first side portion 21A to the fourth side portion 21D may be disposed inside the outer periphery of the drift region 17 in a plan view.

[0037] 6 and 7, second drain region 22 is formed in a surface layer portion of first well region 15. Second drain region 22 may have a higher n-type impurity concentration than first well region 15. The n-type impurity concentration of second drain region 22 is, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 It may be the following.

[0038] 4, the second drain region 22 is exposed from the field insulating film 19 at the second opening 42. The second drain region 22 has a first side portion 22A and a second side portion 22B extending at an interval along the first direction X. The second drain region 22 has a third side portion 22C and a fourth side portion 22D (see FIG. 3) connecting the first side portion 22A and the second side portion 22B. The third side portion 22C and the fourth side portion 22D are formed in an arc shape that bulges outward in the first direction X. Any of the first side portion 22A to the fourth side portion 22D may be disposed inside the outer periphery of the first well region 15 in a plan view.

[0039] Referring to FIG. 5, a gate electrode 20 is formed on the first main surface 3 of the semiconductor chip 2. For clarity, the gate electrode 20 is shown by hatching in FIG. 5. The gate electrode 20 may include a conductive material such as polysilicon or aluminum. The gate electrode 20 is formed in a ring shape in a plan view. The gate electrode 20 may have a pair of first portions 51 facing each other in the second direction Y and a second portion 52 connecting the pair of first portions 51. In this embodiment, the first portions 51 are formed in linear shapes extending parallel to each other along the first direction X, and the second portions 52 are formed in arc shapes bulging outward in the first direction X. An opening 50 is formed in the center of the gate electrode 20 partitioned by the pair of first portions 51 and the pair of second portions 52. The opening 50 is formed in an elliptical shape extending along the first direction X in a plan view. The opening 50 exposes a part of the back gate region 16. Specifically, the opening 50 integrally exposes the source region 23 and the back-gate contact region 24 .

[0040] 7, the region of the back gate region 16 that the gate electrode 20 faces is the channel region 53 of the LDMOSFET 10. The formation of a channel in the channel region 53 is controlled by the gate electrode 20. The thickness of the gate electrode 20 may be, for example, not less than 0.1 μm and not more than 0.4 μm. When the gate electrode 20 forms a channel in the back gate region 16, the gate electrode 20 controls a threshold voltage (V TH) is provided.

[0041] 7, a gate insulating film 54 is formed between the gate electrode 20 and the first main surface 3. The gate insulating film 54 may be, for example, a silicon oxide (SiO2) film formed by thermally oxidizing the first main surface 3. The thickness of the gate insulating film 54 may be, for example, not less than 0.2 nm and not more than 100 nm.

[0042] 7, gate electrode 20 may integrally include an annular control portion 55 on the opening 50 side (inner side) and an annular field plate portion 56 outside control portion 55. Control portion 55 of gate electrode 20 covers back gate region 16 (channel region 53) and drift region 17 via gate insulating film 54 in this order from the inner side to the outer side. Field plate portion 56 of gate electrode 20 is formed on field insulating film 19 above drift region 17.

[0043] 7, a sidewall structure 57 is formed on the side of the gate electrode 20. The sidewall structure 57 is formed on both the inner side (the side of the opening 50) and the outer side of the gate electrode 20.

[0044] 7, a silicide layer 60 is formed on the first main surface 3 except for the portion where the gate insulating film 54 is formed. Therefore, the silicide layer 60 may be a compound containing silicon (Si) and a transition metal such as titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt), or tungsten (W).

[0045] 7, the source region 23 and the back gate contact region 24 are formed in a surface layer portion of the back gate region 16. The source region 23 has a strip shape extending along the first direction X. The source region 23 is an n-type impurity region. The n-type impurity concentration of the source region 23 is, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3or less. The source region 23 may have a higher n-type impurity concentration than the drift region 17. The source region 23 includes a pair of source regions 23 that sandwich the back gate contact region 24 in the second direction Y.

[0046] 4, the source region 23 has a first side portion 23A and a second side portion 23B extending at an interval along the first direction X. The source region 23 has a third side portion 23C and a fourth side portion 23D (see FIG. 3) connecting the first side portion 23A and the second side portion 23B. The third side portion 23C and the fourth side portion 23D are formed in an arc shape that bulges outward in the first direction X. The first side portion 23A to the fourth side portion 23D are all disposed inward from the periphery (first periphery 61 to fourth periphery 64) of the back gate region 16 in a plan view. That is, the source region 23 is formed in a surface layer portion of the back gate region 16, away from the periphery (first periphery 61 to fourth periphery 64) of the back gate region 16 on the inner side.

[0047] A third width W3 in the second direction Y of each source region 23 is 0.8 μm or more and 1.0 μm or less. The third width W3 may be constant over the entire area in the first direction X. Both ends of the pair of source regions 23 may be aligned in the first direction X. Each source region 23 may be formed in a rectangular shape extending elongatedly in the first direction X in a plan view.

[0048] 4, the back-gate contact region 24 is exposed from the field insulating film 19 at the third opening 43. The back-gate contact region 24 has a strip shape extending along the first direction X. The back-gate contact region 24 is formed adjacent to the source region 23. The back-gate contact region 24 is a p-type impurity region. The back-gate contact region 24 may have a higher p-type impurity concentration than the back-gate region 16. The p-type impurity concentration of the back-gate contact region 24 is, for example, 1.0×10 19 cm -3 Above 2.0×10 20 cm -3 It may be the following.

[0049] Referring to FIG. 4, the back gate contact region 24 has a first side portion 24A and a second side portion 24B that extend at intervals along the first direction X. The back gate contact region 24 has a third side portion 24C and a fourth side portion 24D (see FIG. 3) that connect the first side portion 24A and the second side portion 24B. The third side portion 24C and the fourth side portion 24D are formed in an arcuate shape that bulges outward in the first direction X. The first side portion 24A to the fourth side portion 24D are all disposed inside from the peripheries (the first periphery 61 to the fourth periphery 64) of the back gate region 16 in a plan view. That is, the back gate contact region 24 is formed inside and away from the periphery (the first periphery 61 to the fourth periphery 64) of the back gate contact region 24 in the surface layer portion of the back gate region 16.

[0050] Referring to FIG. 7, the fourth width W4 of the back gate contact region 24 in the second direction Y is 0.6 μm or more and 0.8 μm or less. The fourth width W4 is narrower than the third width W3 (W4 < W3). The fourth width W4 may be the same as or wider than the third width W3 (W4 ≧ W3). The fourth width W4 may be constant throughout the first direction X. The back gate contact region 24 may be formed in a rectangular shape that extends long in the first direction X in a plan view.

[0051] Referring to FIGS. 4 and 7, the back gate contact region 24 and the source region 23 are electrically separated by the field insulating film 19 in the surface layer portion of the back gate region 16. The back gate contact region 24 and the source region 23 are adjacent to each other with an interval in the second direction Y. Referring to FIG. 4, the first interval W in the second direction Y between the back gate contact region 24 and the source region 23 11 is 0.8 μm or more and 1.0 μm or less. The first interval W 11 is wider than the fourth width W4 (W 11 > W4). The first interval W 11 may be the same as or narrower than the fourth width W4 (W 11 ≦ W4).

[0052] 2 and 7, the first impurity region 25 is a p-type impurity region. The first impurity region 25 is formed on the second main surface 4 side with respect to the back gate region 16. The first impurity region 25 overlaps the back gate region 16 in a plan view. As shown in FIG. 7, the first impurity region 25 may be in contact with the back gate region 16. Although not shown, the first impurity region 25 may be separated from the back gate region 16 in the depth direction (so as to approach the second main surface 4 side).

[0053] The p-type impurity concentration of the first impurity region 25 is, for example, 1.0×10 15 cm -3 Above 5.0×10 16 cm -3 The p-type impurity concentration of the first impurity region 25 may be equal to or lower than the p-type impurity concentration of the high concentration portion 35 of the back gate region 16. The p-type impurity concentration of the first impurity region 25 may be lower than the p-type impurity concentration of the high concentration portion 35. The p-type impurity concentration of the first impurity region 25 may be higher than the p-type impurity concentration of the high concentration portion 35.

[0054] 2 and 7, the first impurity region 25 is formed in an elliptical shape extending long in the first direction X in a plan view. The first impurity region 25 has a first periphery 71 and a second periphery 72 extending linearly with a gap therebetween along the first direction X. The first impurity region 25 has a third periphery 73 and a fourth periphery 74 connecting the first periphery 71 and the second periphery 72. The third periphery 73 and the fourth periphery 74 face each other in the first direction X. The third periphery 73 and the fourth periphery 74 are formed in an arc shape expanding outward in the first direction X. The first periphery 71, the second periphery 72, the third periphery 73, and the fourth periphery 74 of the first impurity region 25 are spaced inward from the first periphery 61, the second periphery 62, the third periphery 63, and the fourth periphery 64 of the back gate region 16, respectively.

[0055] 2 and 7, the first impurity region 25 is not formed in a region facing the gate electrode 20 in the depth direction (third direction Z). That is, the first impurity region 25 is not formed in a region facing the channel region 53 in the depth direction (third direction Z).

[0056] 7, the depth of the bottom of the first impurity region 25 is shallower than the bottom of the first well region 15. The first impurity region 25 is in contact with the high concentration portion 35 of the back gate region 16. The first impurity region 25 is not in contact with the low concentration portion 36 of the back gate region 16.

[0057] 7, the second impurity region 26 is a p-type region. The second impurity region 26 is formed on the second main surface 4 side with respect to the second well region 18. Although not shown, the second impurity region 26 overlaps with the second well region 18 in a plan view. Although not shown, the second impurity region 26 has a quadrangular ring shape. The second impurity region 26 may be in contact with the second well region 18. Although not shown, the second impurity region 26 may be formed away from the second well region 18 in the depth direction (so as to approach the second main surface 4 side).

[0058] The p-type impurity concentration of the second impurity region 26 is, for example, 1.0×10 15 cm -3 Above 5.0×10 16 cm -3 or less. The p-type impurity concentration of second impurity region 26 is the same as the p-type impurity concentration of second well region 18. The depth of the bottom of second impurity region 26 is the same as the bottom of first impurity region 25. The inner circumferential edge of second impurity region 26 is spaced outward from the inner circumferential edge of second well region 18. The outer circumferential edge of second impurity region 26 is spaced inward from the outer circumferential edge of second well region 18.

[0059] 6, the second impurity region 26 is formed to surround the sides of the first impurity region 25. In other words, the second impurity region 26 faces the first impurity region 25 with an interval therebetween in the first direction X and the second direction Y.

[0060] 6 and 7, the interlayer insulating film 27 is formed on the first main surface 3 of the semiconductor chip 2. The interlayer insulating film 27 covers the gate electrode 20. The interlayer insulating film 27 is formed of, for example, silicon oxide (SiO2), silicon nitride (SiN2), or the like. In this embodiment, the interlayer insulating film 27 is formed of a single layer of silicon oxide, but may be formed of a plurality of interlayer insulating films 27.

[0061] 7, the drain wiring 28 is formed on the interlayer insulating film 27. The drain wiring 28 is electrically connected to the first drain region 21 and the second drain region 22 via a first drain contact 29 and a second drain contact 30, respectively. With reference to FIGS. 4 and 7, the first drain contact 29 is formed penetrating the interlayer insulating film 27 at a position overlapping the first drain region 21 in a plan view. More specifically, the first drain contact 29 is electrically connected to the first drain region 21 via a silicide layer 60. The first drain contact 29 may include a plurality of first drain contacts 29 arranged along the first direction X. Although not shown, the first drain contact 29 may be one long first drain contact 29 along the first direction X.

[0062] 4 and 7, the second drain contact 30 is formed penetrating the interlayer insulating film 27 at a position overlapping the second drain region 22 in a plan view. More specifically, the second drain contact 30 is electrically connected to the second drain region 22 via a silicide layer 60. The second drain contact 30 may include a plurality of second drain contacts 30 arranged along the first direction X. Although not shown, there may be one second drain contact 30 long along the first direction X.

[0063] 7, the source wiring 31 is formed on the interlayer insulating film 27. The source wiring 31 is electrically connected to the source region 23 via a source contact 32. With reference to FIGS. 4 and 7, the source contact 32 is formed penetrating the interlayer insulating film 27 at a position overlapping the source region 23 in a plan view. More specifically, the source contact 32 is electrically connected to the source region 23 via a silicide layer 60. The source contact 32 includes a plurality of source contacts 32 arranged along the first direction X.

[0064] 7, the back gate wiring 33 is formed on the interlayer insulating film 27. The back gate wiring 33 is electrically connected to the back gate contact region 24 via a back gate contact 34. With reference to FIGS. 4 and 7, the back gate contact 34 is formed penetrating the interlayer insulating film 27 at a position overlapping the back gate contact region 24 in a plan view. More specifically, the back gate contact 34 is electrically connected to the back gate contact region 24 via a silicide layer 60. The back gate contact 34 may include a plurality of back gate contacts 34 arranged along the first direction X.

[0065] 4, the multiple source contacts 32 connected to one source region 23 are aligned in the first direction X with the multiple source contacts 32 connected to the other source region 23. The source contacts 32 and the back gate contact 34 are electrically isolated from each other. The source contacts 32 and the back gate contact 34 may be aligned in the first direction X with the drain contacts (the first drain contact 29 and the second drain contact 30).

[0066] In this embodiment, the drain wiring 28, the source wiring 31, and the back gate wiring 33 are made of aluminum (Al), but may be made of other conductive materials (for example, copper (Cu) etc.) The drain wiring 28, the source wiring 31, and the back gate wiring 33 may be referred to as a drain conductive layer, a source conductive layer, and a back gate conductive layer, respectively.

[0067] In this embodiment, the first drain contact 29, the second drain contact 30, the source contact 32, and the back gate contact 34 are made of tungsten (W), but may be made of other conductive materials (e.g., aluminum (Al), copper (Cu), etc.). In this case, it goes without saying that a barrier film such as TiN may be used.

[0068] Although not shown, a gate contact that is mechanically and electrically connected to the gate electrode 20 is embedded in the interlayer insulating film 27. The gate contact is electrically insulated from the first drain contact 29, the second drain contact 30, the source contact 32, and the back gate contact 34.

[0069] As described above, in the LDMOSFET 10, the source region 23 and the back-gate contact region 24 are formed to be electrically separated from each other. Therefore, it is possible to switch the connection destination of the back-gate contact region 24 between the source region 23 and the first drain region 21.

[0070] FIG. 8 is an electric circuit diagram of the semiconductor chip 2. The semiconductor chip 2 includes an LDMOSFET 10 and two body diodes 88. The semiconductor chip 2 includes a source terminal electrode 81, a drain terminal electrode 82, a back gate terminal electrode 83, and a gate terminal electrode 84. The source terminal electrode 81, the drain terminal electrode 82, the back gate terminal electrode 83, and the gate terminal electrode 84 are formed on the outer surface of the semiconductor chip 2. The source terminal electrode 81 is electrically connected to the source wiring 31 (see FIG. 7) of the LDMOSFET 10. The source terminal electrode 81 may be called an output terminal. The drain terminal electrode 82 is electrically connected to the drain wiring 28 (see FIG. 7) of the LDMOSFET 10. The drain terminal electrode 82 may be called an input terminal. The back gate terminal electrode 83 is electrically connected to the back gate wiring 33 (see FIG. 7) of the LDMOSFET 10. The gate terminal electrode 84 is electrically connected to the gate wiring (not shown) of the LDMOSFET 10. The gate contact is electrically connected to this gate wiring.

[0071] A first switch 85 is disposed between the source terminal electrode 81 and the backgate terminal electrode 83. A second switch 86 is disposed between the drain terminal electrode 82 and the backgate terminal electrode 83. The first switch 85 and the second switch 86 are switched between opening and closing by a drive circuit 87. The first switch 85 and the second switch 86 selectively switch the connection destination of the backgate terminal electrode 83 between the source terminal electrode 81 and the drain terminal electrode 82. When the LDMOSFET 10 is in an on state, the first switch 85 is in an open state and the second switch 86 is in a closed state. That is, the connection destination of the backgate terminal electrode 83 is the drain terminal electrode 82. When the LDMOSFET 10 is in an off state, the first switch 85 is in a closed state and the second switch 86 is in an open state. That is, the connection destination of the backgate terminal electrode 83 is the source terminal electrode 81.

[0072] Two body diodes 88 are formed in the path connecting the source terminal electrode 81 and the drain terminal electrode 82. These two body diodes 88 provide an overcurrent prevention function and a reverse current prevention function. Whether the backgate terminal electrode 83 is connected to the source terminal electrode 81 or the drain terminal electrode 82, a current flows through the two body diodes 88. In other words, the semiconductor chip 2 can provide both an overcurrent prevention function and a reverse current prevention function in both the on state of the LDMOSFET 10 and the off state of the LDMOSFET 10.

[0073] In this embodiment, both the overcurrent prevention function and the backflow prevention function are realized in one semiconductor chip 2. Therefore, compared to the case where a total of two chips, one chip with an overcurrent prevention function and one chip with a backflow prevention function, are used, it is possible to reduce the size of the substrate on which the semiconductor chip 2 is arranged.

[0074] Furthermore, if one were to mount both an LDMOSFET for overcurrent prevention and an LDMOSFET for reverse current prevention on a single chip, the chip size would likely increase.

[0075] In contrast, in this embodiment, only one LDMOSFET 10 is formed on one semiconductor chip 2. Therefore, the chip size of the semiconductor chip 2 can be reduced compared to a case where both an LDMOSFET for overcurrent prevention function and an LDMOSFET for reverse current prevention function are mounted on one chip.

[0076] In the semiconductor device described in Patent Document 1, the source region and the backgate contact region are electrically connected to the same source wiring. That is, the semiconductor device described in Patent Document 1 employs a butting structure between the source and the backgate. In such a semiconductor device, the decrease in the on-state breakdown voltage is suppressed.

[0077] In contrast, in this embodiment, in order to realize both the overcurrent prevention function and the backflow prevention function in one semiconductor chip 2, the source region 23 and the backgate contact region 24 are formed to be electrically separated. That is, a structure in which the source and the backgate are separated is adopted. Since a structure in which the backgate and the source are separated is adopted, there is a concern that the on-state breakdown voltage of the semiconductor chip 2 (semiconductor device 1) may decrease.

[0078] Fig. 9 is a graph showing the relationship between the fourth width W4 in the second direction of the back gate contact region 24 and the on-breakdown voltage of the semiconductor device 1. In Fig. 9, the lower limit of the allowable value of the on-breakdown voltage is indicated by a dashed line.

[0079] The on-breakdown voltage of the semiconductor device 1 depends on the fourth width W4 of the back-gate contact region 24. It can be seen from Fig. 9 that when the fourth width W4 is 0.4 µm or more and 0.6 µm or less, the on-breakdown voltage of the semiconductor device 1 can be maintained high. As a result, even when the semiconductor device 1 employs a structure in which the source and back-gate are separated, a decrease in the on-breakdown voltage can be suppressed.

[0080] In this embodiment, a p-type first impurity region 25 is formed below the back gate region 16. By forming a relatively high-concentration p-type impurity region below the back gate region 16, a decrease in the on-breakdown voltage of the semiconductor device 1 can be suppressed. Meanwhile, the concentration in the surface portion of the back gate region 16 remains unchanged. Therefore, a decrease in the on-breakdown voltage of the semiconductor device 1 can be suppressed while suppressing the effect on the element characteristics of the semiconductor device 1.

[0081] As described above, the first impurity region 25 is not formed in a region facing the channel region 53 in the depth direction (third direction Z). If the first impurity region 25 is formed in a region facing the channel region 53 in the depth direction, the threshold voltage (V TH ) may deteriorate. Therefore, in this embodiment, the first impurity region 25 is not formed in a region facing the channel region 53 in the depth direction.

[0082] 10A to 10N are diagrams showing a part of the manufacturing process of the semiconductor device 1 in the order of steps. 10A to 10N correspond to FIG.

[0083] First, referring to Fig. 10A, a semiconductor wafer 101 is prepared. The semiconductor wafer 101 serves as a base for the semiconductor chip 2 (see Figs. 6 and 7). The semiconductor wafer 101 is a p-type wafer. The semiconductor wafer 101 corresponds to the first p-type region 12 of the semiconductor device 1 (see Figs. 6 and 7).

[0084] 10B, a hard mask (not shown) having an opening corresponding to a region where buried region 14 (see FIGS. 6 and 7) is to be formed is disposed, and n-type impurities are selectively introduced into the surface portion of semiconductor wafer 101 through the hard mask. As a result, introduced portion 102 is formed in the surface portion of semiconductor wafer 101. Examples of n-type impurities include P (phosphorus) and As (arsenic).

[0085] Next, referring to FIG. 10C, an epitaxial layer 103 is formed by epitaxially growing silicon of the semiconductor wafer 101. The formation of the epitaxial layer 103 forms a semiconductor wafer structure 111 including a second p-type region 13. The epitaxial layer 103 corresponds to the second p-type region 13. The n-type impurity of the introduction portion 102 introduced into the main surface of the semiconductor wafer 101 is diffused into the p-type epitaxial layer 103 to form a buried region 14. The semiconductor wafer structure 111 has a first wafer main surface 112 on one side and a second wafer main surface 113 on the opposite side. The first wafer main surface 112 and the second wafer main surface 113 correspond to the first main surface 3 and the second main surface 4 of the semiconductor chip 2, respectively (see FIGS. 6 and 7). Next, a sacrificial insulating film 114 is formed on the first wafer main surface 112. The sacrificial insulating film 114 may be, for example, a silicon oxide (SiO 2 ) film formed by thermally oxidizing the surface layer of the first wafer main surface 112 into a film shape.

[0086] Next, referring to FIG. 10D, a first p-type impurity region 25 and a second p-type impurity region 26 are formed.

[0087] Specifically, p-type impurities are selectively introduced into the first wafer main surface 112 through the resist mask RM. Examples of the p-type impurities (first impurities) include B (boron) and Al (aluminum). The openings OP of the resist mask RM correspond to regions in which the p-type first impurity region 25 and the p-type second impurity region 26 are to be formed. The openings OP of the resist mask RM have an elliptical first opening OP1 (corresponding to the first impurity region 25) and an annular second opening OP2 (corresponding to the second impurity region 26) surrounding the lateral sides of the opening. After the introduction of the p-type impurities, the resist mask RM is removed from the semiconductor wafer structure 111. Next, the semiconductor wafer structure 111 is heat-treated to diffuse the introduced p-type impurities. As a result, the p-type first impurity region 25 and the p-type second impurity region 26 are formed.

[0088] As described above, the pattern of the openings OP of the resist mask RM has an elliptical first opening OP1 and an annular second opening OP2. If the pattern of the openings OP of the resist mask RM were only the first opening OP1, the periphery of the first opening OP1 would be pulled by the surrounding resist and spread outward. Therefore, the outer periphery of the first impurity region 25 formed using the first opening OP1 would be displaced outward from its intended position. In this case, the outer periphery of the first impurity region 25 would be located in a region facing the channel region 53 in the depth direction (third direction Z).

[0089] In contrast, in this embodiment, since the second opening OP2 is formed in the resist mask RM, no force acts on the periphery of the first opening OP1 to pull it outward. Therefore, the periphery of the first opening OP1 does not expand outward. This prevents the outer periphery of the first impurity region 25 from shifting from its intended position. This reliably prevents the outer periphery of the first impurity region 25 from facing the channel region 53 in the depth direction (third direction Z).

[0090] Next, with reference to FIG. 10E, the first well region 15, the back gate region 16, the drift region 17 and the second well region 18 are formed in the surface layer portion of the first wafer main surface 112.

[0091] Specifically, the first well region 15 is formed by implanting n-type impurities into the surface layer of the first wafer main surface 112 by ion implantation through the sacrificial insulating film 114. The bottom of the first well region 15 reaches the buried region 14. The formation of the annular first well region 15 divides the second p-type region 13 into a p-type inner region 13A and a p-type outer region 13B. The p-type inner region 13A is surrounded in the first direction X, the second direction Y, and the third direction Z by the n-type region including the buried region 14 and the first well region 15. As a result, the p-type inner region 13A is electrically isolated from the p-type outer region 13B and the first p-type region 12 by the n-type region including the buried region 14 and the first well region 15.

[0092] Furthermore, the back-gate region 16 and the second well region 18 are formed in a surface layer portion of the first wafer main surface 112. Specifically, p-type impurities are implanted into the surface layer portion of the first wafer main surface 112 by ion implantation via the sacrificial insulating film 114, thereby forming the back-gate region 16 and the second well region 18.

[0093] Next, drift region 17 is formed in a surface layer portion of first wafer main surface 112. Specifically, drift region 17 is formed by implanting n-type impurities into the surface layer portion of first wafer main surface 112 by ion implantation via sacrificial insulating film 114. The bottom of drift region 17 does not reach buried region 14.

[0094] In the ion implantation method for forming the drift region 17, n-type impurities are introduced up to a region inside the inner periphery 17A of the drift region 17. This allows the inner periphery 17A of the drift region 17 to be reliably connected to the back gate region 16. By introducing n-type impurities up to a region inside the inner periphery 17A of the drift region 17, the p-type impurity in the periphery of the back gate region 16 is reduced. This forms a low concentration portion 36 in the periphery of the back gate region 16. Since the dose of the p-type impurity is less than the dose of the n-type impurity, the periphery of the back gate region 16 is maintained as a p-type impurity region.

[0095] The order of forming the first well region 15, the back gate region 16, the drift region 17, and the second well region 18 can be changed as appropriate. For example, the back gate region 16 may be formed first, and then the drift region 17 may be formed. Also, for example, the drift region 17 may be formed first, and then the first well region 15 may be formed.

[0096] 10F, a hard mask (not shown) is formed on the sacrificial insulating film 114, and the sacrificial insulating film 114 is selectively removed by etching through the hard mask to form openings 115. Next, a surface layer portion of the first wafer main surface 112 exposed from the openings 115 of the sacrificial insulating film 114 is thermally oxidized to form a field insulating film 19. Thereafter, the sacrificial insulating film 114 is removed.

[0097] 10G, a gate insulating film 54 is formed on the first wafer main surface 112. The gate insulating film 54 may be, for example, a silicon oxide (SiO2) film formed by thermally oxidizing a surface layer portion of the field insulating film 19 on the first wafer main surface 112 exposed from the first opening 41, the second opening 42, the third opening 43, and the fourth opening 44 into a film shape.

[0098] 10H, a base electrode 116 which serves as a base for the gate electrode 20 (see FIGS. 6 and 7) is formed on the first wafer main surface 112 so as to cover the gate insulating film 54 and the field insulating film 19. In this embodiment, the base electrode 116 is made of conductive polysilicon. The base electrode 116 may be formed by, for example, a CVD method.

[0099] 10I, unnecessary portions of the base electrode 116 are removed by etching through a hard mask (not shown) having a predetermined pattern. As a result, the gate electrode 20 is formed. The etching may be, for example, dry etching (for example, an RIE method) or wet etching. Thereafter, the gate insulating film 54 exposed from the gate electrode 20 is removed, thereby exposing the back gate region 16 from the opening 50 and exposing the first well region 15 from the first opening 41 of the field insulating film 19.

[0100] 10J, a base insulating film 117 that serves as a base for the sidewall structure 57 is sequentially formed on the first wafer main surface 112. The base insulating film 117 may be formed by, for example, a CVD method. Next, unnecessary portions of the base insulating film 117 are removed by etch-back. As a result, the sidewall structure 57 is formed by the base insulating film 117 remaining on the inner side portion and the outer side portion of the gate electrode 20.

[0101] Next, referring to FIG. 10K, the first drain region 21 and the second drain region 22 are formed in the surface layer portion of the drift region 17 and the first well region 15, respectively. Also, the source region 23 and the backgate contact region 24 are formed in the surface layer portion of the backgate region 16, respectively. In this embodiment, the source region 23 and the backgate contact region 24 are formed by injecting n-type impurities and p-type impurities into the surface layer portion of the backgate region 16 by ion implantation using the sidewall structure 57 and the field insulating film 19 as a hard mask. That is, the source region 23 and the backgate contact region 24 are formed in a self-aligned manner with respect to the periphery of the sidewall structure 57 of the gate electrode 20 and the periphery of the third opening 43, respectively. The first drain region 21 is formed by injecting n-type impurities into the surface layer portion of the drift region 17 by ion implantation using the field insulating film 19 as a hard mask. That is, the first drain region 21 is formed in a self-aligned manner with respect to the periphery of the first opening 41 in the field insulating film 19. The second drain region 22 is formed by injecting n-type impurities into the surface layer portion of the first well region 15 by ion implantation using the field insulating film 19 as a hard mask. That is, the second drain region 22 is formed in a self-aligned manner with respect to the periphery of the second opening 42 in the field insulating film 19.

[0102] 10L, the silicide layer 60 is formed. To form the silicide layer 60, first, the above-mentioned transition metal is deposited on the second p-type region 13 and the gate electrode 20, and then heat-treated. The exposed portions (silicon) of the second p-type region 13 and the gate electrode 20 react with the transition metal, forming the silicide layer 60.

[0103] 10M, an interlayer insulating film 27 is formed on the first wafer main surface 112. The interlayer insulating film 27 may be formed by, for example, a CVD method.

[0104] 10N, a first drain contact 29, a second drain contact 30, a source contact 32, and a back gate contact 34 are formed in the interlayer insulating film 27 by etching through a hard mask (not shown) having a predetermined pattern, forming a metal film by a CVD method, and etching away unnecessary metal film. Next, a base wiring film that serves as a base for a plurality of wirings is formed on the interlayer insulating film 27 and patterned to form drain wiring 28, source wiring 31, and back gate wiring 33. Thereafter, the semiconductor wafer structure 111 is cut, and a plurality of semiconductor chips 2 are cut out. Through the steps including those described above, the semiconductor device 1 is manufactured.

[0105] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0106] 11 , the back-gate contacts 34 and the source contacts 32 may be arranged to be shifted from each other in the first direction X in a plan view. Even in this case, the multiple back-gate contacts 34 connected to one source region 23 may be aligned in the first direction X with the multiple back-gate contacts 34 connected to the other source region 23.

[0107] 12, the back gate contacts 34 may be in a line shape extending along the first direction X, instead of a dot shape (rectangular shape). As shown in FIG 12, the source contacts 32 may be in a line shape extending along the first direction X, instead of a dot shape (rectangular shape).

[0108] Fig. 13 is a schematic cross-sectional view of a semiconductor device 201 according to another embodiment of the present disclosure, and corresponds to Fig. 7. In Fig. 13, the same components as those described above are denoted by the same reference symbols, and the description thereof will be omitted.

[0109] The semiconductor device 201 differs from the semiconductor device 1 according to the embodiment shown in FIGS. 1 to 10N in that the second well region 18 and the second impurity region 26 are eliminated. The outer peripheral edge 17B of the drift region 17 contacts the first well region 15 over the entire circumferential area of ​​the drift region 17. Since the first well region 15 is electrically connected to the drift region 17, the first well region 15 is at the same potential as the drift region 17. Therefore, in the semiconductor device 201, a drain contact region (corresponding to the second drain contact 30 in the embodiment shown in FIGS. 1 to 10N) is not formed in the first well region 15.

[0110] According to the semiconductor device 201 according to the other embodiment of the present disclosure, the same effects as those described in relation to the embodiment shown in FIGS. 1 to 10N are achieved.

[0111] In each of the above-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing the n-type region with a p-type region and the p-type region with an n-type region in the above description and the accompanying drawings.

[0112] The embodiments of the present disclosure are illustrative in all respects and should not be construed as limiting, and are intended to include modifications in all respects.

[0113] The following characteristics can be extracted from the description of this specification and the drawings. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiment, but are not intended to limit the scope of each clause to the embodiment.

[0114] [Appendix 1-1] A semiconductor chip (2) having a first main surface (3) and a second main surface (4) opposite to the first main surface (3); a first drain region (21) of a first conductivity type formed in a surface layer portion of the first main surface (3); a back gate region (16) of a second conductivity type formed apart from the first drain region (21) in a surface layer portion of the first main surface (3); a first conductivity type source region (23) formed in a surface layer portion of the back gate region (16) and spaced apart inward from the periphery (61-64) of the back gate region (16); a back-gate contact region (24) of a second conductivity type formed in a surface layer portion of the back-gate region (16) and electrically isolated from the source region (23); A semiconductor device (1, 151, 161, 201) including a gate electrode (20) facing a channel region (53) formed in the back gate region (16) between the periphery (61-64) of the back gate region (16) and the source region (23).

[0115] According to this configuration, the source region (23) and the back gate contact region (24) are formed to be electrically separated from each other, so that the connection destination of the back gate contact region (24) can be switched between the source region (23) and the first drain region (21).

[0116] [Appendix 1-2] the back gate region (16) is in the shape of a strip extending in a first direction (Y) along the first main surface (3), The semiconductor device (1, 151, 161, 201) according to appendix 1-1, wherein the source region (23) and the back gate contact region (16) are formed at an interval in a second direction (Y) intersecting the first direction (Y).

[0117] [Appendix 1-3] The semiconductor device (1, 151, 161, 201) according to appendix 1-2, wherein the source region (23) and the back gate contact region (24) are strip-shaped extending along the first direction (Y).

[0118] [Appendix 1-4] The semiconductor device (1, 151, 161, 201) according to appendix 1-3, wherein the width (W4) of the back gate contact region (24) in the second direction (Y) is 0.6 μm or more and 0.8 μm or less.

[0119] [Appendix 1-5] The semiconductor device (1, 151, 161, 201) according to Appendix 1-3 or Appendix 1-4, wherein the source region (23) includes a pair of source regions (23) formed to sandwich the back gate contact region (24) in the second direction (Y).

[0120] [Appendix 1-6] The semiconductor device (1, 151, 161, 201) according to any one of Appendices 1-1 to 1-5, wherein the source region (23) and the back gate contact region (24) are electrically isolated by a field insulating film (19) in a surface portion of the back gate region (16).

[0121] [Appendix 1-7] an interlayer insulating film (27) covering the first main surface (3); a back gate wiring (33) formed on the interlayer insulating film (27); a source wiring (31) which is a wiring separate from the back gate wiring (33) and formed on the interlayer insulating film (27); a back gate contact (34) that penetrates the interlayer insulating film (27) and connects the back gate region (16) and the back gate wiring (33); The semiconductor device (1, 151, 161, 201) according to any one of Supplementary Notes 1-1 to 1-6, further comprising a source contact (32) penetrating the interlayer insulating film (27) and connecting the source region (23) and the source wiring (31).

[0122] [Appendix 1-8] The semiconductor device (1, 151, 161, 201) according to any one of Supplementary Notes 1-1 to 1-7, further including a first impurity region (25) of a second conductivity type formed below the back gate region (16).

[0123] [Appendix 1-9] The semiconductor device (1, 151, 161, 201) according to appendix 1-8, wherein the first impurity region (25) is formed so as not to face the channel region (53) in a depth direction (Z).

[0124] [Appendix 1-10] A semiconductor device (1, 151, 161, 201) according to Appendix 1-8 or Appendix 1-9, wherein a periphery (71-74) of the first impurity region (25) is formed inwardly and away from the periphery (61-64) of the back gate region (16) in a direction along the first main surface (3).

[0125] [Appendix 1-11] The semiconductor device (1, 151, 161, 201) according to any one of Supplementary Notes 1-8 to 1-10, wherein the first impurity region (25) is in contact with the back gate region (16).

[0126] [Appendix 1-12] The semiconductor device (1, 151, 161) according to any one of Supplementary Notes 1-8 to 1-11, further including a second impurity region (26) of a second conductivity type formed so as to surround a side of the first impurity region (25).

[0127] [Appendix 1-13] The semiconductor device further includes a drift region (17) of a first conductivity type formed in a surface layer portion of the first main surface (3), The semiconductor device (1, 151, 161, 201) according to any one of Supplementary Notes 1-1 to 1-12, wherein the first drain region (21) is formed in a surface layer portion of the drift region (17).

[0128] [Appendix 1-14] A semiconductor device (1,151,161,201) described in Appendix 1-13, wherein the back gate region (16) includes the first portion (35) in which the source region (23) and the back gate contact region (24) are formed, and a second portion (36) formed closer to the drift region (17) than the first portion and having a lower second conductivity type impurity concentration than the first portion (35).

[0129] [Appendix 1-15] a first conductivity type well region (15) that is annular in plan view and that surrounds a side of a first region (13A) in which the back gate region (16) and the drift region (17) are formed in a surface layer portion of the first main surface (2); a buried region (14) covering an entire area below the first region (13A), A semiconductor device (1, 151, 161, 201) according to Appendix 1-13 or Appendix 1-14, wherein the well region (15) and the buried region (14) electrically isolate the first region (13A) from a second region (12, 13A), which is another region in the surface portion of the first main surface (3). 1: Semiconductor device 2: Semiconductor chips 3: First main surface 4: Second main surface 5 :1st side 6:Second side 7:Third side 8: 4th side 9: Device area 11:LDMOS area 12: 1st p-type region 13: 2nd p-type region 13A:p-type inner region 13B:p-type outer region 14: Embedded region 15: First well region 16: Back gate region 17: Drift region 17A: Inner edge 17B: Outer edge 18: Second well region 19: Field insulating film 20: Gate electrode 21: First drain region 21A: First side 21B: Second side 21C: Third side 21D: 4th side 22: Second drain region 22A: First side 22B: Second side 22C: Third side 22D: 4th side 23: Source area 23A: First side 23B: Second side 23C: Third side 23D: 4th side 24: Backgate contact area 24A: First side 24B: Second side 24C: Third side 24D: 4th side 25:First impurity region 26:Second impurity region 27: Interlayer insulating film 28: Drain wiring 29: First drain contact 30: Second drain contact 31: Source wiring 32: Source Contact 33: Back gate wiring 34: Backgate contact 35: High concentration part (1st part) 36:Low concentration part (second part) 41: First opening 42: Second opening 43: 3rd opening 44: 4th opening 50: Opening 51 :1st part 52:Second part 53: Channel region 54: Gate insulating film 55: Control section 56: Field plate section 57: Sidewall structure 60: Silicide layer 61: First periphery 62: Second periphery 63: Third periphery 64: 4th periphery 71: First periphery 72: Second periphery 73: Third periphery 74: 4th periphery 81: Source terminal electrode 82: Drain terminal electrode 83: Back gate terminal electrode 84: Gate terminal electrode 85: First switch 86: Second switch 87: Drive circuit 88: Body diode 101: Semiconductor wafer 102: Introduction 103: Epitaxial layer 111: Semiconductor wafer structure 112: First wafer main surface 113: Second wafer main surface 114: Sacrificial insulating film 115 :Aperture 116: Base electrode 117: Base insulating film 151: Semiconductor device 161: Semiconductor devices 201: Semiconductor device OP: Opening OP1: 1st opening OP2: Second opening RM: Resist mask W1: 1st width W2: Second width W3: 3rd width W4: 4th width W 11 :First interval X: 1st direction Y: Second direction Z: Third direction (depth direction)

Claims

1. a semiconductor chip having a first major surface and an opposite second major surface; a first drain region of a first conductivity type formed in a surface layer portion of the first main surface; a back gate region of a second conductivity type formed in a surface portion of the first main surface and spaced apart from the first drain region; a first conductivity type source region formed in a surface layer portion of the back gate region and spaced apart from an inner periphery of the back gate region; a back-gate contact region of a second conductivity type formed in a surface layer portion of the back-gate region and electrically isolated from the source region; a gate electrode facing a channel region formed in the back gate region between the periphery of the back gate region and the source region.

2. the back gate region has a strip shape extending in a first direction along the first main surface, The semiconductor device according to claim 1 , wherein said source region and said back gate contact region are formed at an interval from each other in a second direction intersecting said first direction.

3. The semiconductor device according to claim 2 , wherein the source region and the back gate contact region are strip-shaped and extend along the first direction.

4. The semiconductor device according to claim 3 , wherein the width of said back gate contact region in said second direction is not less than 0.6 μm and not more than 0.8 μm.

5. The semiconductor device according to claim 3 , wherein the source region includes a pair of source regions formed to sandwich the back gate contact region in the second direction.

6. 2. The semiconductor device according to claim 1, wherein said source region and said back gate contact region are electrically isolated by a field insulating film in a surface layer portion of said back gate region.

7. an interlayer insulating film covering the first main surface; a back gate wiring formed on the interlayer insulating film; a source wiring which is a wiring separate from the back gate wiring and is formed on the interlayer insulating film; a back gate contact penetrating the interlayer insulating film and connecting the back gate region and the back gate wiring; 7. The semiconductor device according to claim 1, further comprising a source contact penetrating said interlayer insulating film and connecting said source region and said source wiring.

8. 2. The semiconductor device according to claim 1, further comprising a first impurity region of a second conductivity type formed below said back gate region.

9. 9. The semiconductor device according to claim 8, wherein said first impurity region is formed so as not to face said channel region in a depth direction.

10. 9. The semiconductor device according to claim 8, wherein a periphery of said first impurity region is formed inwardly and apart from said periphery of said back gate region in a direction along said first main surface.

11. 11. The semiconductor device according to claim 8, wherein the first impurity region is in contact with the back gate region.

12. 11. The semiconductor device according to claim 8, further comprising a second impurity region of a second conductivity type formed so as to surround a side of the first impurity region.

13. a drift region of a first conductivity type formed in a surface layer portion of the first main surface, 11. The semiconductor device according to claim 1, wherein the first drain region is formed in a surface layer portion of the drift region.

14. 14. The semiconductor device according to claim 13, wherein the back-gate region includes a first portion in which the source region and the back-gate contact region are formed, and a second portion formed closer to the drift region than the first portion and having a lower second conductivity type impurity concentration than the first portion.

15. a first conductivity type well region that is annular in plan view and that surrounds a side of a first region in which the back gate region and the drift region are formed in a surface layer portion of the first main surface; a buried region covering an entire area below the first region, 14. The semiconductor device according to claim 13, wherein said well region and said buried region electrically isolate said first region from a second region which is another region in a surface layer portion of said first main surface.

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