Semiconductor package

Abstract

To provide a semiconductor package including an interconnect bridge which has a high degree of design freedom, can reduce the overall thickness of the package, and can be manufactured with a simple process and at low cost.SOLUTION: A semiconductor package 500A includes a package substrate 100, a first semiconductor chip 210 arranged on the package substrate and having a first recess portion r1 on a first front surface side facing the package substrate, a second semiconductor chip 220 arranged alongside the first semiconductor chip on the package substrate and having a second recess portion r2 on a second front surface side facing the package substrate, and an interconnect bridge 300 arranged on the first front surface and the second front surface, with at least a portion of the interconnect bridge 300 being disposed in each of the first recess portion and the second recess portion.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to semiconductor packages. [Background technology]

[0002] As the number of cores in CPU and GPU for server products increases rapidly, die split technology that can effectively increase the number of cores is becoming common. In addition, as the demand for packages including HBM (High Bandwidth Memory) increases, technology that connects die to die with fine circuit line width is required. To meet these technical requirements, technologies such as embedding silicon bridges and using silicon interposers have been developed, but there are limitations to commercialization due to price issues and complex assembly processes. Summary of the Invention [Problem to be solved by the invention]

[0003] Among the various objects of the present disclosure is to provide a semiconductor package including an interconnect bridge that allows for greater design flexibility and reduced overall package thickness.

[0004] Another of the various objects of the present disclosure is to provide a semiconductor package including an interconnect bridge that can be manufactured with simple processes and at low cost. [Means for solving the problem]

[0005] One of the various solutions proposed throughout this disclosure is to form recesses in multiple dies, place a bridge in the recess to interconnect the multiple dies, and then mount the multiple dies and the interconnect bridge on a package substrate in that state.

[0006] For example, a semiconductor package according to one example may include a package substrate, a first semiconductor chip disposed on the package substrate and having a first recessed portion on a first front surface side facing the package substrate, a second semiconductor chip disposed alongside the first semiconductor chip on the package substrate and having a second recessed portion on a second front surface side facing the package substrate, and an interconnect bridge disposed on the first and second front surfaces, with at least a portion of the interconnect bridge disposed in each of the first and second recessed portions.

[0007] For example, a semiconductor package according to one example may include a package substrate, first and second semiconductor chips disposed on the package substrate, a molding material disposed on the package substrate and filling at least a portion of the space between the first and second semiconductor chips, a recess portion penetrating the first and second semiconductor chips and a portion of the molding material in a vertical direction from a lower surface of each of the first and second semiconductor chips and the molding material, and an interconnect bridge disposed in the recess portion. Effect of the Invention

[0008] Among the various advantages of the present disclosure is the provision of a semiconductor package including an interconnect bridge that allows for greater design flexibility and reduced package thickness.

[0009] Another advantage of the present disclosure is that it provides a semiconductor package that includes an interconnect bridge that can be manufactured with simple processes and at low cost. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3]1 is a cross-sectional view showing a schematic diagram of a BGA package mounted on a main board of an electronic device. [Figure 4] 1 is a cross-sectional view showing a silicon interposer package mounted on a main board. FIG. [Diagram 5] 1 is a cross-sectional view showing a schematic diagram of an organic interposer package mounted on a main board; [Figure 6] 1 is a cross-sectional view illustrating an example of a semiconductor package. [Figure 7] FIG. 7 is an enlarged cross-sectional view that illustrates an example of a region A in FIG. 6. [Figure 8a] 7A to 7C are cross-sectional views illustrating steps of a manufacturing method for the semiconductor package of FIG. 6. [Figure 8b] 7A to 7C are cross-sectional views illustrating steps of a manufacturing method for the semiconductor package of FIG. 6. [Figure 8c] 7A to 7C are cross-sectional views illustrating steps of a manufacturing method for the semiconductor package of FIG. 6. [Figure 8d] 7A to 7C are cross-sectional views illustrating steps of a manufacturing method for the semiconductor package of FIG. 6. [Figure 8e] 7A to 7C are cross-sectional views illustrating steps of a manufacturing method for the semiconductor package of FIG. 6. [Figure 9] FIG. 11 is a cross-sectional view illustrating another example of a semiconductor package. [Figure 10] 10 is an enlarged cross-sectional view that illustrates an example of a region B in FIG. 9. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for a clearer description.

[0012] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0013] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also coupled to other electronic components described below to form various signal lines 1090.

[0014] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with each other. The chip-related components 1020 can also be in the form of a package including the above-mentioned chips and electronic components.

[0015] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, and may include any of numerous other wireless or wired standards and protocols. The network-related components 1030 may also be combined with the chip-related components 1020 together.

[0016] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may include passive elements in the form of chip components used for various other applications. The other components 1040 may also be combined with the chip-related components 1020 and / or the network-related components 1030.

[0017] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. Other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0018] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device that processes data.

[0019] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0020] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110, are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are mounted on a surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built in. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0021] Semiconductor package including interposer Generally, a semiconductor chip is an integrated circuit of many fine electric circuits, but it cannot function as a finished semiconductor product by itself and may be damaged by external physical or chemical shocks. Therefore, the semiconductor chip is not used as it is, but is packaged and used in electronic devices in the packaged state.

[0022] The reason why semiconductor packaging is necessary is that there is a difference in circuit width between a semiconductor chip and a main board of an electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the size of the connection pads and the distance between the connection pads are very small, whereas in the case of a main board used in an electronic device, the size of the component mounting pads and the distance between the component mounting pads are significantly larger than the scale of the semiconductor chip. Therefore, it is difficult to directly mount a semiconductor chip on such a main board, and a packaging technology that can reduce the difference in circuit width is required.

[0023] A semiconductor package including an interposer manufactured by such packaging technology will be described in more detail below with reference to the drawings.

[0024] FIG. 3 is a cross-sectional view that shows a schematic diagram of a BGA package mounted on a main board of an electronic device.

[0025] Among semiconductor chips, application specific integrated circuits (ASICs) such as graphics processing units (GPUs) are very expensive per chip, so it is very important to package them with a high yield. For this purpose, a ball grid array (BGA) substrate 2210 capable of rewiring thousands to hundreds of thousands of connection pads is prepared before mounting the semiconductor chips, and expensive semiconductor chips such as GPUs 2220 are subsequently mounted and packaged on the BGA substrate 2210 using surface mounting technology (SMT), and then finally mounted on the main board 2110.

[0026] Meanwhile, in the case of the GPU2220, it is necessary to minimize the signal path with a memory such as a High Bandwidth Memory (HBM), and for this purpose, a semiconductor chip such as an HBM2240 is mounted on an interposer 2230, packaged, and stacked in a package on package in which the GPU2220 is mounted in a package on package (POP) form. However, in this case, there is a problem that the thickness of the device becomes very thick, and there is a limit to minimizing the signal path.

[0027] FIG. 4 is a cross-sectional view that illustrates a silicon interposer package mounted on a main board.

[0028] As a solution to the above-mentioned problems, it is possible to consider manufacturing a semiconductor package 2310 including a silicon interposer as an interposer technology in which a first semiconductor chip such as a GPU 2220 and a second semiconductor chip such as an HBM 2240 are surface-mounted side-by-side on a silicon interposer 2250 and then packaged. In this case, the GPU 2220 and the HBM 2240 having thousands to hundreds of thousands of connection pads can be rewired through the interposer 2250, and these can be electrically connected with a minimum number of paths. In addition, the semiconductor package 2310 including such a silicon interposer can be mounted again on a BGA substrate 2210 and rewired, and finally mounted on the main board 2110.

[0029] However, in the case of the silicon interposer 2250, not only is it very difficult to form a through silicon via (TSV), but the manufacturing cost is also quite high, which is disadvantageous in terms of increasing the area and reducing the cost.

[0030] FIG. 5 is a cross-sectional view that illustrates a schematic diagram of an organic interposer package mounted on a main board.

[0031] As a solution to the above-mentioned problems, it is possible to use an organic interposer 2260 instead of the silicon interposer 2250. For example, it is possible to manufacture a semiconductor package 2320 including an organic interposer as an interposer technology in which a first semiconductor chip such as a GPU 2220 and a second semiconductor chip such as an HBM 2240 are surface-mounted side by side on the organic interposer 2260 and then packaged. In this case, it is possible to rewire the GPU 2220 and the HBM 2240 having thousands to hundreds of thousands of connection pads through the interposer 2260, and these can be electrically connected with a minimum number of paths. In addition, if the semiconductor package 2320 including such an organic interposer is mounted again on the BGA substrate 2210 and rewired, it can finally be mounted on the main board 2110. In addition, it is advantageous for increasing the area and reducing the cost.

[0032] However, even when using the organic interposer 2260, the semiconductor chips 2220, 2240 must be mounted on the organic interposer 2260 and then mounted again on the BGA substrate 2210, which may make the process somewhat complicated and may result in a reduced packaging yield.

[0033] Semiconductor package including bridge FIG. 6 is a cross-sectional view that shows a schematic example of a semiconductor package, and FIG. 7 is an enlarged cross-sectional view that shows a schematic example of region A in FIG.

[0034] 1, a semiconductor package 500A according to an example includes a package substrate 100, first and second semiconductor chips 210 and 220 disposed on the package substrate 100, a molding material 410 disposed on the package substrate 100 and filling at least a portion between the first and second semiconductor chips 210 and 220, a recess R formed between the first and second semiconductor chips 210 and 220 and the molding material 410, an interconnect bridge 300 disposed in the recess R, and a semiconductor package 500A formed between the package substrate 100 and the first and second semiconductor chips 210 and 220. The semiconductor chip 210, 220 and / or the package substrate 100 may include a plurality of first connection members 430 connecting the interconnect bridge 300 to the semiconductor chips 210, 220, a plurality of second connection members 440 connecting the interconnect bridge 300 to the first and second semiconductor chips 210, 220, and an insulating material 420 at least partially disposed between the molding material 410, the first and second semiconductor chips 210, 220, the interconnect bridge 300, and the package substrate 100, and embedding the plurality of first connection members 430.

[0035] As described above, the semiconductor package 500A according to an example is mounted on the package substrate 100 with the interconnect bridge 300 attached on the first and second front surfaces of the first and second semiconductor chips 210 and 220, respectively, and therefore has a better design space and a higher degree of freedom than a case in which the interconnect bridge 300 is embedded in the package substrate 100, and can be manufactured with a simpler process and at a lower cost. Nevertheless, the first and second semiconductor chips 210 and 220 and the molding material 410 have recessed portions R formed therein, and the interconnect bridge 300 is disposed in the recessed portions R, thereby reducing the overall thickness of the package.

[0036] Meanwhile, the recessed portion R may include first to third recessed portions r1, r2, and r3. The first recessed portion r1 may be formed on a first front surface side of the first semiconductor chip 210 facing the package substrate 100. The second recessed portion r2 may be formed on a second front surface side of the second semiconductor chip 220 facing the package substrate 100. The third recessed portion r3 may be formed on a lower side of the molding material 410 disposed between the first and second semiconductor chips 210 and 220. The first and second recessed portions r1 and r2 may vertically penetrate parts of the first and second semiconductor chips 210 and 220 from the first and second front surfaces, respectively. The first and second recessed portions r1 and r2 may be exposed from the inner surfaces of the first and second semiconductor chips 210 and 220 to face each other in the horizontal direction. The first and second recessed portions r1 and r2 may be connected to each other via the third recessed portion r3. In this manner, the recess portion R may include the first to third recess portions r1, r2, and r3 formed in the first and second semiconductor chips 210 and 220 and the molding material 410, respectively, and therefore the bottom surface may include the lower surfaces of the first and second semiconductor chips 210 and 220 and the molding material 410, respectively, and the wall surfaces may include the inner surfaces of the first and second semiconductor chips 210 and 220, respectively, and in this case, the bottom surface may be substantially flat. Therefore, the interconnect bridge 300 may be more easily disposed in the recess portion R and more easily connected to each of the first and second semiconductor chips 210 and 220.

[0037] Meanwhile, the molding material 410 may cover the upper surface and / or the outer side surface of each of the first and second semiconductor chips 210 and 220, and the lower surface of the molding material 410 may have a step due to the third recess portion r3. More specifically, the lower surface of the region of the molding material 410 covering the outer side surfaces of each of the first and second semiconductor chips 210 and 220 may be disposed at a different level, for example, lower than the lower surface of the region of the molding material 410 disposed between the first and second semiconductor chips 210 and 220. Therefore, the molding material 410 may not fill the recess portion R unnecessarily.

[0038] Meanwhile, the interconnect bridge 300 may include an organic insulating layer 310, a plurality of metal wiring layers 320 disposed on or within the organic insulating layer 310, and one or more metal via layers 330 disposed within the organic insulating layer 310 and connecting the plurality of metal wiring layers 320 to each other. For example, the interconnect bridge 300 may be an organic bridge. For example, the interconnect bridge 300 may be a high-density printed circuit board including fine circuits. Therefore, compared to the case where a silicon bridge is used, the process can be simplified and costs can be reduced. However, if necessary, a silicon bridge can be used as the interconnect bridge 300 instead of the organic bridge.

[0039] The components of the semiconductor package 500A according to an example will be described in more detail below with reference to the drawings.

[0040] The package substrate 100 may be an organic substrate or a silicon substrate, and may preferably be an organic substrate. The organic substrate may be, but is not limited to, a core-type printed circuit board, a coreless-type printed circuit board, or the like. The organic substrate may have various forms, such as a rigid printed circuit board, a flexible printed circuit board, or a rigid-flexible printed circuit board. The organic substrate may include a plurality of insulating layers, a plurality of wiring layers disposed on or within the plurality of insulating layers, and a plurality of via layers each penetrating at least one of the plurality of insulating layers. The organic substrate may further include a solder resist layer disposed on the outermost surface of the plurality of insulating layers.

[0041] Each of the insulating layers may include an insulating material. Examples of the insulating material include, but are not limited to, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, a material in which the resin is mixed with an inorganic filler such as silica, or a resin impregnated in a core material such as a glass fiber (glass cloth, glass fabric) together with an inorganic filler, for example, copper clad laminate (CCL), Ajinomoto build-up film (ABF), prepreg, etc. The insulating layers may have a distinct boundary between them, or may not have a distinct boundary as necessary. For example, insulating layers that include substantially the same insulating material may have an unclear boundary, but insulating layers that include different insulating materials may have an easier boundary to distinguish. However, the present invention is not limited to this, and the boundary may be clear regardless of the insulating material.

[0042] Each of the wiring layers may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the wiring layers may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). If necessary, a copper foil may be further included. Each of the wiring layers may perform various functions according to the design of the corresponding layer. For example, a ground pattern, a power pattern, a signal pattern, etc. may be included. Here, the signal pattern may include various signals other than the ground pattern, the power pattern, etc., such as a data signal. Each of these patterns may include a line pattern, a plane pattern, and / or a pad pattern.

[0043] Each of the plurality of via layers may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the plurality of via layers may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Each of the plurality of via layers may perform various functions according to the design of the corresponding layer. For example, the plurality of via layers may include a ground via, a power via, a signal via, and the like. Each of the vias of the plurality of via layers may be of a filled type in which a via hole is filled with a metal material, but is not limited thereto, and may be of a conformal type in which a metal material is disposed along the wall surface of a via hole. Each of the vias of the plurality of via layers may have various shapes, such as a cylinder, an hourglass, a taper, and the like.

[0044] The solder resist layer can protect the internal components of the package substrate 100. The material of the solder resist layer is not particularly limited. For example, an insulating material can be used, and in this case, the insulating material can be solder resist. However, the material is not limited thereto, and ABF, etc. can also be used.

[0045] A plurality of pads connected to the plurality of first connection members 430 may be disposed on the upper side of the package substrate 100. The plurality of pads may be disposed embedded in the upper surface of the package substrate 100 or may be disposed protruding from the upper surface of the package substrate 100. The plurality of pads may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The plurality of pads may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). If necessary, a copper foil may be further included. The plurality of pads may include ground pads, power pads, signal pads, etc.

[0046] Each of the first and second semiconductor chips 210 and 220 may include an integrated circuit (IC) die in which hundreds to millions of elements are integrated in one chip. In this case, the integrated circuit may be a logic chip such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an application processor (e.g., AP), an analog-to-digital converter, or an application-specific IC (ASIC), or may be a different type of memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, or a High Bandwidth Memory (HBM), or a Power Management IC (PMIC).

[0047] The first and second semiconductor chips 210 and 220 may each be formed on an active wafer, and in this case, a base material forming each body may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body. A connection pad may be formed on each body, and the connection pad may include a conductive material such as aluminum (Al) or copper (Cu). The first and second semiconductor chips 210 and 220 may each be a bare die, and in this case, metal bumps may be disposed on the connection pads as necessary. The first and second semiconductor chips 210 and 220 may each be a packaged die, and in this case, a redistribution layer may be further formed on the connection pads, and metal bumps may be disposed on the redistribution layer as necessary.

[0048] The first and second semiconductor chips 210 and 220 may have an active surface, e.g., a front surface, on which the first and second connection pads are formed, and the opposite surfaces may be non-active surfaces, e.g., back surfaces. The first and second recesses r1 and r2 may be formed on the active surface side, e.g., the front surface side, of the first and second semiconductor chips 210 and 220, respectively.

[0049] For example, the first semiconductor chip 210 may include a first semiconductor substrate 211, a plurality of first transistor elements 213 disposed on the first semiconductor substrate 211, a first insulating layer 212 disposed on the first semiconductor substrate 211, and a plurality of first metal layers 214 disposed on or within the first insulating layer 212. The plurality of first metal layers 214 may include a plurality of first connection pads, each of which has at least a portion exposed from a lower surface of the first insulating layer 212.

[0050] The first semiconductor substrate 211 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The first semiconductor substrate 211 may be provided, for example, but is not limited to, a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, or a semiconductor on insulator (SeOI) layer.

[0051] The first transistor element 213 may include a gate insulating layer, a gate electrode, a capping layer, a spacer, etc. Source / drain regions may be disposed on both sides of the first transistor element 213. The first transistor element 213 may be located in a cell region and may include, for example, but is not limited to, a DRAM memory element, a flash memory element, or a CIS (CMOS image sensor) element, etc., and may also include other logic elements, power elements, etc.

[0052] The first insulating layer 212 may include an oxide, a nitride, or an oxynitride, for example, but not limited to, silicon oxide, silicon nitride, or silicon oxynitride. The first insulating layer 212 may include a plurality of interlayer insulating layers, each of which may include the same material or different materials. If necessary, an interlayer insulating film may be disposed between the interlayer insulating layers, and a protective layer may be disposed on the interlayer insulating layers.

[0053] The first metal layer 214 may include a conductive material having low resistance, such as copper (Cu), aluminum (Al), or tungsten (W). Each layer of the first metal layer 214 may include the same material or different materials. Each layer of the first metal layer 214 may include a trace pattern, a via pattern, or the like. The trace pattern may include a pad pattern connected to the via pattern. The first metal layer 214 may be surrounded by a diffusion prevention layer. The diffusion prevention layer may include at least one material selected from the group including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), tungsten nitride (WN), nickel (Ni), and nickel boron (NiB). If necessary, a plug may be further included, and the plug may be electrically connected to the first transistor element 213 and the first metal layer 214. The plug may include copper (Cu), tungsten (W), or a combination thereof.

[0054] The second semiconductor chip 220 may also include a second semiconductor substrate, a plurality of second transistor elements disposed on the second semiconductor substrate, a second insulating layer disposed on the second semiconductor substrate, and a plurality of second metal layers disposed on or within the second insulating layer. The second metal layers may also include a plurality of second connection pads each having at least a portion exposed from a lower surface of the second insulating layer. A detailed description of the second semiconductor chip 220 is substantially the same as that of the first semiconductor chip 210.

[0055] The first and second semiconductor chips 210 and 220 may be mounted on the package substrate 100 via a plurality of first connection members 430. For example, some of the plurality of first and second connection pads of each of the first and second semiconductor chips 210 and 220 may be connected to the package substrate 100 via the plurality of first connection members 430. Each of the plurality of first connection members 430 may include a metal post, for example, a copper pillar. Each of the plurality of first connection members 430 may further include a low melting point metal, for example, a solder such as tin (Sn)-aluminum (Al)-copper (Cu), etc., disposed on the metal post.

[0056] The interconnect bridge 300 may include a microcircuit for interconnection between the first and second semiconductor chips 210 and 220, more specifically, a microcircuit for die-to-die interconnection. For example, the interconnect bridge 300 may include an organic insulating layer 310, a plurality of metal wiring layers 320 disposed on or within the organic insulating layer 310, and one or more metal via layers 330 disposed within the organic insulating layer 310 and connecting the plurality of metal wiring layers 320 to each other. For example, the interconnect bridge 300 may be an organic bridge. For example, the interconnect bridge 300 may be a high-density printed circuit board including microcircuits. However, if necessary, a silicon bridge may be used as the interconnect bridge 300 instead of the organic bridge.

[0057] The organic insulating layer 310 may include an organic insulating material. The organic insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin obtained by mixing these resins with an inorganic filler such as silica or impregnating a core material of the inorganic filler, for example, prepreg, ABF, FR-4, BT, etc., but is not limited thereto. The number of layers of the organic insulating layer 310 is not particularly limited and may be variously changed according to the design. The organic insulating layers 310 may have distinct boundaries or may be integrated with each other to the extent that the boundaries are unclear.

[0058] The metal wiring layer 320 may include a power transmission line, a signal transmission line, a ground transmission line, etc. Each of these lines may include a trace pattern, a pad pattern, etc. The metal wiring layer 320 may include a conductive material, specifically a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The metal wiring layer 320 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The metal wiring layers 320 disposed on the uppermost and lowermost sides of the metal wiring layer 320 may include a plurality of first and second connection pads, respectively.

[0059] The metal via layer 330 may include a via for power transmission, a via for signal transmission, a via for ground transmission, etc. Each of these vias may include a via pattern, etc. The metal via layer 330 may include a conductive material, specifically a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The metal via layer 330 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The via pattern of the metal via layer 330 may have a tapered shape on the lower side in cross section, but is not limited thereto. The via pattern of the metal via layer 330 may include a micro via. The via pattern of the metal via layer 330 may include a filled via and / or a conformal via. The via pattern of the metal via layer 330 may include stacked vias and / or staggered vias.

[0060] The interconnect bridge 300 may be attached to the first and second semiconductor chips 210 and 220 via a plurality of second connection members 440. For example, the other parts of the plurality of first and second connection pads may be connected to a plurality of first connection pads of the interconnect bridge 300 via a plurality of second connection members 440. Each of the plurality of second connection members 440 may include metal bumps and / or solder bumps. For example, the second connection members 440 may include only metal bumps, only solder bumps, or both metal bumps and solder bumps. The metal bumps may include copper (Cu), and the solder bumps may include solder, but are not limited thereto. The interconnect bridge 300 may be mounted on the package substrate 100 via a plurality of first connection members 430. The plurality of second connection pads of the interconnect bridge 300 may be connected to the package substrate 100 via the above-mentioned plurality of first connection members 430.

[0061] The molding material 410 may protect the first and second semiconductor chips 210 and 220. The molding material 410 may fill the gap between the first and second semiconductor chips 210 and 220 and cover the upper and outer surfaces of each of the first and second semiconductor chips 210 and 220. The material of the molding material 140 is not particularly limited, and may be, for example, EMC (Epoxy Molding Compound), etc.

[0062] The insulating material 420 can attach the first and second semiconductor chips 210, 220 and the interconnect bridge 300 to the package substrate 100, and can protect the plurality of first connection members 430. The insulating material 420 can fill at least a portion between the molding material 410, the first and second semiconductor chips 210, 220, and the interconnect bridge 300, and between the package substrate 100, and can embed and / or cover the plurality of first connection members 430. The material of the insulating material 420 is not particularly limited, and for example, NCF (Non Conductive Film) or the like can be used.

[0063] 8a to 8e are cross-sectional views illustrating steps of a manufacturing method for the semiconductor package of FIG.

[0064] Referring to FIG. 8 a , after the first and second semiconductor chips 210 and 220 are prepared, the first and second semiconductor chips 210 and 220 are covered with a molding material 410 .

[0065] Referring to FIG. 8b, a mask 450 is used to form recesses R penetrating a portion of each of the first and second semiconductor chips 210 and 220 and the molding material 410. The recesses R may be formed by etching or laser processing. Alternatively, a grinding process may be used. If necessary, a stopper layer for forming the recesses R may be present inside the first and second semiconductor chips 210 and 220. The recesses R may include the first to third recesses r1, r2, and r3 described above.

[0066] 8c, the interconnect bridge 300 is prepared through a separate process and then disposed in the recessed portion R. At this time, the interconnect bridge 300 is connected to the first and second semiconductor chips 210 and 220 using a plurality of second connection members 440.

[0067] Referring to FIG. 8 d , a plurality of first connection members 430 are formed on the first and second semiconductor chips 210 and 220 and the interconnect bridge 300 .

[0068] Referring to FIG. 8e, the first and second semiconductor chips 210, 220 and the interconnect bridge 300 are mounted on the package substrate 100 using a plurality of first connection members 430, and an insulating material 420 is used to attach and / or secure them.

[0069] Through a series of processes, the semiconductor package 500A according to the above-described example can be manufactured, and other contents are substantially the same as those described above.

[0070] FIG. 9 is a cross-sectional view that shows a schematic diagram of another example of a semiconductor package, and FIG. 10 is an enlarged cross-sectional view that shows a schematic diagram of an example of region B in FIG.

[0071] Referring to the drawings, in the semiconductor package 500B according to another example, the interconnect bridge 300 in the semiconductor package 500A according to the above example may be directly connected to each of the first and second semiconductor chips 210 and 220. For example, the first connection pads of the interconnect bridge 300 may be directly connected to other parts of the first and second connection pads of each of the first and second semiconductor chips 210 and 220. For example, the direct connection may be made using direct pad-to-pad bonding, but is not limited thereto. Other details are substantially the same as those described above.

[0072] In the present disclosure, the term "cover" can include not only the case of covering entirely, but also the case of covering at least a part, and can include not only the case of covering directly, but also the case of covering indirectly. Furthermore, the term "fill" can include not only the case of filling completely, but also the case of filling almost completely, and can include the case where some gaps or voids are present.

[0073] In the present disclosure, the term "substantially" can be determined by taking into account process errors and positional deviations that occur in the manufacturing process, measurement errors, etc. For example, being substantially flat can include not only being completely flat, but also being roughly flat.

[0074] In the present disclosure, "on a cross section" may refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from a side, and "on a plane" may refer to the planar shape of an object cut horizontally or the planar shape of an object when viewed from a top or bottom.

[0075] In this disclosure, the vertical direction is used to mean the up-down direction based on the cross section of the drawing for convenience, and the horizontal direction is used to mean the left-right direction based on the cross section of the drawing for convenience. In addition, the lower side, lower part, and lower surface are used to mean the lower side based on the cross section of the drawing for convenience, and the upper side, upper part, and upper surface are used to mean the opposite direction. However, this is a definition of the directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of the directions, and the concepts of up / down and left / right can be changed at any time.

[0076] In the present disclosure, the meaning of "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Moreover, the meaning of "electrically connected" includes both physical connection and non-connection. Furthermore, expressions such as "first" and "second" are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly the second component may be named the first component, without departing from the scope of the right.

[0077] The expression "one example" used in the present disclosure does not mean the same embodiment as the other, but is provided to emphasize and describe the unique features that are different from each other. However, the above-mentioned one example does not exclude being realized in combination with the features of another example. For example, even if the matter described in a particular example is not described in another example, it can be understood as being related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0078] The terms used in the present disclosure are merely used to describe an example and are not intended to limit the present disclosure. In this case, the singular expression includes the plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0079] 1000 electronic equipment 1010 Mainboard 1020 Chip related parts 1030 Network related parts 1040 Other parts 1050 Camera 1060 Antenna 1070 display 1080 Battery 1090 Signal Line 1100 Smartphone 1110 Motherboard 1120 parts 1121 Parts Package 1130 Camera Module 1140 Speaker 2110 Mainboard 2210 BGA Board 2220, 2240 Semiconductor chips 2230 Interposer 2250 Silicon Interposer 2260 Organic Interposer 2310, 2320 Semiconductor packages including interposers Semiconductor packages including 500A and 500B bridges 100 Package Substrate 210, 220 Semiconductor chips 211 Semiconductor substrate 212 Insulating layer 213 Transistor element 214 Metal layer 300 Bridge 310 Organic insulating layer 320 Metal wiring layer 330 Metal via layer 410 Molding material 420 Insulation Materials 430, 440 Connection member 450 Mask R, r1, r2, r3 Recessed part

Claims

1. A package substrate; a first semiconductor chip disposed on the package substrate, the first semiconductor chip having a first recess on a first front surface side facing the package substrate; a second semiconductor chip disposed on the package substrate alongside the first semiconductor chip and having a second recess on a second front surface side facing the package substrate; an interconnect bridge disposed on the first front surface and the second front surface, the interconnect bridge having at least a portion disposed in each of the first recessed portion and the second recessed portion.

2. 2. The semiconductor package of claim 1, wherein the first recess portion and the second recess portion vertically penetrate portions of the first semiconductor chip and the second semiconductor chip from the first front surface and the second front surface, respectively, and are exposed from inner surfaces of the first semiconductor chip and the second semiconductor chip so as to face each other horizontally.

3. a molding material that fills at least a portion between the first semiconductor chip and the second semiconductor chip; A third recess portion is disposed below the molding material, The semiconductor package of claim 2 , wherein the first recessed portion and the second recessed portion are connected to each other through the third recessed portion.

4. the molding material covers an outer side surface of each of the first semiconductor chip and the second semiconductor chip; The semiconductor package according to claim 3 , wherein a lower surface of the molding material has a step due to the third recess portion.

5. a plurality of first connection members that connect the first semiconductor chip, the second semiconductor chip, and the interconnect bridge to the package substrate, respectively; 4. The semiconductor package of claim 3, further comprising: an insulating material that fills spaces between the molding material, the first semiconductor chip, the second semiconductor chip, and the interconnect bridge and the package substrate, and covers the plurality of first connection members.

6. The semiconductor package according to claim 5 , wherein each of the plurality of first connection members includes a metal post.

7. The semiconductor package of claim 1 , further comprising a plurality of second connection members coupling the interconnect bridge to each of the first semiconductor chip and the second semiconductor chip.

8. The semiconductor package according to claim 7 , wherein each of the second connection members includes at least one of a metal bump and a solder bump.

9. The semiconductor package of claim 1 , wherein the interconnect bridge is directly coupled to each of the first semiconductor chip and the second semiconductor chip.

10. A package substrate; a first semiconductor chip and a second semiconductor chip disposed on the package substrate; a molding material disposed on the package substrate and filling at least a portion between the first semiconductor chip and the second semiconductor chip; a recess portion that penetrates a portion of each of the first semiconductor chip, the second semiconductor chip, and the molding material in a vertical direction from a lower surface of each of the first semiconductor chip, the second semiconductor chip, and the molding material; an interconnect bridge disposed in the recess.

11. a bottom surface of the recessed portion including lower surfaces of the first semiconductor chip, the second semiconductor chip, and the molding material, and a wall surface of the recessed portion including inner side surfaces of the first semiconductor chip and the second semiconductor chip, The semiconductor package of claim 10 , wherein a bottom surface of the recess is substantially flat.

12. the first semiconductor chip includes a first semiconductor substrate, a plurality of first transistor elements disposed on the first semiconductor substrate, a first insulating layer disposed on the first semiconductor substrate, and a plurality of first metal layers disposed on or within the first insulating layer, the second semiconductor chip includes a second semiconductor substrate, a plurality of second transistor elements disposed on the second semiconductor substrate, a second insulating layer disposed on the second semiconductor substrate, and a plurality of second metal layers disposed on or within the second insulating layer, 11. The semiconductor package of claim 10, wherein the first metal layers and the second metal layers each include a first connection pad and a second connection pad, at least a portion of which is exposed from the lower surfaces of the first insulating layer and the second insulating layer, respectively.

13. the interconnect bridge includes an organic insulating layer, a plurality of metal wiring layers disposed on or within the organic insulating layer, and one or more metal via layers disposed within the organic insulating layer and connecting the plurality of metal wiring layers to each other; The uppermost and lowermost metal wiring layers among the plurality of metal wiring layers each include a plurality of first connection pads and a plurality of second connection pads, The semiconductor package of claim 12 , wherein at least a portion of each of the first and second connection pads is coupled to the first connection pads.

14. At least another portion of each of the first connection pads and the second connection pads is connected to the package substrate via a plurality of first connection members; The semiconductor package of claim 13 , wherein the plurality of first connection members are embedded in an insulating material.

15. The semiconductor package of claim 14 , wherein at least a portion of each of the first connection pads and the second connection pads is connected to the first connection pads via a plurality of second connection members.

16. The semiconductor package of claim 14 , wherein at least a portion of each of the first and second connection pads is directly connected to the first connection pads.

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