Small-sized transistor structure with controlled dimensions of source / drain and contact opening and related manufacturing method

Abstract

To provide a transistor structure capable of having accurately controlled lengths of a source / drain and a contact opening for effectively reducing a size of the transistor structure, and a related manufacturing method.SOLUTION: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first insulation region. The semiconductor substrate comprises a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first insulation region is adjacent to the first conductive region. A length of the first conductive region between the gate structure and the first insulation region is controlled by a single photolithography process which is configured at the beginning to define the length of the gate structure.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to to Transistor structure and related manufacturing method Specifically, the present invention relates to a transistor structure that can have precisely controlled dimensions of source / drain and contact openings to effectively reduce the size of the transistor structure. do. [Background technology]

[0002] Since the design guidelines for shrinking all dimensions of metal oxide semiconductor field effect transistors (MOSFETs) were disclosed in a paper published by R. Dennard, et al. in 1974, how to shrink the size of transistors is the main technological requirement that has changed the minimum physical feature size of the linear dimensions of silicon wafers from a few micrometers to a few nanometers. The minimum feature size or length, usually called Lambda (λ), is determined by the microminiaturization capability using photolithographic masking techniques with device scaling techniques (measured by the minimized printed line-width resolution, also called λ for ease of illustration and comparison). However, another difficult-to-control factor that limits device shrink is the so-called misalignment tolerance, or Delta-Lambda (Δλ), which is caused by both insufficiency and inaccuracy of photolithographic equipment. Furthermore, due to the misalignment tolerance, it is difficult to make the distance between the gate edge of the transistor and the source (or drain) edge of the transistor smaller than the sum of λ and Δλ. If it is then required to make a square contact hole in the drain (or source) for the connection between the future metal interconnect to the drain (or source) by again using photolithographic masking techniques, it is difficult to make the minimum size of the square contact hole smaller than λ on both sides of the square contact hole. Furthermore, by including the misalignment tolerance of ensuring a square contact hole in the drain, it is difficult to make the length of each edge of the drain (having a rectangular shape) smaller than the sum of λ and Δλ.However, reducing the size of transistors is essential to integrate more transistors in a planar area of ​​a silicon wafer, and a necessary and effective way to achieve the above-mentioned goal is to reduce the area occupied by the source and drain of a transistor, respectively, which can also help reduce leakage current and power consumption.

[0003] Therefore, how to effectively reduce the size of transistors in order to integrate more transistors in a planar area of ​​a silicon wafer has become an important issue for transistor designers. Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first insulating region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first insulating region is adjacent to the first conductive region. The length of the first conductive region between the gate structure and the first insulating region is controlled by a single photolithography process that is initially configured to define the length of the gate structure. [Means for solving the problem]

[0005] According to another aspect of the invention, a length of the first conductive region is substantially equal to a length of the gate structure.

[0006] Another embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first contact hole is electrically connected to the first conductive region. The periphery of the first contact hole is independent of the photolithography process, and the periphery of the first contact hole is within the periphery of the first conductive region.

[0007] According to another aspect of the present invention, the periphery of the first contact hole is surrounded by the periphery of the first conductive region.

[0008] Another embodiment of the present invention provides a manufacturing method for a transistor, the transistor including a gate structure, a channel region, and a first conductive region electrically coupled to the channel region, the manufacturing method includes performing a first photolithography process configured to define a width of the gate structure and a pseudo-length of an active region, and performing a second photolithography process configured to define a length of the gate structure within the active region, the second photolithography process further configured to control a length of the first conductive region between the gate structure and the insulating region.

[0009] According to another aspect of the invention, the pseudo-length of the active area defined by the first photolithography process is about four times the length of the gate structure.

[0010] Another embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first contact hole is positioned above the first conductive region. The first contact hole includes a perimeter surrounded by an outer perimeter of the first conductive region, and a shape of the perimeter of the first contact hole is similar to a shape of the outer perimeter of the first conductive region.

[0011] According to another aspect of the invention, the perimeter of the first conductive region is shaped like a rectangle.

[0012] Another embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first contact hole is positioned above the first conductive region. The length of the first contact hole is less than the length of the gate structure, and a horizontal distance between a sidewall of the gate structure and a sidewall of the first contact hole away from the gate structure is less than the length of the gate structure.

[0013] According to another aspect of the invention, a horizontal distance between a sidewall of the gate structure and a sidewall of the first conductive region that is remote from the gate structure is no greater than a length of the gate structure.

[0014] According to another aspect of the invention, a horizontal distance between a sidewall of the gate structure and a sidewall of the first conductive region remote from the gate structure is approximately equal to a length of the gate structure.

[0015] Another embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first insulating region, a first spacer, a second spacer, a first conductive region, and a first contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The channel region is below the semiconductor surface. The first insulating region extends upward and downward from the semiconductor surface. The first spacer covers a first sidewall of the gate structure and the second spacer covers a sidewall of the first isolation region. The first conductive region is electrically coupled to the channel region and positioned between the gate structure and the first insulating region. The first contact hole is above the first conductive region, and the first contact hole is formed between the first spacer and the second spacer.

[0016] In accordance with another aspect of the invention, the transistor structure further includes a cap layer and a first metal region, the cap layer covering the gate structure, the first metal region filling the first contact hole and contacting the first conductive region, the first metal region extending upwardly from the first conductive region to a predetermined location above a top of the cap layer.

[0017] According to another aspect of the invention, the width of the first metal region is substantially equal to the length of the first contact hole plus the length of the gate structure.

[0018] According to another aspect of the invention, the transistor structure further includes a second insulating region and a second conductive region. The second insulating region extends upward and downward from the semiconductor surface. The second conductive region is electrically coupled to the channel region and is positioned between the gate structure and the second isolation region.

[0019] According to another aspect of the invention, a horizontal distance between the second sidewall of the gate structure and a sidewall of the second insulating region remote from the gate structure is substantially equal to a length of the gate structure.

[0020] According to another aspect of the present invention, the transistor structure further includes a second contact hole positioned above the second conductive region, the second contact hole having a length less than a length of the gate structure.

[0021] According to another aspect of the present invention, the transistor structure further includes a third spacer and a fourth spacer, the third spacer covering a second sidewall of the gate structure, the fourth spacer covering a sidewall of the second insulating region, and the second contact hole is formed between the third spacer and the fourth spacer.

[0022] According to another aspect of the invention, the second conductive region includes a second metal-containing region in the recessed surface below the silicon surface and a second highly doped semiconductor region in the recessed surface.

[0023] According to another aspect of the invention, the transistor structure further includes a second guard insulating layer in the recess and contacting a sidewall of the second metal-containing region, the second metal-containing region being coupled to the semiconductor substrate through a bottom surface of the second metal-containing region.

[0024] Another embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The length of the first conductive region is controlled by a single photolithography process that is initially configured to define the length of the gate structure.

[0025] According to another aspect of the invention, a length of the first conductive region is substantially equal to a length of the gate structure.

[0026] Another embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first contact hole is positioned above the first conductive region. The periphery of the first contact hole is independent of the photolithography process.

[0027] According to another aspect of the present invention, the periphery of the first contact hole is surrounded by the periphery of the first conductive region.

[0028] Another embodiment of the present invention provides a transistor structure including a semiconductor substrate having a semiconductor surface, a gate structure, a channel region beneath the gate structure, a first conductive region electrically coupled to the channel region, and a contact hole positioned above the first conductive region, the contact hole having a length less than a minimum feature length.

[0029] According to another aspect of the invention, the horizontal distance between a sidewall of the gate structure and a sidewall of the contact hole remote from the gate structure is less than the minimum feature length.

[0030] According to another aspect of the invention, a horizontal distance between a sidewall of the gate structure and a sidewall of the first conductive region remote from the gate structure is approximately equal to a minimum feature length.

[0031] Another embodiment of the present invention provides a manufacturing method for a transistor, the transistor including a gate structure and a first conductive region, the manufacturing method includes forming an active area based on a substrate, forming a gate structure and a dummy shield gate structure above the active area, forming a first insulating region to replace the dummy shield gate structure, forming a self-aligned pillar above the active area, removing the self-aligned pillar, and forming a first conductive region between the gate structure and the first insulating region.

[0032] According to another aspect of the invention, prior to the step of removing the self-aligned pillar, the manufacturing method further includes a step of forming a second isolation region above the first isolation region, the self-aligned pillar being between the gate structure and the second insulating region.

[0033] According to another aspect of the invention, after removing the self-aligned pillars, the manufacturing method further includes forming a spacer between the gate structure and the first isolation region to define a contact hole, the contact hole being above the first conductive region.

[0034] According to another aspect of the invention, the length of the contact hole is less than the minimum feature length.

[0035] According to another aspect of the invention, the substrate is a silicon substrate and the self-aligned pillars are intrinsic silicon pillars formed by selective epitaxy growth.

[0036] Another embodiment of the present invention provides a manufacturing method for a transistor, the transistor including a gate structure and a first conductive region, the manufacturing method includes forming an active region based on a substrate, forming a gate structure based on the active region, and forming a self-aligned pillar configured to allocate a contact hole above the first conductive region.

[0037] According to another aspect of the present invention, the manufacturing method further includes forming an isolation region based on the active region before forming the self-aligned pillars.

[0038] According to another aspect of the invention, the manufacturing method further includes removing the self-aligned pillar formed between the gate structure and the isolation region, and forming a spacer between the gate structure and the isolation region to define a contact hole, the contact hole being above the first conductive region.

[0039] According to another aspect of the invention, the length of the contact hole is less than the minimum feature length.

[0040] Another embodiment of the present invention provides a manufacturing method for a transistor, the transistor including a gate structure and a first conductive region, the manufacturing method includes forming an active region based on a substrate, forming a gate structure above the active region, forming the first conductive region adjacent to the gate structure, and defining a contact hole above the first conductive region, the defining the contact hole being independent of a photolithography process.

[0041] According to another aspect of the invention, a first conductive region is formed between a gate structure and an isolation region that extends above an active region.

[0042] According to another aspect of the invention, the contact holes are defined by forming spacers covering the sidewalls of the gate structure and the sidewalls of the isolation region.

[0043] According to another aspect of the invention, the length of the contact hole is less than the minimum feature length.

[0044] Another embodiment of the present invention provides a manufacturing method for a transistor, the transistor including a gate structure and a first conductive region, the manufacturing method includes forming an active region based on a substrate, forming a gate structure based on the active region, forming a first conductive region adjacent to the gate structure, and forming a contact hole above the first conductive region without using a photolithography process to define a shape of the contact hole.

[0045] According to another aspect of the invention, the first conductive region is a gate structure. insulation It is formed between the region.

[0046] According to another aspect of the present invention, the contact hole is formed by forming a contact hole on the sidewall of the gate structure and insulation The region is defined by forming spacers that cover the sidewalls of the region.

[0047] According to another aspect of the invention, the length of the contact hole is less than the minimum feature length. [Brief description of the drawings]

[0048] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0049] [Figure 1] FIG. 1 illustrates a top view of a miniaturized metal-oxide-semiconductor field effect transistor (mMOSFET) in accordance with an embodiment of the present invention.

[0050] [Figure 2A] 1 is a flowchart illustrating a method for manufacturing an mMOSFET in accordance with another embodiment of the present invention.

[0051] [Figure 2B] FIG. 2A is a diagram showing the configuration of FIG. [Figure 2C] FIG. 2A is a diagram showing the configuration of FIG. [Figure 2D] FIG. 2A is a diagram showing the configuration of FIG. [Figure 2E] FIG. 2A is a diagram showing the configuration of FIG. [Figure 2F] FIG. 2A is a diagram showing the configuration of FIG.

[0052] [Diagram 3] FIG. 1 shows a top view of the pad nitride layer and STI-oxide 1.

[0053] [Figure 4] 4 is a cross-sectional view taken along the X direction shown in FIG. 3. FIG.

[0054] [Diagram 5] FIG. 13 illustrates the photolithography misalignment tolerance (PMT) for aligning the edge of the gate structure with the edge of the interface between the source of the mMOSFET and STI-Oxide 1.

[0055] [Figure 6] FIG. 1 shows a new structure that can eliminate the above-mentioned negative effects of PMT.

[0056] [Figure 7] FIG. 2 shows a spin-on dielectric (SOD) being deposited.

[0057] [Figure 8] FIG. 1 shows a well-designed gate mask layer being deposited and etched.

[0058] [Figure 9] FIG. 2 illustrates a dummy shield gate (DSG), a nitride layer, a dielectric insulator, and a p-type substrate corresponding to the DSG being removed by anisotropic etching techniques.

[0059] [Figure 10] FIG. 13 shows the gate mask layer being removed, the SOD layer being etched, and the oxide 2 layer being deposited to form STI-oxide 2.

[0060] [Figure 11] FIG. 13 is a diagram showing the relationship between the position of a real gate (TG) and the position of a dummy shield gate. [Figure 12] FIG. 13 is a diagram showing the relationship between the position of a real gate (TG) and the position of a dummy shield gate. [Figure 13] FIG. 13 is a diagram showing the relationship between the position of a real gate (TG) and the position of a dummy shield gate. [Figure 14] FIG. 13 is a diagram showing the relationship between the position of a real gate (TG) and the position of a dummy shield gate.

[0061] [Figure 15] FIG. 1 illustrates an oxide 3 layer being deposited and etched to form oxide 3 spacers, a lightly doped drain (LDD) formed in a p-type substrate, a nitride layer being deposited and etched back to form nitride spacers, and the dielectric insulator being removed.

[0062] [Figure 16] FIG. 1 shows an intrinsic silicon electrode grown by selective epitaxy growth (SEG) technique.

[0063] [Figure 17]FIG. 1 shows the CVD-STI-Oxide 3 layer being deposited and etched back, the intrinsic silicon electrode being removed, and the source (n+ source) and drain (n+ drain) of the mMOSFET being formed.

[0064] [Figure 18] FIG. 13 shows oxide spacers being deposited and etched to form contact hole openings.

[0065] [Figure 19] FIG. 2 shows a metal 1 layer being deposited and etched to form metal 1 interconnects.

[0066] [Figure 20] FIG. 1 illustrates a metal 1 interconnect being formed and a source and drain being formed by using a merged semiconductor junction and metal conductor (MSMC) structure according to another embodiment of the present invention.

[0067] [Figure 21] FIG. 1 shows that the gate mask layer is removed, then an oxide 2 layer is deposited to fill trenches and other voids on the horizontal silicon surface (HSS) to form STI-oxide 2, and then the STI-oxide 2 is planarized by chemical mechanical polishing (CMP).

[0068] [Figure 22] FIG. 1 illustrates an oxide 3 layer being deposited and etched to form oxide 3 spacers, a lightly doped drain (LDD) formed in a p-type substrate, a nitride layer being deposited and etched back to form nitride spacers, and the dielectric insulator being removed.

[0069] [Figure 23] FIG. 1 shows an intrinsic silicon electrode grown by selective epitaxy growth (SEG) technique.

[0070] [Figure 24] FIG. 13 shows oxide spacers being deposited and etched to form contact hole openings.

[0071] [Diagram 25] FIG. 2 shows a metal 1 layer being deposited and etched to form metal 1 interconnects. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0072] The present invention discloses a new method to precisely control the linear dimensions of the source (or drain) of a transistor, which can be as small as the minimum feature size, Lambda (λ), that can be printed or created on a wafer (e.g., silicon wafer) without adding misalignment tolerance, Delta-Lambda (Δλ). Moreover, contact holes with linear dimensions smaller than λ can be achieved in the drain (or source). Thus, the present invention leads to a new structure of source and drain, with a minimum feature size from the edge of the transistor's gate to the edge of the source (or drain) adjacent to the edge of the transistor isolation, and with contact holes at the source and drain with linear dimensions less than λ. Thus, the present invention avoids the misalignment tolerance caused by photolithographic masking techniques in forming both the source and drain, respectively.

[0073] See Figure 1. Figure 1 illustrates a top view of a miniaturized metal-oxide-semiconductor field-effect transistor (mMOSFET) 100 in accordance with one embodiment of the present invention. As shown in FIG. 1 , mMOSFET 100 includes: (1) gate structure 101 having length G(L) and width G(W); (2) to the left of gate structure 101, source 103 having length S(L) and width S(W), which are the linear dimensions from the edge of gate structure 101 to the edge of isolation region 105; (3) to the right of gate structure 101, drain 107 having length D(L) and width D(W), which are the linear dimensions from the edge of gate structure 101 to the edge of isolation region 105; (4) at the center of source 103, contact hole 109 formed by self-alignment technology has an opening length and width marked CS(L) and CS(W), respectively; and (5) similarly, at the center of drain 107, contact hole 111 formed by self-alignment technology has an opening length and width marked CD(L) and CD(W), respectively.

[0074] To form the mMOSFET 100, a first photolithography process can be used to define the width G(W) and pseudo length of the active area, and a second photolithography process can be used to define the length G(L) of the active area, which is further used to control the length S(L) between the gate structure 101 and the isolation region 105, and in one example, the pseudo length of the active area defined by the first photolithography process is about four times the minimum feature length λ. In one embodiment, the length G(L) can be equal to or substantially equal to the minimum feature length λ. Of course, in another example, the length G(L) can be greater than the minimum feature length λ.

[0075] A first feature of the present invention is that both the length S(L) and the length D(L) can be precisely designed and defined according to the target dimensions that can be produced on the surface of the wafer without being affected by unavoidable photolithographic misalignment tolerances (PMT).

[0076] A second feature of the present invention is that both the length S(L) and the length D(L) can be as small as the minimum feature length λ, which is the process limit defined at the process node (e.g., the minimum length S(L) or the minimum length D(L) is 7 nm for a specified 7 nm node, 28 nm for a specified 28 nm node, or 180 nm for a specified 180 nm node, respectively).

[0077] A third feature of the present invention is that if length G(L) is designed to be λ, then the smallest dimension along the length of mMOSFET 100 (i.e., the distance from the left edge of source 103 to the right edge of drain 107) can be as small as 3λ (i.e., 1λ for length S(L), 1λ for length D(L), and 1λ for length G(L). Then, when not including isolation region 105, mMOSFET 100 can be scaled down to only 3λ to achieve a linear dimension along the length of mMOSFET 100.

[0078] The fourth feature of the present invention is that the well-defined lengths S(L) and D(L) by the self-alignment technique can produce narrower lengths CS(L) of the contact holes 109 and CD(L) of the contact holes 111, respectively, without being limited by photolithographic misalignment tolerances, because the most critical masking step of producing the contact holes 109, 111 is eliminated. Moreover, the deposited interconnect layer of metal 1, which can be fully filled into the contact holes 109, 111 to form native metal contacts connecting metal 1 to both the source 103 and the drain 107, respectively, can be effectively defined by photolithographic masking techniques to achieve a narrow width of metal 1 (i.e., the sum of the contact hole opening and twice the PMT).

[0079] The above-described invention allows MOSFET structures to be scaled to the smallest device linear dimensions (including metal 1 isolation and interconnects) without being magnified by unavoidable photolithographic misalignment tolerances.

[0080] See Figures 2A-2F, 3, 4, 6-19. Figure 2A is a flow chart showing a method for fabricating an mMOSFET according to one embodiment of the present invention, which can produce an mMOSFET with precisely controllable lengths at both the source and drain of the mMOSFET. The detailed steps are as follows:

[0081] Step 10: Get started.

[0082] Step 20: Based on the substrate 102, an active region and a trench structure are formed.

[0083] Step 30: Form true gates and dummy shield gates of the mMOSFET above the horizontal silicon surface (HSS) of the substrate 102.

[0084] Step 40: The dummy shield gate is replaced with an isolation region to define the source / drain region boundaries.

[0085] Step 50: Form source and drain regions of the mMOSFET.

[0086] Step 60: Form smaller contact holes in the boundaries of the source and drain regions, and form a metal 1 interconnect through the contact hole to contact the source or drain region.

[0087] Step 70: End.

[0088] See Figure 2B and Figures 3 and 4. Step 20 may include:

[0089] Step 202 : A pad oxide layer 302 is formed and a pad nitride layer 304 is deposited on the substrate 102 .

[0090] Step 204: The active area of ​​the mMOSFET is defined, and a portion of the silicon material outside the active area is removed to create a trench structure.

[0091] Step 206: An oxide 1 layer is deposited in the trench structure and etched back to form shallow trench isolation (STI-Oxide 1) 306 below the HSS.

[0092] Step 207: The pad oxide layer 302 and the pad nitride layer 304 are removed and a dielectric insulator 402 is formed over the HSS.

[0093] See Figures 2C and 6. Step 30 may include:

[0094] Step 208: A gate layer 602 and a nitride layer 604 are deposited over the HSS.

[0095] Step 210: The gate layer 602 and nitride layer 604 are etched to form the true gate of the mMOSFET and a dummy shield gate having a desired linear distance to the true gate.

[0096] See Figure 2D and Figures 7 to 10. Step 40 may include:

[0097] Step 212: Deposit spin-on dielectrics (SOD) 702 and then etch back the SOD 702.

[0098] Step 214: Form a well-designed gate mask layer 802 by photolithography masking technology.

[0099] Step 216: Using an anisotropic etching technique, the nitride layer 604 above the dummy shield gate (DSG) is removed, and the DSG, a portion of the dielectric insulator 402 corresponding to the DSG, and the p-type substrate 102 corresponding to the DSG are removed.

[0100] Step 218: Remove gate mask layer 802, etch SOD 702, deposit STI-oxide 2 1002, then etch back.

[0101] See Figure 2E and Figures 15-17. Step 50 may include:

[0102] Step 220: deposit and etch back an oxide 3 layer to form oxide 3 spacers 1502, form lightly doped drains (LDDs) 1504 in the p-type substrate 102, deposit and etch back a nitride layer to form nitride spacers 1506, and remove the dielectric insulator 402.

[0103] Step 222: Grow the intrinsic silicon electrode 1602 using selective epitaxy growth (SEG) techniques.

[0104] Step 224: Deposit and etch back a CVD-STI-Oxide 3 layer 1702, remove the intrinsic silicon 1602, and form the source region (n+ source) 1704 and the drain region (n+ drain) 1706 of the mMOSFET.

[0105] See Figure 2F and Figures 18 and 19. Step 60 may include:

[0106] Step 226: Deposit and etch oxide spacers 1802 to form contact hole openings above the source and drain regions.

[0107] Step 228: Deposit and etch metal 1 layer 1902 to form metal 1 interconnects.

[0108] Part I. Utilizing a dummy shield gate (DSG) added on the gate level mask, it is achieved to make the designed distance from the gate edge to the boundary edge between the source and isolation region (GEBESI) sharply on the wafer as well as on the drain (GEBEDI) by avoiding the photolithography misalignment tolerance (PMT).

[0109] Taking an n-type MOSFET as an example, the substrate 102 is a p-type substrate 102, and a detailed description of the above manufacturing method is as follows. Starting at step 20, please refer to FIG. 2B as well as FIG. 3 and FIG. 4. In step 202, a pad oxide layer 302 is formed on the HSS of the p-type substrate 102, and then a pad nitride layer 304 is deposited on the pad oxide layer 302.

[0110] In step 204, the active areas of the mMOSFETs can be defined by photolithographic masking techniques, and the HSS outside the active areas is correspondingly exposed. With the HSS outside the active area pattern exposed, portions of the silicon material outside the active areas can be removed by anisotropic etching techniques to form trench structures.

[0111] In step 206, an oxide 1 layer is deposited to completely fill the trench structure, and then the oxide 1 layer is etched back to form STI-oxide 1 306 below the HSS, as shown in FIG. 4. FIG. 4 is a cross-sectional view along the X direction shown in FIG. 3. In addition, FIG. 3 shows only the pad nitride layer 304 and STI-oxide 1 306, since FIG. 3 is a top view. Next, in step 207, the pad oxide layer 302 and the pad nitride layer 304 on the active area are removed, and a dielectric insulator 402 (having a high K) is formed on top of the HSS.

[0112] FIG. 5 shows a typical state-of-the-art design and processing method to achieve the geometrical relationship between the gate region and the transistor isolation region (STI) at smaller dimensions. After a dielectric insulator 402 (with high K) is formed on the HSS, a gate layer 404 (metal gate) is deposited above the dielectric insulator 402, and then a nitride layer 406 (nitride cap) with a well-designed thickness is deposited above the gate layer 404. Then, as shown in FIG. 5, photolithography masking techniques are utilized to define an area for the gate structure 1, which includes the gate layer 404 and the nitride layer 406, so that the gate structure 1 has a suitable metal gate material that delivers the required work function of MIS (metal insulator to substrate) to achieve a suitable threshold voltage of the mMOSFET. In addition, the STI-oxide 1 306 is made below the HSS, so that a Tri-gate or fin field effect transistor (FinFET) structure (shown in FIG. 5) is formed.

[0113] After a first photolithography process is utilized to define the pseudo length of the active area and a second photolithography process is utilized to define the length G(L) in the active area, the distance from the edge of the gate structure to the edge of the boundary between the source of the mMOSFET (or the drain of the mMOSFET) and the shallow trench isolation, referred to as GEBESI (or GEBEDI), can be defined as shown in FIG. 5.

[0114] However, as shown in FIG. 5, there exists an unavoidable non-ideal factor called photolithographic misalignment tolerance (PMT) during the photolithographic masking technique for aligning the edge of the gate structure 1 with the edge of the boundary between the source of the mMOSFET and the STI-oxide 1 306 (which is also on the other side of the drain of the mMOSFET). If the PMT measured in the linear dimension along the X-direction is Δλ, then Δλ must be correlated to the minimal feature size as determined by the photolithographic resolution of the equipment available for a specified processing node. For example, a 7 nm process node must have λ equal to 7 nm, and the Δλ of the PMT must be on the order of 3.5 nm. Thus, if the desired actual physical length of the source of the mMOSFET (or the drain of the mMOSFET) targets λ (e.g., 7 nm), then the design length of the source of the mMOSFET (or the drain of the mMOSFET) under the prior art process method must be greater than the sum of λ and Δλ (e.g., >10.5 nm).

[0115] Therefore, the present invention utilizes a new structure that can eliminate the above-mentioned negative effects of the PMT, i.e., every dimension of the distance from the edge of the gate structure to the edge of the boundary between the source of the mMOSFET (or the drain of the mMOSFET) and the shallow trench isolation called GEBESI (or GEBEDI) is preferably achieved, without having to leave extra dimension for the PMT along the length of the mMOSFET 100 (i.e., the X-direction shown in Figures 4 and 5).

[0116] In step 208, as shown in FIG. 6, a dielectric insulator 402 (with high K) is formed on the HSS, followed by depositing a gate layer 602 and a nitride layer 604. Then, in step 210, the gate layer 602 and the nitride layer 604 are etched to construct a gate structure (the gate layer 602 can be the gate structure of an mMOSFET). The main difference between the new structure shown in FIG. 6 and the structure shown in FIG. 5 is that when the true gate (TG) of an mMOSFET is defined by photolithographic masking technology, a dummy shield gate (DSG) is also defined parallel to the desired TG, so that a target linear distance (e.g., λ, such as 7 nm in a 7 nm process node) exists between the DSG and the TG without leaving extra dimension (i.e., Δλ) for the PMT. Both the DSG and TG designed on the same mask can be simultaneously formed on top of the dielectric insulator 402 covering the active area. In addition, as shown in FIG. 6, TG2 and TG3 correspond to other mMOSFETs.

[0117] The following steps describe how to replace the dummy shield gate with an isolation region that is elevated above the HSS. In step 212, as shown in FIG. 7, SOD 702 is deposited and etched back using chemical mechanical polishing (CMP) techniques to make the top of SOD 702 flush with the top of nitride layer 604.

[0118] In step 214, as shown in FIG. 8, a gate mask layer 802 is deposited, and then the gate mask layer 802 is etched by photolithographic masking techniques to achieve a target (FIG. 8) of covering TG, TG2, TG3, but exposing DSG with a safe PMT margin Δλ in the middle of such lengths of GEBESI and GEBEDI.

[0119] For clarity, the distance between the TG and its left DSG (right DSG) under the gate mask layer 802 in Fig. 8 can also be marked as GEBESI (or GEBEDI), because after replacing the DSG by an isolation region as described in Figs. 9-10 below, the distance between the TG and DSG in Fig. 8 becomes the distance from the edge of the TG to the edge of the boundary between the source of the mMOSFET (or the drain of the mMOSFET) and the isolation region, as GEBESI (or GEBEDI) as mentioned above in Fig. 5.

[0120] In step 216, as shown in FIG. 9(a), anisotropic etching technique is used to etch the DSG and the nitride layer 604 corresponding to the DSG, and further to etch a part of the dielectric insulator 402 corresponding to the DSG to reach the HSS, and then anisotropic etching technique is used to remove the silicon material of the p-type substrate 102 below the HSS to form a trench 902 below the HSS, and the depth of the trench 902 can be equal to the depth of the bottom of the STI-oxide 1 306. Thus, as shown in FIG. 9(a), PMT is avoided in the creation of precisely controlled lengths of GEBESI and GEBEDI, respectively. Since the lengths of GEBESI and GEBEDI are clearly defined by TG and DSG on the same mask, both the length S(L) of the source region and the length D(L) of the drain region shown in FIG. 1 are thus clearly defined and created. That is, this single photolithography masking technique is not only used to define TG and DSG, but also to control the lengths of GEBESI and GEBEDI. Therefore, the dimensions of length S(L) and length D(L) can be precisely controlled to achieve optimally minimized dimensions even as small as the minimum feature size λ. Since length S(L) and length D(L) can be equal to λ, length S(L) and length D(L) are substantially equal to the length of the TG (i.e., the gate structure). In addition, FIG. 9(b) is a top view corresponding to FIG. 9(a).

[0121] In step 218, the gate mask layer 802 and SOD 702 are removed, as shown in Figure 10(a). Next, an STI-oxide 2 layer 1002 can be deposited to fill the trench 902 and other voids above the HSS, and the STI-oxide 2 layer 1002 can be etched back to a surface level equal to the HSS, as shown in Figure 10(a). Figure 10(b) is a top view corresponding to Figure 10(a).

[0122] The temporarily formed DSG is then replaced by an STI-Oxide 2 layer 1002 to define the boundaries of the source / drain regions. The mMOSFET can then be completed using any existing method to form the lightly doped drain (LDD), spacers surrounding the TG, source and drain regions, with the source and drain regions being formed according to precisely controlled GEBESI and GEBEDI, respectively.

[0123] Part II. Adaptive Dummy Shield Gate (DSG) Design The Dummy Shield Gate (DSG) design principle for variable shape of active area (on active area (AA) mask) is used to achieve the target length of GEBESI and GEBEDI, respectively.

[0124] Since the shape of the isolation region of a transistor and the location of the isolation region from a transistor to an adjacent transistor can be quite different (even from the above embodiment), another structure invention on how to design an adaptive DSG by extending the principles of the above embodiment is described below.

[0125] FIG. 11 shows different geometrical situations where the active areas of adjacent transistors are arranged differently than in FIG. 6. For example, as shown in FIG. 6, adjacent active areas of adjacent transistors are made to be connected before true gate (TG), true gate 2 (TG2), true gate 3 (TG3) and dummy shield gate (DSG) are deposited, and then DSG is used to divide the connected active areas into individual precisely targeted distances by the length of the DSG. However, as shown in FIG. 11, the active areas on the source (or drain) of the transistor are assumed to be completely isolated (by isolation region 1102) from any other active areas before and after the TG of the transistor is defined. Therefore, what is proposed here is how to design both the active areas on the source side and (similarly for the drain) an adaptive DSG as described below. For example, if the final length of the GEBESI is targeted at λ (or any other target length L(S)), the length of the active area mask ("AA mask") corresponding to the GEBESI side must be designed to be equal to the sum of λ and Δλ (or the sum of the length L(S) and Δλ). Then, on the gate mask, the DSG can have a shape as shown in FIG. 11. That is, the rectangular shape of the DSG has a length equal to λ and a width equal to the width of the active area plus 2Δλ (each side shares 0.5Δλ, respectively). The designed distance between the TG and the DSG on the source side is still only the length of the GEBESI, e.g., λ.

[0126] The results derived from the mask level of the active area and gate of FIG. 11 on the wafer level are shown in FIG. 12. As shown in FIG. 12, when the TG is defined by photolithographic masking techniques, the DSG is made parallel to the TG with a target distance between the DSG and the TG (e.g., λ, such as 7 nm in the 7 nm process node). With a nominal process result (i.e., no significant misalignment is induced by the photolithographic process), the DSG partially covers the active area (corresponding to the source) by a distance Δλ, and both the TG and the DSG are printed on top of the dielectric insulator 402 covering the active area. On top of both the TG and the DSG is a nitride cap layer.

[0127] If the PMT causes a shift (e.g., Δλ) of both the TG and DSG toward the right side of the active area (FIG. 13), then the subsequent processing step of removing the DSG to achieve an isolation region (i.e., STI-oxide 2) exactly at the location of this previously existing DSG location as described by the previous processing steps in Part I should result in an STI-oxide 2 layer with length λ, which becomes the physical geometry of the source region with a GEBESI length equal to λ (because the distance between the TG and DSG is designed to be equal to λ). On the other hand, if the PMT causes a shift (e.g., Δλ) of both the TG and DSG toward the left side of the active area (FIG. 14), then the subsequent processing step of removing the DSG and forming the STI-oxide 2 layer will result in an STI-oxide 2 layer with length λ, and the source region will still have its GEBESI length equal to λ.

[0128] When PMT causes an undesired shift along the width direction (i.e., up or down) of the active area, the design of such an adaptive dummy shield gate with a width of the active area plus 2Δλ must not affect the geometric dimensions of the active area. The new design using the adaptive dummy shield gate can always result in an STI-oxide 2 with a length λ and a length of GEBESI that match the designed target (e.g., narrow as λ). The present invention can be reliably applied to all the various shapes of source and drain isolation regions, each with their respective individual target lengths.

[0129] Part III. Precisely defined source (or drain) regions allow for precisely controlled contact hole openings with self-aligned spacers eliminating contact mask and hole opening process steps.

[0130] After disclosing how both GEBESI and GEBEDI can be optimally designed and manufactured to precisely controlled small dimensions (which can be as small as λ), another new invention is how to create dimensions smaller than the respective lengths of GEBESI and GEBEDI (referred to as length CS(L) and length CD(L) as defined in FIG. 1, respectively). Two design and process formulations are described below.

[0131] A. Design and Process (I)

[0132] Continuing with FIG. 10(a), by utilizing TG, in step 220, as shown in FIG. 15(a), an oxide 3 layer is deposited and etched back to form an oxide 3 spacer 1502, which covers the TG, by the following description. Then, a lightly doped zone is formed in the p-type substrate 102, and rapid thermal annealing (RTA) is performed on the lightly doped zone to form a lightly doped drain (LDD) 1504 adjacent to the TG. Then, a nitride layer is deposited and etched back to form a nitride spacer 1506, which covers the oxide 3 spacer 1502. The dielectric insulator 402 not covered by the nitride spacer 1506 and the oxide 3 spacer 1502 is removed. In addition, FIG. 15(b) is a top view corresponding to FIG. 15(a).

[0133] In step 222, as shown in Figure 16(a), by utilizing the exposed HSS as a silicon growth seed, selective epitaxy growth (SEG) technique is used to grow intrinsic silicon 1602 only above the exposed HSS to a height as high as the top of the nitride cap 604 (above the top of the TG). In addition, Figure 16(b) is a top view corresponding to Figure 16(a).

[0134] In step 224, as shown in Fig. 17(a), a CVD-STI-oxide 3 layer 1702 is deposited to fill all the pores and planarized by CMP techniques to achieve a horizontal flat surface up to the top of the nitride cap 604 on top of the TG. Next, the intrinsic silicon 1602 is removed to expose the HSS corresponding to the source and drain regions surrounded by the CVD-STI-oxide 3 layer 1702 and the nitride spacers 1506.

[0135] The intrinsic silicon 1602 is just a kind of self-alignment pillar (SPR) to surround or block the area where the contact hole will be allocated later. Such a self-alignment pillar is not necessarily limited to silicon material. Depending on the material of the seed exposed for selective epitaxy growth, the self-alignment pillar can be a metal material or other semiconductor material (such as SiC, SiGe, GaN, etc.). Furthermore, the substrate can be a silicon substrate, a SiC substrate, a SiGe substrate, or a GaN substrate.

[0136] Any existing method of forming a source region (n+ source) 1704 and a drain region (n+ drain) 1706 of an mMOSFET can be performed to achieve flat surfaces of the source region 1704 and the drain region 1706 with the HSS, where the source region (n+ source) 1704 can be a first conductive region and the drain region (n+ drain) 1706 can be a second conductive region. In addition, as shown in FIG. 17(a), a channel region exists between the lightly doped drain (LDD) 1504 and under the HSS, and the channel region is electrically coupled to the source region (n+ source) 1704 and the drain region (n+ drain) 1706. In addition, as shown in FIG. 17(a), the source region (n+ source) 1704 is located between the gate structure (i.e., TG (gate layer 602)) and the STI-oxide 2 1002 and CVD-STI-oxide 3 layer 1702 located on the left side of the gate structure, and both the STI-oxide 2 1002 and the CVD-STI-oxide 3 layer 1702 located on the left side of the gate structure can be referred to as a first isolation region, and the first isolation region is adjacent to the first conductive region (i.e., the source region (n+ source) 1704). In addition, as shown in FIG. 17(a), the drain region (n+ drain) 1706 is located between the gate structure and the STI-oxide 2 1002 and CVD-STI-oxide 3 layer 1702 located on the right side of the gate structure, and both the STI-oxide 2 1002 and CVD-STI-oxide 3 layer 1702 located on the right side of the gate structure can be called the second isolation region, and the second isolation region is adjacent to the second conductive region (i.e., the drain region (n+ drain) 1706). In addition, as shown in FIG. 17(a), it is clear that the first isolation region and the second isolation region extend upward and downward from the HSS. In addition, FIG. 17(b) is a top view corresponding to FIG. 17(a).

[0137] In step 226 of forming contact holes, as shown in FIG. 18(a), since the CVD-STI-oxide 3 layer 1702 located above the isolation region and the nitride spacer 1506 surrounding the TG are higher than the HSS as four sidewalls, a well-designed oxide spacer 1802 (called oxide spacer for contact holes (oxide-SCH)) is created outside the four sidewalls to form a first contact hole 1804 located above the first conductive region (i.e., source region (n+ source) 1704) and also located within the boundary of the source region 1704. Similarly, a second contact hole 1806 is located above the second conductive region (i.e., drain region (n+ drain) 1706) and also located within the boundary of the drain region 1706. Therefore, as shown in Fig. 18(a), the contact holes 1804 and 1806 are naturally formed in such a self-aligned manner without using any etching technique to make the contact hole opening, and by proper design of the oxide-SCH with thickness tOSCH, such contact hole opening has a length dimension shorter than the length of each of GEBESI and GEBEDI. What is new here is that the contact hole opening is located approximately at the center of the boundary of the source region (or drain region), and the length of the contact hole opening can be designed to be shorter than λ (because the length of the contact hole = the length of GEBESI - twice the thickness tOSCH. Thus, for example, if the thickness tOSCH = 0.2λ and the length of GEBESI = λ, then the length of the contact hole = 0.6λ). Thus, since the length of the contact holes is primarily governed by the thickness tOSCH of the oxide-SCH 1802, the perimeter of the first contact hole 1804 (and the second contact hole 1806) is independent of the photolithographic masking process, and it is clear that the perimeter of the first contact hole 1804 is within the perimeter of the first conductive region and the perimeter of the second contact hole 1806 is within the perimeter of the second conductive region, as shown in FIG. 18(b).

[0138] In addition, as shown in FIG. 18(a), the length of the contact hole opening is shorter than λ, so the length of the first contact hole 1804 (and the length of the second contact hole 1806) is shorter than the length of the gate structure (because the length of the gate structure is equal to λ, as shown in FIG. 6). In addition, as shown in FIG. 18(a), the oxide spacer 1802 has a thickness tOSCH and the length of GEBESI is equal to the length of the gate structure, so it is clear that the horizontal distance between the first sidewall of the gate structure (located on the left side of the gate structure) and the sidewall of the first contact hole 1804 away from the gate structure is shorter than the length of the gate structure (i.e., λ). In addition, as shown in FIG. 18(a), it is also clear that the horizontal distance between the first sidewall of the gate structure and the sidewall of the first conductive region (i.e., the source region 1704) away from the gate structure is approximately equal to the length of the gate structure. Similarly, as shown in FIG. 18( a), the horizontal distance between the second sidewall of the gate structure (located to the right of the gate structure) and the sidewall of the second isolation region away from the gate structure is substantially equal to the length of the gate structure.

[0139] In addition, as shown in FIG. 18(a), an oxide spacer 1802 (i.e., a first spacer) located on the left side of the gate structure and near the gate structure covers a first sidewall of the gate structure, an oxide spacer 1802 (i.e., a second spacer) located on the left side of the gate structure and away from the gate structure covers a sidewall of the first isolation region 1702, and a first contact hole 1804 is formed between the first spacer and the second spacer.

[0140] In addition, as shown in FIG. 18(a), an oxide spacer 1802 (i.e., a third spacer) located on the right side of the gate structure and near the gate structure covers a second sidewall of the gate structure (located on the right side of the gate structure), an oxide spacer 1802 (i.e., a fourth spacer) located on the right side of the gate structure and away from the gate structure covers a sidewall of the second insulating region, and a second contact hole 1806 is formed between the third spacer and the fourth spacer.

[0141] In addition, as shown in Fig. 18(b), it is clear that the periphery of the first contact hole 1804 is surrounded by the periphery of the first conductive region (or source region), the shape of the periphery of the first contact hole 1804 is similar to the shape of the periphery of the first conductive region, and the periphery of the first conductive region has a rectangular shape. A similar situation applies to the second contact hole 1806 and the second conductive region (or drain region).

[0142] According to the present invention, this self-aligned contact hole should appear as a contact length shorter than that of the prior art design and process that creates the contact hole opening by using photolithographic masking process at such dimension smaller than λ and further using complicated etching process techniques. In addition, the present invention eliminates the most difficult to control and most expensive mask to define and create the metal 1 contacts (such as contact holes for source and drain regions) and the subsequent task of drilling the contact hole opening. In addition, FIG. 18(b) is a top view corresponding to FIG. 18(a).

[0143] In step 228 of forming the metal 1 connection, see FIG. 19. After depositing the metal 1 layer 1902 to fill the contact hole, the metal 1 layer 1902 can be defined using photolithographic masking techniques. As shown in FIG. 19, the metal 1 layer 1902 must have a width that completely covers the contact hole opening and leaves any unavoidable PMT at precisely controlled dimensions. That is, the width of the metal 1 layer 1902 is the length of the contact hole opening (above the source region) CS(L) plus 2Δλ, and equally on the contact hole opening above the drain region, the length of the contact hole CD(L) plus 2Δλ. If the length of the contact hole opening can be controlled to 0.6λ (which should be under control since the dimensions of the oxide spacer 1802 in the contact hole can be well controlled as described above in the calculations), the width of the metal 1 layer 1902 can be as small as the sum of the length of the contact hole opening and 2Δλ (in one embodiment of the present invention, if Δλ=0.5λ (i.e., half the length of the gate structure) and the length of the contact hole opening=0.6λ, the width of the metal 1 layer 1902 can be as narrow as 1.6λ to completely cover the contact hole opening under the inevitable PMT, i.e., the width of the metal 1 layer 1902 can be equal to the length of the first contact hole 1804 plus the length of the gate structure to completely cover the contact hole opening under the inevitable PMT). According to the present invention, the width of the metal 1 layer 1902 as narrow as 1.6λ can be one of the minimum widths of the metal 1 interconnects. In addition, the minimum space 1904 between two nearest metal 1 interconnects should not be smaller than λ. Additionally, as shown in FIG. 19 , metal 1 layer 1902 (i.e., first metal region) is filled within first contact hole 1804 and contacts the first conductive region (i.e., source 1704), with the first metal region extending upward from the first conductive region to a predetermined location higher than the top of nitride layer 604 (i.e., cap layer).

[0144] In addition, by using a merged semiconductor junction and metal conductor (MSMC) structure (disclosed in U.S. Patent Application Publication No. 2006 / 0133999, filed on August 12, 2020, the entire text of which is incorporated herein by reference) for the source (and / or drain) of the mMOSFET that is directly connected to the p-type substrate 102 and grounded, as shown in FIG. 20, if there are no adjacent metal 1 interconnects, the width of the CVD-STI-oxide 3 layer 1702 defined by the dummy shield gate can be as small as the minimum feature size λ without being limited by the space between adjacent metal 1 interconnects. 20, the source region includes a first semiconductor region (N+ heavily doped semiconductor region) 1906 and a first metal-containing region 1908, the drain region includes a second semiconductor region (N+ heavily doped semiconductor region) 1910 and a second metal-containing region 1912, a first oxide guard layer (OGL) 1914 covers only the sidewalls of the first metal-containing region 1908 but not the bottom of the first metal-containing region 1908, and a second oxide guard layer 1916 (in the recess shown in FIG. 20) covers the sidewalls and bottom of the second metal-containing region 1912. Thus, the first metal-containing region 1908 is coupled to the p-type substrate 102 through the bottom of the first metal-containing region 1908.

[0145] An important advantage of the present invention is that almost all critical dimensions, such as the lengths of GEBESI, GEBEDI and contact hole openings, and the width of metal 1 interconnects, can be precisely controlled without being affected by PMT uncertainties, thus ensuring their repeatability, quality and reliability due to the uniformity of the critical dimensions.

[0146] B. Design and Process (II)

[0147] The above principle is adopted in the following embodiment, the only difference is how to form the spacer and contact hole opening. Continuing with Fig. 9(a), as shown in Fig. 21(a), remove the gate mask layer 802, then deposit oxide 2 layer to fill the trench 902 and other holes on the HSS to form STI-oxide 2 2102, and then planarize the STI-oxide 2 2102 by CMP to make the top of STI-oxide 2 2102 about the height of the top of SOD 702 and the top of nitride layer 604 on TG. In addition, Fig. 21(b) is a top view corresponding to Fig. 21(a).

[0148] Next, the SOD 702 is removed, as shown in FIG. 22(a). An oxide 3 layer is deposited and etched back by anisotropic etching technique to form an oxide 3 spacer 2202, which covers the TG. Next, a lightly doped zone is formed in the p-type substrate 102, and rapid thermal annealing is performed on the lightly doped zone to form a lightly doped drain (LDD) 2204 next to the TG. Next, a nitride layer is deposited and etched back to form a nitride spacer 2206, which covers the oxide 3 spacer 2202. And then, the previously existing dielectric insulator 402 under the SOD 702 is removed. In addition, FIG. 22(b) is a top view corresponding to FIG. 22(a).

[0149] Next, by using the exposed HSS area as a silicon growth seed, selective epitaxy growth (SEG) technique is utilized to grow intrinsic silicon 2302 only above the exposed HSS to a height as high as the top of the nitride cap 604 above the top of the TG, as shown in FIG. 23(a). The difference from the previous section A of Part III is that the shape of the SEG intrinsic silicon 2302 can be better controlled because two sides of the SEG intrinsic silicon 2302 are sandwiched between the STI-oxide 2 2102 and the TG, and the other two sides of the SEG intrinsic silicon 2302 face the air above the cliff edge of the active area, which is still covered by the dielectric insulator 402 and above the adjacent STI-oxide 1. Next, a CVD-STI-oxide layer 3 layer 2304 (shown in FIG. 23(b)) is deposited to fill all the pores and planarized by CMP techniques to achieve a flat surface leveled to the top of the nitride cap 604 (on top of the TG). In addition, FIG. 23(b) is a top view corresponding to FIG. 23(a).

[0150] 24(a), the intrinsic silicon 2302 is removed to expose the HSS in the regions for source (n+ source) 2402 and drain (n+ drain) 2404, which are surrounded by two walls of the CVD-STI-oxide 3 layer 2304, the walls of the nitride spacer 2206 on the STI-oxide 2 2102, and the walls of the nitride spacer 2206 surrounding the TG. Any existing method for forming the source region 2402 and the drain region 2404 of the mMOSFET can be implemented to achieve a flat surface of the source region 2402 and the drain region 2404 with the HSS.

[0151] As shown in Fig. 24(a), two walls of CVD-STI-oxide 3 layer 2304, nitride spacer 2206 on STI-oxide 2 2102, and nitride spacer 2206 surrounding TG are all higher than HSS as four sidewalls, so another four well-designed oxide spacers 2406 (called oxide spacers for contact holes, oxide-SCH) can be newly created to cover the four sidewalls. Thus, the contact hole opening is naturally formed in such a self-aligned method without using any etching technique to create contact holes, and by proper design of oxide-SCH with thickness of tOSCH, such contact hole opening has a length dimension shorter than each length of GEBESI and GEBEDI. What is new here is that the contact hole opening is located at the center of both the source and drain region boundaries, respectively, and the length of the contact hole opening can be designed to be shorter than λ (because the contact hole length = the length of GEBESI minus two times tOSCH. Thus, for example, if tOSCH = 0.2λ and GEBESI = λ, then the contact hole length = 0.6λ). According to the present invention, this self-aligned contact hole should appear as a contact length shorter than that of any prior art design and process of creating a contact hole opening by using photolithography masking process steps and using complex etching process techniques in such dimensions shorter than λ. In addition, the present invention eliminates the most difficult to control and most expensive mask to define and create the metal 1 contact and the subsequent task of drilling the contact hole opening. In addition, FIG. 24(b) is a top view corresponding to FIG. 24(a).

[0152] Figure 25 shows the result after depositing metal 1 layer 2502 to fill the contact hole opening, and then photolithographic masking techniques can be used to define the metal 1 layer 2502. As shown in Figure 25, the metal 1 layer 2502 must have a width that completely covers the contact hole opening and leaves the inevitable PMT in precisely controlled dimensions. That is, the width of the metal 1 layer 2502 is the length of the contact hole opening CS(L) plus 2Δλ, and equally on the drain, it is the length of the contact hole opening CD(L) plus 2Δλ. If the contact hole opening can be controlled to 0.6λ (which can be under control since the size of the oxide spacer 2406 in the contact hole can be well controlled as described above in the calculation), the width of the metal 1 layer 2502 can be as small as the sum of the length of the contact hole opening and 2Δλ (if Δλ=0.5λ and the length of the contact hole opening=0.6λ, the width of the metal 1 layer 2502 can be as narrow as 1.6λ to completely cover the contact hole opening under the inevitable PMT). According to the present invention, the width of the metal 1 layer 1902 as narrow as 1.6λ can be one of the minimum widths of the metal 1 interconnects. The minimum space 2504 between two nearest metal 1 interconnects should not be smaller than λ. An important advantage of the present invention is that almost all critical dimensions such as the lengths of GEBESI, GEBEDI and contact hole openings, and the width of metal 1 interconnects can be precisely controlled without being affected by PMT uncertainties, thus ensuring their repeatability, quality and reliability due to the uniformity of these critical dimensions.

[0153] In summary, there are several major improvements for future integrated circuit designs that stem from the above embodiments of the present invention for MOSFET structures, by avoiding photolithographic misalignment tolerances, particularly by having fundamental improvements in design and processing regarding the geometric relationships between the gate and source, gate and drain, contact hole openings between metal 1 and source / drain, as well as the width of the metal 1 interconnect and the self-aligned method of filling the contact holes. (1) Accurately define the length S(L) and the length D(L) from the two edges of the gate by eliminating uncertainties due to photolithography misalignment tolerances. (2) Both the length S(L) and the length D(L) can be designed and fabricated to the minimum feature size λ allowed by photolithographic masking and processing resolution, which significantly minimizes the size of the source and drain, thereby reducing the area of ​​the MOSFET and both the standby and active currents and power, and correspondingly improving the operating speed of the MOSFET. (3) Since both the length S(L) and the length D(L) are precisely controlled, the self-alignment technique of the present invention by making spacers from the four sidewalls surrounding both the source and drain, respectively, can precisely make self-aligned contact holes (SACHs) with controllable shapes and sizes near the centers of both the source and drain, respectively. (4) The length of the SACH can be designed to be smaller than the minimum feature size λ, for example, as small as 0.6λ or even narrower. (5) Other width dimensions of such SACHs can be well designed by self-aligned spacers and well-defined active area widths, because the SACHs are formed by spacer technology that relies on well-developed technology that utilizes chemical film deposition with controllable thickness and uses anisotropic etching techniques instead of the state-of-the-art method of defining contact holes by photolithographic masking techniques with difficult-to-control misalignment tolerances and shapes of the contact holes, so the contact hole openings of the present invention can be well designed and defined (although the contact holes may not have a uniform square contact shape, they have a well-defined rectangular shape and the filling result actually depends on the narrow length dimension of the contact holes). (6) Eliminates the most challenging and expensive contact creation steps and masks. (7) Change the contact hole design from one square hole or multiple square holes with complete separation between multiple contact holes to a rectangular shape of a single contact hole or single contact trench, so that the source (or drain) width (or length) can be made almost the same as the gate width (or length) without being limited by using a dog-bone layout to adjust the dimensional difference between the gate width and the source (or drain) width, which may have multiple square contact holes. (8) Metal 1 interconnects with well-designed thickness can reliably fill all existing contact holes, because the success of this filling depends on the smallest dimension of the contact hole, which is usually the length of the SACH, and the state-of-the-art two-step process for forming contact studs (such as the tungsten stud process and the tungsten fill plus planarization process known as the metal 1 damascene process) can be simplified into one metal 1 deposition process. (9) In such an integrated SACH and metal 1 formation process, the gate is buried under a nitride cap and protected by a spacer, both of which create a flat plateau on the remaining area outside the SACH, and the metal 1 interconnects can be designed with multiple layout methods to create an optimally distributed interconnect network of metal 1. (10) By combining the above advantages, the new mMOSFET structure can be made to have a very small size with a minimum length dimension of 4λ (i.e., length S(L)=λ, length D(L)=λ, gate length=λ, including 1 / 2λ to account for the left isolation and 1 / 2λ to account for the right isolation) and a minimum width dimension of 2λ, i.e., 8λ, making the world's smallest single transistor with both contact holes and metal 1 interconnects in contacting both the source and drain, respectively. 2 This can be achieved with an area (region).

[0154] Of course, depending on design requirements, the length G(L), the length S(L) or the length D(L) can be greater than the minimum feature length λ. (11) All advantages are limited by their application to single MOSFETs, as well as CMOS (complementary metal oxide semiconductor) circuits, such as many optimized functional cells for their area. For example, SRAMs (static random access memories), NAND gates, NOR gates, and random logic gates can be achieved by using the design and fabrication principles invented herein to reduce chip area, current, power, and speed with the precision, repeatability, uniformity, and robustness limits attributed to the invention by eliminating uncertainties from photolithography misalignment tolerances and employing novel self-aligned design and process techniques.

[0155] While the invention has been illustrated and described with reference to embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. [Prior art documents] [Patent documents]

[0156] [Patent Document 1] U.S. Patent Application Serial No. 16 / 991,044

Claims

1. 1. A method for fabricating a transistor including a gate structure and a first conductive region, comprising the steps of: forming an active region based on a substrate; forming the gate structure and a dummy shield gate structure over the active region; forming a first isolation region to replace the dummy shield gate structure; forming self-aligned pillars above the active area; removing the self-aligned pillars and forming the first conductive region between the gate structure and the first isolation region. Manufacturing method.

2. Prior to the step of removing the self-aligned pillars, the method further comprises: forming a second isolation region above the first isolation region, the self-aligned pillar being further characterized in being between the gate structure and the second isolation region. The method of claim 1 .

3. After removing the self-aligned pillars, the method includes: forming a spacer between the gate structure and the first isolation region to define a contact hole; The contact hole is further characterized in being above the first conductive region. The method of claim 1 .

4. The method of claim 3 further characterized in that the length of the contact hole is less than a minimum feature length.

5. The method of claim 3 , further characterized in that defining the contact holes is independent of a photolithography process.

6. The method of claim 1 further characterized in that the substrate is a silicon substrate and the self-aligned pillars are intrinsic silicon pillars formed by selective epitaxy growth.

7. The method of claim 1 , wherein the self-aligned pillar is further characterized in that it is configured to allocate a contact hole above the first conductive region.

8. The method of claim 1 , wherein the first isolation region is further characterized in that it extends upwardly above the active area.

9. performing a first photolithography process configured to define a width of the gate structure and a length of the active area; performing a second photolithography process configured to define a length of the gate structure within the active area; The second photolithography process is further configured to define a length of the first conductive region. The method of claim 1 .

10. 10. The method of claim 9, further characterized in that a length of the active area defined by the first photolithography process is equal to about four times a minimum feature length.

11. a semiconductor substrate having a semiconductor surface; a gate structure having a length; A channel region; a first conductive region electrically coupled to the channel region; a contact hole is positioned above the first conductive region; The contact hole is surrounded by an outer periphery of the first conductive region. Transistor structure.

12. 12. The transistor structure of claim 11, further characterized in that a horizontal distance between a sidewall of the gate structure and a sidewall of the contact hole remote from the gate structure is less than the minimum feature length.

13. an isolation region extending upwardly and downwardly from the semiconductor surface; a first spacer covering a first sidewall of the gate structure and a second spacer covering a sidewall of the isolation region; The contact hole may be further characterized in that it is between the first spacer and the second spacer. The transistor structure of claim 11.

14. a cap layer covering the gate structure; a first metal region filling the contact hole and contacting the first conductive region; the first metal region is further characterized in extending upwardly from the first conductive region to a predetermined location above a top of the cap layer. The transistor structure of claim 11.

15. 12. The transistor structure of claim 11, further characterized in that the periphery of the contact hole is independent of the photolithography process.

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