Semiconductor device

Abstract

To provide a transistor using an oxide semiconductor having high on-state characteristics; and provide a high-function semiconductor device having a transistor capable of fast response and high-speed drive.SOLUTION: In a transistor having an oxide semiconductor, by introducing (adding) an oxygen defect inducing factor to an oxide semiconductor layer, a source region and a drain region selectively become low resistance. By introducing the oxygen defect inducing factor to the oxide semiconductor layer, oxygen defect which functions as a donor can be effectively formed in the oxide semiconductor layer. As the introducing oxygen defect inducing factor, it is preferable to be introduced by ion implantation by using any one or a plurality of metal elements selected from titanium, tungsten and molybdenum.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] Thin film transistors (TFTs) are fabricated using semiconductor thin films formed on substrates with insulating surfaces. The technology of constructing electronic devices such as thin film transistors and electro-optical devices is attracting attention. Silicon-based semiconductors are widely used as semiconductor thin films that can be applied to thin-film transistors. Although the above-mentioned materials are well known, oxide semiconductors have been attracting attention as other materials.

[0004] As for transistors using oxide semiconductors, In transistors using oxide semiconductors, For the purpose of uniformity and high-speed operation, hydrogen or heavy metals are contained in the source and drain electrodes. Hydrogen is diffused into the oxide semiconductor layer, and the source electrode and the drain electrode in the oxide semiconductor layer are connected to each other. There have been reports of techniques for reducing the resistance in the region where the resistance is increased (see, for example, Patent Document 1). see). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2008-72025 A Summary of the Invention [Problem to be solved by the invention]

[0006] When the on-state characteristics of a transistor using an oxide semiconductor are improved, high-speed response can be achieved in a semiconductor device. A high-speed operation becomes possible, and a semiconductor device with higher performance can be realized.

[0007] In view of the above, one embodiment of the present invention provides a transistor including an oxide semiconductor and having excellent on-state characteristics. One of our goals is to provide

[0008] Another embodiment of the present invention is a high-performance semiconductor device having a transistor capable of high-speed response and high-speed operation. An object of the present invention is to provide a semiconductor device. [Means for solving the problem]

[0009] In a transistor having an oxide semiconductor layer, a factor for inducing oxygen defects is introduced into the oxide semiconductor layer. The source region and the drain region are selectively doped with an oxide semiconductor layer. By introducing oxygen vacancy inducing factors, oxygen that functions as a donor in the oxide semiconductor layer is Therefore, oxygen defect inducers are important for oxide semiconductors. The donor factor reduces the resistance of the oxide semiconductor layer.

[0010] The oxygen vacancy inducing factors to be introduced are titanium (Ti), tungsten (W), and molybdenum. (Mo), Aluminum (Al), Cobalt (Co), Zinc (Zn), Indium (In ), silicon (Si), and boron (B). Furthermore, in addition to the oxygen deficiency inducing factors, hydrogen or nitrogen may also be added. It is more preferable to use a metal element having a high affinity for oxygen as the oxygen defect inducing factor. In this case, the oxygen deficiency inducing factors may be ions or hydrides, fluorides, or chlorides. It is preferable to use the ion:

[0011] The introduction of oxygen vacancy inducing factors into the oxide semiconductor layer in this specification is This is done by selectively implanting ions into the silicon layer or by doping. After the treatment, a heat treatment may be carried out.

[0012] One embodiment of the present invention disclosed in this specification is a semiconductor device having a channel formation region on a substrate having an insulating surface. an oxide semiconductor layer provided with a source region and a drain region including an oxygen vacancy inducing factor; A gate insulating layer is provided on the oxide semiconductor layer, and a gate insulating layer overlapping a channel formation region is provided on the gate insulating layer. a gate electrode layer, an insulating layer covering the gate insulating layer, the oxide semiconductor layer, and the gate electrode layer; A source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region are provided on the and a drain electrode layer.

[0013] Another embodiment of the configuration of the invention disclosed in this specification is a channel-shaped a synthesis region, a first region including an oxygen deficiency inducing factor, and a second region including an oxygen deficiency inducing factor. A gate insulating layer is provided on the oxide semiconductor layer. A gate electrode layer overlapping a channel forming region, a gate insulating layer, an oxide semiconductor layer, and a gate electrode An insulating layer covering the electrode layer, and a source electrode layer and a drain electrode layer electrically connected to the source region on the insulating layer. and a drain electrode layer electrically connected to the source region. the second region is provided between the channel formation region and the first region, and the first This is a semiconductor device having a higher resistance than the region.

[0014] Another embodiment of the invention disclosed in this specification is a semiconductor device having an insulating surface. a gate insulating layer is formed over the oxide semiconductor layer; and a gate electrode layer is formed over the gate insulating layer. and then performing a treatment to introduce an oxygen defect inducing factor into the oxide semiconductor layer to selectively form oxygen defects. By this, a channel formation region, a source region, and a drain region are formed in the oxide semiconductor layer. An insulating layer is formed to cover the gate insulating layer, the oxide semiconductor layer, and the gate electrode layer. A source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region are provided. A method for manufacturing a semiconductor device in which a drain electrode layer is formed.

[0015] Another embodiment of the invention disclosed in this specification is a semiconductor device having an insulating surface. a gate insulating layer is formed over the oxide semiconductor layer; and a gate electrode layer is formed over the gate insulating layer. an insulating layer covering the gate insulating layer, the oxide semiconductor layer, and the gate electrode layer; By selectively forming oxygen defects in the oxide semiconductor layer through the introduction of oxygen defect inducing factors, A first region functions as a source region and a drain region, and a second region has a higher resistance than the first region. A source region and a channel forming region are formed on the insulating layer, and the source region is electrically connected to the source region. and a drain electrode layer electrically connected to the drain region. This is the manufacturing method.

[0016] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the specific names used in this specification are not intended to identify the invention. This does not indicate the Effect of the Invention

[0017] By introducing oxygen vacancy inducing factors into the oxide semiconductor layer, donors and In this way, oxygen vacancies that function as a catalyst can be effectively formed.

[0018] The source and drain regions have low resistance due to the introduction of oxygen defect inducing factors. In a transistor having an oxide semiconductor layer, the contact between the oxide semiconductor layer and the electrode layer is The tact resistance can be reduced, improving the on-state characteristics. This results in a transistor with excellent electrical characteristics. It is possible to use this as data.

[0019] A transistor with high electrical characteristics is capable of high-speed response and high-speed operation. By providing the above, a highly functional semiconductor device can be obtained. [Brief description of the drawings]

[0020] [Figure 1] 1A to 1C illustrate a semiconductor device and one embodiment of a manufacturing method of the semiconductor device. [Diagram 2] 1A to 1C illustrate a semiconductor device and one embodiment of a manufacturing method of the semiconductor device. [Diagram 3] 1A to 1C illustrate a semiconductor device and one embodiment of a manufacturing method of the semiconductor device. [Figure 4] 1A to 1C illustrate a semiconductor device and one embodiment of a manufacturing method of the semiconductor device. [Diagram 5] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 6] FIG. [Figure 7] FIG. 13 is a graph showing the calculated relationship between the introduction depth and the concentration of oxygen-defect-inducing factors. [Figure 8] Calculated density of states. [Figure 9] A diagram showing the calculated structure. [Figure 10] A diagram showing the calculated density of states of atoms. [Figure 11]1A to 1C illustrate a semiconductor device and one embodiment of a manufacturing method of the semiconductor device. [Figure 12] 1A to 1C illustrate a semiconductor device and one embodiment of a manufacturing method of the semiconductor device. [Figure 13] 1A to 1C illustrate a semiconductor device and one embodiment of a manufacturing method of the semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0022] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor will be described as an example of a semiconductor device.

[0023] 1A to 1D illustrate an example of a transistor and a method for manufacturing the transistor.

[0024] The transistor 410 shown in FIG. 1D is a thin film transistor having a top gate structure. Also called a planar type thin film transistor.

[0025] The transistor 410 is formed on a substrate 400 having an insulating surface, an insulating layer 407, and a channel-shaped a source region 414a including an oxygen vacancy inducing factor, and a The oxide semiconductor layer 403 in which the drain region 414b is provided and the gate insulating layer 402 and a gate electrode layer 401.

[0026] The oxide semiconductor layer 403, the gate insulating layer 402, and the gate electrode layer 401 are covered with an insulating layer 4 409 and an insulating layer 411 are laminated, and the solenoid 409 is connected to the insulating layer 411. The source electrode layer 405a and the drain electrode layer 414b are formed in the source region 414a and the drain region 414b, respectively. An electrode layer 405b is provided in electrical contact therewith.

[0027] The source region 414a and the drain region 414b are formed by introducing oxygen vacancy inducing factors. This is a low resistance region in which a toner is formed.

[0028] Hereinafter, a process of manufacturing a transistor 410 on a substrate 400 will be described with reference to FIGS. Explain.

[0029] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In either case, it is necessary for the material to have sufficient heat resistance to withstand the subsequent heat treatment.

[0030] For example, when a glass substrate is used as the substrate, if the temperature of the subsequent heat treatment is high, distortion may occur. It is recommended to use a glass substrate with a melting point of 730°C or higher. Glass materials such as vitreous glass, aluminoborosilicate glass, and barium borosilicate glass are used. In addition, practical heat-resistant glass, which is made of boron oxide (B2O3), is used. A glass substrate containing a large amount of BaO may also be used.

[0031] Instead of the above glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may be used. Alternatively, crystallized glass may be used. A plastic substrate or the like can also be used as appropriate.

[0032] An insulating layer 407 serving as a base film is formed on a substrate 400. It has the function of preventing the diffusion of impurity elements, and is used in silicon nitride layers, silicon oxide layers, and nitride oxide layers. Silicon layer, silicon oxynitride layer, aluminum nitride layer, aluminum oxide layer, oxynitride layer A laminated structure of one or more films selected from an aluminum layer and an aluminum oxynitride layer. The insulating layer 407 can be formed by a method such as a plasma CVD method or a For example, the insulating layer 407 may be formed by a method such as a sputtering method. The silicon layer can be formed by a sputtering method.

[0033] An oxide semiconductor film is formed over the insulating layer 407.

[0034] The oxide semiconductor used for the oxide semiconductor film is an oxide of a quaternary metal, In-Sn- Ga-Zn-O system, In-Ga-Zn-O system which is an oxide of ternary metal, In-Sn- Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O The Sn-Al-Zn-O system, the In-Zn-O system which is an oxide of binary metals, and the Sn-Z nO series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg-O series, In-Mg-O series In-O, Sn-O, Zn-O, etc. can be used. An In-Ga-Zn-O oxide semiconductor is an oxide that contains at least In, Ga, and Zn. There is no particular limitation on the composition ratio. In addition, elements other than In, Ga, and Zn may be included. The oxide semiconductor film may contain SiO2.

[0035] The oxide semiconductor film is an oxide represented by the chemical formula InMO3(ZnO)m (m>0). A semiconductor can be used, where M is selected from Ga, Al, Mn, and Co. It represents one or more metal elements. For example, M is Ga, Ga and Al, Ga and Mn, Or Ga and Co.

[0036] The oxide semiconductor film can be formed by a sputtering method. Oxide semiconductor was deposited by sputtering using an In-Ga-Zn-O oxide target. A film is formed and processed into an island shape to form an oxide semiconductor layer 420 (see FIG. 1A).

[0037] A gate insulating layer 402 is formed on the oxide semiconductor layer 420. The gate insulating layer 402 is a Using the Zuma CVD method or sputtering method, etc., a silicon oxide layer, a silicon nitride layer, an oxide Silicon nitride layer, silicon oxynitride layer, aluminum oxide layer, aluminum nitride layer, oxide A single layer or a multilayer of an aluminum nitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer is formed. For example, a silicon oxide film having a thickness of 100 nm can be formed by sputtering. A conductive layer is formed to serve as the gate insulating layer 402 .

[0038] The gate insulating layer 402 is a silicon oxide layer and a silicon nitride layer from the oxide semiconductor layer 420 side. For example, the first gate insulating layer may be formed by sputtering. This forms a silicon oxide layer (SiOx(x>0)) with a thickness of 5 nm to 300 nm. A second gate insulating layer having a thickness of 50 nm to 200 nm is formed on the first gate insulating layer. A silicon nitride layer (SiNy (y>0)) may be laminated. The thickness of the gate insulating layer 402 is The thickness may be appropriately set depending on the characteristics required for the thin film transistor, and may range from 30 nm to 400 nm. It can be about m.

[0039] A gate electrode layer 401 is formed over the gate insulating layer 402 (see FIG. 1B). Gate electrode The material of layer 401 is molybdenum, titanium, chromium, tantalum, tungsten, aluminum, etc. The material is made of metals such as aluminum, copper, neodymium, scandium, etc., or alloys made of these materials. The insulating layer may be formed as a single layer or a multilayer.

[0040] For example, the gate electrode layer 401 may have a two-layer laminate structure of molybdenum on an aluminum layer. A two-layer structure with a layer of molybdenum laminated on a copper layer, or a two-layer structure with a layer of molybdenum laminated on a copper layer, or The structure has a two-layer structure with a titanium nitride layer or tantalum nitride layer laminated on a copper layer, and a titanium nitride layer and a molybdenum layer. It is preferable to use a two-layer structure in which a tongue layer is laminated with a butene layer. A layer of tungsten or tungsten nitride and an alloy of aluminum and silicon or aluminum It is preferable to use a laminated structure of a titanium-titanium alloy and a titanium nitride layer or a titanium layer. Note that the gate electrode layer can also be formed using a light-transmitting conductive film. An example of a conductive film having such a structure is a light-transmitting conductive oxide.

[0041] Next, oxygen vacancy inducing factors 421 are introduced into the oxide semiconductor layer 420 to form a source region 414 a, The oxide semiconductor layer 403 including the drain region 414b and the channel formation region 413 is formed. (See FIG. 1C.) For example, the acid contained in the source region 414a and the drain region 414b The concentration of the defect-inducing factor 421 is 1×1019atoms / cm3 or more. It should be less than oms / cm3.

[0042] After the introduction of oxygen defect inducer 421, heat treatment (for example, 200°C to 600°C) may be performed.

[0043] In this specification, the concentration of the oxygen vacancy inducing factor is the concentration of the oxygen vacancy inducing factor introduced into the oxide semiconductor layer after the oxide semiconductor layer is formed. This is the concentration of oxygen defect inducing factors introduced by the film formation process. The same elements as the oxygen vacancy inducing factors mentioned above shall not be taken into consideration.

[0044] The oxygen vacancy inducers 421 include titanium (Ti), tungsten (W), and molybdenum ( Mo), Aluminum (Al), Cobalt (Co), Zinc (Zn), Indium (In) , silicon (Si), and boron (B) are used. In addition to the oxygen vacancy inducing factors, hydrogen or nitrogen can be used to induce oxygen vacancies. Good too.

[0045] By selectively introducing oxygen vacancy inducing factors 421 into the oxide semiconductor layer 420, This effectively induces oxygen vacancies in the introduction region. Since the oxygen vacancies function as donors, An oxide semiconductor having a source region 414a and a drain region 414b selectively made to have a low resistance. A layer 403 can be formed.

[0046] In this embodiment, in the process of introducing the oxygen defect inducing factor 421, the gate electrode layer 401 is Thus, the gate electrode is formed in a self-aligned manner in the oxide semiconductor layer 403. The region overlapping with the electrode layer 401 is a channel formation region 41 without the oxygen vacancy inducing factor 421 being introduced. 3, while oxygen defect inducer 421 is introduced into the region not overlapping with the gate electrode layer 401. The source region 414a and the drain region 414b are formed by doping the oxide semiconductor layer. A mask is provided to cover at least the channel formation region of 420, and oxygen defect inducing factor 4 is The mask may be a resist mask formed by a photolithography process. A stamp mask can be used.

[0047] The effect of reducing resistance by forming oxygen defects in an oxide semiconductor layer was calculated using a computer. The oxide semiconductor layer was made of In-Ga-Zn-O oxide semiconductor. The calculations were performed using In-Ga-Zn The composition of the -O-based oxide semiconductor material was In:Ga:Zn:O=1:1:1:4.

[0048] First, the melt-quench method using classical MD (molecular dynamics) calculations was used to calculate the In-G We prepared an amorphous structure of a-Zn-O oxide semiconductor. The calculations are performed for structures with a molecular weight of 5.9 g / cm3. For intermetallic compounds, a Born-Mayer-Huggins type potential is used. For the Lennard-Jones type potential, we use the NVT ensemble The calculation was performed using Materials Explorer. Ta.

[0049] Then, the structure obtained by the classical MD calculation was analyzed based on density functional theory (DFT). The structure was optimized by first-principles calculations (quantum MD calculations) using the plane wave pseudopotential method based on the The density of states was calculated by optimizing the structure. The optimization was performed and the density of states was calculated. The calculation program was CASTEP, and the exchange correlation The functional used was GGA-PBE.

[0050] FIG. 8 shows the density of states of the structure obtained by the above calculation. FIG. 8(B) shows the density of states for a structure without oxygen vacancies, and FIG. 8(C) shows the density of states for a structure with oxygen vacancies. where 0 (eV) represents the energy corresponding to the Fermi level. From (B), in a structure without oxygen vacancies, the Fermi level is at the top of the valence band. In contrast, in a structure with oxygen vacancies, the Fermi level is found to exist in the conduction band. In structures with elementary defects, the Fermi level exists in the conduction band, so the number of electrons that contribute to conduction is This increases the electrical conductivity and results in a structure with low resistance (high conductivity).

[0051] Therefore, oxygen vacancies can be effectively induced by selectively introducing oxygen vacancy inducing factors into the oxide semiconductor layer. By this, a source region and a drain region with low resistance are formed in the oxide semiconductor layer. It is possible.

[0052] In addition, it is more preferable to use a metal element having a high oxygen affinity as the oxygen defect inducing factor 421. Examples of metal elements with high oxygen affinity include titanium, aluminum, manganese, Magnesium, zirconium, beryllium, etc. Copper, etc. may also be used. stomach.

[0053] Next, the effect of using metal elements with high oxygen affinity as oxygen vacancy inducers will be discussed. The explanation will be based on the results of calculations using a computer. Here, the metal elements with high oxygen affinity are Titanium is used as the material for the oxide semiconductor layer, and an In-Ga-Zn-O-based oxide semiconductor material is used as the oxide semiconductor layer. Although calculations have been performed for the case where the ion exchange coefficient is used, one embodiment of the disclosed invention is not limited thereto. In the calculation, the composition of the In-Ga-Zn-O oxide semiconductor material is In:Ga: The Zn:O ratio was 1:1:1:4.

[0054] By introducing a metal element with high oxygen affinity, the amorphous oxide semiconductor is converted to an oxygen-affinity semiconductor. We confirmed that oxygen moves to highly compatible metal elements.

[0055] As an oxide semiconductor, titanium (Ti) was added to an In-Ga-Zn-O oxide semiconductor. The electronic state of the structure was calculated using the following calculation model and conditions:

[0056] The structure of the In-Ga-Zn-O oxide semiconductor containing Ti used in the calculation is shown in Figure 9. The structure is a stoichiometric In-Ga-Zn-O structure created by first-principles molecular dynamics calculations. The structure is a Ti-based oxide semiconductor. The black circles represent metal atoms and the white circles represent oxygen atoms. The large black circles represent Ti. The number of atoms is shown in Fig. 9 for the In-Ga-Zn-O oxide semiconductor containing Ti. The conductor structure contains 12 each of In, Ga, and Zn, 48 O, and 1 Ti. .

[0057] The density of the In-Ga-Zn-O oxide semiconductor structure containing Ti is The experimental value for the -O-based oxide semiconductor was fixed at 5.9 g / cm3. For this structure, the following calculation The calculation was performed under the conditions described above. The first-principles calculation was performed using the first-principles calculation software CAS TEP was used.

[0058] The In-Ga-Zn-O oxide semiconductor structure containing Ti shown in Figure 9 shows that the As the temperature is lowered to 500K and then 300K, the number of particles (N), volume (V), and temperature (T) Under constant conditions (NVT ensemble), the time step size is 1 fsec, and the number of steps is 2 at each temperature. 000step, electron cutoff energy 260eV, reciprocal lattice mesh (k point) Calculate the structure as 1×1×1, and then add the electron cutoff energy of 4 to the final structure. 20 eV, reciprocal lattice mesh (k point) 2 × 2 × 2, structural optimization calculation was performed, and the energy It has a stable structure with low gy.

[0059] As shown in Figure 9, titanium is bonded to oxygen.

[0060] The electron cutoff for the In-Ga-Zn-O oxide semiconductor structure containing Ti in Figure 9 The energy is 420 eV, the mesh (k-points) of the reciprocal lattice is 3 × 3 × 3, and the density of electron states is The degree was calculated.

[0061] Figure 10(A) shows the overall density of states in the In-Ga-Zn-O oxide semiconductor structure. The partial density of states of Ti in the In-Ga-Zn-O oxide semiconductor structure containing Ti is shown in (B). In Fig. 10(A) and (B), the horizontal axis represents energy and the vertical axis represents density of states. The origin of energy represents the energy of the most occupied level of electrons. As shown in Figure 10(B), When Ti is added to an In-Ga-Zn-O oxide semiconductor, electrons enter the lower end of the conduction band. You can understand.

[0062] From the above results, when Ti is introduced into In-Ga-Zn-O oxide semiconductors, When oxygen combines with water, the stoichiometric ratio is deviated. This causes an oxygen deficiency. In amorphous In-Ga-Zn-O oxide semiconductors, oxygen vacancies act as electron donors. As a result, there is an excess of electrons. Therefore, when Ti, which easily bonds with oxygen, is introduced, This causes oxygen defects and generates carriers.

[0063] In this way, by introducing a metal element having a high oxygen affinity into the oxide semiconductor layer, In the inlet region, oxygen atoms move from the oxide semiconductor layer to the metal element, and oxygen defects become more efficient. As a result, the increase in oxygen vacancies functioning as donors results in The introduction region becomes more efficiently low resistance.

[0064] The source and drain regions have low resistance due to the introduction of oxygen defect inducing factors. In a transistor having an oxide semiconductor, the contact between the oxide semiconductor layer and the electrode layer is Since the contact resistance can be reduced, the on-characteristics (e.g., on-current and field effect mobility) are improved. Therefore, a transistor with excellent electrical characteristics can be obtained.

[0065] The introduction of oxygen vacancy inducing factors 421 into the oxide semiconductor layer 420 is performed by This is carried out by selectively implanting ions or doping into the oxide layer 420. Titanium is used as the defect inducer 421 and is implanted into the oxide semiconductor layer 420 by ion implantation. Ion implantation methods include those using titanium tetrachloride (TiCl4) liquefied gas and , and vaporizing a solid source.

[0066] In the oxygen defect inducing factor introduction process, the introduction conditions (acceleration energy, oxygen defect induction factor, etc.) Depending on the amount of irradiation (implantation amount or dose amount) of the electrons, the mask (gate electrode in this embodiment) Even in the region overlapping with the oxide semiconductor layer 401, oxygen vacancy inducing factors are included in a part of the oxide semiconductor layer. Therefore, the region where the oxygen defect inducing factor is introduced depends on the introduction conditions, the mask thickness, etc. This can be controlled by setting the size appropriately.

[0067] For example, the introduction conditions for the introduction of oxygen defect inducing factors into the oxide semiconductor layer are A software called RIM (Transport of Ion in Matter) The calculation was performed using TRIM, which calculates the ion implantation process using the Monte Carlo method. The model used for the calculation is a silicon oxide film as the insulating layer 407, an oxide The semiconductor layer 420 is an amorphous In-Ga-Zn-O film (composition: InGaZnO4, density 6.2 g / cm3, film thickness 50 nm), and a silicon oxide film (density 2 The oxide semiconductor layer 420 is a gate insulating layer. The oxygen defect inducing factor 421 was introduced through the layer 402. The ion implantation method was used with titanium ions (Ti+) at a dose of 1×1015cm-2. The acceleration energy was set to three conditions: 100 keV, 150 keV, and 200 keV. The calculation was carried out based on the above.

[0068] The relationship between the introduction depth and concentration of oxygen vacancy inducing factors calculated is shown in Figure 7. In Figure 7, the horizontal axis is The vertical axis represents the depth (nm) of the oxygen defect inducing factor from the surface of the oxide semiconductor layer 420. As shown in Figure 7, the acceleration energy The energy was 100 keV, 150 keV, and 200 keV, and the oxide semiconductor layer was 42 Titanium ions, which are oxygen vacancy inducing factors, are introduced into 0 at a concentration of about 1×1020 atoms / cm3. It can be confirmed that this has been done.

[0069] Therefore, in the above calculation model, the oxide semiconductor layer has a concentration of 1×1019 atoms / cm3 To form source and drain regions with a density of 1×1021 atoms / cm3 or less The titanium ion introduction conditions are a dose of 1×1014 cm-2 or more and 1×1016 cm-2 or more. Hereinafter, the acceleration energy may be set to 100 keV or more and 200 keV or less.

[0070] An oxygen defect inducing factor may also be introduced into the channel formation region 413 of the oxide semiconductor layer 403. In this case, oxygen defect inducing factors are added to the oxide semiconductor layer 420 before the gate electrode layer 401 is formed. The oxygen vacancy inducing factor is introduced before the oxide semiconductor film is processed into islands. The oxygen defect inducing factor may also be introduced into the channel formation region 413 to form oxygen defects as donors. By making the material have a low resistance (e.g. n-type) as a gate, the electrical characteristics of the transistor can be controlled more effectively. It can be controlled.

[0071] After the oxygen defect inducing factor introduction treatment, a heat treatment (for example, 200°C to 600°C) is performed. That's fine.

[0072] The concentration of the oxygen defect inducing factor contained in the channel forming region 413 is The impurity concentration of the source region 414a and the drain region 414b is lower than that of the source region 414a and the drain region 414b. The concentration of oxygen vacancy inducers contained in the drain region 414b is 1×1019atoms / c m3 or more and 1×1021 atoms / cm3 or less, for example, The concentration of 3 may be less than 1×1014 atoms / cm3.

[0073] Next, an insulating layer 403, a gate insulating layer 402, and a gate electrode layer 401 are 409 and insulating layer 411 are laminated.

[0074] The insulating layer 409 and the insulating layer 411 are formed of an inorganic insulating film such as an oxide insulating layer or a nitride insulating layer. The insulating layers 409 and 411 can be preferably formed by a process using a process A plasma CVD method, a sputtering method, or the like may be used.

[0075] The insulating layer 409 is typically a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. Alternatively, an inorganic insulating film such as an aluminum oxynitride film can be used.

[0076] The insulating layer 411 may be a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or a silicon oxynitride film. An inorganic insulating film such as an aluminum film can be used.

[0077] In addition, a planarizing insulating film is formed on the insulating layer 411 in order to reduce surface irregularities caused by the transistor. The planarization insulating film may be formed of polyimide, acrylic, benzocyclobutene, poly Organic materials having heat resistance, such as polyamide and epoxy, can be used. In addition to the materials, low-k materials, siloxane resins, and PSG (phosphorus glass) are also available. ), BPSG (borophosphorus glass), etc. can be used. A planarizing insulating film may be formed by stacking a plurality of insulating films. The method of formation is not particularly limited, and may be a sputtering method, a SOG method, a spin coating method, or the like, depending on the material. Coating, dip, spray coating, droplet ejection method (inkjet method, screen printing, off set printing, etc.), doctor knife, roll coater, curtain coater, knife coater etc. can be used.

[0078] An opening is formed in the insulating layer 409 and the insulating layer 411, reaching the source region 414a and the drain region 414b. A conductive film is formed in the opening and processed by etching to form a contact hole. A source electrode layer 405 is in contact with and electrically connects the source region 414a and the drain region 414b. A drain electrode layer 405b is formed (see FIG. 1(D)). 410 can be created.

[0079] The conductive film used for the source electrode layer 405a and the drain electrode layer 405b is, for example, Al , Cr, Cu, Ta, Ti, Mo, W, or the above elements are included The alloy may be a combination of the above elements. Cr, Ta, Ti, Mo, W, etc. on either or both of the upper and lower metal layers such as Cu. The high melting point metal layers may be laminated. Elements such as r, Nd, Sc, and Y are added to prevent the occurrence of hillocks and whiskers in the Al film. By using aluminum materials with added nitride, it is possible to improve heat resistance. Conductive nitride materials of the above metals such as titanium may also be used. For this purpose, a deposition method, a sputtering method, or the like may be used.

[0080] The source electrode layer 405a and the drain electrode layer 405b may have a single-layer structure or a stack of two or more layers. For example, a single layer structure of an aluminum film containing silicon, A two-layer structure in which a titanium film is laminated on top of a titanium film, and an aluminum film is laminated on top of the titanium film. Examples include a three-layer structure in which a Ti film is formed on top of the first layer.

[0081] In addition, the source electrode layer 405a, the drain electrode layer 405b (wiring formed in the same layer as this The conductive film (including the layer) may be formed of a conductive metal oxide. The oxides are indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide Indium zinc oxide alloy (In2O3-ZnO) or the above metal oxide material with silicon or Alternatively, a material containing silicon oxide can be used.

[0082] As described above, the source region 414a and the drain region 414b are made low-resistance by the introduction of oxygen vacancy inducing factors. The transistor 410 having the oxide semiconductor having the drain region 414b is an oxide semiconductor The contact resistance between the layer 403 and the source electrode layer 405a and the drain electrode layer 405b can be reduced. Therefore, the on-state characteristics are improved, making it possible to produce a transistor with excellent electrical characteristics. It becomes.

[0083] A transistor with high electrical characteristics is capable of high-speed response and high-speed operation. By providing the above, a highly functional semiconductor device can be obtained.

[0084] (Embodiment 2) In this embodiment mode, one embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor will be described as an example of a semiconductor device. In the transistor shown in embodiment 1, a region containing oxygen defect inducing factors at a lower concentration than the source region and the drain region; Therefore, the parts and steps having the same functions as those in the above embodiment are as follows: The embodiment can be carried out in the same manner as described above, and the repeated explanation will be omitted. A detailed explanation will be omitted.

[0085] 2(A) to 2(D) and 3(A) to 3(D) show transistors and An example of a method for producing the capacitor is shown below.

[0086] The transistor 440 shown in FIG. 2D is a top-gate thin film transistor. Also called a planar type thin film transistor.

[0087] The transistor 440 is formed on a substrate 400 having an insulating surface, an insulating layer 407, a channel forming Region 413, low concentration oxygen defect inducing factor containing regions 415a and 415b, oxygen defect inducing factor A source region 414a including an oxygen vacancy inducing factor and a drain region 414b including an oxygen vacancy inducing factor are provided. The gate insulating layer 402 and the gate electrode layer 401 are formed in the oxide semiconductor layer 433 .

[0088] The oxide semiconductor layer 433, the gate insulating layer 402, and the gate electrode layer 401 are covered with an insulating layer 4 409 and an insulating layer 411 are laminated, and the solenoid 409 is connected to the insulating layer 411. The source electrode layer 405a and the drain electrode layer 414b are formed in the source region 414a and the drain region 414b, respectively. An electrode layer 405b is provided in electrical contact therewith.

[0089] Low concentration oxygen defect inducing factor containing regions 415a, 415b, source region 414a and drain region The region 414b is a region containing an oxygen defect inducing factor, and is a low concentration oxygen defect inducing factor containing region. The source region 414a and the drain region 415b have a higher concentration of oxygen defect inducing factors than the source region 414a and the drain region 415b. The region 414b can be said to be a region containing high concentration oxygen defect inducing factors. In the present embodiment, the source region 414a and the drain region 414b are regions containing high concentration oxygen defect inducing factors. The region 414b is referred to as a first region, while the low concentration oxygen defect inducing factor containing regions 415a and 415b are referred to as a second region. It is also called region 2.

[0090] The low concentration oxygen defect inducer containing regions 415a and 415b, the source region 414a, and the drain region The donor region 414b is a low-resistance region in which donors are formed by oxygen vacancy inducing factors. The low concentration oxygen defect inducing factor containing regions 415a and 415b are The oxygen defect inducing factors contained in the source region 414a and the drain region 414b are Since the concentration of is low, the resistance is higher than that of the source and drain regions.

[0091] Therefore, in the oxide semiconductor layer 433 of the transistor 440, the channel formation region 413 , low concentration oxygen defect inducing factor containing regions 415a and 415b, source region 414a and drain region The resistance decreases in the order of the in-region 414b.

[0092] Hereinafter, a transistor 440 is manufactured over a substrate 400 with reference to FIGS. 2A to 2D. The process will be explained.

[0093] As shown in FIG. 1B of the first embodiment, an island-shaped semiconductor device is formed on a substrate 400 on which an insulating layer 407 is provided. An oxide semiconductor layer 420, a gate insulating layer 402, and a gate electrode layer 401 are formed (FIG. 2(A)).

[0094] A region corresponding to a channel formation region of the oxide semiconductor layer 420 (which overlaps with the gate electrode layer 401) The oxygen defect inducing factor may also be introduced into the second region (the second region) to include the oxygen defect inducing factor. In this case, oxygen defect inducing factors are introduced into the oxide semiconductor layer 420 before the gate electrode layer 401 is formed. The oxygen vacancy inducing factor introduction process is performed before processing the oxide semiconductor film into islands. It is also possible to introduce oxygen defect inducing factors into the channel formation region and use oxygen defects as donors to reduce the By making it resistive (e.g. n-type), the electrical characteristics of the transistor can be more controlled. can be done.

[0095] After the oxygen defect inducing factor introduction treatment, a heat treatment (for example, 200°C to 600°C) is performed. That's fine.

[0096] Next, an insulating layer covering the oxide semiconductor layer 420, the gate insulating layer 402, and the gate electrode layer 401 is Form 409 (see FIG. 2(B)).

[0097] Next, an oxygen defect inducing factor 434 is introduced into the oxide semiconductor layer 420 to form a low-concentration oxygen defect inducing factor 434. The electron-containing regions 415a, 415b, the source region 414a, the drain region 414b, the channel An oxide semiconductor layer 433 including the formation region 413 is formed (see FIG. 2C). The concentration of the oxygen defect inducing factor 434 contained in the source region 414a and the drain region 414b is The concentration should be between 1×1019 atoms / cm3 and 1×1021 atoms / cm3. The low concentration oxygen defect inducing factor containing regions 415a and 415b are the source region 414a and the drain region 414b. The concentration of the oxygen defect inducing factor-containing region 414b may be lower than that of the oxygen defect inducing factor-containing region 414b. The concentration of oxygen vacancy inducer 434 contained in 5a and 415b is 1×1018 atoms / It is sufficient to set it to about cm3.

[0098] After the introduction of oxygen defect inducer 434, heat treatment (for example, 200°C to 600°C) may be performed.

[0099] The oxygen vacancy inducer 434 is titanium (Ti), tungsten (W), molybdenum ( Mo), Aluminum (Al), Cobalt (Co), Zinc (Zn), Indium (In) , silicon (Si), and boron (B) are used. In addition to the oxygen vacancy inducing factors, hydrogen or nitrogen can be used to induce oxygen vacancies. In addition, as the oxygen defect inducing factor 434, a metal element having a high oxygen affinity may be used. More preferred.

[0100] By selectively introducing oxygen vacancy inducing factors 434 into the oxide semiconductor layer 420, This effectively induces oxygen vacancies in the introduction region. Since the oxygen vacancies function as donors, Selectively reduced-resistance low-concentration oxygen defect inducer-containing regions 415a and 415b, source region The oxide semiconductor layer 433 having the drain region 414a and the drain region 414b can be formed. do.

[0101] In addition, a concentration distribution is set in the region where oxygen vacancy inducing factors are introduced, and a high-resistance channel formation region and a low Between the resistive source region or drain region, a resistive layer having a higher resistance than the source region and the drain region is provided. The low-concentration oxygen defect inducing factor-containing regions 415a and 415b have a lower resistance than the channel formation region. By having the above structure, the oxide semiconductor layer 433 has a structure in which the conductivity is changed stepwise. This suppresses electric field concentration and prevents the application of a high electric field locally, improving the breakdown voltage of the transistor. Furthermore, high reliability can be imparted to the semiconductor device.

[0102] In this embodiment, in the process of introducing the oxygen defect inducing factor 434, the gate electrode layer 401 is Thus, the gate electrode is formed in a self-aligned manner in the oxide semiconductor layer 433. The region overlapping with the electrode layer 401 is a channel formation region 41 without the oxygen vacancy inducing factor 434 being introduced. 3, while oxygen defect inducer 434 is introduced into the region not overlapping with the gate electrode layer 401. The source region 414a and the drain region 414b are formed by doping the gate electrode layer 4 Since the insulating layer 409 provided on the side of the gate electrode layer 401 also serves as a mask, Therefore, the introduction of the insulating layer 409 into the oxide semiconductor layer 420 overlapping with the insulating layer 409 provided in the A region of the oxide semiconductor layer 420 overlapping with the insulating layer 409 provided on the side surface of the gate electrode layer 401 In the region (between the channel forming region 413 and the source region 414a or the drain region 414b), This is due to the infiltration of oxygen vacancy inducers 434 introduced into the source or drain region. Since the oxygen deficiency inducing factor 434 is introduced, the low concentration oxygen deficiency inducing factor-containing region 415a, The result is 415b.

[0103] The introduction of the oxygen defect inducing factor 434 into the oxide semiconductor layer 420 is performed by 420 is selectively implanted using ion implantation or doping.

[0104] In the oxygen defect inducing factor introduction process, the introduction conditions (acceleration energy, oxygen defect induction factor, etc.) Depending on the amount of irradiation (implantation amount or dose amount) of the electrons, the mask (gate electrode in this embodiment) Even in the region overlapping with the oxide semiconductor layer 401, oxygen vacancy inducing factors are included in a part of the oxide semiconductor layer. Therefore, the region where the oxygen defect inducing factor is introduced depends on the introduction conditions, the mask thickness, etc. This can be controlled by setting the size appropriately.

[0105] As in this embodiment, the source region 414a and the drain region 414b are formed through the insulating layer 409. The oxygen vacancy inducer 434 introduced into 14b wraps around to form low-concentration oxygen vacancy inducers. When the containing regions 415a and 415b are formed, the thickness of the insulating layer 409 and the acceleration energy By adjusting the concentration of oxygen vacancy inducer-containing regions 415a and 415b in the channel length direction, Determine the width (for example, 20 nm to 1 μm, typically 20 nm to 200 nm). It is possible.

[0106] In Figure 2, a single oxygen deficiency inducing factor introduction treatment resulted in the formation of low-concentration oxygen deficiency inducing factor-containing region 4. 15a, 415b, source region 414a, and drain region 414b are formed in a self-aligned manner. However, multiple oxygen defect induction factor introduction treatments may be performed. An example of the introduction of a defect-inducing factor will be described.

[0107] As in FIG. 2A, an island-shaped oxide semiconductor layer 42 is formed on a substrate 400 on which an insulating layer 407 is provided. 0, a gate insulating layer 402, and a gate electrode layer 401 are formed (see FIG. 3(A)).

[0108] Next, the oxide semiconductor layer 420 is treated with the gate electrode layer 401 as a mask to form an oxygen defect inducing factor 43 0 is selectively introduced to form a channel forming region 413, an oxygen defect inducing factor containing region 431a, For example, oxygen deficiency inducer-containing regions 431a and 431b are formed (see FIG. 3(B)). The concentration of oxygen defect inducer 430 contained in 31b is about 1×1018atoms / cm3. It is sufficient to use degrees.

[0109] Next, a channel forming region 413 and oxygen deficiency inducing factor containing regions 431a and 431b are An insulating layer 409 is formed to cover the oxide semiconductor layer, the gate insulating layer 402, and the gate electrode layer 401. do.

[0110] Next, oxygen defect inducer-containing regions 431a and 431b of the oxide semiconductor layer are The low-concentration oxygen defect inducing factor-containing regions 415a and 415b and the source region 4 14a, the drain region 414b, and the oxide semiconductor layer 433 including the channel formation region 413. For example, the source region 414a and the drain region 414b are formed (see FIG. 3C). The concentration of oxygen vacancy inducer 432 contained in the material is 1×1019 atoms / cm3 or more. It is sufficient to set the concentration to 21 atoms / cm3 or less.

[0111] After the introduction of oxygen defect inducer 432, heat treatment (for example, 200°C to 600°C) may be performed.

[0112] In addition, the insulating layer 409 provided on the side of the gate electrode layer 401 also serves as a mask. The oxygen is introduced into the oxide semiconductor layer 420 overlapping the electrode layer 401 and the insulating layer 409 provided on the side surface. The introduction of defect-inducing factor 432 is inhibited, and the low-concentration oxygen defect-inducing factor-containing regions 415a, 41 The result is 5b.

[0113] The oxygen vacancy inducers 430 and 432 are made of the same material as the oxygen vacancy inducer 434. It is possible.

[0114] In addition, when an oxygen defect inducing factor is introduced into the channel formation region 413, the channel formation The concentration of the oxygen defect inducing factor contained in the synthesis region 413 is set to 4 The impurity concentration of the source region 414a and the drain region 414b is lower than that of the source region 414a and the drain region 414b. As in the embodiment, oxygen vacancy induced in the source region 414a and the drain region 414b The concentration of the causative agent is 1×1019 atoms / cm3 or more and 1×1021 atoms / cm3 or more. The lower part shows the oxygen deficiency inducing factor contained in the low concentration oxygen deficiency inducing factor-containing regions 415a and 415b. If the concentration is about 1×10 atoms / cm, for example, the channel formation region 41 The concentration of 3 may be less than 1×1014 atoms / cm3.

[0115] After the introduction process of FIG. 3C is completed, an insulating layer 411 is formed on the insulating layer 409. 409 and an insulating layer 411 are provided with openings (conduits) reaching the source region 414a and the drain region 414b. A conductive film is formed in the opening and etched to form the source region. A source electrode layer 405a and a drain electrode layer 405b are in contact with and electrically connected to the drain region 414a and the drain region 414b. Through the above steps, the transistor 440 is formed. can be produced.

[0116] As described above, the low-concentration oxygen vacancy-inducing factor-containing film was reduced in resistance by the introduction of the oxygen vacancy-inducing factor. The source region 414a is a region containing a high concentration of oxygen defect inducing factors. The transistor 440 including the oxide semiconductor layer 433 having the drain region 414b is The oxide semiconductor layer 433 is in contact with the source electrode layer 405a and the drain electrode layer 405b. Since the gate resistance can be reduced, the on-characteristics (for example, on-current and field effect mobility) are improved. Therefore, a transistor with excellent electrical characteristics can be obtained.

[0117] A transistor with high electrical characteristics is capable of high-speed response and high-speed operation. By providing the above, a highly functional semiconductor device can be obtained.

[0118] Furthermore, by using an oxide semiconductor layer whose conductivity is changed stepwise, This suppresses field concentration and prevents the application of localized high electric fields, improving the breakdown voltage of transistors and This makes it possible to impart high reliability to the conductor device.

[0119] (Embodiment 3) In this embodiment mode, another embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor will be described as an example of a semiconductor device. Formation process of the transistor described in Embodiment 1 or 2 and the source electrode layer and the drain electrode layer Therefore, the present embodiment has the same parts and functions as the above embodiment. The parts and steps can be performed in the same manner as in the above embodiment, and repeated explanations will be omitted. Further, detailed explanations of the same parts will be omitted.

[0120] In the first and second embodiments, the source and drain electrode layers are formed of oxide semiconductor layers. The oxide semiconductor layer is electrically connected to the insulating layer by a contact. In this embodiment, the oxide semiconductor is used without an insulating layer. A source electrode layer and a drain electrode layer are formed directly on and in contact with the conductor layer.

[0121] 11A to 11D show an example of a transistor and a method for manufacturing the transistor. .

[0122] The transistor 510 shown in FIG. 11D is a thin film transistor having a top gate structure. It is.

[0123] The transistor 510 is formed on a substrate 500 having an insulating surface, an insulating layer 507, a channel forming Region 513, oxygen deficiency inducing factor non-introduced regions 511a and 511b, containing oxygen deficiency inducing factors A source region 512a and a drain region 512b including an oxygen defect inducing factor are provided. The first source electrode layer 555a, the first drain electrode layer 555b, and the second a second source electrode layer 545a, a second drain electrode layer 545b, a gate insulating layer 502, and It has a gate electrode layer 501 .

[0124] The source region 512a and the drain region 512b are formed in the oxide semiconductor layer 503. An electrode layer 501, a first source electrode layer 555a, a first drain electrode layer 555b, a second A region not covered by the first source electrode layer 545a or the second drain electrode layer 545b, the first source electrode layer 555a, the first drain electrode layer 555b, and the second source electrode layer 545a or a surface portion of the oxide semiconductor layer 503 covered with the second drain electrode layer 545b; The source region 512a and the drain region 512b are formed in a region having a thickness of 100 nm or less due to oxygen vacancies. This is a low resistance region in which a donor is formed by the electron 521.

[0125] On the other hand, in the oxide semiconductor layer 503, the first source electrode layer 555a or the first drain The oxygen vacancy inducing layer 507 is provided in the vicinity of the interface with the insulating layer 507. The non-electron-introduced regions 511a and 511b do not contain the oxygen-defect-inducing factor 521.

[0126] Note that the oxygen defect inducing factor 521 is also introduced into the channel formation region 513 of the oxide semiconductor layer 503. In this case, oxygen may be introduced into the oxide semiconductor layer 520 before the gate electrode layer 501 is formed. The introduction process of the defect inducing factor 521 is performed. The introduction process of the oxygen defect inducing factor 521 is performed on the oxide semiconductor. The oxygen defect inducing factor may be present in the channel forming region 513. When 521 is introduced, the oxygen defect inducing factor 521 is introduced into the entire oxide semiconductor layer 503. Therefore, the oxygen defect inducing factor non-introduced regions 511a and 511b are also provided with the same concentration as the channel formation region. This means that the oxygen defect inducing factor 521 is contained to a certain extent.

[0127] The oxygen vacancy inducing factor 521 is also introduced into the channel formation region 513, and oxygen vacancies are used as donors. By lowering the resistance (e.g., making it n-type), the electrical characteristics of the transistor can be more controlled. This can be done.

[0128] After the introduction of oxygen defect inducer 521, heat treatment (for example, 200°C to 600°C) may be performed.

[0129] The concentration of the oxygen defect inducing factor contained in the channel forming region 513 is The impurity concentration of the source region 512a and the drain region 512b is lower than that of the source region 512a and the drain region 512b. The concentration of oxygen vacancy inducers contained in the drain region 512b is 1×1019atoms / c m3 or more and 1×1021 atoms / cm3 or less, for example, The concentration of 3 may be less than 1×1014 atoms / cm3.

[0130] Hereinafter, a transistor 510 is formed on a substrate 500 using FIG. 11(A) to FIG. 11(D). The process for doing so will be described.

[0131] An island-shaped oxide semiconductor layer 520 is provided on a substrate 500 on which an insulating layer 507 is provided. A first source electrode layer 555a and a second source electrode layer 555b are in contact with one end of the semiconductor layer 520. A stack of an electrode layer 545a is formed and is in contact with the other end of the oxide semiconductor layer 520. A stack of a drain electrode layer 555b and a second drain electrode layer 545b is formed.

[0132] A first source electrode layer 555a and a first drain electrode layer 555b in contact with the oxide semiconductor layer 520 A metal nitride layer is used as 555b, and the second source electrode layer 545a and the second drain electrode layer 545b are formed. It is preferable to use a metal layer as the first solenoid electrode layer 545b. A titanium nitride film is used as the source electrode layer 555a and the first drain electrode layer 555b. A titanium film is used for the source electrode layer 545a and the second drain electrode layer 545b.

[0133] The first source electrode layer 555a, the first drain electrode layer 555b, and the second source electrode layer 54 The drain electrode layer 545a and the second drain electrode layer 545b are thin conductive films.

[0134] An oxide semiconductor layer 520, a first source electrode layer 555a, a first drain electrode layer 555b, A gate insulating layer 50 is formed on the second source electrode layer 545a and the second drain electrode layer 545b. 2, and a gate electrode layer 501 is formed on the gate insulating layer 502 (see FIG. 11(B)). ).

[0135] Next, oxygen defect inducing factors 521 are introduced into the oxide semiconductor layer 520 to form a source region 512 a, Drain region 512b, channel formation region 513, oxygen defect inducing factor non-introduced region 511a 511b, an oxide semiconductor layer 503 including the oxide semiconductor layer 511b is formed (see FIG. 11C). The concentration of the oxygen defect inducing factor 521 contained in the source region 512a and the drain region 512b is 1 × 1019 atoms / cm3 or more and 1 × 1021 atoms / cm3 or less may be used.

[0136] After the introduction of oxygen defect inducer 521, heat treatment (for example, 200°C to 600°C) may be performed.

[0137] The oxygen vacancy inducers 521 include titanium (Ti), tungsten (W), molybdenum ( Mo), Aluminum (Al), Cobalt (Co), Zinc (Zn), Indium (In) , silicon (Si), and boron (B) are used. In addition to the oxygen defect inducing factor 521, hydrogen or nitrogen may be added. As the oxygen defect inducing factor 521, a metal element having high oxygen affinity may be used. It is preferable to have one.

[0138] By selectively introducing oxygen defect inducing factors 521 into the oxide semiconductor layer 520, This effectively induces oxygen vacancies in the introduction region. Since the oxygen vacancies function as donors, An oxide semiconductor having a source region 512a and a drain region 512b selectively made to have a low resistance. A layer 503 can be formed.

[0139] In this embodiment, the oxygen defect inducing factor 521 is introduced into the oxide semiconductor layer 520 by a gel. Using the gate electrode layer 501 as a mask, the gate insulating layer 502 and the first source electrode layer 55 are 5a, a first drain electrode layer 555b, a second source electrode layer 545a, and a second drain The electron beam passes through the electrode layer 545b.

[0140] In the region overlapping with the gate electrode layer 501, the oxygen defect inducing factor 521 is not introduced and a channel is not formed. This results in area 513.

[0141] The first source electrode layer 555a, the first drain electrode layer 555b, and the second source electrode layer 54 5a and the second drain electrode layer 545b are made of a thin conductive film, and the introduction conditions are controlled. By this, the oxygen defect inducing factor 521 is transferred to the first source electrode layer 555a and the first drain electrode layer 555b, the second source electrode layer 545a, and the second drain electrode layer 545b. The dopant can be introduced near the interface with the oxide semiconductor layer 520. In this manner, the oxide semiconductor layer 503 and the first source electrode layer 555a or the first drain electrode The source region 512, which is a region containing oxygen defect inducing factors 521, is also formed near the interface with the layer 555b. Therefore, the oxide semiconductor layer 503 and the drain region 512b can be formed. The first source electrode layer 555a or the first drain electrode layer 555b is a low-resistance source The connection can be made via the region 512a or the drain region 512b.

[0142] On the other hand, the oxide layer overlapping the first source electrode layer 555a or the first drain electrode layer 555b In the semiconductor layer 503, oxygen defect inducing factors 521 are introduced near the interface with the insulating layer 507. The oxygen defect inducing factor non-introduced regions 511a and 511b are formed. The defect-inducing factor non-introduced regions 511a and 511b and the channel formation region 513 are not subjected to the introduction process. This does not include oxygen defect inducing factors.

[0143] Through the above steps, the transistor 510 can be manufactured.

[0144] The source region 512a and the drain region 512b are made low-resistance by the introduction of the oxygen defect inducing factor 521. By providing the region 512b, the transistor 510 including the oxide semiconductor layer 503 The oxide semiconductor layer 503, the first source electrode layer 555a, and the first drain electrode layer 555 Since the contact resistance with b is reduced, the on-characteristics (e.g., on-current and field effect mobility) ) is improved. Therefore, a transistor with excellent electrical characteristics can be obtained.

[0145] A transistor with high electrical characteristics is capable of high-speed response and high-speed operation. By providing the above, a highly functional semiconductor device can be obtained.

[0146] Also, as in the second embodiment, between the channel formation region and the source region or the drain region, A structure having a region containing oxygen defect inducing factors at a lower concentration than the source region and the drain region is used. This is also fine.

[0147] By using an oxide semiconductor layer whose conductivity is gradually changed, electric field concentration in a transistor can be prevented. This can suppress the application of localized high electric fields, improving the breakdown voltage of transistors and This provides high reliability.

[0148] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0149] (Embodiment 4) In this embodiment, an example of a transistor including an oxide semiconductor layer and a manufacturing method thereof will be described with reference to FIGS. This will be described in detail with reference to Figure 13. Parts that are the same as those in the above embodiment or parts that have similar functions The steps and processes can be performed in the same manner as in the above embodiment, and repeated explanations will be omitted. Detailed explanations of the same parts will be omitted.

[0150] 12 and 13 show an example of a cross-sectional structure of a transistor. Transistors 640 and 650 have a top-gate structure similar to that of transistor 510 shown in FIG. is a thin film transistor.

[0151] In the oxide semiconductor layer of this embodiment, before the treatment for introducing the oxygen defect inducing factor, n-type impurities are added. Hydrogen is removed from the oxide semiconductor layer, and impurities other than the main components of the oxide semiconductor layer are minimized. By purifying it to such a high level that it is made into the true (i type), or into the true type. By removing impurities such as hydrogen and water as much as possible, highly purified intrinsic (i-type) semiconductors or We are getting close to that.

[0152] In addition, the number of carriers in the highly purified oxide semiconductor layer is extremely small (close to zero). , the carrier concentration is less than 1×1014 / cm3, preferably less than 1×1012 / cm3, More preferably, it is less than 1×10 11 / cm 3 .

[0153] Since the number of carriers in the oxide semiconductor layer is extremely small, the off-state current can be reduced. The lower the current, the more preferable.

[0154] Specifically, the transistor including the above-described oxide semiconductor layer has a channel width of The off-state current of the device must be 1×104zA / μm (1×10-17A / μm) or less. can be reduced to 1×103zA / μm (1×10-18A / μm) or less.

[0155] The difficulty in passing an off-state current through a transistor can be expressed as an off-state resistivity. Resistivity is the resistivity of the channel formation region when the transistor is off, and off resistivity is It can be calculated from the off-state current.

[0156] The off-resistance of the transistor including the oxide semiconductor layer of this embodiment is 1×10 Ω m More preferably, the resistance is 1×10 10 Ω·m or more.

[0157] In addition, the transistors 640 and 650 including the above-described oxide semiconductor layer have a temperature dependence of on-state current. Almost no dependence is observed and the off-current remains very small.

[0158] Hereinafter, a transistor will be described on a substrate 600 having an insulating surface with reference to FIGS. The steps for producing the star 640 will now be described.

[0159] The substrate 600 may be the same as the substrate 400 shown in the first embodiment. In this embodiment, a glass substrate is used as the substrate 600 .

[0160] An insulating layer 607 serving as a base film is formed over a substrate 600. The border layer 607 may be a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an oxide It is preferable to use an oxide insulating layer such as an aluminum nitride layer. For this purpose, a plasma CVD method, a sputtering method, or the like can be used. In order to prevent hydrogen from being contained in the insulating layer 607, an insulating layer 607 is formed by sputtering. It is preferable.

[0161] In this embodiment mode, a silicon oxide layer is formed as the insulating layer 607 by a sputtering method. The substrate 600 is transferred to a processing chamber and treated with a spatula containing high-purity oxygen from which hydrogen and moisture have been removed. A silicon semiconductor target is introduced and an insulating layer 607 is formed on the substrate 600. The silicon oxide layer is formed on the substrate 600. The substrate 600 may be at room temperature or may be heated. .

[0162] For example, quartz (preferably synthetic quartz) is used, the substrate temperature is 108° C., and the distance between the substrate and the target is 100 nm. The distance between the TS and the oxygen sensor was 60 mm, the pressure was 0.4 Pa, the high-frequency power supply was 1.5 kW, and the oxygen sensor and and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) atmosphere. A silicon oxide film is formed by F sputtering. The film thickness is 100 nm. Instead of quartz (preferably synthetic quartz), a silicon target is used to form a silicon oxide film. The sputtering gas can be oxygen or oxygen and The process is carried out using a mixture of argon and argon gas.

[0163] In this case, it is preferable to form the insulating layer 607 while removing residual moisture in the processing chamber. This is to prevent the insulating layer 607 from containing hydrogen, a hydroxyl group, or moisture.

[0164] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 In order to exhaust the compounds containing hydrogen atoms such as fluorine, the insulating layer 607 is formed in the treatment chamber. The concentration of impurities contained can be reduced.

[0165] The insulating layer 607 may have a laminated structure, for example, a silicon nitride layer, a nitride layer, and a nitride insulating layer such as a silicon oxide layer, an aluminum nitride layer, or an aluminum oxide nitride layer; The insulating layer may have a stacked structure of the oxide insulating layer and the oxide insulating layer.

[0166] For example, a spatula containing high-purity nitrogen from which hydrogen and moisture have been removed is used between the silicon oxide layer and the substrate. A target gas is introduced and a silicon nitride layer is formed using a silicon target. In the same manner as for the silicon oxide layer, the silicon nitride layer is formed while removing the residual moisture in the processing chamber. When forming a silicon nitride layer, the substrate may be heated during the film formation. stomach.

[0167] When a silicon nitride layer and a silicon oxide layer are laminated as the insulating layer 607, the silicon nitride layer The silicon oxide layer and the silicon oxide layer are formed in the same processing chamber using a common silicon target. First, nitrogen-containing sputtering gas is introduced to the silicon tubing mounted in the processing chamber. A silicon nitride layer was formed using a 1000 nm target, and then the sputtering gas was switched to an oxygen-containing gas. The silicon oxide layer is then formed using the same silicon target. The silicon nitride layer and the silicon layer can be formed successively without exposure to the atmosphere. This makes it possible to prevent impurities such as hydrogen and moisture from being adsorbed onto the surface.

[0168] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm to 30 nm, is formed on the insulating layer 607. An oxide semiconductor film having a thickness of 1 nm or less is formed.

[0169] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced. Reverse sputtering is performed to generate plasma, and the powdery material ( It is preferable to remove particles or debris from the target. The substrate was heated by applying a voltage to the substrate side using an RF power supply in an argon atmosphere without applying a voltage to the substrate side. This method involves forming plasma near the plate to modify the surface. Nitrogen, helium, oxygen, etc. may also be used.

[0170] The oxide semiconductor used for the oxide semiconductor film is an oxide of a quaternary metal, In-Sn-G a-Zn-O system, In-Ga-Zn-O system, which is an oxide of a ternary metal, In-Sn-Z nO system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system , Sn-Al-Zn-O system, In-Zn-O system, which is an oxide of binary metals, Sn-Zn -O system, Al-Zn-O system, Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O, Sn-O, Zn-O, etc. can be used. The conductive film may contain SiO2. In this embodiment, the oxide semiconductor film is an In-Ga -The film is formed by sputtering using a Zn-O oxide target. The semiconductor film is heated under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically It can be formed by sputtering in an atmosphere of oxygen (typically argon). do.

[0171] As a target for forming an oxide semiconductor film by a sputtering method, for example, The ratio is In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] (i.e., I n:Ga:Zn=1:1:0.5 [atom ratio]) can be used. , In:Ga:Zn=1:1:1 [atom ratio], or In:Ga:Zn=1:1:2 [ A target having a composition ratio of [atomic ratio] may be used. The filling rate of the oxide target is The content is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using an oxide semiconductor target, the formed oxide semiconductor film becomes a dense film.

[0172] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. It is preferable to use a high-purity gas from which any impurities have been removed.

[0173] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate temperature is preferably maintained at 100° C. or more and 600° C. or less. The temperature is preferably 200° C. or higher and 400° C. or lower. In addition, the concentration of impurities in the oxide semiconductor film can be reduced. Damage caused by etching is reduced. In addition, hydrogen and moisture are removed while removing residual moisture in the processing chamber. The removed sputtering gas is introduced, and an oxide semiconductor is deposited on the substrate 600 using the target. To remove residual moisture in the processing chamber, an adsorption-type pump such as a cryopump is used. It is preferable to use a vacuum pump. The process chamber is evacuated using a cryopump, e.g. , hydrogen, water (H2O), and other compounds containing hydrogen atoms (preferably compounds containing carbon atoms) Since the gas such as fluorine and fluorine is exhausted, the concentration of impurities in the oxide semiconductor film formed in the treatment chamber is can be reduced.

[0174] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed direct current (DC) power supply is used, the powdery substances (particulates) generated during film formation can be easily removed. This is preferable because it reduces the amount of dirt and dust that accumulates on the surface of the film and makes the film thickness uniform. The appropriate thickness varies depending on the oxide semiconductor material, and the thickness can be appropriately selected depending on the material. .

[0175] Next, the oxide semiconductor film is formed into an island-shaped oxide semiconductor layer 620 by a photolithography process. In addition, a resist mask for forming an island-shaped oxide semiconductor layer 620 is formed by inkjet printing. If the resist mask is formed by the inkjet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0176] Note that the etching of the oxide semiconductor film here may be performed by dry etching or wet etching. Alternatively, both may be used.

[0177] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride ( CCl4) and the like) are preferred.

[0178] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing added sulfur, etc. can be used.

[0179] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0180] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide water: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0181] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium, etc. contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0182] In order to etch the desired shape, the etching conditions (etching Adjust the etching conditions (liquid, etching time, temperature, etc.) as appropriate.

[0183] Next, first heat treatment is performed on the oxide semiconductor layer 620. The first heat treatment temperature can be set to 1000° C. or lower to 1500° C., so that the compound semiconductor layer 620 can be dehydrated or dehydrogenated. The temperature is from 400° C. to 750° C., or from 400° C. to less than the distortion point of the substrate.

[0184] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing equipment such as RTA (Rapid Thermal Annealing) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gas is used.

[0185] For example, the first heat treatment is performed by heating an inert gas to a high temperature of 650° C. or more and 700° C. or less. The substrate is then moved into the inert gas chamber and heated for a few minutes. GRTA can be used to heat the gas out. GRTA allows high-temperature heating in a short time. It becomes possible.

[0186] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0187] In addition, the oxide semiconductor layer is heated as heat treatment for dehydration or dehydrogenation, and a high-purity Oxygen gas, high purity NO gas, or ultra-dry air (dew point below -40℃, preferably - Cooling may be performed by introducing oxygen gas or N2O gas into the reactor. It is preferable that the oxygen gas or N2O introduced into the heat treatment device is not included. The purity of the gas should be 6N (99.9999%) or higher, preferably 7N (99.99999%). or more (i.e., impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably 0. It is preferable to keep the concentration of impurities below 1 ppm. The oxygen, the main component of oxide semiconductors, is also reduced during the process. This makes the oxide semiconductor layer 620 highly purified and electrically i-type (intrinsic).

[0188] In this embodiment, the substrate 600 is introduced into an electric furnace, which is one type of heat treatment device, and an oxide semiconductor is formed. The layer was heated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to air. Thus, the oxide semiconductor layer 620 can be obtained without causing any damage to the oxide semiconductor layer. Thus, the dehydration or dehydrogenation is carried out under an inert gas atmosphere such as nitrogen or a rare gas. When the heat treatment is performed, the oxide semiconductor layer 620 becomes n-type due to oxygen vacancies. This reduces the resistance.

[0189] The oxide semiconductor layer 620 may be formed by changing the conditions of the first heat treatment or the material of the oxide semiconductor layer. In some cases, the film may be crystallized to become a microcrystalline film or a polycrystalline film. Depending on the conditions or the material of the oxide semiconductor film, an amorphous oxide semiconductor film containing no crystalline components may be obtained. In some cases, the oxide semiconductor may be a conductive film. In some cases, it may be a semiconductor film.

[0190] In addition, the first heat treatment is performed on the oxide semiconductor film before it is processed into the island-shaped oxide semiconductor layer 620. In that case, after the first heat treatment, the substrate is removed from the heating device, A photolithography process is carried out.

[0191] The oxide semiconductor layer 620 described in this embodiment is used to form a channel formation region and a source region or Between the drain region, a lower concentration of oxygen defect inducing factors is included than between the source region and the drain region. Transistors 640, 650 having regions are shown in FIGS. 12(A) through 12(E) and 13(F). This will be described with reference to Figures 13(A) to 13(C).

[0192] An oxide semiconductor layer 620 is formed on a substrate 600 provided with an insulating layer 607 having an insulating surface. (See FIG. 12(A)).

[0193] A first source electrode layer 625a and a second source electrode layer 625b are in contact with one end of the oxide semiconductor layer 620. A first electrode layer 635a is formed in contact with the other end of the oxide semiconductor layer 620. A first drain electrode layer 625b and a second drain electrode layer 635b are stacked.

[0194] The first source electrode layer 625a and the first drain electrode layer 62 A metal nitride layer is used as the second source electrode layer 635a and the second drain electrode layer 635b. It is preferable to use a metal layer as the pole layer 635b. The electrode layer 625a and the first drain electrode layer 625b are made of titanium nitride films. The first drain electrode layer 635a and the second drain electrode layer 635b are made of an aluminum film and a titanium film. A lamination with a membrane is used.

[0195] An oxide semiconductor layer 620, a first source electrode layer 625a, a first drain electrode layer 625b, A gate insulating layer 60 is formed on the second source electrode layer 635a and the second drain electrode layer 635b. Form 2.

[0196] The gate insulating layer 602 has a thickness of at least 1 nm and is formed by a method such as sputtering. The insulating layer 602 can be formed by appropriately using a method that does not allow impurities such as water and hydrogen to be mixed into the insulating layer 602. Cut.

[0197] In this embodiment, a silicon oxide film having a thickness of 100 nm is sputtered as the gate insulating layer 602. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering. In a rare gas (typically argon) atmosphere, in an oxygen atmosphere, or in a rare gas (typically argon) atmosphere The target can be silicon oxide and oxygen. A silicon target or a silicon target can be used. Silicon oxide is formed by sputtering in an oxygen and nitrogen atmosphere using a sintered material. The gate insulating layer 602 formed in contact with the oxide semiconductor layer 620 can be resistant to moisture and It does not contain impurities such as hydrogen ions or hydroxyl groups, and blocks these from entering from the outside. The inorganic insulating film is typically a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. An aluminum oxynitride film, an aluminum nitride film, or the like is used.

[0198] In this case, the gate insulating layer 602 is formed while removing the residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 620 and the gate insulating layer 602 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed up.

[0199] To remove residual moisture from inside the processing chamber, use an adsorption type vacuum pump such as a cryopump. It is preferable that the processing chamber evacuated using a cryopump is filled with, for example, hydrogen or water ( Since compounds containing hydrogen atoms such as hydrogen ions (H2O) are exhausted, the gate insulating film formed in the processing chamber is The concentration of impurities contained in the edge layer 602 can be reduced.

[0200] Next, a second heat treatment (for example, 200 The heating is performed at a temperature of from 250° C. to 400° C., preferably from 250° C. to 350° C., for example, in a nitrogen atmosphere. The second heat treatment is performed at 250° C. for 1 hour under atmospheric pressure. A part of the semiconductor layer (including at least the channel forming region) is in contact with the gate insulating layer 602. It is heated.

[0201] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. Heat treatment is performed to remove hydrogen, moisture, hydroxyl groups, hydrides (also called hydrogen compounds), etc. The impurities are intentionally removed from the oxide semiconductor layer, and the impurities are simultaneously reduced by the impurity removal process. It is possible to supply oxygen, which is a main component material of oxide semiconductors, which are easily damaged. Therefore, at least a part of the oxide semiconductor layer including the channel formation region is highly purified and It becomes type I (true) electrically.

[0202] In this embodiment, the oxide semiconductor layer 620 is not in direct contact with the gate insulating layer 602. The region overlapping with the first source electrode layer 625a or the first drain electrode layer 625b is Since oxygen is not supplied by the second heat treatment, the region remains an n-type low resistance region.

[0203] A gate electrode layer 601 is formed over the gate insulating layer 602 (see FIG. 12B).

[0204] Note that a region corresponding to a channel formation region of the oxide semiconductor layer 620 (the gate electrode layer 601 and the The oxygen defect inducing factor may also be introduced into the overlapping region to include the oxygen defect inducing factor. In this case, the oxide semiconductor layer 620 is oxidized due to oxygen defects before the gate electrode layer 601 is formed. The oxygen vacancy inducing factor is introduced before the oxide semiconductor film is processed into islands. The oxygen defect inducing factor may also be introduced into the channel formation region to make the oxygen defects act as donors. By making the material have a lower resistance (e.g., n-type), the electrical characteristics of the transistor can be controlled more precisely. It is possible.

[0205] After the oxygen defect inducing factor introduction treatment, a heat treatment (for example, 200°C to 600°C) is performed. If an oxygen defect inducing factor is introduced before the first heat treatment, the heat treatment may be the first For example, the treatment for introducing oxygen vacancy-inducing factors and the treatment for introducing nitrogen The oxide semiconductor layer is made intrinsic by performing heat treatment at 200° C. to 600° C. in an atmosphere. can be made low resistance (n-type).

[0206] The oxide semiconductor layer 620 in this embodiment is a highly purified oxide semiconductor layer. The effect of introducing oxygen vacancy inducing factors is remarkable. Even a small amount can effectively control the electrical characteristics of the transistor.

[0207] Next, the gate electrode layer 601, the first source electrode layer 625a, and the first the first drain electrode layer 625b, the second source electrode layer 635a, and the second drain electrode layer 6 35b is used as a mask to selectively introduce oxygen defect inducer 630 into channel formation region 61 3. Oxygen deficiency inducing factor-containing regions 631a and 631b, and oxygen deficiency inducing factor non-introduced region 611 For example, the oxygen deficiency inducer-containing region 63a and 611b are formed (see FIG. 12(C)). The concentration of oxygen defect inducer 630 contained in 1a and 631b is 1×1018 atoms / It is sufficient to set it to about cm3.

[0208] By selectively introducing oxygen defect inducing factors 630 into the oxide semiconductor layer 620, This effectively induces oxygen vacancies in the introduction region. Since the oxygen vacancies function as donors, An oxide semiconductor having selectively reduced resistance oxygen defect inducer-containing regions 631a and 631b. A body layer can be formed.

[0209] In the region overlapping with the gate electrode layer 601, the oxygen defect inducing factor 630 is not introduced and a channel is not formed. This results in area 613.

[0210] The oxygen defect inducing factor 630 is not introduced into the oxygen defect inducing factor non-introduced regions 611a and 611b. However, it is possible to carry out dehydration or dehydrogenation under an inert gas atmosphere such as nitrogen or a rare gas. Since the first heat treatment for the purpose of n-type conversion has been performed, it is an n-type low resistance region. The first source electrode layer 625a or the first drain electrode layer 625b is , can be connected via an n-type low resistance region.

[0211] Next, the channel forming region 613, the oxygen defect inducing factor containing regions 631a and 631b, and the oxygen An oxide semiconductor layer including defect-inducing-factor-free regions 611a and 611b, and a first source electrode layer 625a, a first drain electrode layer 625b, a second source electrode layer 635a, a second drain An insulating layer 609 is formed to cover the gate electrode layer 635b, the gate insulating layer 602, and the gate electrode layer 601. do.

[0212] Next, oxygen defect inducer-containing regions 631a and 631b of the oxide semiconductor layer are The low-concentration oxygen defect inducing factor-containing regions 615a and 615b and the source region 6 14a, drain region 614b, channel formation region 613, oxygen defect inducing factor non-introduced region An oxide semiconductor layer 633 including 611a and 611b is formed (see FIG. 12D). For example, the concentration of oxygen defect inducer 632 contained in the source region 614a and the drain region 614b The concentration is between 1×1019 atoms / cm3 and 1×1021 atoms / cm3. Good.

[0213] In addition, the insulating layer 609 provided on the side of the gate electrode layer 601 also serves as a mask. The oxygen is introduced into the oxide semiconductor layer 620 overlapping the electrode layer 601 and the insulating layer 609 provided on the side surface. The introduction of the defect-inducing factor 632 is inhibited, and the low-concentration oxygen defect-inducing factor-containing regions 615a, 61 In particular, in this embodiment, since the gate electrode layer 601 is thick, the oxide semiconductor The introduction of oxygen defect inducing factors 632 into the conductor layer 620 is further inhibited.

[0214] In addition, when the oxygen defect inducing factor is introduced into the channel forming region 613, the channel forming region 613 is The concentration of the oxygen defect inducing factor contained in the growth region 613 is reduced to that of the low concentration oxygen defect inducing factor containing region 6 The impurity concentration of the source region 614a and the drain region 614b is lower than that of the source region 614a and the drain region 614b. As in the embodiment, oxygen vacancies are induced in the source region 614a and the drain region 614b. The concentration of the causative agent is 1×1019 atoms / cm3 or more and 1×1021 atoms / cm3 or more. The lower part shows the oxygen deficiency inducing factor contained in the low concentration oxygen deficiency inducing factor-containing regions 615a and 615b. If the concentration is about 1×10 atoms / cm, for example, the channel formation region 61 The concentration of 3 may be less than 1×1014 atoms / cm3.

[0215] Through the above steps, the transistor 640 can be manufactured (see FIG. 12E).

[0216] In a transistor 650 shown in FIG. 13C, a gate insulating layer overlaps with a gate electrode layer 601. The area other than the above is removed, forming an island-shaped gate insulating layer 604. Therefore, the insulating layer 609 is The low-concentration oxygen vacancy inducing factor containing regions 615a and 615b of the oxide semiconductor layer 633, the source region region 614a, drain region 614b, first source electrode layer 625a, first drain electrode layer 625b, a second source electrode layer 635a, a second drain electrode layer 635b, and a gate It is provided in contact with the electrode layer 601 .

[0217] As in the transistor 640, after the steps up to FIG. 12C, a gate electrode layer 601 is formed. Using this as a mask, the gate insulating layer is etched to form an island-shaped gate insulating layer 604 (FIG. 13(A)).

[0218] The etching of the gate insulating layer forms oxygen defect inducing factor containing regions 631a and 631b. In this case, the oxygen defect inducing factor is introduced into the exposed The ions are directly introduced into the oxide semiconductor layer 620 .

[0219] Next, the channel forming region 613, the oxygen defect inducing factor containing regions 631a and 631b, and the oxygen An oxide semiconductor layer including defect-inducing-factor-free regions 611a and 611b, and a first source electrode layer 625a, a first drain electrode layer 625b, a second source electrode layer 635a, a second drain An insulating layer 609 is formed to cover the gate electrode layer 635b, the gate insulating layer 604, and the gate electrode layer 601. In FIG. 13, an oxygen vacancy inducing factor-containing region 631 in an oxide semiconductor layer 633 The gate insulating layer on 631a, 631b has been removed, so that the insulating layer 609 is exposed to oxygen vacancies. It is formed adjacent to the recessive induction factor-containing regions 631a and 631b.

[0220] Next, oxygen defect inducer-containing regions 631a and 631b of the oxide semiconductor layer are The low-concentration oxygen defect inducing factor-containing regions 615a and 615b and the source region 6 14a, drain region 614b, channel formation region 613, oxygen defect inducing factor non-introduced region An oxide semiconductor layer 633 including 611a and 611b is formed (see FIG. 13B). For example, the concentration of oxygen defect inducers 636 contained in the source region 614a and the drain region 614b The concentration is between 1×1019 atoms / cm3 and 1×1021 atoms / cm3. Good.

[0221] In addition, the insulating layer 609 provided on the side of the gate electrode layer 601 also serves as a mask. The oxygen is introduced into the oxide semiconductor layer 620 overlapping the electrode layer 601 and the insulating layer 609 provided on the side surface. The introduction of the defect-inducing factor 636 is inhibited, and the low-concentration oxygen defect-inducing factor-containing regions 615a, 61 In particular, in this embodiment, the thickness of the gate electrode layer 601 is large, and Since the insulating layer 604 is also formed, oxygen defect inducing factors 636 in the oxide semiconductor layer 620 The introduction of this technology will be further hindered.

[0222] Through the above steps, the transistor 650 can be manufactured.

[0223] The oxygen defect inducing factors 630, 632, and 636 include titanium (Ti), tungsten (W ), Molybdenum (Mo), Aluminum (Al), Cobalt (Co), Zinc (Zn), Indium (In), silicon (Si), and boron (B) are selected from one or more of the following: In addition to the oxygen vacancy inducing factors, hydrogen or In addition, oxygen vacancy inducers 630, 632, and 636 may be oxygen. It is more preferable to use a metal element having a high affinity with oxygen.

[0224] As described above, the low-concentration oxygen vacancy-inducing factor-containing film was reduced in resistance by the introduction of the oxygen vacancy-inducing factor. The source region 614a is a region containing a high concentration of oxygen defect inducing factors. a transistor 640 including an oxide semiconductor layer 633 having a drain region 614b; 650 is a semiconductor layer including an oxide semiconductor layer 633, a first source electrode layer 625a, and a first drain electrode layer Since the contact resistance with 625b can be reduced, the on-characteristics (e.g., on-current and field effect Therefore, a transistor with excellent electrical characteristics can be obtained.

[0225] A transistor with high electrical characteristics is capable of high-speed response and high-speed operation. By providing the above, a highly functional semiconductor device can be obtained.

[0226] Furthermore, by using an oxide semiconductor layer whose conductivity is changed stepwise, This suppresses field concentration and prevents the application of localized high electric fields, improving the breakdown voltage of transistors and This makes it possible to impart high reliability to the conductor device.

[0227] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0228] (Embodiment 5) A semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIG. The same parts as those in the second embodiment or parts having similar functions and steps are the same as those in the first embodiment. Alternatively, the same process as in the second embodiment can be performed, and a repeated explanation will be omitted.

[0229] First, an insulating layer 407 is formed on a substrate 400. Then, a first oxide film is formed on the insulating layer 407. and forming a first oxide semiconductor layer on the first oxide semiconductor layer by a first heat treatment. The region containing the oxide semiconductor layer 450a is crystallized to form a first oxide semiconductor layer 450a (see FIG. 4A). .

[0230] The first oxide semiconductor layer 450a formed on the insulating layer 407 is an oxide of a ternary metal. The oxide semiconductor material is expressed by the chemical formula InMXZnYOZ (Y = 0.5 to 5). Here, M is gallium (Ga), aluminum (Al), boron (B), etc. It represents one or more elements selected from the group 13 elements of Zn and O. The amount is arbitrary, including the case where the content of M is zero (i.e., X=0). On the other hand, In and Z The n content is not zero. That is, the above notation includes In-Ga-Zn-O and In- Zn-O and others.

[0231] In addition, the first oxide semiconductor layer 450a may be made of an oxide of a quaternary metal, In—Sn -Ga-Zn-O system, ternary metal oxides In-Sn-Zn-O system, Sn-Ga -Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O and binary metal oxides The materials are Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, Sn-O, Zn-O, and other base materials can also be used.

[0232] In this embodiment, the first oxide semiconductor layer 450a is made of an In-Ga-Zn-O based oxide. The film is formed by sputtering using a semiconductor target.

[0233] The relative density of the oxide semiconductor in the oxide semiconductor target is 80% or more, preferably 95% or more. The relative density of the oxide semiconductor target is preferably 99.9% or more. By using the above, a dense first oxide semiconductor layer 450a is formed. In this embodiment, the first oxide semiconductor layer 450a is intentionally crystallized by performing heat treatment later. Therefore, it is preferable to use an oxide semiconductor target which is easily crystallized.

[0234] The first oxide semiconductor layer 450a is formed in a rare gas (typically, argon) atmosphere. It is preferable to use an oxygen atmosphere or a mixed atmosphere of a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed. It is preferred to use a high purity gas atmosphere.

[0235] When the first oxide semiconductor layer 450a is formed, for example, in a treatment chamber maintained in a reduced pressure state, The substrate is held in the processing chamber at a temperature of 200° C. or higher and 600° C. or lower. While removing moisture, a sputtering gas from which hydrogen and water have been removed is introduced to target metal oxide. The first oxide semiconductor layer 450a is formed as a substrate. By forming the conductor layer 450a, the impurities contained in the first oxide semiconductor layer 450a are The first oxide can be reduced. Also, damage caused by sputtering is reduced. Before, during, or after the deposition of the semiconductor layer 450a, the semiconductor layer 450a remains in the sputtering device. It is preferable to remove the moisture remaining in the processing chamber. It is preferable to use an adsorption type vacuum pump such as a cryopump. Since hydrogen, water, and the like have been removed from the evacuated treatment chamber, the first oxide semiconductor layer 45 The impurity concentration of 0a can be reduced.

[0236] Before the first oxide semiconductor layer 450a is formed, moisture remaining in the sputtering apparatus is removed. It is recommended to perform a preheating process to remove the above. The inside of the bar is heated to 200°C or higher and 600°C or lower under reduced pressure. After the preheating process, the substrate or the After the sputtering device is cooled, the oxide semiconductor layer is formed without being exposed to the air. The target coolant should be oil or fat, not water. Nitrogen can be introduced and exhausted without heating. Repeating the process will produce a certain level of effect, but it is even better if you do it while heating.

[0237] The first oxide semiconductor layer 450a is formed under the following conditions: Distance: 170 mm, pressure: 0.4 Pa, direct current (DC) power: 0.5 kW, atmosphere: oxygen In addition, if a pulsed direct current (DC) power source is used, This reduces dust (powder or flake-like material formed during film formation) and improves film thickness distribution. The thickness of the first oxide semiconductor layer 450a is preferably greater than or equal to 3 nm and less than or equal to 15 nm. In the present embodiment, the thickness is set to 5 nm or less. The appropriate thickness varies depending on the semiconductor material and its application. The method may be selected depending on the purpose.

[0238] The temperature of the first heat treatment is 450° C. or higher and 850° C. or lower, preferably 550° C. or higher and 750° C. or lower. The heating time is set to 1 minute or more and 24 hours or less. Heat treatment is performed at 700°C for 1 hour in a nitrogen atmosphere to dehydrate or dehydrogenate the material. After the oxidation, the atmosphere is changed to an oxygen atmosphere to form the first oxide semiconductor layer 45. Oxygen is supplied to the inside of the first oxide semiconductor layer 40a by the first heat treatment. Water (including hydroxyl groups), hydrogen, etc. in 50a can be removed.

[0239] In the first heat treatment, nitrogen, oxygen, helium, neon, argon, or the like is used. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon is 6N (99.99 99%) or more, preferably 7N (99.99999%) or more (i.e. impurity concentration of 1pp It is preferable that the concentration of H2O is 20ppm or less, preferably 0.1ppm or less. m or less, more preferably in ultra-dry air with HO of 1 ppm or less, A first heat treatment may be performed. Water (including hydroxyl groups), hydrogen, and the like in layer 450a can be removed.

[0240] The first heat treatment results in a crystalline region (non-single crystal region) at least in a region including the surface. The first oxide semiconductor layer 450a is formed. The crystalline region formed in the region including the surface is The crystals grow from the surface to the inside. The crystalline regions have an average thickness of 2n The crystal region is a plate-like crystal having a thickness of 10 nm or more and a thickness of 10 nm or less. The term "almost perpendicular" refers to a region having crystals with their c-axes oriented in the -1 This refers to a state within 0° or within +10° from the vertical.

[0241] The heat treatment device used in the first heat treatment is not particularly limited, and may be a heat treatment device that uses a heat source such as a resistance heating element. A device for heating the workpiece by thermal conduction or thermal radiation from the heat source can be used.

[0242] Next, a first oxide semiconductor layer 450a having a crystalline region at least in a region including a surface thereof is Then, a second oxide semiconductor layer 454 is formed (see FIG. 4B).

[0243] The second oxide semiconductor layer 454 is made of a quaternary metal oxide semiconductor layer, similar to the first oxide semiconductor layer 450a. The oxide In-Sn-Ga-Zn-O system and the oxide of a ternary metal In-Ga- Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, and binary metal oxides I n-Zn-O series, Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg Oxide semiconductors such as In-O, In-Mg-O, In-O, Sn-O, and Zn-O. The electrode can be formed using:

[0244] The second oxide semiconductor layer 454 is made of a material having the same main component as the first oxide semiconductor layer 450a. Use materials with the same crystal structure and close lattice constants (mismatch of 1% or less). ) is preferably used. Alternatively, it may be formed using materials having different main components.

[0245] In the case where the materials having the same main component are used, the second oxide semiconductor layer 454 is crystallized later. In this case, crystal growth can be easily performed using the crystalline regions of the first oxide semiconductor layer 450a as seeds. In addition, the effective film thickness can be increased, making it suitable for applications such as power devices. Furthermore, when the main components are the same, the interface properties such as adhesion and electrical properties are also different. It's good.

[0246] In this embodiment, the second oxide semiconductor layer 454 is an In—Ga—Zn—O-based oxide semiconductor. The second oxide semiconductor layer 45 is formed by a sputtering method using a conductive target. The sputtering method for forming the fourth oxide semiconductor layer 450a is the same as that for forming the first oxide semiconductor layer 450a. The second oxide semiconductor layer 454 may be formed in the same manner as in the case of the ring method. It is preferable that the thickness of the first oxide semiconductor layer 450a is thicker than that of the first oxide semiconductor layer 450b. The sum of the thicknesses of the oxide semiconductor layer 450a and the second oxide semiconductor layer 454 is 3 nm or more and 50 nm or less. The second oxide semiconductor layer 454 is preferably formed so as to have the following structure. The appropriate thickness varies depending on the oxide semiconductor material and the application, so the thickness depends on the material and the application. The selection may be made according to the application.

[0247] Next, the second oxide semiconductor layer 454 is subjected to second heat treatment, and the first oxide semiconductor layer 45 The crystal region of Oa is used as a seed for crystal growth to form a second oxide semiconductor layer 450b ( See Figure 4(C).

[0248] The temperature of the second heat treatment is 450° C. or higher and 850° C. or lower, preferably 600° C. or higher and 700° C. or lower. The heating time of the second heat treatment is from 1 minute to 400 hours, preferably from 5 hours. The time limit is from 10 hours to 20 hours, typically 10 hours.

[0249] In the second heat treatment, nitrogen, oxygen, helium, neon, argon, etc. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gas such as helium, neon, or argon is preferably 6N or more. It is preferable to use a pressure of 7N or more. In addition, in ultra-dry air with H2O of 20ppm or less, More preferably, the second heat treatment is performed in ultra-dry air with an H2O content of 1 ppm or less. Such second heat treatment may remove water (hydroxide) from the second oxide semiconductor layer 450b. This allows the removal of impurities and high purity, i.e., the removal of hydrogen and other impurities. The first oxide semiconductor layer 450a and the second oxide semiconductor layer 450b are i-type or substantially i-type. Layer 450b can be formed.

[0250] In addition, the inside of the furnace was kept in a nitrogen atmosphere during the heating of the second heat treatment, and the inside of the furnace was kept in an oxygen atmosphere during the cooling. The atmosphere may be switched to a nitrogen atmosphere, and crystallization may be performed in a nitrogen atmosphere (this process is also called dehydration or After the hydrogen-removal process, the atmosphere is switched to an oxygen atmosphere to perform the second hydrogen-removal process. Oxygen can be supplied to the inside of the oxide semiconductor layer 450b.

[0251] In this manner, by performing the second heat treatment, the second oxide semiconductor layer 454 and the first oxide semiconductor layer 455 are The crystalline region formed at the interface of the second oxide semiconductor layer 450a to the entire second oxide semiconductor layer 454 The second oxide semiconductor layer 450b can be formed by crystallizing the second oxide semiconductor layer 450b. The first oxide semiconductor layer 450 is a crystal layer having a higher crystal orientation by the heat treatment. It can be a.

[0252] For example, an In-Ga-Zn-O-based oxide semiconductor material is used for the second oxide semiconductor layer 450b. When used, it is represented by InGaO3(ZnO)m (m>0, but m is not limited to a natural number). The crystals represented by the formula In2Ga2ZnO7 (In:Ga:Zn:O = 2:2:1:7) Such crystals may include crystals in which the c-axis is aligned in the same direction as the first heat treatment. The direction is approximately perpendicular to the surfaces of the first oxide semiconductor layer 450a and the second oxide semiconductor layer 450b. The orientation is such that

[0253] Here, the above-mentioned crystal contains any one of In, Ga, and Zn, and has an a-axis and It can be considered as a laminated structure of layers parallel to the a-axis and b-axis. In general, the above crystals are made up of layers containing In and layers not containing In (Ga or The layer has a structure in which layers containing Zn or a layer containing Zn are stacked in the c-axis direction.

[0254] In the In-Ga-Zn-O oxide semiconductor crystal, the a-axis and The conductivity in the direction parallel to the a-axis is good. In semiconductor crystals, the electrical conduction is mainly controlled by In, and The 5s orbital of In overlaps with the 5s orbital of the adjacent In, forming a carrier path. This is achieved by:

[0255] In addition, the first oxide semiconductor layer 450a is formed so as to have an amorphous region at the interface with the insulating layer 407. In the case of such a structure, the second heat treatment is performed to remove the oxide semiconductor layer 450a from the surface thereof. Crystal growth occurs from the crystalline region formed on the lower surface of the first oxide semiconductor layer toward the lower surface of the first oxide semiconductor layer. In some cases, the amorphous region may be crystallized. Depending on the processing conditions, the amorphous regions may remain.

[0256] The first oxide semiconductor layer 450a and the second oxide semiconductor layer 454 are made of oxide semiconductors having the same main component. When a conductive material is used, the first oxide semiconductor layer 450a is crystallized as shown in FIG. The second oxide semiconductor layer 454 is grown upward as a crystal seed toward the surface of the second oxide semiconductor layer 454. The first oxide semiconductor layer 450a and the second oxide semiconductor layer 450b are formed. The semiconductor layer 450b has the same crystal structure as the semiconductor layer 450a. However, the boundary between the first oxide semiconductor layer 450a and the second oxide semiconductor layer 450b cannot be distinguished. Therefore, the first oxide semiconductor layer 450a and the second oxide semiconductor layer 450b are regarded as the same layer. Sometimes it can be done.

[0257] The heat treatment device used for the second heat treatment is also used under the same conditions as those for the first heat treatment. can be done.

[0258] Next, the first oxide semiconductor layer 450a and The second oxide semiconductor layer 450b is processed into an island shape to form the island-shaped oxide semiconductor layer 450. (See Figure 4(D)).

[0259] The island-shaped oxide semiconductor layer 450 thus formed is used to form a semiconductor layer having a thickness of 100 nm or less, and the manufacturing method described in any of Embodiments 1 to 3 is used. In combination, a transistor according to one embodiment of the present invention can be formed.

[0260] As shown in this embodiment, the oxide semiconductor layer is formed in two separate steps and is subjected to heat treatment in two separate steps. By performing this process, the thickness of the film can be adjusted regardless of the material of the underlying material, whether it is an oxide, nitride, or metal. It is possible to obtain a crystal region with a c-axis oriented perpendicular to the film surface. In addition, when using a general silicon semiconductor, the crystal structure is destroyed after ion implantation. This resulted in a significant increase in resistivity, so it was necessary to restore the crystallinity by heat treatment. In this embodiment, the oxide semiconductor in the portion where the oxygen vacancy inducing factor is ion-implanted is The crystal structure collapses and becomes amorphous. Even in the amorphous state, the necessary conductivity can be obtained if there are sufficient carriers. No annealing is required after implantation.

[0261] Such a transistor using an oxide semiconductor layer having a crystalline region has a high field-effect transition property. It is possible to realize high on-state characteristics such as high mobility. In addition, it is possible to realize a transistor with low off-state current. It can be realized.

[0262] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0263] (Embodiment 6) The transistors shown as examples in any of the above-mentioned embodiments 1 to 5 can be used in a pixel portion and a driver circuit. In this way, a semiconductor device having a display function (also called a display device) can be manufactured. The transistors and part or the whole of the driver circuit are formed on the same substrate as the pixel section, A moon panel can be formed.

[0264] Display devices having various display elements using the transistors illustrated in any of the embodiments 1 to 5 can be used. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0265] In FIG. 5A, a pixel portion 4002 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided and the semiconductor device is sealed with a second substrate 4006. In A), a region surrounded by a sealant 4005 on a first substrate 4001 and The semiconductor layer is formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate in a different region. A scanning line driver circuit 4004 and a signal line driver circuit 4003 are also mounted. A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a signal line driver circuit 4005 are provided to the pixel portion 4002. Various signals and potentials are transmitted through the FPC (Flexible Printed Circuit). )Powered by 4018a and 4018b.

[0266] In FIG. 5B and FIG. 5C, a pixel portion 4002 is provided on a first substrate 4001. A sealant 4005 is provided so as to surround the scanning line driver circuit 4004 . In addition, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are in a synchronous with the first substrate 4001. The display element is sealed by a sealing material 4005 and a second substrate 4006. In FIG. 5B and FIG. 5C, the first substrate 4001 is surrounded by a sealant 4005. A single crystal semiconductor film or a polycrystalline semiconductor film is formed on a separately prepared substrate in a region different from the region where the semiconductor device is mounted. A signal line driver circuit 4003 formed of a conductor film is mounted. In the above embodiment, a signal line driver circuit 4003 and a scanning line driver circuit 4004 are separately formed. Various signals and potentials applied to the pixel portion 4002 are supplied from an FPC 4018. .

[0267] In addition, in FIG. 5B and FIG. 5C, a signal line driver circuit 4003 is separately formed. However, the present invention is not limited to this configuration. The circuit may be formed separately and mounted, or may be a part of a signal line driver circuit or a part of a scanning line driver circuit. Alternatively, only the portion may be formed separately and mounted.

[0268] The method of connecting the separately formed drive circuit is not particularly limited, and may be any of the following: ip On Glass) method, wire bonding method, or TAB (Tape A A method such as a utomated bonding method can be used. This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the OG method. FIG. 5B shows an example in which a signal line driver circuit 4003 is mounted by the COG method, and FIG. 4003) is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0269] The display device includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs, etc., including the above, are mounted.

[0270] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC or TAB tape. Modules with TCP attached, TAB tape or TCP with printed wiring board attached The IC (integrated circuit) is directly mounted on the installed module or display element using the COG method. The display device includes all of the modules installed in the display device.

[0271] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. The semiconductor device has a plurality of transistors, examples of which are shown in the first to fifth embodiments. A transistor having such a structure can be applied.

[0272] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. The liquid crystal materials used are: Depending on the conditions, cholesteric phase, smectic phase, cubic phase, chiral nematic phase, etc. It shows phases such as cubic and isotropic.

[0273] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing at least a few percent by weight of a chiral agent is used in the liquid crystal layer. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a short response speed of 1 msec or less. Since the liquid crystal display is optically isotropic, no alignment treatment is required and the viewing angle dependency is small. Since there is no need to provide a rubbing treatment, the It is possible to prevent electrostatic damage, which may occur during the manufacturing process, and to reduce defects and damage to liquid crystal display devices. Therefore, it is possible to improve the productivity of the liquid crystal display device. The electrical characteristics of transistors that use conductor layers are significantly affected by static electricity. Therefore, the temperature of a transistor using an oxide semiconductor layer may vary significantly and deviate from the design range. It is more effective to use a blue phase liquid crystal material in a liquid crystal display device having the above-mentioned structure.

[0274] The liquid crystal material has a resistivity of 1×109 Ω·cm or more, and preferably 1×1011 The resistivity is preferably 1×1012 Ω·cm or more, and more preferably 1×1012 Ω·cm or more. The resistivity values ​​stated herein are those measured at 20°C.

[0275] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. The capacitance is set so that the charge can be held for a certain period of time, taking into account factors such as the capacitance of the capacitor. The value may be set in consideration of the off-state current of the transistor. By using a transistor having a high-purity oxide semiconductor layer as shown in FIG. A storage volume having a volume of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal volume in the storage volume. It is enough to set the amount.

[0276] There are two types of LCD displays: TN (Twisted Nematic) and IPS (In-P lane-Switching) mode, FFS(Fringe Field Switching) mode, ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode, etc.

[0277] In addition, normally black type liquid crystal display devices, such as those using a vertical alignment (VA) mode, The liquid crystal display device may be a transmission type liquid crystal display device. There are several types of vertical alignment modes, including: For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV mode, etc. can be used.

[0278] The present invention can also be applied to VA type liquid crystal display devices. VA type LCDs are a type of display that controls the arrangement of liquid crystal molecules in LCD panels. In this method, the liquid crystal molecules are oriented vertically to the panel surface when no voltage is applied. In addition, a pixel is divided into several regions (subpixels), each of which is illuminated in a different direction. It is said to be a multi-domain or multi-domain design that is designed to defeat molecules. The method can be used.

[0279] In addition, in display devices, they are used as black matrices (light-shielding layers), polarizing members, phase difference members, reflectors, etc. Optical members (optical substrates) such as a prevention member are provided as appropriate. For example, a polarizing substrate and a retardation substrate Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0280] The display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is The color is not limited to the three colors red, green, and blue. For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. The present invention is not limited to display devices with a single display, but can also be applied to display devices with a monochrome display. can.

[0281] In addition, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element utilizing electroluminescence is made of a light-emitting material They are classified according to whether they are organic or inorganic compounds. Generally, the former are called organic E The latter is called an inorganic EL element.

[0282] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0283] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. This is a localized emission that uses

[0284] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display) and is a paper-based display. It is possible to make a display that is as easy to read as a regular display, consumes less power than other displays, and is thinner and lighter in size. This has the advantage that

[0285] The electrophoretic display device may have various forms, but it has a first particle having a positive charge and A microcapsule containing a negatively charged second particle and a negatively charged second particle is introduced into a solvent or solute. By applying an electric field to the microcapsules, The particles in the cell are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. In addition, the first particles or the second particles contain a dye, and they do not migrate in the absence of an electric field. The color of the first particle and the color of the second particle are different (including colorless). )

[0286] In this way, the electrophoretic display device is a so-called This is a display that utilizes the dielectrophoretic effect.

[0287] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0288] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0289] In addition, display devices using the twist ball display method can also be used as electronic paper. The twist ball display method uses black and white spherical particles as the display element. The insulating layer is disposed between a first electrode layer and a second electrode layer, and the first electrode layer and the second electrode layer are electrically connected to each other. This is a method of displaying information by controlling the orientation of spherical particles by applying a potential difference to the electrode layer. be.

[0290] The transistors described in any of Embodiments 1 to 5 can be applied to the display device shown as the above example. Thus, it is possible to provide a display device having various functions.

[0291] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0292] (Embodiment 7) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0293] FIG. 6(A) shows a semiconductor device according to any one of the first to sixth embodiments as at least one component. The notebook-type personal computer is manufactured by mounting the main body 3001 and the housing 3 3002, a display unit 3003, a keyboard 3004, etc.

[0294] FIG. 6B shows a semiconductor device according to any one of the first to sixth embodiments as at least one component. The main body 3021 has a display unit 3023. An external interface 3025 and an operation button 3024 are also provided. A stylus 3022 is included as an accessory for the function.

[0295] The semiconductor device described in any one of the first to sixth embodiments can be used as electronic paper. FIG. 6(C) shows an electronic book created by mounting the electronic paper as a part. FIG. 6C shows an example of an electronic book. For example, an electronic book 2700 is a case. The device is made up of two housings, a body 2701 and a housing 2703. 2703 is integrated with an axis portion 2711, and is opened and closed around the axis portion 2711. With this configuration, it is possible to operate like a paper book. become.

[0296] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2705 in FIG. 6C) and An image can be displayed on a display unit (display unit 2707 in FIG. 6C).

[0297] FIG. 6C shows an example in which an operation unit and the like are provided in the housing 2701. The body 2701 includes a power source 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. A keyboard and a pointing device may be provided on the rear of the housing. On the front and sides, there are external connection terminals (earphone terminal, USB terminal, etc.), a recording medium insertion part, etc. Furthermore, the electronic book 2700 may have a function as an electronic dictionary. The above configuration may also be used.

[0298] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0299] FIG. 6(D) shows a semiconductor device having at least one component, which is shown in any one of the first to sixth embodiments. This mobile phone is constructed by mounting the two housings 2800 and 2801. The housing 2801 includes a display panel 2802, a speaker 2803, a microphone, and a microphone array. Phone 2804, pointing device 2806, camera lens 2807, external connection The housing 2800 is also provided with a terminal 2808 and the like. It is equipped with a solar cell 2810, an external memory slot 2811, etc. Also, an antenna is built into the housing 2801.

[0300] The display panel 2802 is equipped with a touch panel, and in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also implements a boost circuit to boost the voltage supplied to each circuit to the voltage required.

[0301] The display direction of the display panel 2802 changes appropriately depending on the usage mode. Since it has a camera lens 2807 on the same surface as 2802, video telephony is possible. The speaker 2803 and the microphone 2804 are not limited to voice calls, but can also be used for video calls, Recording and playback are possible. Furthermore, the housing 2800 and the housing 2801 can be slid. As shown in 6(D), it can be folded up from the unfolded state, making it convenient to carry. It is possible to reduce the size.

[0302] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication with a personal computer, etc. A recording medium can be inserted into the memory slot 2811 to accommodate larger amounts of data storage and transfer. do.

[0303] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0304] FIG. 6(E) shows a semiconductor device having at least one component, which is a semiconductor device according to any one of the first to sixth embodiments. This is a digital video camera that is manufactured by implementing the above. The main body 3051, the display unit (A) 3057 , eyepiece 3053, operation switch 3054, display unit (B) 3055, battery 3056 It is composed of the following:

[0305] FIG. 6(F) shows a semiconductor device having at least one component, which is shown in any one of the first to sixth embodiments. 96 shows an example of a television device 9600 that is implemented as a In the embodiment, a display unit 9603 is incorporated in a housing 9601. In addition, the housing 9601 is supported by a stand 9605. This shows a configuration that maintains the same characteristics as the previous example.

[0306] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. The remote control can also be operated by the remote control. A display unit for displaying the output information may be provided.

[0307] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0308] This embodiment mode can be freely combined with any of the first to sixth embodiment modes. [Explanation of symbols]

[0309] 400 Substrates 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating Layer 409 Insulating layer 410 Transistor 411 Insulating layer 413 Channel formation region 414a Source Region 414b Drain region 415a Low concentration oxygen deficiency inducing factor-containing region 415b Low concentration oxygen deficiency inducing factor-containing region 420 Oxide semiconductor layer 421 Oxygen deficiency inducer 430 Oxygen deficiency inducer 431a Oxygen deficiency inducer-containing region 431b Oxygen deficiency inducer-containing region 432 Oxygen deficiency inducer 433 Oxide Semiconductor Layer 434 Oxygen deficiency inducer 440 Transistor 450 Oxide semiconductor layer 450a First oxide semiconductor layer 450b Second oxide semiconductor layer 454 Second oxide semiconductor layer 500 boards 501 Gate electrode layer 502 Gate insulation layer 503 Oxide semiconductor layer 507 Insulating layer 510 Transistor 511a Oxygen deficiency factor non-introduced region 511b Oxygen deficiency factor non-introduced region 512a Source Region 512b Drain region 513 Channel formation region 520 Oxide semiconductor layer 521 Oxygen deficiency inducer 545a second source electrode layer 545b Second drain electrode layer 555a First source electrode layer 555b First drain electrode layer 600 Substrates 601 Gate electrode layer 602 Gate insulating layer 604 Gate insulation layer 607 Insulating Layer 609 Insulating layer 611a Oxygen deficiency factor non-introduced region 611b Oxygen deficiency factor non-introduced region 613 Channel formation region 614a Source Region 614b Drain region 615a Low concentration oxygen deficiency inducing factor-containing region 615b Low concentration oxygen deficiency inducing factor-containing region 620 Oxide semiconductor layer 625a first source electrode layer 625b first drain electrode layer 630 Oxygen deficiency inducer 631a Oxygen deficiency inducer-containing region 631b Oxygen deficiency inducer-containing region 632 Oxygen deficiency inducer 633 Oxide Semiconductor Layer 635a second source electrode layer 635b second drain electrode layer 636 Oxygen deficiency inducer 640 Transistor 650 Transistors 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 2800 Chassis 2801 Case 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 Solar Cell 2811 External memory slot 3001 Main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main unit 3022 Stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 First substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Second Board 4018 FPC 4018a FPC 4018b FPC 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand

Claims

[Claim 1] an oxide semiconductor layer over an insulating surface; a gate insulating layer above the oxide semiconductor layer; a gate electrode layer over the gate insulating layer; a source electrode layer above the oxide semiconductor layer; a drain electrode layer above the oxide semiconductor layer, the oxide semiconductor layer has a channel formation region, a first region, and a second region; the first region is electrically connected to the source electrode layer; the second region is electrically connected to the drain electrode layer; the first region contains more of an element selected from one or more of titanium, tungsten, molybdenum, cobalt, zinc, and silicon than the channel formation region; The semiconductor device according to claim 1, wherein the second region contains more of an element selected from the group consisting of titanium, tungsten, molybdenum, cobalt, zinc, and silicon than the channel formation region.

Images