Method for manufacturing semiconductor device

Abstract

To provide a method for manufacturing a semiconductor device with improved yield.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a SiC layer 10 on a single-crystal SiC layer of a substrate having a polycrystalline SiC substrate 2 and a single-crystal SiC layer 6 thereon; forming, on the SiC layer, a first insulating film 40 and a second insulating film 32 separated from each other in an X-direction by a third width W3; removing a first portion 5 of the single-crystal SiC layer extending in a Y-direction intersecting the X-direction and a second portion 7 of the SiC layer provided on the first portion and extending in the Y-direction, below and between the first insulating film and the second insulating film, to form a second groove 72 having a second width W2 narrower than the third width in the X-direction, extending in the Y-direction, cutting the single-crystal SiC layer and the SiC layer, and having the polycrystalline SiC substrate exposed on its bottom; and forming, by dicing, a first groove 82 provided below the second groove, having a first width W1 narrower than the second width in a first direction, extending in the Y-direction, and cutting the polycrystalline SiC substrate.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] SiC (silicon carbide) is expected to be a material for next-generation semiconductor devices. Compared to Si (silicon), silicon carbide has about three times the band gap, about ten times the breakdown electric field strength, and about three times the thermal conductivity. Therefore, by using SiC, it is possible to realize semiconductor devices that are low-loss and capable of operating at high temperatures. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-034255 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a method for manufacturing a semiconductor device with improved yield. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to an embodiment includes the steps of: forming a SiC layer on the single-crystal SiC layer of a substrate having a polycrystalline SiC substrate having a first surface and a second surface; and forming a first insulating film and a second insulating film on the SiC layer, the first insulating film and the second insulating film being spaced apart from each other by a third width in a first direction parallel to the second surface; forming a first portion of the single-crystal SiC layer between the first insulating film and the second insulating film and extending in a second direction parallel to the second surface and intersecting the first direction; and a second portion of the SiC layer provided on the first portion and extending in the second direction to form a second groove having a second width narrower than the third width in the first direction, extending in the second direction, cutting the single crystal SiC layer and the SiC layer, and exposing the polycrystalline SiC substrate at a bottom thereof, and forming a first groove by dicing, provided below the second groove, having a first width narrower than the second width in the first direction, extending in the second direction, and cutting the polycrystalline SiC substrate. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 is a schematic cross-sectional view of a substrate according to the first embodiment. [Diagram 2] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 3] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 4] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 5] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 9] 4 is a flowchart showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 10]5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 11] 5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 12] 5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 13] 5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 14] 10 is a flowchart showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 15] FIG. 11 is a schematic diagram of a predetermined layer in the third embodiment. [Figure 16] FIG. 11 is a schematic diagram of a predetermined layer in the third embodiment. [Figure 17] FIG. 13 is a schematic diagram of a predetermined layer in a comparative example of the third embodiment. [Figure 18] FIG. 13 is a schematic diagram of a predetermined layer in a comparative example of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same members are designated by the same reference numerals, and the description of members that have already been described will be omitted as appropriate.

[0008] In the following description, n + , n, n - And, p + , p, p - When the notations are used, these notations indicate the relative high and low impurity concentrations in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The types are simply n-type and p-type. + type, p -The type is sometimes simply referred to as p-type.

[0009] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained, for example, by SCM (Scanning Capacitance Microscopy). The distance, such as the depth, of the impurity region can be obtained, for example, by SIMS. The distance, such as the width and depth of the impurity region can be obtained, for example, from an SCM image.

[0010] Hereinafter, the first conductivity type will be referred to as n-type, and the second conductivity type will be referred to as p-type.

[0011] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing is described as "upper" and the downward direction of the drawing is described as "lower." In this specification, the concepts of "upper" and "lower" are not necessarily terms that indicate a relationship with the direction of gravity.

[0012] (First embodiment) A method for manufacturing a semiconductor device according to the present embodiment includes the steps of: forming a SiC layer on the single-crystal SiC layer of a substrate having a polycrystalline SiC substrate having a first surface and a second surface; forming a first insulating film and a second insulating film spaced apart from each other by a third width in a first direction parallel to the second surface on the SiC layer; removing a first portion of the single-crystal SiC layer below the first insulating film and the second insulating film, the first portion extending in a second direction parallel to the second surface and intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, to form a second groove having a second width narrower than the third width in the first direction, extending in the second direction, and cutting the single-crystal SiC layer and the SiC layer, and having the polycrystalline SiC substrate exposed at a bottom thereof; and forming a first groove by dicing, the first groove being provided below the second groove, having a first width narrower than the second width in the first direction, extending in the second direction, and cutting the polycrystalline SiC substrate.

[0013] 1 to 8 are schematic cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment, and Fig. 9 is a flow chart showing the manufacturing process of the semiconductor device of this embodiment.

[0014] The semiconductor device 100 of this embodiment is a semiconductor chip. The semiconductor device 100 of this embodiment is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, the semiconductor device 100 is not limited to this and may be, for example, a PIN diode or the like.

[0015] First, a substrate 4 as shown in FIG. 1 is prepared.

[0016] The substrate 4 includes a polycrystalline SiC substrate 2 and a single-crystalline SiC layer 6 .

[0017] The polycrystalline SiC substrate 2 has a first surface 1 and a second surface 3. The second surface 3 is provided on the opposite side to the first surface 1.

[0018] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The first surface 1 and the second surface 3 are provided parallel to the XY plane. The X direction is an example of a first direction. The Y direction is an example of a second direction. The -X direction is an example of a third direction.

[0019] The thickness of the polycrystalline SiC substrate 2 in the Z direction is, for example, about 350 μm.

[0020] The single crystal SiC layer 6 is provided on the second surface 3 of the polycrystalline SiC substrate 2. The single crystal SiC layer 6 has a thickness in the Z direction of, for example, 0.4 μm or more and 0.7 μm or less.

[0021] The substrate 4 is, for example, a substrate in which a single crystal SiC layer 6 is bonded to a polycrystalline SiC substrate 2.

[0022] Voids (holes) V may be formed between the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6. The voids (holes) V are thought to be formed, for example, due to circumstances such as the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6 not being properly bonded together. Note that in Fig. 2 and subsequent figures, illustration of the voids (holes) V between the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6 is omitted.

[0023] Next, a SiC layer 10 is formed on the single crystal SiC layer 6 by epitaxial growth using, for example, a CVD (Chemical Vapor Deposition) method (S102 in FIGS. 2 and 9). The SiC layer 10 is an epitaxial SiC layer. Note that, as shown in FIG. 2, a part of the SiC layer 10 may be formed directly on the polycrystalline SiC substrate 2.

[0024] Next, the device structure of the semiconductor device 100 is formed on the SiC layer 10. For example, the conductive film 20, the conductive film 22, the conductive film 24, and the conductive film 26 are formed. For example, when the semiconductor device 100 is a MOSFET, the conductive film 20, the conductive film 22, the conductive film 24, and the conductive film 26 are the source electrode of the MOSFET. The conductive film 20, the conductive film 22, the conductive film 24, and the conductive film 26 include a conductive material such as Al (aluminum), Au (gold), Ag (silver), Cu (copper), etc.

[0025] Next, the insulating film 30 and the insulating film 40 are formed on the SiC layer 10 such that the conductive film 20 is provided between the insulating film 30 and the insulating film 40. Also, the insulating film 32 and the insulating film 42 are formed on the SiC layer 10 such that the conductive film 22 is provided between the insulating film 32 and the insulating film 42. Also, the insulating film 34 and the insulating film 44 are formed on the SiC layer 10 such that the conductive film 24 is provided between the insulating film 34 and the insulating film 44. Also, the insulating film 36 and the insulating film 46 are formed on the SiC layer 10 such that the conductive film 26 is provided between the insulating film 36 and the insulating film 46. The insulating film 30, the insulating film 32, the insulating film 34, the insulating film 36, the insulating film 40, the insulating film 42, the insulating film 44, and the insulating film 46 are, for example, interlayer insulating films of the semiconductor device 100. The insulating film 30, the insulating film 32, the insulating film 34, the insulating film 36, the insulating film 40, the insulating film 42, the insulating film 44, and the insulating film 46 include, for example, an insulating material such as polyimide (S104 in FIG. 3 and FIG. 9).

[0026] 7, which will be described later, for example, one semiconductor device 100 includes a conductive film 20, an insulating film 30, and an insulating film 40. Also, for example, one semiconductor device 100 includes a conductive film 22, an insulating film 32, and an insulating film 42. Also, for example, one semiconductor device 100 includes a conductive film 24, an insulating film 34, and an insulating film 44. Also, for example, one semiconductor device 100 includes a conductive film 26, an insulating film 36, and an insulating film 46.

[0027] The insulating film 40 (an example of a first insulating film) and the insulating film 32 (an example of a second insulating film) are spaced apart from each other by a third width in the X direction. The spaced apart portion between the insulating film 40 and the insulating film 32 is a dicing line 52. The insulating film 42 (an example of a first insulating film) and the insulating film 34 (an example of a second insulating film) are spaced apart from each other by the third width in the X direction. The spaced apart portion between the insulating film 42 and the insulating film 34 is a dicing line 54. The insulating film 44 (an example of a first insulating film) and the insulating film 36 (an example of a second insulating film) are spaced apart from each other by the third width in the X direction. The spaced apart portion between the insulating film 44 and the insulating film 36 is a dicing line 56. A dicing line 50 is provided on the −X direction side of the insulating film 30. A dicing line 58 is provided on the +X direction side of the insulating film 46. The third width is illustrated as “W3” in FIG. 8 described later.

[0028] Dicing lines 50, 52, 54, 56, and 58 are portions that will be diced using, for example, a blade in a later process. Dicing lines 50, 52, 54, 56, and 58 each extend in the Y direction.

[0029] Similarly, dicing lines (not shown) extending in the X direction may be provided.

[0030] Next, a photomask (mask) 60, for example, a photoresist, is formed on the polycrystalline SiC substrate 2, the SiC layer 10, the conductive film 20, the conductive film 22, the conductive film 24, the conductive film 26, the insulating film 30, the insulating film 32, the insulating film 34, the insulating film 36, the insulating film 40, the insulating film 42, the insulating film 44, and the insulating film 46 (FIG. 4). Note that the photomask 60 in the portions of the dicing lines 52, 54, 56, and 58 has openings parallel to the Y direction.

[0031] Next, using a photomask (mask) 60, the portion of the single crystal SiC layer 6 extending in the Y direction and the portion of the SiC layer 10 extending in the Y direction below between the insulating film 40 and the insulating film 32 are removed along the dicing line 52. Here, the portion of the single crystal SiC layer 6 extending in the Y direction that is removed is the first portion 5 of the single crystal SiC layer 6 illustrated in FIG. 8. Also, the portion of the SiC layer 10 extending in the Y direction that is removed is the second portion 7 of the SiC layer 10 illustrated in FIG. 8. Thereby, a second groove 72 that cuts the single crystal SiC layer 6 and the SiC layer 10 is formed (S106 in FIG. 5 and FIG. 9). The width of the second groove 72 is the second width. The second width is narrower than the third width. The second width is illustrated as "W2" in FIG. 8.

[0032] Similarly, a second groove 74 is formed along the dicing line 54 below between the insulating film 42 and the insulating film 34. A second groove 76 is formed along the dicing line 56 below between the insulating film 44 and the insulating film 36. A second groove 78 is formed along the dicing line 58. A second groove 70 is also formed.

[0033] Here, the second grooves 70, 72, 74, 76, and 78 are formed by reactive ion etching (RIE) using a fluorine-based gas such as SF6 (sulfur hexafluoride). Note that the fluorine-based gas such as SF6 may be diluted with Ar (argon) or the like.

[0034] Here, it is preferable that the polycrystalline SiC substrate 2 is exposed at the bottoms of the second grooves 70, 72, 74, 76 and 78.

[0035] The second grooves 70, 72, 74, 76, and 78 may be formed by using plasma dicing, wet etching, chemical dry etching (CDE), or the like.

[0036] Next, the photomask 60 is removed (FIG. 6).

[0037] Next, a first groove 82 is formed by dicing using, for example, a blade B. The first groove 82 is provided below the second groove 72, has a first width narrower than the second width in the X direction, extends in the Y direction, and cuts the polycrystalline SiC substrate 2. Similarly, the first groove 80 is formed below the second groove 70. Similarly, the first groove 84 is formed below the second groove 74. Note that a first groove (not shown) is also formed below the second groove 76 and the second groove 78 (S108 in Figs. 7 and 9). Note that the first groove 82 may be formed by laser dicing or plasma dicing. The first width is illustrated as "W1" in Fig. 8.

[0038] Here, the first surface 1 of the polycrystalline SiC substrate 2 is attached to a dicing tape S, for example.

[0039] The individual portions separated by the first grooves are peeled off from the dicing tape S to obtain the semiconductor device 100 of this embodiment.

[0040] FIG. 8 is an enlarged schematic cross-sectional view of the first groove 82 and the second groove 72. As shown in FIG.

[0041] The width of the first groove 82 in the X direction is a first width W1. The width of the second groove 72 in the X direction is a second width W2. In the X direction, the insulating film 40 and the insulating film 32 are spaced apart by a third width W3.

[0042] The second width W2 is preferably larger than the first width W1 by width W1b in the X direction and width W1a in the -X direction. Here, width W1b and width W1a are preferably 10 μm or more and 25 μm or less, respectively. Therefore, the second width W2 is preferably larger than the first width W1 by 10 μm or more and 25 μm or less in the X direction and -X direction, respectively.

[0043] The third width W3 is preferably larger than the second width W2 by width W2b in the X direction and width W2a in the -X direction. Here, width W2a and width W2b are preferably 5 μm or more and 10 μm or less, respectively. Therefore, the third width W3 is preferably larger than the second width W2 by 5 μm or more and 10 μm or less in the X direction and -X direction, respectively.

[0044] Next, the effects of this embodiment will be described.

[0045] It is difficult to manufacture a high-quality single-crystal SiC substrate. Therefore, it is conceivable to manufacture a bonded substrate by thermally peeling off a single-crystal SiC base material from a polycrystalline SiC substrate 2 while the base material is attached to the polycrystalline SiC substrate 2 to form a thin plate, and then bonding the single-crystal SiC layer to the polycrystalline SiC substrate 2.

[0046] However, there is a problem in that voids (vacancies) are formed between the polycrystalline SiC substrate 2 and the single-crystalline SiC layer 6.

[0047] When such a bonded substrate is diced, there is a problem in that the single crystal SiC layer is chipped or peeled off.

[0048] In the portion where a void (vacancy) is formed between the polycrystalline SiC substrate 2 and the single-crystalline SiC layer, for example, the single-crystalline SiC layer is in a state of being floating from the polycrystalline SiC substrate 2. In addition, in the portion where a void (vacancy) is formed between the polycrystalline SiC substrate 2 and the single-crystalline SiC layer, the single-crystalline SiC layer and the polycrystalline SiC substrate 2 are in a state of being partially bonded with a very small area. When cutting such a void portion, the single-crystalline SiC layer, which is relatively thinner than the polycrystalline SiC substrate 2, is peeled off by contact with the blade or frictional force, resulting in chipping or peeling. Such chipping or peeling can cause a decrease in the electrical characteristics and reliability of the semiconductor device. Similar chipping and peeling can also occur when laser dicing or plasma dicing is performed.

[0049] Furthermore, such bonded substrates may have a laminated substrate structure with different crystal structures, which can cause problems such as substrate warping due to differences in stress between the polycrystalline SiC substrate 2 and the single-crystal SiC layer, or distortion at the bonding interface between the polycrystalline SiC substrate 2 and the single-crystal SiC layer.

[0050] Therefore, the method for manufacturing the semiconductor device of the present embodiment includes the steps of: forming a SiC layer on the single-crystal SiC layer of the substrate having a polycrystalline SiC substrate having a first surface and a second surface, and a single-crystal SiC layer provided on the second surface; forming a first insulating film and a second insulating film spaced apart from each other by a third width in a first direction parallel to the second surface on the SiC layer; removing a first portion of the single-crystal SiC layer below the first insulating film and the second insulating film, the first portion extending in a second direction parallel to the second surface and intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, to form a second groove having a second width narrower than the third width in the first direction, extending in the second direction, and cutting the single-crystal SiC layer and the SiC layer, and having the polycrystalline SiC substrate exposed at its bottom; and forming a first groove by dicing, the first groove being provided below the second groove, having a first width narrower than the second width in the first direction, extending in the second direction, and cutting the polycrystalline SiC substrate.

[0051] According to the method for manufacturing a semiconductor device of this embodiment, a second groove is formed to cut the single crystal SiC layer 6 and the SiC layer 10 before dicing. This makes it possible to suppress chipping and peeling of the single crystal SiC layer 6 and the SiC layer 10 that occurs when forming the first groove by dicing. Therefore, according to the method for manufacturing a semiconductor device of this embodiment, it is possible to provide a method for manufacturing a semiconductor device with improved yield.

[0052] Furthermore, since the single crystal SiC layer and the SiC layer are divided into small areas during the manufacturing process, the above-mentioned warpage of the substrate can be suppressed.

[0053] The second width W2 is preferably 10 μm or more and 25 μm or less in the X direction and the −X direction than the first width W1. The widths W1a and W1b (FIG. 8) are preferably larger than the kerf deviation width caused by the meandering of the cut line of the substrate, which is caused by the mechanical accuracy of the dicing device, the specifications of the blade B (blade thickness, strength), the cutting speed of the dicing device, etc. This kerf deviation width is about 10 μm in the X direction and the −X direction. Therefore, the second width W2 is preferably 10 μm or more larger than the first width W1 in the X direction and the −X direction. On the other hand, if the difference between the second width W2 and the first width W1 in the X direction and the −X direction is larger than 25 μm, the number of semiconductor chips that can be obtained is reduced, which is not preferable.

[0054] The third width W3 is preferably 5 μm to 10 μm larger than the second width W2 in both the X direction and the −X direction. During dry etching, the SiC layer under the insulating film may be etched back and the insulating film may protrude like an eaves. To prevent this, the third width W3 is preferably 5 μm or more larger than the second width W2 in both the X direction and the −X direction. On the other hand, it is sufficient that the third width W3 is 10 μm larger than the second width W2.

[0055] It is preferable that the polycrystalline SiC substrate 2 is exposed at the bottoms of the second groove 70, the second groove 72, the second groove 74, the second groove 76, and the second groove 78. In other words, it is preferable that a part of the second groove is formed so as to extend into the polycrystalline SiC substrate 2.

[0056] For example, a case where the first groove is formed by dicing using a blade will be described. When the void V comes into contact with the blade and the polycrystalline SiC substrate 2 is cut further, there are cases where the polycrystalline SiC substrate 2 cannot be cut smoothly. For example, it is presumed that some unintended pressure is applied to the surrounding polycrystalline SiC substrate 2, single crystal SiC layer 6, and SiC layer 10 by the gas in the void V. If a part of the second groove is formed so as to cut into the polycrystalline SiC substrate 2, it is possible to reliably avoid contact between the SiC layer 10, single crystal SiC layer 6, and void V and the blade during dicing to form the first groove.

[0057] According to the method for manufacturing a semiconductor device of the present embodiment, it is possible to provide a method for manufacturing a semiconductor device with improved yield.

[0058] Second embodiment The method for manufacturing a semiconductor device according to the present embodiment includes the steps of: forming a SiC layer on the single-crystal SiC layer of a substrate having a polycrystalline SiC substrate having a second surface; and forming a third insulating film and a fourth insulating film, each containing an oxide, spaced apart from each other by a second width in a first direction parallel to the second surface on the SiC layer; and forming a first portion of the single-crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction below the third insulating film and the fourth insulating film. the first insulating film and the fourth insulating film, forming a first insulating film and a second insulating film on the SiC layer, the first insulating film and the second insulating film being spaced apart in the first direction by a third width greater than the second width and sandwiching the second groove; and forming, by dicing, a first groove that is provided below the second groove, has a first width in the first direction narrower than the second width, extends in the second direction, and cuts the polycrystalline SiC substrate.

[0059] Here, the description of the contents that overlap with the first embodiment will be omitted.

[0060] 10 to 13 are schematic cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment, and Fig. 14 is a flow chart showing the manufacturing process of the semiconductor device of this embodiment.

[0061] As in the first embodiment, the SiC layer 10 is formed on the single crystal SiC layer 6 by epitaxial growth using, for example, a CVD (Chemical Vapor Deposition) method (S202 in FIG. 14).

[0062] Next, an insulating film 62 containing an oxide, an insulating film 63 containing an oxide (an example of a third insulating film), an insulating film 64 containing an oxide (an example of a fourth insulating film), an insulating film 65 containing an oxide, an insulating film 66 containing an oxide, and an insulating film 67 containing an oxide are formed on the SiC layer 10. The insulating films 62 and 63 are spaced apart from each other by a second width in the X direction. The insulating films 63 and 64 are spaced apart from each other by a second width in the X direction. The insulating films 64 and 65 are spaced apart from each other by a second width in the X direction. The insulating films 65 and 66 are spaced apart from each other by a second width in the X direction. The insulating films 66 and 67 are spaced apart from each other by the second width in the X direction (S204 in FIGS. 10 and 14).

[0063] The spaced apart portion between insulating film 62 and insulating film 63 is dicing line 50. The spaced apart portion between insulating film 63 and insulating film 64 is dicing line 52. The spaced apart portion between insulating film 64 and insulating film 65 is dicing line 54. The spaced apart portion between insulating film 65 and insulating film 66 is dicing line 56. The spaced apart portion between insulating film 66 and insulating film 67 is dicing line 58.

[0064] Next, using insulating films 62, 63, 64, 65, 66 and 67 as masks, a second groove 70 is formed in dicing line 50, a second groove 72 in dicing line 52, a second groove 74 in dicing line 54, a second groove 76 in dicing line 56, and a second groove 78 in dicing line 58 (S206 in Figures 11 and 14).

[0065] Here, the insulating film 62, the insulating film 63, the insulating film 64, the insulating film 65, the insulating film 66, and the insulating film 67 include, for example, an oxide. The insulating film 62, the insulating film 63, the insulating film 64, the insulating film 65, the insulating film 66, and the insulating film 67 include, for example, silicon oxide.

[0066] Next, the insulating films 62, 63, 64, 65, 66 and 67 are removed (S208 of S14).

[0067] Next, the device structure of the semiconductor device 100 is formed on the SiC layer 10. For example, the conductive film 20, the conductive film 22, the conductive film 24, and the conductive film 26 are formed. Next, the insulating film 30 and the insulating film 40 are formed on the SiC layer 10 such that the conductive film 20 is provided between the insulating film 30 and the insulating film 40. Also, the insulating film 32 and the insulating film 42 are formed on the SiC layer 10 such that the conductive film 22 is provided between the insulating film 32 and the insulating film 42. Also, the insulating film 34 and the insulating film 44 are formed on the SiC layer 10 such that the conductive film 24 is provided between the insulating film 34 and the insulating film 44. Also, the insulating film 36 and the insulating film 46 are formed on the SiC layer 10 such that the conductive film 26 is provided between the insulating film 36 and the insulating film 46.

[0068] Here, the insulating film 40 (an example of a first insulating film) and the insulating film 32 (an example of a second insulating film) are spaced apart from each other by a third width in the X direction. The insulating film 42 (an example of a first insulating film) and the insulating film 34 (an example of a second insulating film) are spaced apart from each other by the third width in the X direction. The insulating film 44 (an example of a first insulating film) and the insulating film 36 (an example of a second insulating film) are spaced apart from each other by the third width in the X direction (S210 in FIGS. 12 and 14).

[0069] Next, a first groove 82 that is provided below the second groove 72, has a first width narrower than the second width in the X direction, extends in the Y direction, and cuts the polycrystalline SiC substrate 2 is formed, for example, by dicing using a blade B. Similarly, a first groove 80 is formed below the second groove 70. Similarly, a first groove 84 is formed below the second groove 74. Note that first grooves (not shown) are also formed below the second groove 76 and the second groove 78 (S212 in FIGS. 13 and 14).

[0070] Here, the first surface 1 of the polycrystalline SiC substrate 2 is attached to a dicing tape S, for example.

[0071] The individual portions separated by the first grooves are peeled off from the dicing tape S to obtain the semiconductor device 100 of this embodiment.

[0072] For example, there may be a case where it is required to ensure the resistance of a photomask during dry etching because the SiC layer 10 is thick. In such a case, a manufacturing method using the insulating films 62, 63, 64, 65, 66, and 67 as masks, as in the manufacturing method of the semiconductor device of this embodiment, is suitable.

[0073] According to the method for manufacturing a semiconductor device of this embodiment, it is possible to provide a method for manufacturing a semiconductor device with improved yield.

[0074] Third embodiment The method for manufacturing a semiconductor device of this embodiment differs from the methods for manufacturing a semiconductor device of the first and second embodiments in that in the step of forming the second groove, a predetermined layer having a third portion that is a part of the first portion and a fourth portion that is provided on the third portion and is a part of the second portion is formed in the second groove. Here, a description of the contents that overlap with the first and second embodiments will be omitted.

[0075] 15A to 15C are schematic top views showing a manufacturing process of the semiconductor device of this embodiment. The schematic cross-sectional view shown in FIG. 6 corresponds to, for example, the AA' cross section in FIG.

[0076] Fig. 16 is a schematic diagram of the predetermined layer 102 of this embodiment. Fig. 16(a) is a schematic top view of the predetermined layer 102 of this embodiment. Fig. 16(b) is a schematic cross-sectional view of the predetermined layer 102 of this embodiment taken along the line BB' of Fig. 16(a).

[0077] In the process of forming the second grooves 70, 72, 74, 76, and 78, a predetermined layer 102 is formed in each of the second grooves. Here, in the process of forming the second grooves, the portion of the single-crystal SiC layer 6 extending in the Y direction that is removed is the first portion 5 of the single-crystal SiC layer 6 (FIG. 8). In addition, in the process of forming the second grooves, the portion of the SiC layer 10 extending in the Y direction that is removed is the second portion 7 of the SiC layer 10 (FIG. 8). The predetermined layer 102 has a third portion 9 that is a portion of the first portion 5 that is not removed and left in the second grooves, and a fourth portion 11 that is a portion of the second portion that is not removed and left in the second grooves. The fourth portion 11 is provided on the third portion 9.

[0078] In addition, when a portion of the second groove 70, the second groove 72, the second groove 74, the second groove 76 and the second groove 78 are each formed in the polycrystalline SiC substrate 2, a portion of the polycrystalline SiC substrate 2 around the specified layer 102 is also removed.

[0079] In Fig. 16(a), the shape of the predetermined layer 102 is a cross shape when viewed from above. However, the shape of the predetermined layer 102 when viewed from above is not limited to a cross shape. For example, the shape of the predetermined layer 102 when viewed from above may be a rectangle.

[0080] In the dicing device, a camera captures an image of the pattern arranged on the dicing line, and performs an alignment operation (alignment) of the substrate 4. The predetermined layer 102 is used as a reference (alignment mark) for aligning the substrate 4.

[0081] Fig. 17 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device in a comparative embodiment of this embodiment. Fig. 18 is a schematic view of a predetermined layer 1002 in a comparative embodiment of this embodiment. Fig. 18(a) is a schematic top view of the predetermined layer 1002 in the comparative embodiment. Fig. 18(b) is a schematic cross-sectional view of the predetermined layer 1002 in the comparative embodiment at the A-A' cross section of Fig. 18(a).

[0082] The predetermined layer 1002 has a metal layer 1004 provided on the single crystal SiC layer 6 and the SiC layer 10. Here, the metal layer 1004 contains a metal material such as Al (aluminum). The metal layer 1004 corresponds to, for example, the conductive film 20 shown in the first and second embodiments. The single crystal SiC layer 6 and the SiC layer 10 around the metal layer 1004 are not removed by dry etching or the like.

[0083] The metal layer 1004 of the comparative example contains a conductive material such as Al, similar to the conductive film 20. In this case, the surface may become rough or the shape may change due to the influence of manufacturing processes after formation, such as sintering heat treatment, a developer used in photolithography, or a chemical used to remove the photoresist. If the surface becomes rough and light is diffused or the shape differs from the predetermined shape, there is a problem that the alignment accuracy decreases.

[0084] In the method for manufacturing a semiconductor device according to the present embodiment, a predetermined layer 102 having a single crystal SiC layer 6 and a portion of a SiC layer 10 is formed. Therefore, the number of manufacturing steps can be reduced compared to the comparative example in which a predetermined layer 1002 having a metal layer is formed. In addition, since the predetermined layer 102 is made of SiC, it is less susceptible to the effects of process steps compared to the predetermined layer 1002 containing a metal material. Therefore, the alignment of the substrate 4 can be performed more satisfactorily.

[0085] According to the method for manufacturing a semiconductor device of this embodiment, it is possible to provide a method for manufacturing a semiconductor device with improved yield.

[0086] Although some embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0087] The above-described embodiments can be summarized as the following technical solutions. (Technical proposal 1) forming a SiC layer on the single crystal SiC layer of a substrate having a polycrystalline SiC substrate with a first surface and a second surface, and a single crystal SiC layer provided on the second surface; forming a first insulating film and a second insulating film spaced apart from each other by a third width in a first direction parallel to the second surface on the SiC layer; a step of removing a first portion of the single-crystal SiC layer, the first portion being parallel to the second surface and extending in a second direction intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, below the first insulating film and the second insulating film, to form a second groove having a second width narrower than the third width in the first direction, extending in the second direction, cutting the single-crystal SiC layer and the SiC layer, and having the polycrystalline SiC substrate exposed at a bottom thereof; forming a first groove by dicing, the first groove having a first width narrower than the second width in the first direction and extending in the second direction to cut the polycrystalline SiC substrate; A method for manufacturing a semiconductor device comprising the steps of: (Technical proposal 2) forming a SiC layer on the single crystal SiC layer of a substrate having a polycrystalline SiC substrate with a first surface and a second surface, and a single crystal SiC layer provided on the second surface; forming a third insulating film and a fourth insulating film containing an oxide on the SiC layer, the third insulating film and the fourth insulating film being spaced apart from each other by a second width in a first direction parallel to the second surface; forming a second groove having the second width in the first direction, extending in the second direction, and cutting the single-crystal SiC layer and the SiC layer by removing a first portion of the single-crystal SiC layer below the third insulating film and the fourth insulating film, the first portion being parallel to the second surface and extending in a second direction intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction; removing the third insulating film and the fourth insulating film; forming a first insulating film and a second insulating film spaced apart from each other by a third width greater than the second width in the first direction on the SiC layer and sandwiching the second trench; forming a first groove by dicing, the first groove having a first width narrower than the second width in the first direction and extending in the second direction to cut the polycrystalline SiC substrate; A method for manufacturing a semiconductor device comprising the steps of: (Technical proposal 3) The second width is greater than the first width by 10 μm or more and 25 μm or less in both the first direction and a third direction opposite to the first direction. A method for manufacturing a semiconductor device according to Technical Scheme 1 or 2. (Technical proposal 4) The third width is greater than the second width by 5 μm or more and 10 μm or less in both the first direction and a third direction opposite to the first direction. A method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 3. (Technical proposal 5) forming the second groove by dry etching using a photoresist provided on the first insulating film and the second insulating film as a mask; A method for manufacturing a semiconductor device according to any one of technical proposals 1, 3, and 4. (Technical proposal 6) In the step of forming the second groove, a third portion that is a part of the first portion; and a fourth portion disposed on the third portion and being a part of the second portion; forming a predetermined layer having A method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 5. [Explanation of symbols]

[0088] 1 Page 1 2 Polycrystalline SiC substrate 3 Side 2 4. Board 6 Single crystal SiC layer 7 Part 3 10 SiC layer 11 Part 4 20 Conductive Film 22 Conductive Film 24 Conductive Film 26 Conductive Film 30 Insulating film 32 Insulating film 34 Insulating film 36 Insulating Film 40 Insulating film 42 Insulating film 44 Insulating Film 46 Insulating Film 50 Dicing Line 52 Dicing Line 54 Dicing Line 56 Dicing Line 58 Dicing Line 60 Photomask 62 Insulating film 63 Insulating Film 64 Insulating Film 65 Insulating Film 66 Insulating Film 67 Insulating Film 70 Second groove 72 Second groove 74 Second groove 76 Second groove 78 Second groove 80 1st groove 82 First groove 84 First groove 100 Semiconductor device 102 Predetermined layer 1002 Predetermined layer B-Blade S Dicing Tape V void W1 1st width W2 Second width W3 3rd width

Claims

1. forming a SiC layer on the single crystal SiC layer of a substrate having a polycrystalline SiC substrate with a first surface and a second surface, and a single crystal SiC layer provided on the second surface; forming a first insulating film and a second insulating film spaced apart from each other by a third width in a first direction parallel to the second surface on the SiC layer; a step of removing a first portion of the single-crystal SiC layer below between the first insulating film and the second insulating film, the first portion being parallel to the second surface and extending in a second direction intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, to form a second groove having a second width in the first direction narrower than the third width, extending in the second direction, cutting the single-crystal SiC layer and the SiC layer, and having a bottom at which the polycrystalline SiC substrate is exposed; forming a first groove by dicing, the first groove having a first width narrower than the second width in the first direction and extending in the second direction to cut the polycrystalline SiC substrate; A method for manufacturing a semiconductor device comprising the steps of:

2. forming a SiC layer on the single crystal SiC layer of a substrate having a polycrystalline SiC substrate with a first surface and a second surface, and a single crystal SiC layer provided on the second surface; forming a third insulating film and a fourth insulating film containing an oxide on the SiC layer, the third insulating film and the fourth insulating film being spaced apart from each other by a second width in a first direction parallel to the second surface; forming a second groove having the second width in the first direction, extending in the second direction, and cutting the single crystal SiC layer and the SiC layer by removing a first portion of the single crystal SiC layer below between the third insulating film and the fourth insulating film, the first portion being parallel to the second surface and extending in a second direction intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction; removing the third insulating film and the fourth insulating film; forming a first insulating film and a second insulating film spaced apart from each other by a third width greater than the second width in the first direction on the SiC layer and sandwiching the second trench; forming a first groove by dicing, the first groove having a first width narrower than the second width in the first direction and extending in the second direction to cut the polycrystalline SiC substrate; A method for manufacturing a semiconductor device comprising the steps of:

3. The second width is greater than the first width by 10 μm or more and 25 μm or less in both the first direction and a third direction opposite to the first direction.

3. The method for manufacturing a semiconductor device according to claim 1.

4. The third width is greater than the second width by 5 μm or more and 10 μm or less in the first direction and in a third direction opposite to the first direction, 3. The method for manufacturing a semiconductor device according to claim 1.

5. forming the second groove by dry etching using a photoresist provided on the first insulating film and the second insulating film as a mask; The method for manufacturing a semiconductor device according to claim 1.

6. In the step of forming the second groove, a third portion that is a part of the first portion; and a fourth portion provided on the third portion and being a part of the second portion; forming a predetermined layer having 3. The method for manufacturing a semiconductor device according to claim 1.

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