Semiconductor device

Abstract

To allow measurement of dimensions.SOLUTION: A semiconductor device 10 includes: a semiconductor substrate 30 that is formed into a rectangular shape when seen from a Z direction, and includes four corner parts 41-44 and four substrate side faces 33-36 forming the four corner parts 41-44; a circuit pattern 80 that is formed on the semiconductor substrate 30; and a measurement pattern 90 that is formed separate from the circuit pattern 80 when seen from the Z direction. When seen from the Z direction, the semiconductor substrate 30 is divided into a plurality of areas RA along an X direction and a Y direction in which the two substrate side faces 33, 35 constituting the one corner part 41 extend. The plurality of areas RA include four areas RA1-RA4 including the corner parts 41-44, respectively, and the measurement pattern 90 is arranged in at least two areas of the four areas RA1-RA4.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices are configured to include various wirings. For example, Patent Document 1 discloses a semiconductor integrated circuit integrated on a semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-241497 A

[0004] [overview] Incidentally, as wiring formed on a semiconductor substrate becomes finer, measurement of the dimensions of the wiring is sometimes performed.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate formed in a rectangular shape when viewed in a thickness direction, the semiconductor substrate including four corner portions and four substrate side surfaces forming the four corner portions, a circuit pattern formed on the semiconductor substrate, and a measurement pattern formed at a distance from the circuit pattern when viewed in the thickness direction, the semiconductor substrate being divided into a plurality of regions along a first direction and a second direction in which the two substrate side surfaces constituting one of the corner portions extend when viewed in the thickness direction, the plurality of regions including four regions each including a corner portion, and the measurement pattern being disposed in at least two of the four regions. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to one embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing wiring of the semiconductor device of FIG. [Diagram 3]FIG. 3 is an enlarged plan view showing a part of the semiconductor device of FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of a portion of the semiconductor device of FIG. [Diagram 5] 5A to 5C are schematic cross-sectional views showing a process for forming some of the components of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a schematic plan view of a semiconductor device according to a modified example. [Figure 7] FIG. 7 is a schematic plan view of a semiconductor device according to a modified example.

[0007] [Detailed Description] Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure. Terms such as "first", "second", and "third" in the present disclosure are used merely to distinguish objects and do not rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The term "at least one" as used herein means "one or more" of the desired options. As an example, the term "at least one" as used herein means "only one option" or "both of two options" if the number of options is two. As another example, the term "at least one" as used herein means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] (Overview of Semiconductor Device) FIG. 1 is a schematic plan view showing an example of a semiconductor device 10. FIG. 2 is a schematic plan view showing wiring of the semiconductor device 10 of FIG. 1. FIG. 3 is an enlarged plan view showing a part of the semiconductor device 10 of FIG. 2. FIG. 4 is a schematic cross-sectional view of a part of the semiconductor device 10 of FIG. 3. The term "plan view" used in this disclosure refers to viewing the semiconductor device 10 in the Z direction of the mutually orthogonal XYZ axes shown in FIG. 1. Here, the X direction is an example of a "first direction" and the Y direction is an example of a "second direction".

[0011] (Schematic configuration of semiconductor device) As shown in FIG. 1, the semiconductor device 10 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. The semiconductor device 10 includes a device front surface 11 and a device back surface 12 facing opposite sides to each other in the Z direction, and four device side surfaces 13 to 16 connecting the device front surface 11 and the device back surface 12 in the Z direction. The device side surfaces 13 and 14 extend along the X direction and constitute both end surfaces of the semiconductor device 10 in the Y direction. The device side surfaces 15 and 16 extend along the Y direction and constitute both end surfaces of the semiconductor device 10 in the X direction. In one example, the semiconductor device 10 may be formed in a square shape in a plan view. In one example, the device front surface 11 is a mounting surface, and the semiconductor device 10 is a surface-mounted package arranged facing a circuit board on which the device front surface 11 is mounted. The semiconductor device 10 may include a plurality of pads 17 on the device back surface 12.

[0012] The semiconductor device 10 may include a passivation film 20 covering the device back surface 12. The passivation film 20 has insulating properties. The passivation film 20 has openings 21 that partially expose electrodes formed on the device front surface 11 of the semiconductor device 10 as pads 17.

[0013] The semiconductor device 10 includes a semiconductor substrate 30, an insulating layer 60, and layer wiring 70. In Fig. 2, the layer wiring 70 is shown by a solid line through the insulating layer 60. The semiconductor substrate 30 is formed in a rectangular shape in a plan view. The semiconductor substrate 30 may be formed of a material including Si (silicon) or SiC (silicon carbide). In one example, the semiconductor substrate 30 may be formed in a square shape in a plan view. The semiconductor substrate 30 includes a substrate front surface 31 and a substrate back surface 32 facing opposite sides to each other in the Z direction, and four substrate side surfaces 33 to 36 connecting the substrate front surface 31 and the substrate back surface 32 in the Z direction. In one example, the substrate back surface 32 constitutes the device back surface 12. In one example, the substrate side surfaces 33 to 36 are included in the device side surfaces 13 to 16.

[0014] The first substrate side surface 33 and the second substrate side surface 34 extend along the X direction and are spaced apart in the Y direction. The first substrate side surface 33 and the second substrate side surface 34 face opposite each other in the Y direction. The first substrate side surface 33 and the second substrate side surface 34 constitute both end surfaces of the semiconductor substrate 30 in the Y direction. The third substrate side surface 35 and the fourth substrate side surface 36 extend along the Y direction and are spaced apart in the X direction. The third substrate side surface 35 and the fourth substrate side surface 36 face opposite each other in the X direction. The third substrate side surface 35 and the fourth substrate side surface 36 constitute both end surfaces of the semiconductor substrate 30 in the X direction.

[0015] The semiconductor substrate 30 includes four corners 41-44 formed by the first to fourth substrate side surfaces 33-36. The first corner 41 is a corner formed by the first substrate side surface 33 and the third substrate side surface 35. The second corner 42 is a corner formed by the first substrate side surface 33 and the fourth substrate side surface 36. The third corner 43 is a corner formed by the second substrate side surface 34 and the third substrate side surface 35. The fourth corner 44 is a corner formed by the second substrate side surface 34 and the fourth substrate side surface 36. It can be said that the semiconductor substrate 30 includes the four corners 41-44 and the four substrate side surfaces 33-36 that form the four corners 41-44.

[0016] As shown in FIG. 2, the semiconductor substrate 30 includes an element region 50. The element region 50 includes an element region 51 disposed in the center of the semiconductor substrate 30, and element regions 51 and 52 around the element region 51. In FIG. 2, the element regions 51 and 52 are indicated by dashed lines. The element regions 51 and 52 are regions in which various devices for functioning the semiconductor device 10 are formed. In one example, the element region 52 is a region in which devices for input / output functions for the semiconductor device 10 are formed, and is electrically connected to the pad 17 shown in FIG. 1. The element regions 51 and 52 shown in FIG. 2 are merely examples, and the shapes, arrangements, and the like may be changed as appropriate.

[0017] 4, an insulating layer 60 is formed on the substrate surface 31. The insulating layer 60 may be composed of a plurality of insulating films 61-63. The plurality of insulating films 61-63 may be referred to as interlayer insulating films. The insulating layer 60 may be formed of a material including SiO2 (silicon oxide), SiN (silicon nitride), and the like.

[0018] The layer wiring 70 is formed on the semiconductor substrate 30. The semiconductor device 10 may include a plurality of layer wirings 70 in the thickness direction. It can be said that the semiconductor device 10 has a multi-layer wiring structure including at least two layer wirings 70. In one example, as shown in FIG. 4, the semiconductor device 10 may include a first layer wiring 71, a second layer wiring 72, a third layer wiring 73, and a fourth layer wiring 74.

[0019] The layer wiring 70 includes a circuit pattern 80 and a measurement pattern 90. The circuit pattern 80 is a wiring electrically connected to the element regions 51 and 52 of the semiconductor device 10. The circuit pattern 80 may be formed of a material including Cu (copper), Al (aluminum), W (tungsten), Ti (titanium), polysilicon, etc.

[0020] The measurement pattern 90 is formed apart from the circuit pattern 80 in plan view. The measurement pattern 90 includes a pattern formed in the same manner as a part of the circuit pattern 80. The measurement pattern 90 is arranged in at least two corners of the first to fourth corners 41 to 44 in plan view. In detail, the semiconductor substrate 30 is divided into a plurality of regions RA along the X direction and the Y direction in which the first substrate side surface 33 and the third substrate side surface 35 constituting the first corner portion 41 extend in plan view. In one example, the semiconductor substrate 30 is divided into 16 regions RA by three auxiliary lines HX perpendicular to the first substrate side surface 33 extending along the X direction and three auxiliary lines HY perpendicular to the third substrate side surface 35 extending along the Y direction. The corner portion serving as the basis for the division may be any of the second corner portion 42, the third corner portion 43, and the fourth corner portion 44. The number of auxiliary lines HX and HY dividing the semiconductor substrate 30 may be changed to any number equal to or greater than one.

[0021] The multiple regions RA include first to fourth regions RA1 to RA4 including the first to fourth corners 41 to 44. The measurement pattern 90 is arranged in at least two of the first to fourth regions RA1 to RA4 including the first to fourth corners 41 to 44. For example, the measurement pattern 90 may be arranged in a first region RA1 including the first corner 41 and a second region RA2 including the second corner 42. The first region RA1 and the second region RA2 are two regions including both ends of the first substrate side surface 33 in the X direction in which the first substrate side surface 33 extends. It can be said that the measurement pattern 90 is arranged in two regions RA1 and RA2 including both ends of one first substrate side surface 33. The substrate side surface defining the two regions in which the measurement pattern 90 is arranged may be any of the second substrate side surface 34, the third substrate side surface 35, and the fourth substrate side surface 36.

[0022] The measurement patterns 90 may also be arranged in a first region RA1 and a fourth region RA4 located diagonally across the semiconductor substrate 30. The measurement patterns 90 may also be arranged in a second region RA2 and a third region RA3 located diagonally across the semiconductor substrate 30. The measurement patterns 90 may also be arranged in three regions, such as the first region RA1, the second region RA2, and the third region RA3. In the semiconductor device 10 shown as an example, the measurement patterns 90 are arranged in each of the regions RA1 to RA4.

[0023] As shown in FIG. 2, the circuit pattern 80 may include a frame-shaped circuit pattern 81. The frame-shaped circuit pattern 81 is formed in a frame shape along the first to fourth substrate side surfaces 33 to 36. The frame-shaped circuit pattern 81 may include, for example, wiring to which a high potential voltage and a low potential voltage are supplied as operating power sources for the semiconductor device 10. In one example, the frame-shaped circuit pattern 81 may include a high potential power supply wiring and a ground wiring. The high potential power supply wiring and the ground wiring may be formed in wiring layers at different positions in the Z direction. In one example, the frame-shaped circuit pattern 81 shown by a solid line in FIG. 2 may be a ground wiring. The measurement pattern 90 is disposed outside the frame-shaped circuit pattern 81.

[0024] The circuit pattern 80 may include a connection pattern formed on the element regions 51 and 52. In FIG. 2, two circuit wirings 82 and 83 are shown. In one example, the circuit wirings 82 and 83 are formed in different wiring layers. A plurality of circuit wirings 82 and 83 may be provided. In FIG. 2, the circuit wiring 82 is shown by a solid line, and the circuit wiring 83 is shown by a dashed line. The circuit wiring 82 may include a first wiring 821 extending in the X direction and a second wiring 822 extending in the Y direction from both ends of the first wiring 821. The circuit wiring 83 may include a third wiring 831 extending in the Y direction and a fourth wiring 832 extending in the X direction from both ends of the third wiring 831.

[0025] The semiconductor substrate 30 may include a frame-shaped peripheral region OR along the first to fourth substrate side surfaces 33 to 36, and an inner region IR surrounded by the peripheral region OR. The peripheral region OR may be, for example, a region outside the frame-shaped circuit pattern 81. The peripheral region OR may also be a region outside the element region 50. The measurement pattern 90 is disposed outside the frame-shaped circuit pattern 81. It can be said that the measurement pattern 90 is formed in the peripheral region OR.

[0026] The frame-shaped circuit pattern 81 includes straight line portions 811 extending along the first to fourth board side surfaces 33 to 36. The frame-shaped circuit pattern 81 may include inclined portions 812 formed at an angle to the board side surfaces 33 to 36 in a plan view at the first to fourth corner portions 41 to 44. The straight line portions 811 have ends connected to the inclined portions 812. Ends 811A of the respective straight line portions 811 may be included in regions RA1 to RA4 including the corner portions 41 to 44.

[0027] In one example, the measurement pattern 90 in the first region RA1 and the measurement pattern 90 in the third region RA3 are arranged along the third substrate side surface 35. The measurement pattern 90 in the second region RA2 and the measurement pattern 90 in the fourth region RA4 are arranged along the fourth substrate side surface 36.

[0028] The measurement pattern 90 of the first region RA1 is disposed outside the inclined portion 812. The measurement pattern 90 of the second region RA2 is disposed next to the end 811A of the straight portion 811 connected to the inclined portion 812. The measurement pattern 90 of the third region RA3 is disposed next to the end 811A of the straight portion 811 connected to the inclined portion 812. The measurement pattern 90 of the fourth region RA4 is disposed outside the inclined portion 812. The measurement pattern 90 of the first region RA1 and the measurement pattern 90 of the fourth region RA4 located at diagonal corners of the semiconductor substrate 30 can be said to be disposed outside the inclined portions 812 of the first region RA1 and the fourth region RA4. The measurement pattern 90 of the second region RA2 and the measurement pattern 90 of the third region RA3 located at diagonal corners of the semiconductor substrate 30 can be said to be disposed next to the end 811A of the straight portion 811 connected to the inclined portion 812 of the second region RA2 and the third region RA3.

[0029] Fig. 3 shows an example of a transistor 110 included in an element region 52 of the semiconductor device 10 and a measurement pattern 90. Fig. 4 shows a partial cross-sectional view of the semiconductor device 10 on which the transistor 110 and the measurement pattern 90 of Fig. 3 are formed. The transistor 110 shown in Figs. 3 and 4 may be a MOSFET, for example. This transistor 110 is an example of a functional device included in the semiconductor device 10. The transistor 110 may be used, for example, as a protection element connected to the pad 17 shown in Fig. 1.

[0030] 3 and 4, the transistor 110 includes a well region 111 formed in a semiconductor substrate 30, and a plurality of gate electrodes 115 arranged on the well region 111. When viewed from the Z direction, a source region 112 and a drain region 113 are formed in the well region 111 with the gate electrode 115 sandwiched therebetween. Also, a back gate region 114 is formed in the well region 111. An insulating layer 60 is formed on the semiconductor substrate 30.

[0031] The insulating layer 60 includes a plurality of insulating films 61 to 63. Layer wirings 72 to 74 are formed on the upper surfaces of the insulating films 61 to 63. In the insulating film 61, a layer wiring 71 is formed. The layer wiring 72 on the first insulating film 61 includes a source wiring 121, a drain wiring 122, and a back gate wiring 123 connected to the transistor 110. The source wiring 121, the drain wiring 122, and the back gate wiring 123 are electrically connected to the source region 112, the drain region 113, and the back gate region 114 by contacts 124.

[0032] The layer wiring 73 on the second insulating film 62 includes a source wiring 131 and a drain wiring 132 connected to the transistor 110. The source wiring 131 and the drain wiring 132 are electrically connected to the source wiring 121 and the drain wiring 122 of the layer wiring 72 on the first insulating film 61 by vias 134.

[0033] The layer wiring 74 on the second insulating film 62 includes a drain wiring 142 connected to the transistor 110. The drain wiring 142 is electrically connected to the drain wiring 132 of the layer wiring 73 on the second insulating layer 60 by a via 144. In one example, the gate electrode 115 and the layer wirings 72, 73 on the first and second insulating films 61, 62 are formed to extend in the Y direction, and the layer wiring 74 on the third insulating film 63 is formed to extend in the X direction. The layer wiring 71 includes the gate electrode 115. The layer wirings 71 to 74 correspond to the "first layer wiring" and the "second layer wiring". The gate electrode 115, the source wirings 121, 131, the drain wirings 122, 132, 142, and the back gate wiring 123 correspond to the "first layer circuit pattern" and the "second layer circuit pattern".

[0034] As shown in FIG. 4, the measurement pattern 90 may include a first measurement pattern 91, a second measurement pattern 92, a third measurement pattern 93, and a fourth measurement pattern 94. The first measurement pattern 91 is disposed at the same position as the gate electrode 115 in the Z direction. The second measurement pattern 92 is disposed on the first insulating film 61. The third measurement pattern 93 is disposed on the second insulating film 62. The fourth measurement pattern 94 is disposed on the third insulating film 63. The second measurement pattern 92 may be included in the layer wiring 72 on the first insulating film 61. The third measurement pattern 93 may be included in the layer wiring 73 on the second insulating film 62. The fourth measurement pattern 94 may be included in the layer wiring 74 on the second insulating film 62. The first to fourth measurement patterns 91 to 94 correspond to the "first layer measurement pattern" and the "second layer measurement pattern". Although the first to fourth measurement patterns 91 to 94 are shown aligned in the Z direction in FIG. 4, they may be arranged at positions shifted in at least one of the X and Y directions.

[0035] 3 is, in one example, a first measurement pattern 91 arranged at the same position in the Z direction as the gate electrode 115. The first measurement pattern 91 corresponds to a "gate measurement pattern" formed at the same position as the gate electrode 115. Also, the measurement pattern 90 shown in FIG. 3 is, in one example, a second measurement pattern 92 shown in FIG. 4. In FIG. 3, the two measurement patterns 91, 92 are arranged apart in the Y direction, but the two measurement patterns 91, 92 may be arranged so that at least a portion of them overlap in a plan view.

[0036] The first measurement pattern 91 may include a first pattern 911 having a rectangular shape elongated in the first direction and a second pattern 912 having a rectangular shape elongated in the Y direction. The pattern width W11 of the first pattern 911 may be equal to the wiring width W1 of the gate electrode 115. The pattern width W12 of the second pattern 912 may be equal to the wiring width W1 of the gate electrode 115. In one example, the pattern width W11 of the first pattern 911 and the pattern width W12 of the second pattern 912 are equal to each other. Here, if the difference between the two pattern widths is within 10% of one of the pattern widths, it can be said that the two pattern widths are equal to each other. Note that the pattern width W11 of the first pattern 911 and the pattern width W12 of the second pattern 912 may be different from each other. The pattern width W11 is an example of a first width, and the pattern width W12 is an example of a second width.

[0037] The second measurement pattern 92 may include a first pattern 921 having a rectangular shape elongated in the first direction and a second pattern 922 having a rectangular shape elongated in the Y direction. A pattern width W21 of the first pattern 921 and a pattern width W22 of the second pattern 922 may be equal to or smaller than the wiring width of the thinnest wiring pattern among the wiring patterns included in the circuit pattern 80. In one example, the pattern width W21 of the first pattern 921 and the pattern width W22 of the second pattern 922 are equal to each other. The pattern width W21 of the first pattern 921 and the pattern width W22 of the second pattern 922 may be different from each other. The pattern width W21 is an example of a first width, and the pattern width W22 is an example of a second width.

[0038] The pattern width W21 of the first pattern 921 of the second measurement pattern 92 may be equal to the pattern width W11 of the first pattern 911 of the first measurement pattern 91. The pattern width W22 of the second pattern 922 of the second measurement pattern 92 may be equal to the pattern width W12 of the second pattern 912 of the first measurement pattern 91. In other words, the shape of the second measurement pattern 92 may be the same as the shape of the first measurement pattern 91. The shape of the second measurement pattern 92 and the shape of the first measurement pattern 91 may be different.

[0039] FIG. 5 is a cross-sectional view relating to one process of forming the transistor 110 and the first test pattern 91 of the test pattern 90 shown in FIG. An insulating film 64 is formed on the semiconductor substrate 30, and a conductive film 201 is formed on the insulating film 64. The conductive film 201 is for forming the gate electrode 115 and the first measurement pattern 91 shown in FIG. 4, and may be formed of a material containing polysilicon, for example. A mask 202 is formed on the conductive film 201. The mask 202 is used to form the layer wiring 71. The mask 202 includes a gate mask portion 203 formed to cover a portion of the conductive film 201 corresponding to the gate electrode 115, and a measurement mask portion 204 formed to cover a portion of the conductive film 201 corresponding to the first measurement pattern 91.

[0040] The width of this mask 202 is measured in the inspection. The width of the mask 202 affects the gate electrode 115 formed by the gate mask portion 203. In one example, the width W4 of the measurement mask portion 204 is formed to be the same as the width W3 of the gate mask portion 203. Therefore, by measuring the measurement mask portion 204 included in the mask 202, the width W3 of the gate mask portion 203 can be inspected. As shown in FIGS. 3 to 5, the gate electrode 115 is formed by the gate mask portion 203, and the first measurement pattern 91 is formed by the measurement mask portion 204. Therefore, it can be said that the gate electrode 115 can be inspected by the first measurement pattern 91.

[0041] The mask 202 shown in Fig. 5 is an example of a mask used to form the layer wiring 71 including the gate electrode 115 and the first measurement pattern 91 shown in Fig. 4. The same applies to masks used to form the other layer wirings 72-74, and it can be said that the source wirings 121, 131, drain wirings 122, 132, 142, etc. can be similarly inspected by the measurement patterns 92-94.

[0042] The circuit pattern 80 included in the semiconductor device 10 may have different wiring widths because the wiring width varies depending on the location within the semiconductor device 10. For this reason, in a semiconductor device in which the measurement pattern 90 is arranged only in one corner, it is not possible to perform highly accurate inspection of the circuit pattern 80.

[0043] In the semiconductor device 10 of this embodiment, the measurement patterns 90 are arranged in at least two of the first to fourth regions RA1 to RA4 including the first to fourth corner portions 41 to 44. Therefore, for the circuit pattern 80 having different wiring widths depending on the location, highly accurate inspection can be performed by using the measurement patterns 90 in different corner portions. By arranging the measurement patterns 90 in three regions, and further in each of the first to fourth regions RA1 to RA4 including the first to fourth corner portions 41 to 44, more accurate inspection can be performed.

[0044] The wiring width of the circuit pattern 80 may vary depending on the direction in which the circuit pattern 80 faces. For example, a difference may occur between the wiring width of the first wiring 821 and the wiring width of the second wiring 822 of the circuit wiring 82 shown in FIG. 2. The measurement pattern 91 includes a rectangular first pattern 911 that is long in the X direction and a rectangular second pattern 912 that is long in the Y direction. Therefore, it is possible to inspect both the circuit pattern 80 that is long in the X direction and has a wiring width in the Y direction, and the circuit pattern 80 that is long in the Y direction and has a wiring width in the X direction.

[0045] (effect) As described above, according to this embodiment, the following effects are achieved. (1) The semiconductor device 10 includes a semiconductor substrate 30 formed in a rectangular shape when viewed from the Z direction, including four corners 41-44 and four substrate side surfaces 33-36 that form the four corners 41-44, a circuit pattern 80 formed on the semiconductor substrate 30, and a measurement pattern 90 formed apart from the circuit pattern 80 when viewed from the Z direction. When viewed from the Z direction, the semiconductor substrate 30 is divided into a plurality of regions RA along the X direction and the Y direction in which the two substrate side surfaces 33, 35 that form one corner 41 extend. The plurality of regions RA include four regions RA1-RA4 that each include the corners 41-44, and the measurement pattern 90 is disposed in at least two of the four regions RA1-RA4. This semiconductor device 10 can perform highly accurate inspection of the circuit pattern 80, whose wiring width varies depending on the location, by using the measurement patterns 90 of the different corners.

[0046] (2) The measurement patterns 90 may be disposed in two areas RA1, RA4 (RA2, RA3) located diagonally across from each other on the semiconductor substrate 30. This semiconductor device 10 can perform highly accurate inspection of the circuit pattern 80, which has different wiring widths depending on the location, by using the measurement patterns 90 at different corners.

[0047] (3) Measurement patterns 90 may be arranged in two areas RA1 and RA3 including both ends of one substrate side surface, for example, third substrate side surface 35. This semiconductor device 10 can perform highly accurate inspection of circuit patterns 80 having different wiring widths depending on the location by using measurement patterns 90 at different corners.

[0048] (4) The measurement patterns 90 may be arranged in three regions respectively. In this semiconductor device 10, for the circuit pattern 80 having different wiring widths depending on the location, the measurement patterns 90 in different corners can be used to perform more accurate inspection.

[0049] (5) The measurement patterns 90 may be arranged in each of the four regions RA1 to RA4. In the semiconductor device 10, the circuit pattern 80 having different wiring widths depending on the location can be inspected more accurately by using the measurement patterns 90 at different corners.

[0050] (6) The circuit pattern 80 may include circuit wiring 82 (first wiring 821) extending in the X direction, and the measurement pattern 91 (90) may include a first pattern 911 having a rectangular shape elongated in the X direction and a second pattern 912 having a rectangular shape elongated in the Y direction. With the first pattern 911 of the measurement pattern 91, the semiconductor device 10 can inspect the wiring width of the first wiring 821 extending in the X direction.

[0051] (7) The circuit wiring 82 may include a first wiring 821 extending in the X direction and a second wiring 822 extending in the Y direction. The pattern width W11 of the first pattern 911 in the Y direction may be equal to the pattern width W12 of the second pattern 912 in the X direction. The wiring width of the circuit pattern 80 may vary depending on the direction in which the circuit pattern 80 faces. For example, there may be a difference between the wiring width of the first wiring 821 and the wiring width of the second wiring 822 of the circuit wiring 82. The measurement pattern 91 includes a rectangular first pattern 911 that is long in the X direction and a rectangular second pattern 912 that is long in the Y direction. Therefore, it is possible to inspect both the circuit pattern 80 that is long in the X direction and has a wiring width in the Y direction, and the circuit pattern 80 that is long in the Y direction and has a wiring width in the X direction.

[0052] (8) The circuit pattern 80 includes a plurality of circuit wirings 82, and at least one of the pattern width W11 and the pattern width W12 may be equal to or smaller than the wiring width of the narrowest circuit wiring among the plurality of circuit wirings 82. The semiconductor device 10 is capable of inspecting the circuit pattern 80.

[0053] (9) The circuit pattern 80 includes a frame-shaped circuit pattern 81 formed in a frame shape along the substrate side surfaces 33-36, and the measurement pattern 90 may be disposed outside the frame-shaped circuit pattern 81 in the regions RA1-RA4. The semiconductor device 10 can inspect the circuit pattern 80 without being affected by the circuit pattern 80 located inside the frame-shaped circuit pattern 81.

[0054] (10) The frame-shaped circuit pattern 81 includes inclined portions 812 formed at an angle with respect to the substrate side surfaces 33-36 when viewed from the Z direction in the corners 41-44, and the measurement patterns 90 arranged in at least two regions may be arranged outside the inclined portions 812. The measurement patterns 90 can be arranged without affecting the frame-shaped circuit pattern 81.

[0055] (11) The first to fourth layer wirings 71 to 74 may include first to fourth measurement patterns 91 to 94 corresponding to the respective layer wirings 71 to 74. This allows highly accurate inspection to be performed on each of the first to fourth layer wirings 71 to 74.

[0056] (Example of change) The above embodiment can be modified, for example, as follows. The above embodiment and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, the same reference numerals as in the above embodiment are used for the parts common to the above embodiment, and the description thereof will be omitted.

[0057] The shape of the semiconductor device 10, the arrangement of the measurement pattern 90, etc. may be changed as appropriate. FIG. 6 is a schematic plan view of a semiconductor device 10A according to a modified example. The semiconductor device 10A of the modified example is formed in a rectangular shape in a plan view in which the length in the Y direction is shorter than the length in the X direction. The semiconductor device 10A of the modified example includes a semiconductor substrate 30A formed in a rectangular shape in a plan view. The semiconductor substrate 30A includes a first substrate side surface 33 and a second substrate side surface 34 extending in the X direction, and a third substrate side surface 35 and a fourth substrate side surface 36 extending in the Y direction. The lengths of the first substrate side surface 33 and the second substrate side surface 34 are greater than the lengths of the third substrate side surface 35 and the fourth substrate side surface 36.

[0058] The semiconductor substrate 30A of this modified example is divided into 16 regions RA by three auxiliary lines HX perpendicular to the first substrate side surface 33 extending along the X direction with respect to the first corner portion 41, and three auxiliary lines HY perpendicular to the third substrate side surface 35 extending along the Y direction. The corner portion serving as the basis for the division may be any of the second corner portion 42, the third corner portion 43, and the fourth corner portion 44. The number of auxiliary lines HX and HY dividing the semiconductor substrate 30A may be changed to any number equal to or greater than one.

[0059] The measurement patterns 90 are arranged in at least two of the first to fourth regions RA1 to RA4 including the first to fourth corners 41 to 44. The measurement patterns 90 in the first region RA1 and the third region RA3 are arranged closer to the third substrate side surface 35. The measurement patterns 90 in the second region RA2 and the fourth region RA4 are arranged closer to the fourth substrate side surface 36. The semiconductor substrate 30A of the semiconductor device 10A of this modified example includes the first substrate side surface 33 and the second substrate side surface 34 which are long sides, and the third substrate side surface 35 and the fourth substrate side surface 36 which are short sides. The measurement patterns 90 are arranged closer to the third substrate side surface 35 and the fourth substrate side surface 36 which are short sides. It can be said that the measurement patterns 90 are arranged along the third substrate side surface 35 and the fourth substrate side surface 36 which extend in the Y direction.

[0060] 7 is a schematic plan view of a modified semiconductor device 10B. In a semiconductor substrate 30B of the modified semiconductor device 10B, the lengths of a third substrate side surface 35 and a fourth substrate side surface 36 extending in the Y direction are greater than the lengths of a first substrate side surface 33 and a second substrate side surface 34 extending in the X direction. A measurement pattern 90 is disposed closer to the first substrate side surface 33 and the second substrate side surface 34, which are the longer sides. It can be said that the measurement pattern 90 is disposed along the first substrate side surface 33 and the second substrate side surface 34 extending in the X direction.

[0061] 2, the measurement pattern 90 may be provided along each of the substrate side surfaces 33 to 36. For example, in the first region RA1 including the first corner 41, the measurement pattern 90 may be provided along each of the third substrate side surface 35 and the first substrate side surface 33. Similarly, in the second region RA2 including the second corner 42, the measurement pattern 90 may be provided along each of the fourth substrate side surface 36 and the first substrate side surface 33. In the third region RA3 including the third corner 43, the measurement pattern 90 may be provided along each of the third substrate side surface 35 and the second substrate side surface 34. In the fourth region RA4 including the fourth corner 44, the measurement pattern 90 may be provided along each of the fourth substrate side surface 36 and the second substrate side surface 34.

[0062] The term "on" as used in this disclosure includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which another layer is formed between the first layer and the second layer.

[0063] The Z-axis direction used in the present disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to the present disclosure (for example, the structure shown in FIG. 1) are not limited to the "up" and "down" of the Z-axis direction described in this specification being "up" and "down" of the vertical direction. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.

[0064] (Additional Note) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples for the purpose of aiding understanding, and the components described in each appendix should not be limited to the components indicated by the reference symbols.

[0065] (Appendix 1) a semiconductor substrate (30) formed in a rectangular shape when viewed in a thickness direction, the semiconductor substrate (30) including four corner portions (41-44) and four substrate side surfaces (33-36) that form the four corner portions (41-44); A circuit pattern (80) formed on the semiconductor substrate (30); a measurement pattern (90) formed at a distance from the circuit pattern (80) when viewed from the thickness direction; Including, The semiconductor substrate (30) is divided into a plurality of regions (RA) along a first direction and a second direction in which the two substrate side surfaces (33-36) constituting one of the corner portions (41-44) extend, when viewed from the thickness direction, and The plurality of regions (RA) include four regions (RA1 to RA4) each including the corner portion (41 to 44), The measurement pattern (90) is disposed in at least two of the four regions (RA1 to RA4). Semiconductor device.

[0066] (Appendix 2) The measurement patterns (90) are disposed in two of the regions (RA1 to RA4) located diagonally opposite each other on the semiconductor substrate (30). 2. The semiconductor device according to claim 1.

[0067] (Appendix 3) The measurement patterns (90) are arranged in two of the regions (RA1 to RA4) including both ends of one of the substrate side surfaces (33 to 36), respectively. 2. The semiconductor device according to claim 1.

[0068] (Appendix 4) 2. The semiconductor device according to claim 1, wherein the measurement patterns (90) are arranged in each of the three regions (RA1 to RA4).

[0069] (Appendix 5) 2. The semiconductor device according to claim 1, wherein the measurement patterns (90) are arranged in each of the four regions (RA1 to RA4).

[0070] (Appendix 6) The circuit pattern (80) includes circuit wiring extending in at least one of the first direction and the second direction, The plurality of measurement patterns (91, 92) include a first pattern (911, 921) having a rectangular shape that is long in the first direction, and a second pattern (912, 922) having a rectangular shape that is long in the second direction, 6. The semiconductor device according to claim 1,

[0071] (Appendix 7) 7. The semiconductor device according to claim 6, wherein a first width (W11, W21) of the first pattern (911, 921) in the second direction is equal to a second width (W12, W22) of the second pattern (912, 922) in the first direction.

[0072] (Appendix 8) The circuit pattern (80) includes a plurality of circuit wirings (81, 82), At least one of the first width (W11, W21) and the second width (W12, W22) is equal to or smaller than the wiring width of the narrowest wiring pattern among the plurality of wiring patterns. 8. The semiconductor device according to claim 7.

[0073] (Appendix 9) The circuit pattern (80) includes a frame-shaped circuit pattern (81) formed in a frame shape along the substrate side surface (33 to 36), the measurement pattern (90) is disposed outside the frame-shaped circuit pattern (81) in the regions (RA1 to RA4); 9. The semiconductor device according to claim 1,

[0074] (Appendix 10) the frame-shaped circuit pattern (81) includes, at the corners (41-44), inclined portions (812) formed obliquely with respect to the substrate side surfaces (33-36) when viewed in the thickness direction, The measurement patterns (90) arranged in at least two of the regions (RA1 to RA4) are arranged outside the inclined portion (812). 10. The semiconductor device according to claim 9.

[0075] (Appendix 11) The frame-shaped circuit pattern (81) includes a straight portion (811) having an end portion (811A) connected to the inclined portion (812), The measurement pattern (90) in the area (RA1 to RA4) including the end portion is disposed next to the end portion (811A). 11. The semiconductor device according to claim 10.

[0076] (Appendix 12) 12. The semiconductor device according to any one of claims 1 to 11, wherein the measurement patterns (90) arranged in at least two of the regions (RA1 to RA4) have the same shape when viewed from the thickness direction.

[0077] (Appendix 13) 13. The semiconductor device according to claim 1, wherein the semiconductor substrate (30) has a square shape when viewed in the thickness direction.

[0078] (Appendix 14) The length of the substrate side surface (33 to 36) in the first direction is greater than the length of the substrate side surface (33 to 36) in the second direction, The measurement pattern (90) is disposed along the substrate side surface (33 to 36) extending in the first direction. 13. The semiconductor device according to claim 1,

[0079] (Appendix 15) The length of the substrate side surface (33 to 36) in the first direction is greater than the length of the substrate side surface (33 to 36) in the second direction, The measurement pattern (90) is disposed along the substrate side surface (33 to 36) extending in the second direction. 13. The semiconductor device according to claim 1,

[0080] (Appendix 16) The semiconductor device has a multilayer wiring structure including a first layer wiring and a second layer wiring, The circuit pattern (80) is a first layer circuit pattern included in the first layer wiring; a second layer circuit pattern included in the second layer wiring; Including, Each of the measurement patterns (90) is a first layer measurement pattern included in the first layer wiring; a second layer measurement pattern included in the second layer wiring; Including, 16. The semiconductor device according to claim 1,

[0081] (Appendix 17) The circuit pattern (80) includes a gate electrode (115) of a MOSFET (110); The measurement pattern (90) includes a gate measurement pattern (91) having the same wiring width as the gate electrode (115). 17. The semiconductor device according to claim 1,

[0082] (Appendix 18) 18. The semiconductor device according to claim 17, wherein the gate measurement pattern (91) is formed at the same position as the gate electrode (115) in the thickness direction.

[0083] (Appendix 19) 19. The semiconductor device according to claim 1, wherein a plurality of the measurement patterns (90) are arranged along two of the substrate side surfaces (33-36) extending in the first direction.

[0084] (Appendix 20) the semiconductor substrate (30) includes a frame-shaped outer peripheral region (OR) along the substrate side surfaces (33-36) and an inner region (IR) surrounded by the outer peripheral region (OR), The measurement pattern (90) is formed in the outer circumferential region (OR). 19. The semiconductor device according to claim 1.

[0085] (Appendix 21) a semiconductor substrate (30) formed in a rectangular shape when viewed in a thickness direction and including first to fourth corner portions (41 to 44); A circuit pattern (80) formed on the semiconductor substrate (30); a measurement pattern (90) formed at a distance from the circuit pattern (80) when viewed from the thickness direction; Including, the semiconductor substrate (30) includes a first substrate side surface (33-36) and a second substrate side surface (33-36) extending in a first direction, and a third substrate side surface (33-36) and a fourth substrate side surface (33-36) extending in a second direction perpendicular to the first direction when viewed in the thickness direction, the semiconductor substrate (30) includes a frame-shaped outer periphery region (OR) along the first to fourth substrate side surfaces (33 to 36) and an inner region (IR) surrounded by the outer periphery region (OR), The measurement pattern (90) is formed in the outer circumferential region (OR). Semiconductor device.

[0086] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0087] 10, 10A, 10B Semiconductor device 11 Device surface 12 Back of the device 13~16 Side of device 17 Pad 20 Passivation film 21 Opening 30, 30A, 30B Semiconductor substrate 31 Board surface 32 Back side of board 33~36 1st~4th board side 41~44 1st~4th corners 50, 51, 52 Element area 60 Insulating layer 61 to 63 First to third insulating films 64 Insulating Film 70 layer wiring 71~74 1st~4th layer wiring 80 Circuit Pattern 81 Frame-shaped circuit pattern 811 Straight section 811A End 812 Slope 82 Circuit wiring 821 1st wiring 822 2nd wiring 83 Circuit wiring 831 3rd wiring 832 4th wiring 90 Measurement Patterns 91~94 1st to 4th measurement patterns 911 1st pattern 912 2nd pattern 921 First Pattern 922 2nd Pattern 110 Transistor 115 Gate electrode 201 Conductive film 202 Mask 203 Gate mask section 204 Measurement mask section HX,HY auxiliary line IR Inner Region OR outer area RA area RA1~RA4 1st~4th area W1 Wiring width W11, W12 Pattern width W21, W22 Pattern width W3, W4 width

Claims

1. A semiconductor substrate formed in a rectangular shape when viewed in a thickness direction, the semiconductor substrate including four corner portions and four substrate side surfaces forming the four corner portions; A circuit pattern formed on the semiconductor substrate; A measurement pattern formed at a distance from the circuit pattern when viewed from the thickness direction; Including, The semiconductor substrate is divided into a plurality of regions along a first direction and a second direction in which the two substrate side surfaces constituting one of the corner portions extend, when viewed from the thickness direction; the plurality of regions include four regions each including the corner portion, The measurement pattern is disposed in at least two of the four regions. Semiconductor device.

2. the measurement patterns are disposed in two diagonally opposite corners of the semiconductor substrate, The semiconductor device according to claim 1 .

3. The measurement patterns are disposed in two of the regions including both ends of one of the substrate side surfaces, The semiconductor device according to claim 1 .

4. The semiconductor device according to claim 1 , wherein the measurement patterns are arranged in three of the regions.

5. The semiconductor device according to claim 1 , wherein the measurement patterns are arranged in four of the regions.

6. the circuit pattern includes circuit wiring extending in at least one of the first direction and the second direction, The plurality of measurement patterns include a first pattern having a rectangular shape that is long in the first direction and a second pattern having a rectangular shape that is long in the second direction. The semiconductor device according to claim 1 .

7. The semiconductor device according to claim 6 , wherein a first width of said first pattern in said second direction is equal to a second width of said second pattern in said first direction.

8. the circuit pattern includes a plurality of wiring patterns, At least one of the first width and the second width is equal to or smaller than a wiring width of a narrowest wiring pattern among the plurality of wiring patterns. The semiconductor device according to claim 7.

9. the circuit pattern includes a frame-shaped circuit pattern formed in a frame shape along a side surface of the substrate, the measurement pattern is disposed outside the frame-shaped circuit pattern in the region; The semiconductor device according to claim 1 .

10. the frame-shaped circuit pattern includes an inclined portion formed at the corner portion obliquely with respect to a side surface of the substrate when viewed from the thickness direction, the measurement patterns arranged in at least two of the regions are arranged outside the inclined portion; The semiconductor device according to claim 9.

11. the frame-shaped circuit pattern includes a straight portion having an end portion connected to the inclined portion, the measurement pattern in the region including the edge is disposed adjacent to the edge; The semiconductor device according to claim 10.

12. The semiconductor device according to claim 1 , wherein the measurement patterns arranged in at least two of the regions have the same shape when viewed from the thickness direction.

13. The semiconductor device according to claim 1 , wherein the semiconductor substrate has a square shape when viewed in the thickness direction.

14. a length of the side surface of the substrate in the first direction is greater than a length of the side surface of the substrate in the second direction; The measurement pattern is disposed along a side surface of the substrate extending in the first direction. The semiconductor device according to claim 1 .

15. a length of the side surface of the substrate in the first direction is greater than a length of the side surface of the substrate in the second direction; The measurement pattern is disposed along a side surface of the substrate extending in the second direction. The semiconductor device according to claim 1 .

16. The semiconductor device has a multilayer wiring structure including a first layer wiring and a second layer wiring, The circuit pattern is a first layer circuit pattern included in the first layer wiring; a second layer circuit pattern included in the second layer wiring; Including, Each of the measurement patterns is a first layer measurement pattern included in the first layer wiring; a second layer measurement pattern included in the second layer wiring; Including, The semiconductor device according to claim 1 .

17. the circuit pattern includes a gate electrode of a MOSFET; The measurement pattern includes a gate measurement pattern having the same wiring width as the gate electrode. The semiconductor device according to claim 1 .

18. 18. The semiconductor device according to claim 17, wherein the gate measurement pattern is formed at the same position as the gate electrode in the thickness direction.

19. The semiconductor device according to claim 1 , wherein a plurality of the measurement patterns are arranged along two of the substrate side surfaces extending in the first direction.

20. the semiconductor substrate includes a frame-shaped outer peripheral region along a side surface of the substrate, and an inner region surrounded by the outer peripheral region, The measurement pattern is formed in the outer circumferential region. The semiconductor device according to claim 1 .

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