Semiconductor device

Abstract

To provide a semiconductor device which is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena.SOLUTION: A semiconductor device includes: a first capacitive element; a signal cancellation circuit that generates a first voltage corresponding to a first input voltage in a sampling mode and applies it to one end of the first capacitive element, and holds the generated first voltage in a hold mode while applying it to one end of the first capacitive element; a sampling circuit that samples the first input voltage in the sampling mode and holds a second voltage corresponding to the sampled first input voltage in the hold mode while applying it to the other end of the first capacitive element; a negative feedback circuit that generates an output signal corresponding to the voltage at the other end of the first capacitive element in the hold mode and applies a feedback signal to one end of the first capacitive element; an AD converter that performs AD conversion on the input voltage; and an addition / subtraction circuit that performs addition / subtraction of the output signal of the negative feedback circuit and the output signal of the AD converter.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device capable of operating with high precision by suppressing errors caused by dielectric relaxation phenomena. [Background technology]

[0002] Patent Document 1 discloses a charge redistribution type successive approximation AD conversion circuit that suppresses errors in AD conversion caused by dielectric relaxation phenomena. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-107985 A Summary of the Invention [Problem to be solved by the invention]

[0004] Not only the charge redistribution type successive approximation AD conversion circuit disclosed in Patent Document 1, but also AD conversion circuits in which the sampling capacitive element and the DA conversion capacitive element are separated, and top plate sampling AD conversion circuits are required to suppress errors caused by the dielectric relaxation phenomenon and operate with high precision.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present disclosure includes a first capacitive element, a signal cancellation circuit that, in a sampling mode, generates a first voltage corresponding to a first input voltage and applies it to one end of the first capacitive element, and in a hold mode after the sampling mode, holds the generated first voltage and applies it to one end of the first capacitive element, a sampling circuit that samples the first input voltage in the sampling mode, and in a hold mode, holds a second voltage corresponding to the sampled first input voltage and applies it to the other end of the first capacitive element, a negative feedback circuit that, in the hold mode, generates an output signal corresponding to the voltage at the other end of the first capacitive element, and applies a feedback signal corresponding to the output signal to one end of the first capacitive element, a first AD converter that performs AD conversion on the first input voltage, and an adding / subtracting circuit that performs addition / subtraction between an output signal of the negative feedback circuit and an output signal of the first AD converter, and outputs the result. Effect of the Invention

[0007] The present disclosure can provide a semiconductor device capable of operating with high precision by suppressing errors caused by the dielectric relaxation phenomenon. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a timing chart showing the operation of the semiconductor device shown in FIG. [Diagram 3] FIG. 3 is a circuit diagram showing a first modified example of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram showing a specific example of the semiconductor device shown in FIG. [Diagram 5] FIG. 5 is a circuit diagram showing a second modification of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a circuit diagram showing a third modified example of the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 10] FIG. 10 is a circuit diagram showing a first modified example of the semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a circuit diagram showing a specific example of the semiconductor device shown in FIG. [Figure 12] FIG. 12 is a circuit diagram showing a second modified example of the semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a circuit diagram showing a configuration example of a semiconductor device according to the third embodiment. [Figure 15] FIG. 15 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 16] FIG. 16 is a circuit diagram showing a first modified example of the semiconductor device according to the third embodiment. [Figure 17] FIG. 17 is a circuit diagram showing a first configuration example of a semiconductor device that has been previously examined. [Figure 18] FIG. 18 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 19] FIG. 19 is a diagram showing an equivalent circuit of a capacitance element Cs having a dielectric relaxation phenomenon. [Figure 20] FIG. 20 is a circuit diagram showing a second configuration example of a semiconductor device that has been previously examined. [Figure 21] FIG. 21 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 22] FIG. 22 is a circuit diagram showing a third configuration example of a semiconductor device that has been previously examined. [Figure 23]FIG. 23 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 24] FIG. 24 is a circuit diagram showing a fourth configuration example of a semiconductor device that has been previously examined. [Diagram 25] FIG. 25 is a timing chart showing the operation of the semiconductor device shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be interpreted narrowly based on the description in the drawings. Also, the same elements are given the same reference numerals, and duplicated explanations will be omitted.

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0011] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, values, amounts, ranges, etc.).

[0012] <Preliminary review by inventors, etc.> Before describing the semiconductor device according to the present embodiment, a semiconductor device previously examined by the present inventors will be described.

[0013] 17 is a circuit diagram showing a configuration example of a previously examined semiconductor device 6. The semiconductor device 6 is a so-called single-input charge redistribution type successive approximation AD converter, which converts an analog input voltage Vin into a digital output signal ADOUT using a binary search algorithm and outputs the converted signal.

[0014] Specifically, the semiconductor device 6 includes a negative feedback circuit 62, a capacitance element Cs, and switches SW61 to SW63. The negative feedback circuit 62 includes a comparator 621, a successive approximation register circuit (SAR Logic) 622, and a DA converter 623.

[0015] The capacitance element Cs is provided between the non-inverting input terminal of the comparator 621 and the node Ns. The switch SW61 is provided between an input terminal (hereinafter referred to as the input terminal Vin) to which an input voltage Vin is supplied from the outside of the semiconductor device 6 and the node Ns (one end of the capacitance element Cs). The switch SW63 is provided between the non-inverting input terminal (the other end of the capacitance element Cs) of the comparator 621 and a reference voltage terminal (hereinafter referred to as the reference voltage terminal Vss) to which a reference voltage Vss is supplied. The reference voltage Vss is supplied to the inverting input terminal of the comparator 621.

[0016] The successive approximation register circuit 622 outputs a digital signal (a control signal for controlling a switch of the DA converter 623) according to the comparison result of the comparator 621, and outputs an output signal ADOUT of a determined digital value. The DA converter 623 converts the digital signal output from the successive approximation register circuit 622 into an analog voltage and outputs it. The switch SW62 is provided between the output of the DA converter 623 and a node Ns.

[0017] 18 is a timing chart showing the operation of the semiconductor device 6. Note that each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 6 include at least a sampling mode and a hold mode.

[0018] As shown in FIG. 18, first, in the sampling mode, the switch SW61 indicates an on state, the switch SW62 indicates an off state, and the switch SW63 indicates an on state. As a result, the input voltage Vin is sampled. That is, a charge according to the input voltage Vin is accumulated in the node Ns (one end of the capacitance element Cs). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin. After that, in the hold mode, the switch SW61 switches from on to off, the switch SW62 switches from off to on, and the switch SW63 switches from on to off. As a result, the sampled input voltage Vin is held in the capacitance element Cs.

[0019] At this time, the negative feedback circuit 62 generates an analog voltage such that the voltage Vm of the non-inverting input terminal of the comparator 621 indicates the reference voltage Vss, that is, an analog voltage such that the voltage Vdac of the node Ndac indicates the input voltage Vin, and outputs it to the node Ndac.

[0020] Specifically, the negative feedback circuit 62 performs a successive approximation operation between the output voltage of the DA converter 623 and the input voltage Vin, using the comparator 621 and the successive approximation register circuit 622. Then, the semiconductor device 6 outputs the output signal ADOUT having the digital value determined in the negative feedback circuit 62.

[0021] However, the semiconductor device 6 has a problem in that it cannot operate with high precision due to an error in AD conversion caused by the dielectric relaxation phenomenon.

[0022] Fig. 19 is a diagram showing an equivalent circuit of a capacitance element Cs having a dielectric relaxation phenomenon. As shown in Fig. 19, in addition to an intrinsic capacitance Cstd, a plurality of series circuits each consisting of a parasitic resistance and a parasitic capacitance are connected in parallel to the capacitance element Cs. The time constants of each of these plurality of series circuits are different from each other, and it is known that they are a distributed constant model having a wide frequency band.

[0023] 18, for example, the operation mode of the semiconductor device 6 may be switched from the sampling mode to the hold mode in a state (dotted line) in which the input voltage Vin has not yet reached an ideal level (solid line). This causes the voltage Vm of the non-inverting input terminal (the other end of the capacitive element Cs) of the comparator 621 to fluctuate in the hold mode, and as a result, the semiconductor device 6 may not be able to perform AD conversion processing with high accuracy.

[0024] Therefore, the inventors next examined the semiconductor device 7. 20 is a circuit diagram showing a configuration example of a previously examined semiconductor device 7. Compared with the semiconductor device 6, the semiconductor device 7 further includes a sub AD converter 712, a sub DA converter 713, a capacitance element Cdac, and switches SW71 to SW73.

[0025] The capacitance element Cdac has the same capacitance value as the capacitance element Cs and is provided between the inverting input terminal of the comparator 621 and a node Ndac. The switch SW71 is provided between the input terminal Vin and the node Ndac (one end of the capacitance element Cdac). The switch SW73 is provided between the inverting input terminal of the comparator 621 (the other end of the capacitance element Cdac) and a reference voltage terminal. The sub AD converter 712 and the sub DA converter 713 are provided in parallel with the switch SW71 between the input terminal Vin and the node Ndac. The AD converter 712 converts the analog input voltage Vin into a digital signal and outputs it. The DA converter 713 converts the digital signal output from the AD converter 712 into an analog voltage and outputs it. The switch SW72 is provided between the output of the DA converter 713 and the node Ndac.

[0026] 21 is a timing chart showing the operation of the semiconductor device 7. Each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 7 include at least a sampling mode and a hold mode.

[0027] As shown in FIG. 21, first, in the sampling mode, the switches SW61 and SW71 indicate an ON state, the switches SW62 and SW72 indicate an OFF state, and the switches SW63 and SW73 indicate an ON state. As a result, the input voltage Vin is sampled. That is, a charge according to the input voltage Vin is accumulated in the node Ns (one end of the capacitance element Cs). Also, a charge according to the input voltage Vin is accumulated in the node Ndac (one end of the capacitance element Cdac). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin. Also, the voltage Vdac of the node Ndac ideally indicates the input voltage Vin. After that, in the hold mode, the switches SW61 and SW71 are switched from ON to OFF, the switches SW62 and SW72 are switched from OFF to ON, and the switches SW63 and SW73 are switched from ON to OFF. As a result, the sampled input voltage Vin is held in the capacitance element Cs. Also, the sampled input voltage Vin is held in the capacitance element Cdac. Strictly speaking, it is desirable to have a sequence in which the switch SW71 switches from on to off, the switch SW72 switches from off to on, the switches SW63 and SW73 switch from on to off, and then the switch SW61 switches from on to off, and the switch SW62 switches from off to on. This is because it is possible to eliminate the influence of errors in the AD converter 712 and the DA converter 713. However, this strict timing operation is not necessary when the influence of dielectric relaxation is taken into consideration.

[0028] At this time, the negative feedback circuit 62 generates an analog voltage such that the non-inverting input terminal of the comparator 621 indicates the same voltage value as the inverting input terminal, that is, an analog voltage such that the node Ndac indicates the input voltage Vin, and outputs it to the node Ndac.

[0029] Specifically, the negative feedback circuit 62 performs a successive approximation operation between the output voltage of the DA converter 623 and the input voltage Vin, using the comparator 621 and the successive approximation register circuit 622. Then, the semiconductor device 7 outputs the output signal ADOUT having the digital value determined in the negative feedback circuit 62.

[0030] Here, in the semiconductor device 7, an error in the input voltage Vin occurs due to the dielectric relaxation phenomenon in each of the capacitance elements Cs and Cdac. Therefore, in the semiconductor device 7, the comparator 621 can cancel these error components and make a comparison. In other words, the semiconductor device 7 can operate with high precision by suppressing the error in AD conversion caused by the dielectric relaxation phenomenon.

[0031] In recent years, there has been a demand for accurate operation by suppressing errors caused by the dielectric relaxation phenomenon not only in the semiconductor device 7, which is a charge redistribution type successive approximation type AD conversion circuit, but also in AD conversion circuits in which the sampling capacitance element and the DA conversion capacitance element are separated, and in top plate sampling type AD conversion circuits, etc. A brief description will be given below with reference to Figs. 22 to 25.

[0032] 22 is a circuit diagram showing a configuration example of a previously examined semiconductor device 8. The semiconductor device 8 is an AD converter in which a capacitance element for sampling and a capacitance element for DA conversion are separated.

[0033] Specifically, compared to the semiconductor device 6, the semiconductor device 8 further includes a capacitive element Cdac in addition to the capacitive element Cs, and includes switches SW81, SW81a, SW82, SW82a, and SW83 instead of the switches SW61 to SW63.

[0034] The capacitance element Cs is provided between the non-inverting input terminal of the comparator 621 and a node Ns. The switch SW81 is provided between the input terminal Vin and the node Ns (one end of the capacitance element Cs). The switch SW82 is provided between the node Ns and a reference voltage terminal Vss. The capacitance element Cdac is provided between the non-inverting input terminal of the comparator 621 and a node Ndac. The switch SW81a is provided between the reference voltage terminal Vss and the node Ndac (one end of the capacitance element Cdac). The switch SW82a is provided between the output of the DA converter 623 and the node Ndac. The switch SW83 is provided between the non-inverting input terminal of the comparator 621 and a reference voltage terminal Vss.

[0035] Other configurations of the semiconductor device 8 are similar to those of the semiconductor device 6, and therefore description thereof will be omitted.

[0036] 23 is a timing chart showing the operation of the semiconductor device 8. Note that each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 8 include at least a sampling mode and a hold mode.

[0037] As shown in Fig. 23, first, in the sampling mode, the switches SW81 and SW81a are in an ON state, the switches SW82 and SW82a are in an OFF state, and the switch SW83 is in an ON state. As a result, sampling of the input voltage Vin is performed. That is, a charge according to the input voltage Vin is accumulated in the node Ns (one end of the capacitance element Cs). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin. At this time, the voltage Vdac of the node Ndac indicates the reference voltage Vss.

[0038] After that, in the hold mode, the switches SW81 and SW81a are switched from on to off, the switches SW82 and SW82a are switched from off to on, and the switch SW83 is switched from on to off. As a result, the sampled input voltage Vin is held in the capacitance element Cs. Here, when the switch SW82 is turned on and the voltage Vs of the node Ns transitions from the input voltage Vin to the reference voltage Vss, the negative feedback circuit 62 generates an analog voltage such that the voltage Vm of the non-inverting input terminal of the comparator 621 indicates the reference voltage Vss, i.e., an analog voltage such that the voltage Vdac of the node Ndac indicates the input voltage Vin, and outputs it to the node Ndac.

[0039] Specifically, the negative feedback circuit 62 performs a successive approximation operation between the output voltage of the DA converter 623 and the input voltage Vin, using a comparator 621 and a successive approximation register circuit 622. Then, the semiconductor device 8 outputs an output signal ADOUT having a digital value determined in the negative feedback circuit 62.

[0040] 24 is a circuit diagram showing a configuration example of a previously examined semiconductor device 9. The semiconductor device 9 is a so-called top plate sampling type AD converter.

[0041] Specifically, compared to the semiconductor device 6, the semiconductor device 9 includes switches SW91, SW91a, and SW92 instead of the switches SW61 to SW63.

[0042] The switch SW91 is provided between the non-inverting input terminal (node ​​Ns) of the comparator 621 and the input terminal Vin. The capacitance element Cs is provided between the non-inverting input terminal of the comparator 621 and the node Ndac. The switch SW91a is provided between the node Ndac (one end of the capacitance element Cs) and the input terminal Vin. The switch SW92 is provided between the output of the DA converter 623 and the node Ndac.

[0043] The rest of the configuration of the semiconductor device 9 is similar to that of the semiconductor device 6, and therefore a description thereof will be omitted.

[0044] 25 is a timing chart showing the operation of the semiconductor device 9. Note that each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 9 include at least a sampling mode and a hold mode.

[0045] As shown in FIG. 25, first, in the sampling mode, the switches SW91 and SW91a are in an on state, and the switch SW92 is in an off state. This causes sampling of the input voltage Vin. That is, a charge according to the input voltage Vin is accumulated in the non-inverting input terminal of the comparator 621. This causes the voltage Vs of the non-inverting input terminal of the comparator 621 to ideally indicate the input voltage Vin. At this time, the voltage Vdac of the node Ndac indicates the reference voltage Vss.

[0046] After that, in the hold mode, the switches SW91 and SW91a are switched from on to off, and the switch SW92 is switched from off to on. As a result, the sampled input voltage Vin is held in the capacitance element Cs. At this time, the negative feedback circuit 62 generates an analog voltage such that the non-inverting input terminal of the comparator 621 indicates the reference voltage Vss, that is, an analog voltage such that the node Ndac indicates -Vin, and outputs it to the node Ndac.

[0047] Specifically, the negative feedback circuit 62 performs a successive approximation operation between the output voltage of the DA converter 623 and the input voltage Vin, using a comparator 621 and a successive approximation register circuit 622. Then, the semiconductor device 9 outputs an output signal ADOUT having a digital value determined in the negative feedback circuit 62.

[0048] In recent years, there has been a demand for accurate operation by suppressing errors caused by the dielectric relaxation phenomenon not only in the semiconductor device 7 which is a charge redistribution type successive approximation AD conversion circuit but also in the semiconductor device 8 which is an AD conversion circuit in which the capacitance element for sampling and the capacitance element for DA conversion are separated, and in the semiconductor device 9 which is a top plate sampling AD conversion circuit, etc. Thus, a semiconductor device 1 capable of suppressing errors caused by the dielectric relaxation phenomenon and operating accurately has been found.

[0049] <Embodiment 1> 1 is a circuit diagram showing a configuration example of a semiconductor device 1 according to embodiment 1. The semiconductor device 1 is an AD converter in which a capacitance element for sampling and a capacitance element for DA conversion are separated, and converts an analog input voltage Vin into a digital output signal ADOUT and outputs it.

[0050] Specifically, the semiconductor device 1 includes a signal cancellation circuit 11, a negative feedback circuit 12, an adder circuit 13, capacitance elements Cs and Cdac, and switches SW11 to SW13. The signal cancellation circuit 11 includes an inversion circuit 111, a sub AD converter 112, an inversion circuit 113, a sub DA converter 114, switches SW11a and SW11b, and a switch SW12a. The negative feedback circuit 12 includes a comparator 121, a successive approximation register circuit 122, and a DA converter 123. For example, the switches SW11 to SW13 and the capacitance element Cs configure a sampling circuit.

[0051] The capacitance element Cs is provided between a non-inverting input terminal of the comparator 121 and a node Ns. The switch SW11 is provided between an input terminal Vin and a node Ns (one end of the capacitance element Cs). The switch SW12 is provided between the node Ns and a reference voltage terminal Vss. The switch SW13 is provided between the non-inverting input terminal of the comparator 121 and a reference voltage terminal Vss. The reference voltage Vss is supplied to the inverting input terminal of the comparator 121.

[0052] The capacitive element Cdac has the same capacitance value as the capacitive element Cs, and is provided between the non-inverting input terminal of the comparator 121 and the node Ndac. The signal cancellation circuit 11 is provided between the input terminal Vin and the node Ndac (one end of the capacitive element Cdac).

[0053] In the signal cancellation circuit 11, the inversion circuit 111 inverts and outputs the input voltage Vin. Here, in the inversion of the inversion circuit 111, if the input to the inversion circuit 111 is x, the output of the inversion circuit 111 is y, and the common potential inverted by the inversion circuit 111 is Vcm1, then the relationship y=-(x-Vcm1)+Vcm1 holds. Hereinafter, the inversion of voltage by each inversion circuit means the relationship of the above formula.

[0054] The AD converter 112, the inversion circuit 113, and the DA converter 114 are provided on a path between the input terminal Vin and the node Ndac that is different from the inversion circuit 111. The AD converter 112 converts the sampled input voltage Vin into a digital signal and outputs it. The inversion circuit 113 inverts the output signal of the AD converter 112 and outputs it. The DA converter 114 converts the output signal of the inversion circuit 113 into an analog voltage and outputs it.

[0055] In this embodiment, a case where the gain of each of the inverting circuits 111 and 113 is −1 will be described as an example. However, if the capacitance element Cdac is configured to have a capacitance value such that Cdac=Cs / k holds, where Cdac is the capacitance value of the capacitive element Cdac and Cs is the capacitance value of the capacitive element Cs, the gain of each of the inverting circuits 111 and 113 may be −k.

[0056] The switch SW11a is provided between the output of the inversion circuit 111 and the node Ndac. The switch SW11b is provided between the output of the DA converter 114 and the node Ndac. The switches SW11a and SW11b function as a selection circuit that selects and outputs either the output of the inversion circuit 111 or the output of the DA converter 114.

[0057] The successive approximation register circuit 122 outputs a digital signal (a control signal for controlling a switch of the DA converter 123) according to the comparison result of the comparator 121, and outputs an output signal of a determined digital value. The DA converter 123 converts the digital signal output from the successive approximation register circuit 122 into an analog voltage and outputs it. The switch SW12a is provided between the output of the DA converter 123 and a node Ndac.

[0058] The adder circuit 13 adds the output of the AD converter 112 and the output of the successive approximation register circuit 122, and outputs the addition result as a digital output signal ADOUT.

[0059] 2 is a timing chart showing the operation of the semiconductor device 1. Each switch is turned off by a low-level control signal and turned on by a high-level control signal. The operation modes of the semiconductor device 1 include at least a sampling mode and a hold mode. The sampling mode is composed of a first sampling mode and a second sampling mode.

[0060] First, in the first sampling mode, the switch SW11 indicates an on state, the switch SW11a indicates an on state, the switch SW11b indicates an off state, the switches SW12 and SW12a indicate an off state, and the switch SW13 indicates an on state. As a result, sampling of the input voltage Vin is performed. That is, a charge according to the input voltage Vin is accumulated in the node Ns (one end of the capacitance element Cs). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin. Also, a charge according to the voltage obtained by inverting the input voltage Vin is accumulated in the node Ndac (one end of the capacitance element Cdac). As a result, the voltage Vdac of the node Ndac ideally indicates the voltage Vinx obtained by inverting the input voltage Vin.

[0061] Thereafter, in the second sampling mode, the switch SW11a switches from on to off, and the switch SW11b switches from off to on. As a result, the AD converter 112 converts the input voltage Vin sampled and held in the first sampling mode into a digital signal and outputs it. The inversion circuit 113 inverts the output signal of the AD converter 112 and outputs it. The DA converter 114 converts the output signal of the inversion circuit 113 into an analog voltage and outputs it to the node Ndac.

[0062] Then, in the hold mode, the switch SW11 is switched from on to off, the switch SW11b is switched from on to off, the switches SW12 and SW12a are switched from off to on, and the switch SW13 is switched from on to off. As a result, the sampled input voltage Vin is held in the capacitance element Cs. Also, the sampled output voltage (corresponding to the voltage Vinx) of the DA converter 114 is held in the capacitance element Cdac.

[0063] Here, when the switch SW12 is turned on and the voltage Vs of the node Ns transitions from the input voltage Vin to the reference voltage Vss, the negative feedback circuit 12 generates an analog voltage such that the voltage Vm of the non-inverting input terminal of the comparator 121 indicates the reference voltage Vss, i.e., an analog voltage such that the voltage Vdac of the node Ndac transitions from the voltage Vinx to the reference voltage Vss, and outputs it to the node Ndac.

[0064] Specifically, the negative feedback circuit 12 uses a comparator 121 and a successive approximation register circuit 122 to perform a successive approximation operation between an output voltage of a DA converter 123 and an input voltage Vin.

[0065] Here, in the semiconductor device 1, an error occurs in the capacitance element Cs due to the dielectric relaxation phenomenon, and an error of the opposite polarity to the error occurring in the capacitance element Cs occurs in the capacitance element Cdac due to the dielectric relaxation phenomenon. Therefore, in the voltage Vm of the non-inverting input terminal of the comparator 121 to which the other end of the capacitance element Cs and the other end of the capacitance element Cdac are commonly connected, these error components are cancelled. However, in the voltage Vm of the non-inverting input terminal of the comparator 121, the component of the input voltage Vin (input signal component) is also cancelled.

[0066] Therefore, the semiconductor device 1 uses the adder circuit 13 to add the input signal component (the AD conversion result of the input voltage Vin) output from the AD converter 112 to the signal component output from the successive approximation register circuit 122 that has not been canceled by the signal cancellation circuit 11, and outputs the addition result as a digital output signal ADOUT. This allows the semiconductor device 1 to output a highly accurate digital output signal ADOUT in which errors have been canceled.

[0067] In this way, the semiconductor device 1 according to this embodiment samples the input voltage Vin and its inverted voltage, and holds them in the capacitive elements Cs and Cdac commonly connected to the non-inverting input terminal of the comparator 121. As a result, the semiconductor device 1 according to this embodiment can cancel the error caused by the dielectric relaxation phenomenon and the error of opposite polarity caused by the dielectric relaxation phenomenon, and can therefore accurately take in the input voltage Vin, convert it into a digital output signal ADOUT, and output it.

[0068] <First Modification of Semiconductor Device 1> 3 is a circuit diagram showing a semiconductor device 1a as a first modified example of the semiconductor device 1. Compared to the semiconductor device 1, the semiconductor device 1a includes a signal cancellation circuit 11a instead of the signal cancellation circuit 11 and a negative feedback circuit 12a instead of the negative feedback circuit 12.

[0069] Negative feedback circuit 12a does not include DA converter 123, and instead uses DA converter 114 to achieve the function of DA converter 123. In other words, DA converter 114 is also used as DA converter 123. In signal cancellation circuit 11a, switch SW12a is provided between the output of successive approximation register circuit 122 and the input of DA converter 114. Other configurations of semiconductor device 1a are similar to those of semiconductor device 1, and therefore description thereof will be omitted.

[0070] The semiconductor device 1a can achieve effects equivalent to those of the semiconductor device 1. Furthermore, the semiconductor device 1a can reduce the number of DA converters compared to the semiconductor device 1, and therefore the circuit scale can be reduced.

[0071] Next, a specific configuration example of the semiconductor device 1a will be described with reference to Fig. 4. Fig. 4 is a circuit diagram showing a specific example of the semiconductor device 1a.

[0072] 4, the DA converter 114 includes capacitive elements Cu0 and Cu1 exhibiting a minimum capacitance value 2^0·C, n-1 (n is an integer equal to or greater than 2) capacitive elements Cu2 to Cun that are binary-weighted with respect to the capacitance value of the capacitive element Cu1, and switches Su0, Su1 to Sun provided corresponding to the capacitive elements Cu0, Cu1 to Cun, respectively. Here, the switches Su0, Su1 to Sun are not only used as a part of the DA converter 114 but also used as the switch SW11a. The capacitive elements Cu0, Cu1 to Cun are not only used as a part of the DA converter 114 but also used as the capacitive element Cdac. The DA converter 114 is also used as the DA converter 123 provided in the negative feedback circuit 12 of the semiconductor device 1.

[0073] <Second Modification of Semiconductor Device 1> 5 is a circuit diagram showing a semiconductor device 1b as a second modified example of the semiconductor device 1. Compared to the semiconductor device 1a, the semiconductor device 1b includes a signal cancellation circuit 11b instead of the signal cancellation circuit 11a, and includes switches SW11c and SW11d instead of the switch SW11.

[0074] Compared to the signal cancellation circuit 11a, the signal cancellation circuit 11b does not include the inversion circuit 111. The switch SW11a is provided between the node Ndac and an inversion circuit INV1 that generates an inverted voltage of the common voltage Vcm.

[0075] The switch SW11c is provided between the node Ns and a voltage supply terminal (hereinafter referred to as the voltage supply terminal Vcm) to which a common voltage Vcm is supplied. The switch SW11d is provided between the input terminal Vin and the node Ns. In other words, the switch SW11d is provided at the location where the switch SW11 was provided.

[0076] The rest of the configuration of the semiconductor device 1b is similar to that of the semiconductor device 1a, so a description thereof will be omitted.

[0077] 6 is a timing chart showing the operation of the semiconductor device 1b. Each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 1b include at least a sampling mode and a hold mode. The sampling mode is composed of a first sampling mode and a second sampling mode.

[0078] First, in the first sampling mode, the switches SW11a and SW11c are in the on state, the switches SW11b and SW11d are in the off state, the switches SW12 and SW12a are in the off state, and the switch SW13 is in the on state. As a result, charges corresponding to the common voltage Vcm and the inverted voltage of the common voltage Vcm are stored in the node Ns (one end of the capacitance element Cs) and the node Ndac (one end of the capacitance element Cdac), respectively. As a result, the voltage Vs of the node Ns and the voltage Vdac of the node Ndac indicate the common voltage Vcm and the inverted voltage of the common voltage Vcm, respectively.

[0079] Then, in the second sampling mode, the switches SW11a and SW11c are switched from on to off, and the switches SW11b and SW11d are switched from off to on. This causes sampling of the input voltage Vin. That is, a charge corresponding to the input voltage Vin is accumulated in the node Ns (one end of the capacitance element Cs). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin.

[0080] In the second sampling mode, the AD converter 112 converts the input voltage Vin sampled and held in the first sampling mode into a digital signal and outputs it. The inversion circuit 113 inverts the output signal of the AD converter 112 and outputs it. The DA converter 114 converts the output signal of the inversion circuit 113 into an analog voltage and outputs it to a node Ndac. As a result, the voltage Vdac of the node Ndac ideally indicates a voltage Vinx obtained by inverting the input voltage Vin.

[0081] Then, in the hold mode, the switches SW11b and SW11d are switched from on to off, the switches SW12 and SW12a are switched from off to on, and the switch SW13 is switched from on to off, so that the sampled input voltage Vin is held in the capacitance element Cs, and the voltage Vinx obtained by inverting the sampled input voltage Vin is held in the capacitance element Cdac.

[0082] Here, when the switch SW12 is turned on and the voltage Vs of the node Ns transitions to the reference voltage Vss, the negative feedback circuit 12 generates an analog voltage such that the voltage Vm of the non-inverting input terminal of the comparator 121 indicates the reference voltage Vss, i.e., an analog voltage such that the voltage Vdac of the node Ndac transitions from the voltage of Vinx to the reference voltage Vss, and outputs it to the node Ndac.

[0083] Specifically, the negative feedback circuit 12 uses a comparator 121 and a successive approximation register circuit 122 to perform a successive approximation operation between an output voltage of a DA converter 123 and an input voltage Vin.

[0084] Here, in the semiconductor device 1b, an error occurs in the capacitance element Cs due to the dielectric relaxation phenomenon, and an error of the opposite polarity occurs in the capacitance element Cdac due to the dielectric relaxation phenomenon. Therefore, in the voltage Vm of the non-inverting input terminal of the comparator 121 to which the other end of the capacitance element Cs and the other end of the capacitance element Cdac are commonly connected, these error components are cancelled. However, in the voltage Vm of the non-inverting input terminal of the comparator 121, the component of the input voltage Vin (input signal component) is also cancelled.

[0085] Therefore, the semiconductor device 1b uses the adder circuit 13 to add the input signal component (the AD conversion result of the input voltage Vin) output from the AD converter 112 to the signal component output from the successive approximation register circuit 122 that has not been canceled by the signal cancellation circuit 11b, and outputs the addition result as a digital output signal ADOUT. This allows the semiconductor device 1b to output a highly accurate digital output signal ADOUT in which errors have been canceled.

[0086] In this way, when the input voltage Vin is not supplied in the first sampling mode, the semiconductor device 1b can achieve the same effect as the semiconductor device 1a by applying the common voltage Vcm to the capacitance element Cs and waiting with the inverted voltage of the common voltage Vcm applied to the capacitance element Cdac. Also, the semiconductor device 1b can achieve the same effect as the semiconductor device 1a by applying the input voltage Vin to the node Ns in the second sampling mode and applying a voltage equivalent to the input voltage Vin obtained from the signal cancellation circuit output to the node Ndac. However, a larger effect can be expected when the input voltage Vin does not change significantly in the second sampling mode (i.e., the input voltage Vin behaves like a DC voltage).

[0087] <Third Modification of Semiconductor Device 1> 7 is a circuit diagram showing a semiconductor device 1c as a third modified example of the semiconductor device 1. Compared to the semiconductor device 1, the semiconductor device 1c includes a negative feedback circuit 12c instead of the negative feedback circuit 12, and further includes an AD converter 14. The negative feedback circuit 12c includes an operational amplifier 124.

[0088] The other end of the capacitive element Cs and the other end of the capacitive element Cdac are both connected to an inverting input terminal of the operational amplifier 124. A reference voltage Vss is supplied to a non-inverting input terminal of the operational amplifier 124. A switch SW12a is provided between the output of the operational amplifier 124 and a node Ndac (one end of the capacitive element Cdac).

[0089] The operational amplifier 124 amplifies and outputs the potential difference between the voltage Vm of the inverting input terminal and the voltage Vss of the non-inverting input terminal. The output voltage of the operational amplifier 124 is fed back and applied to a node Ndac via a switch SW12a.

[0090] The AD converter 14 converts the output voltage of the operational amplifier 124 into a digital signal and outputs it. The adder circuit 13 adds the input signal component (the AD conversion result of the input voltage Vin) output from the AD converter 112 to the signal component output from the AD converter 14 that has not been canceled by the signal cancellation circuit 11c, and outputs the addition result as a digital output signal. This allows the semiconductor device 1c to output a highly accurate digital output signal ADOUT in which errors have been canceled.

[0091] As a result, the semiconductor device 1c can achieve effects equivalent to those of the semiconductor device 1.

[0092] <Embodiment 2> 8 is a circuit diagram showing a configuration example of a semiconductor device 2 according to embodiment 2. The semiconductor device 2 is a so-called top plate sampling type AD converter.

[0093] Specifically, the semiconductor device 2 includes a signal cancellation circuit 21, a negative feedback circuit 22, an adder circuit 23, a capacitive element Cs, and a switch SW21. The signal cancellation circuit 21 includes a sub AD converter 212, a sub DA converter 214, switches SW21a and SW21b, and a switch SW22. The negative feedback circuit 22 includes a comparator 221, a successive approximation register circuit 222, and a DA converter 223. For example, the switch SW21 configures a sampling circuit.

[0094] The switch SW21 is provided between the non-inverting input terminal of the comparator 221 and the input terminal Vin. The capacitance element Cs is provided between the non-inverting input terminal of the comparator 221 and the node Ndac. The signal cancellation circuit 21 is provided between the input terminal Vin and the node Ndac (one end of the capacitance element Cs).

[0095] In the signal cancellation circuit 21, the switch SW21a is provided on a path between the input terminal Vin and the node Ndac. The AD converter 212, the DA converter 214, and the switch SW21b are provided on a path between the input terminal Vin and the node Ndac that is different from the path on which the switch SW21a is provided. The AD converter 212 samples and holds the input voltage Vin, and converts the held input voltage Vin into a digital signal and outputs it. The DA converter 214 converts the output signal of the AD converter 212 into an analog voltage and outputs it. The switches SW21a and SW21b function as a selection circuit that selects and outputs either the input voltage Vin or the DA converter 214.

[0096] The successive approximation register circuit 222 outputs a digital signal (a control signal for controlling a switch of the DA converter 223) according to the comparison result of the comparator 221, and outputs an output signal of a determined digital value. The DA converter 223 converts the digital signal output from the successive approximation register circuit 222 into an analog voltage and outputs it. The switch SW22 is provided between the output of the DA converter 223 and the node Ndac.

[0097] The adder circuit 23 adds the output of the AD converter 212 and the output of the successive approximation register circuit 122, and outputs the addition result as a digital output signal ADOUT.

[0098] 9 is a timing chart showing the operation of the semiconductor device 2. Each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 2 include at least a sampling mode and a hold mode. The sampling mode is composed of a first sampling mode and a second sampling mode.

[0099] First, in the first sampling mode, the switch SW21 indicates an on state, the switch SW21a indicates an on state, the switch SW21b indicates an off state, and the switch SW22 indicates an off state. As a result, sampling of the input voltage Vin is performed. That is, a charge according to the input voltage Vin is accumulated in the node Ns (the other end of the capacitance element Cs and the non-inverting input terminal of the comparator 221). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin. Also, a charge according to the input voltage Vin is accumulated in the node Ndac (one end of the capacitance element Cs). As a result, the voltage Vdac of the node Ndac ideally indicates the input voltage Vin.

[0100] Thereafter, in the second sampling mode, the switch SW21a switches from on to off, and the switch SW21b switches from off to on. As a result, the AD converter 212 converts the input voltage Vin sampled and held in the first sampling mode into a digital signal and outputs it. The DA converter 214 converts the output signal of the AD converter 212 into an analog voltage and outputs it to the node Ndac.

[0101] After that, in the hold mode, the switch SW21 is switched from on to off, the switch SW21b is switched from on to off, and the switch SW22 is switched from off to on. As a result, the differential potential between the sampled input voltage Vin and the output voltage of the signal cancellation circuit 21a is held in the capacitance element Cs. At this time, the negative feedback circuit 22 generates an analog voltage such that the voltage Vs of the non-inverting input terminal of the comparator 221 indicates the reference voltage Vss, that is, an analog voltage such that the voltage Vdac of the node Ndac indicates the reference voltage Vss, and outputs it to the node Ndac.

[0102] Specifically, the negative feedback circuit 22 uses a comparator 221 and a successive approximation register circuit 222 to perform a successive approximation operation between an output voltage of a DA converter 223 and an input voltage Vin.

[0103] Here, in the semiconductor device 2, the voltage Vs at the node Ns, which is one end of the capacitance element Cs, and the voltage Vdac at the node Ndac, which is the other end, behave so as to cancel each other's signal components. In other words, the semiconductor device 2 controls the potential difference between the node Ns and the node Ndac to always be constant, thereby preventing errors due to the dielectric relaxation phenomenon from occurring in the first place. However, in the voltage Vm at the non-inverting input terminal of the comparator 221, the component of the input voltage Vin (input signal component) is also cancelled.

[0104] Therefore, the semiconductor device 2 uses the adder circuit 23 to add the input signal component (AD conversion result of the input voltage Vin) output from the AD converter 212 to the signal component output from the successive approximation register circuit 222 that has not been canceled by the signal cancellation circuit 21, and outputs the addition result as a digital output signal ADOUT. This allows the semiconductor device 2 to output a highly accurate digital output signal ADOUT in which errors have been canceled.

[0105] In this way, the semiconductor device 2 according to the present embodiment samples the input voltage Vin and holds it at one end and the other end of the capacitance element Cs connected to the non-inverting input terminal of the comparator 221. As a result, the semiconductor device 2 according to the present embodiment can prevent errors from occurring due to the dielectric relaxation phenomenon in the first place by canceling the signal applied to the capacitance element Cs, and can therefore accurately take in the input voltage Vin and accurately convert it into a digital output signal ADOUT for output.

[0106] The semiconductor device 2 may use a configuration of a negative feedback circuit 12c having an operational amplifier instead of the negative feedback circuit 22. In that case, the semiconductor device 2 further includes a configuration of an AD converter 14 that performs AD conversion on the output signal of the negative feedback circuit.

[0107] <First Modification of Semiconductor Device 2> 10 is a circuit diagram showing a semiconductor device 2a as a first modified example of the semiconductor device 2. Compared to the semiconductor device 2, the semiconductor device 2a includes a signal cancellation circuit 21a instead of the signal cancellation circuit 21 and a negative feedback circuit 22a instead of the negative feedback circuit 22.

[0108] The negative feedback circuit 12a does not include the DA converter 223, and instead uses the DA converter 214 to achieve the function of the DA converter 223. In other words, the DA converter 214 is also used as the DA converter 223. In the signal cancellation circuit 21a, the switch SW22 is provided between the output of the successive approximation register circuit 222 and the input of the DA converter 214. The other configurations of the semiconductor device 2a are similar to those of the semiconductor device 2, and therefore will not be described.

[0109] The semiconductor device 2a can achieve effects equivalent to those of the semiconductor device 2. Furthermore, the semiconductor device 2a can reduce the number of DA converters compared to the semiconductor device 2, and therefore the circuit scale can be reduced.

[0110] Next, a specific configuration example of the semiconductor device 2a will be described with reference to Fig. 11. Fig. 11 is a circuit diagram showing a specific example of the semiconductor device 2a.

[0111] 11, the DA converter 214 includes capacitive elements Cu0 and Cu1 exhibiting a minimum capacitance value 2^0·C, n-1 (n is an integer of 2 or more) capacitive elements Cu2 to Cun binary-weighted with respect to the capacitance value of the capacitive element Cu1, and switches Su0, Su1 to Sun provided corresponding to the capacitive elements Cu0, Cu1 to Cun, respectively. Here, the switches Su0, Su1 to Sun are not only used as a part of the DA converter 214 but also used as the switch SW21a. The capacitive elements Cu0, Cu1 to Cun are not only used as a part of the DA converter 214 but also used as the capacitive element Cs. The DA converter 214 is also used as the DA converter 223 provided in the negative feedback circuit 22 of the semiconductor device 2.

[0112] <Second Modification of Semiconductor Device 2> 12 is a circuit diagram showing a semiconductor device 2b as a second modified example of the semiconductor device 2. Compared to the semiconductor device 2a, the semiconductor device 2b includes a signal cancellation circuit 21b instead of the signal cancellation circuit 21a, and includes switches SW21c and SW21d instead of the switch SW21.

[0113] In the signal cancellation circuit 21b, the path of the switch SW21a is different from that of the signal cancellation circuit 21a. The switch SW21a is provided between the node Ndac and the voltage supply terminal Vcm. The switch SW21c is provided between the node Ns and the voltage supply terminal Vcm. The switch SW21d is provided between the input terminal Vin and the node Ns. The other configurations of the semiconductor device 2b are similar to those of the semiconductor device 2a, and therefore the description thereof will be omitted.

[0114] 13 is a timing chart showing the operation of the semiconductor device 2b. Each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 2b include at least a sampling mode and a hold mode. The sampling mode is composed of a first sampling mode and a second sampling mode.

[0115] First, in the first sampling mode, the switches SW21a and SW21c are in an on state, the switches SW21b and SW21d are in an off state, and the switch SW22 is in an off state. As a result, charges according to the common voltage Vcm are accumulated in the node Ns (the other end of the capacitance element Cs and the non-inverting input terminal of the comparator 221) and the node Ndac (one end of the capacitance element Cs). As a result, the voltage Vs of the node Ns and the voltage Vdac of the node Ndac both indicate the common voltage Vcm.

[0116] After that, in the second sampling mode, the switches SW21a and SW21c are switched from on to off, and the switches SW21b and SW21d are switched from off to on. This causes sampling of the input voltage Vin. That is, a charge corresponding to the input voltage Vin is accumulated in the node Ns (the other end of the capacitance element Cs). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin.

[0117] In the second sampling mode, the AD converter 212 converts the input voltage Vin sampled and held in the first sampling mode into a digital signal and outputs it. The DA converter 214 converts the output signal of the AD converter 212 into an analog voltage and outputs it to the node Ndac. As a result, the voltage Vdac of the node Ndac ideally indicates the input voltage Vin.

[0118] After that, in the hold mode, the switches SW21b and SW21d are switched from on to off, and the switch SW22 is switched from off to on. As a result, the differential potential between the sampled input voltage Vin and the output voltage of the signal cancellation circuit 21b is held in the capacitance element Cs. At this time, the negative feedback circuit 22a generates an analog voltage such that the voltage Vs of the non-inverting input terminal of the comparator 221 indicates the reference voltage Vss, that is, an analog voltage such that the voltage Vdac of the node Ndac indicates the reference voltage Vss, and outputs it to the node Ndac.

[0119] Here, in the semiconductor device 2b, the voltage Vs at the node Ns, which is one end of the capacitance element Cs, and the voltage Vdac at the node Ndac, which is the other end, behave so as to cancel each other's signal components. In other words, the semiconductor device 2b controls the potential difference between the node Ns and the node Ndac to always be constant, thereby preventing errors due to the dielectric relaxation phenomenon from occurring in the first place. However, in the voltage Vm at the non-inverting input terminal of the comparator 221, the component of the input voltage Vin (input signal component) is also cancelled.

[0120] Therefore, the semiconductor device 2b uses the adder circuit 23 to add the input signal component (AD conversion result of the input voltage Vin) output from the AD converter 212 to the signal component output from the successive approximation register circuit 222 that has not been canceled by the signal cancellation circuit 21b, and outputs the addition result as a digital output signal ADOUT. This allows the semiconductor device 2b to output a highly accurate digital output signal ADOUT in which errors have been canceled.

[0121] In this way, when the input voltage Vin is not supplied in the first sampling mode, the semiconductor device 2b can achieve the same effect as the semiconductor device 2a by waiting with the common voltage Vcm applied to the capacitance element Cs. Also, the semiconductor device 2b can achieve the same effect as the semiconductor device 2a by applying the input voltage Vin to the node Ns in the second sampling mode and applying a voltage equivalent to the input voltage Vin obtained from the signal cancellation circuit output to the node Ndac. However, a larger effect can be expected when the input voltage Vin does not change significantly in the second sampling mode (i.e., the input voltage Vin behaves like a DC voltage).

[0122] <Embodiment 3> 14 is a circuit diagram showing a configuration example of a semiconductor device 3 according to embodiment 3. While the semiconductor device 1 is a single-ended AD converter, the semiconductor device 3 is an AD converter that performs AD conversion on a differential input signal.

[0123] Specifically, the semiconductor device 3 includes signal cancellation circuits 31p and 31n, a negative feedback circuit 32, an adding / subtracting circuit 33, capacitance elements Csp and Csn, capacitance elements Cdacp and Cdacn, switches SW31p and SW31n, a switch SW32, and a switch SW33. The negative feedback circuit 32 includes a comparator 321, a successive approximation register circuit 322, and a DA converter 323p and a DA converter 323n.

[0124] First, in the semiconductor device 3, a signal cancellation circuit 31p, a comparator 321, a successive approximation register circuit 322, a DA converter 323p, capacitance elements Csp, Cdacp, and switches SW31p, SW32, and SW33 are mainly used as a circuit for processing a positive-side input signal (input voltage) Vinp, which is one of a pair of differential input signals. Note that the signal cancellation circuit 31p, the comparator 321, the successive approximation register circuit 322, the DA converter 323p, the capacitance elements Csp, Cdacp, and the switches SW31p, SW32, and SW33 correspond to the signal cancellation circuit 11, the comparator 121, the successive approximation register circuit 122, the DA converter 123, the capacitance elements Cs, Cdac, and the switches SW11, SW12, and SW13 in the semiconductor device 1 shown in FIG. 1, respectively.

[0125] In the semiconductor device 3, a signal cancellation circuit 31n, a comparator 321, a successive approximation register circuit 322, a DA converter 323n, capacitance elements Csn, Cdacn, and switches SW31n, SW32, and SW33 are mainly used as a circuit for processing a negative-side input signal (input voltage) Vinn, which is the other of the pair of differential input signals. Note that the signal cancellation circuit 31n, the comparator 321, the successive approximation register circuit 322, the DA converter 323n, the capacitance elements Csn, Cdacn, and the switches SW31n, SW32, and SW33 correspond to the signal cancellation circuit 11, the comparator 121, the successive approximation register circuit 122, the DA converter 123, the capacitance elements Cs, Cdac, and the switches SW11, SW12, and SW13 in the semiconductor device 1 shown in FIG. 1, respectively.

[0126] The capacitance element Csp is provided between the non-inverting input terminal of the comparator 321 and a node Nsp. The switch SW31p is provided between the input terminal Vinp and the node Nsp (one end of the capacitance element Csp). The capacitance element Csn is provided between the inverting input terminal of the comparator 321 and a node Nsn. The switch SW31n is provided between the input terminal Vinn and the node Nsn (one end of the capacitance element Csn). The switch SW32 is provided between the node Nsp and the node Nsn. The switch SW33 is provided between the non-inverting input terminal and the inverting input terminal of the comparator 321.

[0127] The capacitive element Cdacp is provided between the non-inverting input terminal of the comparator 321 and the node Ndacp. The signal cancellation circuit 31p is provided between the input terminal Vinp and the node Ndacp (one end of the capacitive element Cdacp).

[0128] The signal cancellation circuit 31p includes a sub AD converter 312p, an inversion circuit 313p, a sub DA converter 314p, a switch SW31ap, a switch SW31bp, and a switch SW32ap. The AD converter 312p, the inversion circuit 313p, the DA converter 314p, the switch SW31ap, the switch SW31bp, and the switch SW32ap correspond to the AD converter 112, the inversion circuit 113, the DA converter 114, the switch SW11a, the switch SW11b, and the switch SW12a provided in the signal cancellation circuit 11 shown in FIG. 1, respectively. Here, the signal cancellation circuit 31p does not require a circuit corresponding to the inversion circuit 111 by using the negative side input voltage Vinn (i.e., a voltage obtained by inverting the input voltage Vinp). Specifically, the switch SW31ap is provided between the input terminal Vinn and the node Ndacp.

[0129] The capacitive element Cdacn is provided between the inverting input terminal of the comparator 321 and the node Ndacn. The signal cancellation circuit 31n is provided between the input terminal Vinn and the node Ndacn (one end of the capacitive element Cdacn).

[0130] The signal cancellation circuit 31n includes a sub AD converter 312n, an inversion circuit 313n, a sub DA converter 314n, a switch SW31an, a switch SW31bn, and a switch SW32an. The AD converter 312n, the inversion circuit 313n, the DA converter 314n, the switch SW31an, the switch SW31bn, and the switch SW32an correspond to the AD converter 112, the inversion circuit 113, the DA converter 114, the switch SW11a, the switch SW11b, and the switch SW12a provided in the signal cancellation circuit 11 shown in FIG. 1, respectively. Here, the signal cancellation circuit 31n does not require a circuit corresponding to the inversion circuit 111 by using a positive input voltage Vinp (i.e., a voltage obtained by inverting the input voltage Vinn). Specifically, the switch SW31an is provided between the input terminal Vinp and a node Ndacn.

[0131] The successive approximation register circuit 322 outputs a digital signal (a control signal for controlling each switch of the DA converters 123p, 123n) according to the comparison result of the comparator 321, and outputs an output signal of a determined digital value. The DA converter 323p converts the digital signal output from the successive approximation register circuit 322 into an analog voltage and outputs it. The switch SW32ap is provided between the output of the DA converter 323p and a node Ndacp. The DA converter 323n converts the digital signal output from the successive approximation register circuit 322 into an analog voltage and outputs it. The switch SW32an is provided between the output of the DA converter 323n and a node Ndacn.

[0132] The adder-subtractor circuit 33 adds the difference between the output of the AD converter 312p and the output of the AD converter 312n to the output of the successive approximation register circuit 322, and outputs the addition result as a digital output signal ADOUT.

[0133] 15 is a timing chart showing the operation of the semiconductor device 3. Each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 3 include at least a sampling mode and a hold mode. The sampling mode is composed of a first sampling mode and a second sampling mode.

[0134] First, in the first sampling mode, the switches SW31p and SW31n indicate an on state, the switches SW31ap and SW31an indicate an on state, the switches SW31bp and SW31bn indicate an off state, the switches SW32, SW32ap and SW32an indicate an off state, and the switch SW33 indicates an on state. As a result, sampling of the input voltages Vinp and Vinn is performed. That is, a charge according to the input voltage Vinp is accumulated in the node Nsp (one end of the capacitance element Csp), and a charge according to the input voltage Vinn is accumulated in the node Nsn (one end of the capacitance element Csn). As a result, the voltage Vsp of the node Nsp ideally indicates the input voltage Vinp, and the voltage Vsn of the node Nsn ideally indicates the input voltage Vinn. In addition, a charge according to the voltage Vinn obtained by inverting the input voltage Vinp is stored in the node Ndacp (one end of the capacitance element Cdacp), and a charge according to the voltage Vinp obtained by inverting the input voltage Vinn is stored in the node Ndacn (one end of the capacitance element Cdacn). As a result, the voltage Vdacp of the node Ndacp ideally indicates the voltage Vinn, and the voltage Vdacn of the node Ndacn ideally indicates the voltage Vinp.

[0135] Thereafter, in the second sampling mode, the switches SW31ap and SW31an are switched from on to off, and the switches SW31bp and SW31bn are switched from off to on. Thereby, the AD converter 312p converts the input voltage Vinp sampled and held in the first sampling mode into a digital signal and outputs it. The inversion circuit 313p inverts the output signal of the AD converter 312p and outputs it. The DA converter 314p converts the output signal of the inversion circuit 313p into an analog voltage and outputs it to the node Ndacp. Also, the AD converter 312n converts the input voltage Vinn sampled and held in the first sampling mode into a digital signal and outputs it. The inversion circuit 313n inverts the output signal of the AD converter 312n and outputs it. The DA converter 314n converts the output signal of the inversion circuit 313n into an analog voltage and outputs it to the node Ndacn.

[0136] Thereafter, in the hold mode, the switches SW31p and SW31n are switched from on to off, the switches SW31bp and SW31bn are switched from on to off, the switches SW32, SW32ap and SW32an are switched from off to on, and the switch SW33 is switched from on to off. As a result, the sampled input voltages Vinp and Vinn are held in the capacitance elements Csp and Csn, respectively. Also, the sampled output voltage of the DA converter 314p (corresponding to the voltage Vinn) and the sampled output voltage of the DA converter 314n (corresponding to the voltage Vinp) are held in the capacitance elements Cdacp and Cdacn, respectively.

[0137] Here, the switch SW32 is turned on to differentially short-circuit the nodes Nsp and Nsn, and the negative feedback circuit 32 controls the voltage Vdacp of the node Ndacp and the voltage Vdacn of the node Ndacn so that the voltage Vmp of the non-inverting input terminal of the comparator 321 and the voltage Vmn of the inverting input terminal of the comparator 321 match.

[0138] Here, in the semiconductor device 3, an error occurs in the capacitance elements Csp and Csn due to the dielectric relaxation phenomenon, and an error of the opposite polarity occurs in the capacitance elements Cdacp and Cdacn due to the dielectric relaxation phenomenon. Therefore, in the difference voltage between the voltage Vmp of the non-inverting input terminal of the comparator 321 to which the other end of the capacitance element Csp and the other end of the capacitance element Cdacp are commonly connected, and the voltage Vmn of the inverting input terminal of the comparator 321 to which the other end of the capacitance element Csn and the other end of the capacitance element Cdacn are commonly connected, these error components are cancelled. However, in the voltages Vmp and Vmn of the non-inverting input terminals of the comparator 321, the component of the input voltage Vin (input signal component) is also cancelled.

[0139] Therefore, the semiconductor device 3 uses the adder-subtractor circuit 33 to add the difference between the input signal component (AD conversion result of the input voltage Vinp) output from the AD converter 312p and the input signal component (AD conversion result of the input voltage Vinn) output from the AD converter 312n to the signal component output from the successive approximation register circuit 322 that has not been canceled by the signal cancellation circuits 31p, 31n, and outputs the addition result as a digital output signal ADOUT. This allows the semiconductor device 3 to output a highly accurate digital output signal ADOUT in which the settling error has been canceled.

[0140] In this way, the semiconductor device 3 according to the present embodiment can achieve effects equivalent to those of the semiconductor device 1.

[0141] <First Modification of Semiconductor Device 3> 16 is a circuit diagram showing a first modified example of the semiconductor device 3 as a semiconductor device 3a. Compared to the semiconductor device 3, the semiconductor device 3a includes signal cancellation circuits 41p and 42n instead of the signal cancellation circuits 31p and 31n, and includes an adder circuit 33a instead of the adder-subtractor circuit 33. Compared to the signal cancellation circuit 31p, the signal cancellation circuit 41p includes an AD converter 412p that performs AD conversion on a differential input signal instead of the single-ended AD converter 312p. Compared to the signal cancellation circuit 41n, the signal cancellation circuit 41n does not include the AD converter 312n and the inverting circuit 313n. In the signal cancellation circuit 41n, the DA converter 314n is configured to convert the output signal of the AD converter 412p into an analog voltage. Other configurations of the semiconductor device 3a are the same as those of the semiconductor device 3, so their description will be omitted.

[0142] The semiconductor device 3a can achieve effects equivalent to those of the semiconductor device 3. Furthermore, the semiconductor device 3a can reduce the number of AD converters, thereby reducing the circuit scale.

[0143] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist of the invention.

[0144] Furthermore, in the present disclosure, a part or all of the processing of the semiconductor devices 1 to 3 can be realized by causing a CPU (Central Processing Unit) to execute a computer program.

[0145] The above-mentioned program includes a set of instructions (or software code) for making the computer perform one or more functions described in the embodiment when the program is loaded into the computer. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or the tangible storage medium includes a random-access memory (RAM), a read-only memory (ROM), a flash memory, a solid-state drive (SSD) or other memory technology, a CD-ROM, a digital versatile disc (DVD), a Blu-ray® disk or other optical disk storage, a magnetic cassette, a magnetic tape, a magnetic disk storage or other magnetic storage device. The program may be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or the communication medium includes an electrical, optical, acoustic, or other form of propagating signal. [Explanation of symbols]

[0146] 1 Semiconductor device 1a, 1b, 1c Semiconductor device 2. Semiconductor Devices 2a, 2b Semiconductor device 3. Semiconductor Devices 3a Semiconductor device 11 Signal Cancellation Circuit 11a, 11b Signal cancellation circuit 12 Negative feedback circuit 12a, 12c Negative feedback circuit 13 Adding Circuit 14 A / D converter 21 Signal Cancellation Circuit 21a, 21b Signal cancellation circuit 22 Negative feedback circuit 22a Negative feedback circuit 23 Addition Circuit 31p Signal Cancellation Circuit 31n signal cancellation circuit 32 Negative feedback circuit 41p Signal Cancellation Circuit 41n signal cancellation circuit 111 Inverting circuit 112 A / D converter 113 Inverting Circuit 114 Digital to analog converter 121 Comparator 122 Successive approximation register circuit 123 DA Converter 124 Operational Amplifiers 212 A / D converter 214 Digital to analog converter 221 Comparator 222 Successive approximation register circuit 223 DA Converter Cs capacitive element Cdac Capacitor SW11 Switch SW11a, SW11b, SW11c, SW11d switches SW12 Switch SW12a Switch SW13 Switch SW21 Switch SW21a, SW21b, SW21c, SW21d Switch SW22 Switch

Claims

1. A first capacitive element; a signal cancellation circuit that, in a sampling mode, generates a first voltage corresponding to a first input voltage and applies the first voltage to one end of the first capacitance element, and, in a hold mode after the sampling mode, holds the generated first voltage and applies the first voltage to one end of the first capacitance element; a sampling circuit that samples the first input voltage in a sampling mode, and applies a second voltage corresponding to the sampled first input voltage to the other end of the first capacitive element while holding the second voltage in a hold mode; a negative feedback circuit that generates an output signal according to a voltage at the other end of the first capacitance element in a hold mode and applies a feedback signal corresponding to the output signal to one end of the first capacitance element; a first AD converter that performs AD conversion on the first input voltage; an adder / subtractor circuit that performs addition / subtraction on an output signal of the negative feedback circuit and an output signal of the first AD converter and outputs the result of the addition / subtraction; A semiconductor device comprising:

2. The sampling circuit includes: a second capacitance element having one end connected to the other end of the first capacitance element; a first switch that applies the first input voltage to the other end of the second capacitive element in a sampling mode and holds the first input voltage in the second capacitive element in a hold mode; a second switch that transitions a voltage at the other end of the second capacitive element to a reference voltage in a hold mode, thereby transitioning a voltage at one end of the second capacitive element to the second voltage; having The semiconductor device according to claim 1 .

3. The signal cancellation circuit includes: a first inverter circuit that generates a voltage obtained by inverting the first input voltage; a sub-AD converter that samples the first input voltage in a sampling mode and converts the sampled first input voltage into a digital signal while holding the sampled first input voltage in a hold mode; a second inversion circuit that inverts the output signal of the sub AD converter and outputs the inverted signal; a sub DA converter that converts an output signal of the second inversion circuit into an analog voltage; a selection circuit that, in a sampling mode, selects the voltage generated by the first inversion circuit and outputs it as the first voltage, and, in a hold mode, selects the analog voltage output from the sub AD converter and outputs it as the first voltage; Equipped with The semiconductor device according to claim 2 .

4. The first AD converter is constituted by the sub AD converter. The semiconductor device according to claim 3 .

5. The sub DA converter includes: A plurality of sub-capacitance elements; a plurality of sub-switches provided corresponding to the plurality of sub-capacitance elements, having The plurality of sub-capacitor elements are also used as the first capacitor elements. The semiconductor device according to claim 3 .

6. the signal cancellation circuit is configured to apply a common voltage or an inverted voltage thereof as the first voltage to one end of the first capacitance element in a first sampling mode and to apply a voltage obtained by inverting the first input voltage as the first voltage to one end of the first capacitance element in a second sampling mode, the sampling circuit is configured to apply the common voltage to the other end of the second capacitive element in a first sampling mode, and to apply the first input voltage to the other end of the second capacitive element in a second sampling mode. The semiconductor device according to claim 2 .

7. the signal cancellation circuit generates the first voltage having an amplitude corresponding to a capacitance value of each of the first capacitive element and the second capacitive element. The semiconductor device according to claim 2 .

8. The negative feedback circuit includes: a comparator having one input terminal supplied with the voltage at the other end of the first capacitive element and having another input terminal supplied with a reference voltage; a successive approximation register circuit for generating a digital output signal according to a comparison result of the comparator; a DA converter that converts the output signal generated by the successive approximation register circuit into an analog voltage and outputs the analog voltage as the feedback signal; Equipped with the adder / subtractor circuit performs addition / subtraction on the output signal generated by the successive approximation register circuit and the output signal of the first AD converter, and outputs the result of the addition / subtraction. The semiconductor device according to claim 2 .

9. The negative feedback circuit includes: a comparator having one input terminal supplied with the voltage at the other end of the first capacitive element and having another input terminal supplied with a reference voltage; a successive approximation register circuit for generating a digital output signal according to a comparison result of the comparator; Equipped with the negative feedback circuit converts the output signal generated by the successive approximation register circuit into an analog voltage using the sub DA converter and outputs the analog voltage as the feedback signal; the adder / subtractor circuit performs addition / subtraction on the output signal generated by the successive approximation register circuit and the output signal of the first AD converter, and outputs the result of the addition / subtraction. The semiconductor device according to claim 3 .

10. a second AD converter that performs AD conversion on the output signal of the negative feedback circuit; The negative feedback circuit includes: an operational amplifier that generates an output signal according to a potential difference between a voltage at the other end of the first capacitance element and a reference voltage and the feedback signal corresponding to the output signal; the adding / subtracting circuit performs addition / subtraction on the output signal of the second AD converter and the output signal of the first AD converter, and outputs the result of the addition / subtraction. The semiconductor device according to claim 2 .

11. The sampling circuit includes: a first switch that samples the first input voltage in a sampling mode, and applies the sampled first input voltage to the other end of the first capacitive element as the second voltage while holding the sampled first input voltage in a hold mode; The semiconductor device according to claim 1 .

12. The signal cancellation circuit includes: a sub-AD converter that samples the first input voltage in a sampling mode and converts the sampled first input voltage into a digital signal while holding the sampled first input voltage in a hold mode; a sub DA converter for converting an output signal of the sub AD converter into an analog voltage; a selection circuit that, in a sampling mode, selects the first input voltage and outputs it as the first voltage, and that, in a hold mode, selects an analog voltage output from the sub AD converter and outputs it as the first voltage; Equipped with The semiconductor device according to claim 11.

13. The first AD converter is constituted by the sub AD converter. The semiconductor device according to claim 12.

14. The sub DA converter includes: A plurality of sub-capacitance elements; a plurality of sub-switches provided corresponding to the plurality of sub-capacitance elements, having The plurality of sub-capacitor elements are also used as the first capacitor elements. The semiconductor device according to claim 12.

15. the signal cancellation circuit is configured to apply, as the first voltage, an intermediate voltage between the first input voltage and a voltage obtained by inverting the first input voltage to one end of the first capacitance element in a first sampling mode and to apply, as the first voltage, the first input voltage to one end of the first capacitance element in a second sampling mode, the sampling circuit is configured to apply the intermediate voltage to the other end of the first capacitive element in a first sampling mode, and to apply the first input voltage to the other end of the first capacitive element in a second sampling mode. The semiconductor device according to claim 11.

16. The negative feedback circuit includes: a comparator having one input terminal supplied with the voltage at the other end of the first capacitive element and having another input terminal supplied with a reference voltage; a successive approximation register circuit for generating a digital output signal according to a comparison result of the comparator; a DA converter that converts the output signal generated by the successive approximation register circuit into an analog voltage and outputs the analog voltage as the feedback signal; Equipped with the adder / subtractor circuit performs addition / subtraction on the output signal generated by the successive approximation register circuit and the output signal of the first AD converter, and outputs the result of the addition / subtraction. The semiconductor device according to claim 11.

17. The negative feedback circuit includes: a comparator, the voltage at the other end of the first capacitive element being supplied to a non-inverting input terminal and a reference voltage being supplied to an inverting input terminal; a successive approximation register circuit for generating a digital output signal according to a comparison result of the comparator; Equipped with the negative feedback circuit converts the output signal generated by the successive approximation register circuit into an analog voltage using the sub DA converter and outputs the analog voltage as the feedback signal; the adder / subtractor circuit performs addition / subtraction on the output signal generated by the successive approximation register circuit and the output signal of the first AD converter, and outputs the result of the addition / subtraction. The semiconductor device according to claim 12.

18. a second AD converter that performs AD conversion on the output signal of the negative feedback circuit; The negative feedback circuit includes: an operational amplifier that generates an output signal according to a potential difference between a voltage at the other end of the first capacitance element and a reference voltage and the feedback signal corresponding to the output signal; the adding / subtracting circuit performs addition / subtraction on the output signal of the second AD converter and the output signal of the first AD converter, and outputs the result of the addition / subtraction. The semiconductor device according to claim 11.

19. A third capacitive element; a second signal cancellation circuit that, in a sampling mode, generates a third voltage corresponding to a second input voltage that constitutes a differential input signal together with the first input voltage, and applies the third voltage to one end of the third capacitance element, and, in a hold mode, holds the generated third voltage and applies the third voltage to one end of the third capacitance element; a second sampling circuit that samples the second input voltage in a sampling mode and applies a fourth voltage corresponding to the sampled second input voltage to the other end of the third capacitive element while holding the fourth voltage in a hold mode; Further equipped with the negative feedback circuit is configured to generate an output signal according to a potential difference between a voltage at the other end of the first capacitive element and a voltage at the other end of the third capacitive element in a hold mode, apply the feedback signal corresponding to the output signal to one end of the first capacitive element, and apply a second feedback signal corresponding to the output signal to one end of the third capacitive element. The semiconductor device according to claim 1 .

20. The sampling circuit includes: a second capacitance element having one end connected to the other end of the first capacitance element; a first switch that applies the first input voltage to the other end of the second capacitive element in a sampling mode and holds the first input voltage in the second capacitive element in a hold mode; a second switch that transitions a voltage at the other end of the second capacitive element to a reference voltage in a hold mode, thereby transitioning a voltage at one end of the second capacitive element to the second voltage; having The second sampling circuit includes: a fourth capacitance element having one end connected to the other end of the third capacitance element; a third switch that applies the second input voltage to the other end of the fourth capacitive element in a sampling mode and holds the second input voltage in the fourth capacitive element in a hold mode; and a fourth switch that transitions a voltage at the other end of the fourth capacitive element to a reference voltage in a hold mode, thereby transitioning a voltage at one end of the fourth capacitive element to the fourth voltage; having The signal cancellation circuit includes: a sub-AD converter that samples the first input voltage in a sampling mode and converts the sampled first input voltage into a digital signal while holding the sampled first input voltage in a hold mode; a first inversion circuit that inverts an output signal of the sub AD converter and outputs the inverted signal; a sub DA converter that converts an output signal of the first inversion circuit into an analog voltage; a selection circuit that, in a sampling mode, selects the second input voltage and outputs it as the first voltage, and that, in a hold mode, selects an analog voltage output from the sub AD converter and outputs it as the first voltage; having The second signal cancellation circuit includes: a second sub-A / D converter that samples the second input voltage in a sampling mode and converts the sampled second input voltage into a digital signal while holding the second input voltage in a hold mode; a second inversion circuit that inverts an output signal of the second sub-A / D converter and outputs the inverted signal; a second sub-DA converter that converts an output signal of the second inversion circuit into an analog voltage; a second selection circuit that, in a sampling mode, selects the first input voltage and outputs it as the third voltage, and, in a hold mode, selects the analog voltage output from the second sub-A / D converter and outputs it as the third voltage; having 20. The semiconductor device according to claim 19.

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