Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device having a structure in which chipping hardly occurs.SOLUTION: A semiconductor device 1 includes a semiconductor substrate 2 and a convex pattern structure 6 provided on a first main surface 2a of the semiconductor substrate 2. The pattern structure 6 located within a first predetermined distance D1 from a first side surface 3a along a first direction and the pattern structure 6 located within the first predetermined distance D1 from a second side surface 3b along the first direction are symmetrical with respect to a line extending in a second direction. The pattern structure 6 located within a second predetermined distance D2 from a third side surface 3c along the second direction and the pattern structure 6 located within the second predetermined distance D2 from a fourth side surface 3d along the second direction are symmetrical with respect to a line extending in the first direction.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present specification relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] The method for manufacturing a semiconductor device includes a step of dividing a semiconductor wafer, in which a plurality of element regions are arranged in a matrix, into individual pieces for each element region. In such a dividing step, a scribe and break method may be adopted. The scribe and break method is a method in which a weak portion is formed along the boundary between adjacent element regions, and then a dividing member is pressed along the boundary to divide the semiconductor wafer. The scribe and break method is useful for relatively hard materials, since the semiconductor wafer is divided by cleavage starting from the weak portion. In addition, the scribe and break method can narrow the scribe line, so that the number of pieces per semiconductor wafer can be increased, thereby reducing the manufacturing cost. Patent Document 1 discloses an example of a method for manufacturing a semiconductor device using the scribe and break method. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-104578 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the scribe and break method, when a dividing member is pressed against the semiconductor wafer to divide it, a phenomenon called chipping, in which part of the chip is chipped off, may occur. This specification provides a semiconductor device having a structure that is less susceptible to chipping, and a method for manufacturing a semiconductor device that suppresses the occurrence of chipping. [Means for solving the problem]

[0005] The semiconductor device (1) disclosed in the present specification may include a semiconductor substrate (2) having a first main surface (2a), a second main surface (2b) facing the first main surface, and side surfaces (3a, 3b, 3c, 3d) extending between the first main surface and the second main surface, the side surfaces including a first side surface (3a) and a second side surface (3b) facing each other in a first direction parallel to the first main surface and the second main surface, and a third side surface (3c) and a fourth side surface (3d) facing each other in a second direction parallel to the first main surface and the second main surface and perpendicular to the first direction, the side surfaces being cleavage planes, and a convex pattern structure (6) provided on the first main surface of the semiconductor substrate. The pattern structure located within a first predetermined distance (D1) from the first side surface along the first direction and the pattern structure located within the first predetermined distance from the second side surface along the first direction may be symmetrical with respect to a line extending in the second direction. The pattern structure within a second predetermined distance (D2) from the third side surface along the second direction and the pattern structure within the second predetermined distance from the fourth side surface along the second direction may be symmetrical with respect to a line extending in the first direction. This semiconductor device has a structure that is less susceptible to chipping when a semiconductor wafer is divided into individual pieces.

[0006] A manufacturing method of a semiconductor device (1) disclosed in the present specification may include a pattern structure forming step of forming a convex pattern structure (6) on a first main surface of a semiconductor wafer (2) having the first main surface (2a) and a second main surface (2b), the pattern structure being formed in each of a plurality of element regions (3) arranged in a matrix in the semiconductor wafer; and a dividing step of dividing the semiconductor wafer along a plurality of first scribe lines (12x) extending in a first direction parallel to the first main surface and the second main surface and a plurality of second scribe lines (12y) extending in a second direction parallel to the first main surface and the second main surface and perpendicular to the first direction, the dividing member (22) being pressed against the plurality of first scribe lines and the plurality of second scribe lines to divide the semiconductor wafer, thereby forming a plurality of individual semiconductor devices. Each of the plurality of individual semiconductor devices may include a semiconductor substrate having side surfaces (3a, 3b, 3c, 3d) extending between the first main surface and the second main surface, the side surfaces including a first side surface (3a) and a second side surface (3b) opposing each other in the first direction, and a third side surface (3c) and a fourth side surface (3d) opposing each other in the second direction. The pattern structure located within a first predetermined distance (D1) from the first side surface along the first direction and the pattern structure located within the first predetermined distance from the second side surface along the first direction may be symmetrical with respect to a line extending in the second direction. The pattern structure located within a second predetermined distance (D2) from the third side surface along the second direction and the pattern structure located within the second predetermined distance from the fourth side surface along the second direction may be symmetrical with respect to a line extending in the first direction. In this method for manufacturing a semiconductor device, a uniform load is applied to each of adjacent element regions in the dividing step, so that the occurrence of chipping is suppressed. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view that diagrammatically illustrates a layout of a semiconductor wafer. [Diagram 2]1A is a cross-sectional view including adjacent element regions in the x-axis direction, and shows a schematic pattern structure; FIG. 1B is a cross-sectional view including adjacent element regions in the y-axis direction, and shows a schematic pattern structure; [Diagram 3] FIG. 4 is an enlarged plan view showing a schematic layout of four element regions. [Figure 4] FIG. 2 is a plan view showing a schematic layout of an individual semiconductor device; [Diagram 5] FIG. 2 is a plan view showing a schematic layout of an individual semiconductor device; [Figure 6] FIG. 4 is a diagram for explaining a protective tape attaching step. [Figure 7] FIG. 4 is a diagram for explaining a crack formation process. [Figure 8] FIG. [Figure 9] FIG. [Figure 10] FIG. [Figure 11] FIG. 13 is a diagram for explaining a division step of a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The technology disclosed in this specification will be described below with reference to the drawings. For the purpose of clarity of illustration, only some of the repeated structures in the drawings are labeled with reference numerals. Below, the structures of the semiconductor wafer and semiconductor device will be described using mutually orthogonal xyz coordinates. The x-axis and y-axis extend parallel to the main surfaces of the semiconductor wafer and semiconductor device's semiconductor substrate, and the z-axis extends parallel to the thickness direction of the semiconductor wafer and semiconductor device's semiconductor substrate.

[0009] 1 is a schematic plan view showing the layout of a semiconductor wafer 2. The material of the semiconductor wafer 2 is not particularly limited, and may be, for example, silicon carbide, a nitride semiconductor, or silicon. In this example, the material of the semiconductor wafer 2 is silicon carbide. A plurality of element regions 3 are arranged in a matrix in the semiconductor wafer 2. The plurality of element regions 3 include a plurality of actual element regions 3A that are not hatched, and a plurality of test element regions 3B that are hatched (also referred to as "TEG (Test Element Group) regions").

[0010] The actual element region 3A is a region where an element structure is formed, and is a region that becomes a semiconductor device after being singulated. The element structure formed in the actual element region 3A is not particularly limited, and may be, for example, a MOSFET, an IGBT, or a diode. In this example, the element structure formed in the actual element region 3A is a MOSFET.

[0011] The test element region 3B is a region where a test pattern is formed. The test pattern of the test element region 3B is not particularly limited, but may be, for example, a test pattern for evaluating a process when forming an element structure of the actual element region 3A, or a test pattern for evaluating electrical characteristics of the element structure of the actual element region 3A. The test element region 3B is appropriately formed in the semiconductor wafer 2 according to its purpose.

[0012] The multiple element regions 3 are partitioned by scribe lines 12. The scribe lines 12 include multiple first scribe lines 12x extending in the x-axis direction and multiple second scribe lines 12y extending in the y-axis direction. Each of the multiple first scribe lines 12x extends in the y-axis direction at intervals from one another. Each of the multiple second scribe lines 12y extends in the x-axis direction at intervals from one another. The scribe lines 12 include planned division lines 4 for dividing the semiconductor wafer 2. The planned division lines 4 are imaginary lines, not lines actually marked on the semiconductor wafer 2.

[0013] FIG. 2 shows a schematic cross-sectional view including adjacent element regions 3. FIG. 2(A) is a cross-sectional view including adjacent element regions 3 in the x-axis direction, and FIG. 2(B) is a cross-sectional view including adjacent element regions 3 in the y-axis direction. The element regions 3 shown in the figure may be either actual element regions 3A or test element regions 3B. That is, the cross-sectional view of FIG. 2(A) shows a cross-sectional view including any element regions 3 adjacent in the x-axis direction in the semiconductor wafer 2, and the cross-sectional view of FIG. 2(B) shows a cross-sectional view including any element regions 3 adjacent in the y-axis direction in the semiconductor wafer 2. As shown in FIG. 2, the semiconductor wafer 2 includes a first main surface 2a and a second main surface 2b extending parallel to the xy plane and facing each other in the z-axis direction. On the first main surface 2a of the semiconductor wafer 2, a convex pattern structure 6 protruding from the first main surface 2a is provided in each of the multiple element regions 3. When the element region 3 is an actual element region 3A, the pattern structure 6 provided in the actual element region 3A is a pattern of a protective film of an insulator (polyimide in this example), metal electrodes, etc., which constitute the element structure. The pattern structure 6 provided in the actual element region 3A has a common shape among a plurality of actual element regions 3A. When the element region 3 is a test element region 3B, the pattern structure 6 provided in the test element region 3B is a pattern of a protective film of an insulator (polyimide in this example), metal electrodes, etc., formed as a test pattern.

[0014] The scribe line 12 is defined as a region between adjacent element regions 3 where no pattern structure 6 is provided. As shown in Fig. 2(A), the width of the second scribe line 12y is 2 × W2, and the width of each second scribe line 12 in the element region 3 is W2. As shown in Fig. 2(B), the width of the first scribe line 12x is 2 × W1, and the width of each first scribe line 12x in the element region 3 is W1. Note that the width W1 of the first scribe line 12x and the width W2 of the second scribe line 12y may be the same size or may be different sizes.

[0015] 3 is a schematic enlarged plan view including four element regions 3 (four actual element regions 3A in this example) of the first main surface 2a of the semiconductor wafer 2. Each of the four element regions 3 is provided with a polyimide protective film 7 shown in gray, and a plurality of aluminum electrode portions 8 surrounded by the protective film 7. The plurality of electrode portions 8 include a pair of main electrodes and a plurality of signal electrodes for inputting and outputting gate signals and sensor signals. The protective film 7 and the electrode portions 8 form a pattern structure 6.

[0016] Here, the relationship between the scribe line 12 and the pattern structure 6 will be described. FIGS. 4 and 5 show the semiconductor device 1 after being divided into individual pieces. Each of the semiconductor wafers 2 divided along the scribe line 12 is called a semiconductor substrate. As will be described in the manufacturing method described later, the semiconductor substrate of the semiconductor device 1 divided using the scribe and break method has four cleavage planes. The first side surface 3a and the second side surface 3b extend between the first main surface 2a and the second main surface 2b along the z-axis direction and face each other in the x-direction parallel to the first main surface 2a and the second main surface 2b. The third side surface 3c and the fourth side surface 3d extend between the first main surface 2a and the second main surface 2b along the z-axis direction and face each other in the y-direction parallel to the first main surface 2a and the second main surface 2b.

[0017] As shown in FIG. 4, the pattern structure located within the first predetermined distance D1 from the first side 3a along the x direction and the pattern structure located within the first predetermined distance D1 from the second side 3b along the x direction are symmetrical with respect to a line extending in the y direction. In this example, the pattern structure located within the first predetermined distance D1 is only the polyimide protective film 7. Therefore, the structure of the protective film 7 located within the first predetermined distance D1 from the first side 3a along the x direction and the structure of the protective film 7 located within the first predetermined distance D1 from the second side 3b along the x direction are symmetrical with respect to a line extending in the y direction. That is, the heights of the protective films 7 within the first predetermined distance D1 that are symmetrical with respect to the line extending in the y direction are the same. The first predetermined distance D1 is defined as twice the width W2 of the second scribe line 12y of the individualized semiconductor device 1 as shown in FIG. 2(A).

[0018] As shown in FIG. 5, the pattern structure located within the second predetermined distance D2 from the third side 3c along the y direction and the pattern structure located within the second predetermined distance D2 from the fourth side 3d along the y direction are symmetrical with respect to a line extending in the x direction. In this example, the pattern structure located within the second predetermined distance D2 is only the polyimide protective film 7. Therefore, the structure of the protective film 7 located within the second predetermined distance D2 from the third side 3c along the y direction and the structure of the protective film 7 located within the second predetermined distance D2 from the fourth side 3d along the y direction are symmetrical with respect to a line extending in the x direction. That is, the heights of the protective films 7 within the second predetermined distance D2, which are symmetrical with respect to a line extending in the x direction, are the same. The second predetermined distance D2 is defined as twice the width W1 of the first scribe line 12x, as shown in FIG. 2(B).

[0019] The pattern structures 6 of the multiple real element regions 3A in the semiconductor wafer 2 have a common shape. Therefore, when the above relationship is established, the pattern structures 6 that face each other across the scribe line 12 between the adjacent real element regions 3A in the semiconductor wafer 2 are symmetrical with respect to the planned dividing line 4. The pattern structure of the test element region 3B may have a common shape with the pattern structure of the real element region 3A within the predetermined distances D1 and D2. In this case, when the above relationship is established, the pattern structures 6 that face each other across the scribe line 12 between the adjacent real element regions 3A and test element regions 3B in the semiconductor wafer 2 are symmetrical with respect to the planned dividing line 4. As described below, when the above relationship is established, the effect of suppressing chipping when the semiconductor wafer 2 is divided into individual pieces is obtained.

[0020] (Method of manufacturing a semiconductor device) In the method for manufacturing a semiconductor device disclosed in this specification, an element structure including a pattern structure 6 is formed in each of element regions 3 in a semiconductor wafer 2, and then the semiconductor wafer 2 is divided into individual pieces using a scribe-and-break method to manufacture semiconductor devices 1. The scribe-and-break method will be described below with reference to the drawings.

[0021] (Protective tape application process and crack formation process) As shown in FIG. 6, in the protective tape attachment step, a protective tape 14 is attached to the first main surface 2a side of the semiconductor wafer 2. The protective tape 14 is attached so as to span the surface of the pattern structure 6 formed in each of the multiple element regions 3 in the semiconductor wafer 2. The material of the protective tape 14 is not particularly limited, and may be, for example, a resin. Next, the semiconductor wafer 2 is placed on a stage 16 with the surface of the semiconductor wafer 2 to which the protective tape 14 is attached facing down. The stage 16 has a vacuum suction device (not shown), which can suction the semiconductor wafer 2 and fix it to the stage 16.

[0022] Next, as shown in FIG. 7, in the crack formation step, a groove accompanied by a crack 5 is formed in the semiconductor wafer 2 by pressing a scribing wheel 18 against the second main surface 2b of the semiconductor wafer 2. A metal electrode (not shown) may be formed on the entire surface of the second main surface 2b of the semiconductor wafer 2. In this case, the scribing wheel 18 is pressed against the second main surface 2b of the semiconductor wafer 2 via the metal electrode. The scribing wheel 18 is a disk-shaped member, and is rotatably supported by a support device (not shown). In the crack formation step, the scribing wheel 18 is moved along the planned division line 4 while being pressed against the second main surface 2b of the semiconductor wafer 2. The scribing wheel 18 rolls on the second main surface 2b of the semiconductor wafer 2 like a tire rolling on a road surface. The scribing wheel 18 is an example of a "pressing member."

[0023] When the second main surface 2b of the semiconductor wafer 2 is pressed by the scribing wheel 18, compressive stress is generated in a surface region of the second main surface 2b of the semiconductor wafer 2. A groove is formed at the location pressed by the scribing wheel 18, while tensile stress is generated inside the semiconductor wafer 2 directly below the region where the compressive stress is generated. The tensile stress is generated in a direction away from the planned division line 4 along the second main surface 2b of the semiconductor wafer 2 directly below the region where the compressive stress is generated. This tensile stress forms a crack 5 inside the semiconductor wafer 2, extending in the thickness direction of the semiconductor wafer 2. The crack 5 is formed near the surface of the second main surface 2b of the semiconductor wafer 2.

[0024] (splitting process) Next, a dividing step shown in Figs. 8 to 10 is performed. In Figs. 8 to 10, the semiconductor wafer 2 is again drawn with the first main surface 2a side facing up. In the dividing step, the break bar 22 is pressed along the dividing lines 4, and the semiconductor wafer 2 is divided along the dividing lines 4. Here, first, as shown in Fig. 8, the semiconductor wafer 2 is placed on two support tables 24. The two support tables 24 are arranged with a gap between them. When the semiconductor wafer 2 is placed on the support table 24, the semiconductor wafer 2 is placed so that the gap is located below the position to be divided (the position where the break bar 22 is pressed). Thereafter, as shown in Fig. 9, the break bar 22 is pressed against the first main surface 2a of the semiconductor wafer 2 via the protective tape 14. The break bar 22 is an example of a "dividing member".

[0025] Since there is no support 24 below the break bar 22, when the break bar 22 is pressed against the first main surface 2a of the semiconductor wafer 2 via the protective tape 14, the semiconductor wafer 2 is bent so as to enter the gap between the two support stands 24. Here, the crack 5 is formed on the second main surface 2b side of the semiconductor wafer 2. Therefore, when the break bar 22 is pressed against the semiconductor wafer 2 from the first main surface 2a side, the semiconductor wafer 2 is bent with the pressed part (line) as an axis, and a force is applied to the second main surface 2b side of the semiconductor wafer 2 in a direction that separates the two element regions 3 adjacent to the split position against the crack 5. Also, as described above, tensile stress is applied around the crack 5. Therefore, when the break bar 22 is pressed against the first main surface 2a, the crack 5 extends in the thickness direction of the semiconductor wafer 2, and the semiconductor wafer 2 is cleaved along the crystal plane starting from the crack 5. As a result, the semiconductor wafer 2 is split. In the dividing step, the above-mentioned step of pressing the break bar 22 against the first main surface 2a of the semiconductor wafer 2 is repeatedly performed along each of the planned dividing lines 4. This allows the semiconductor wafer 2 to be divided along the boundaries of each element region 3. As a result, the semiconductor wafer 2 is divided into a plurality of semiconductor devices 1 as shown in FIG.

[0026] As described above, the semiconductor device 1 is manufactured by forming the cracks 5 with the scribing wheel 18 and dividing the semiconductor wafer 2 with the break bar 22. Since the semiconductor wafer 2 is divided by cleavage starting from the cracks 5 rather than by cutting (dicing), this method is also useful for relatively hard silicon carbide. Furthermore, the scribe-and-break method can narrow the scribe lines 12x, 12y, which allows the number of pieces per semiconductor wafer 2 to be increased, thereby reducing manufacturing costs.

[0027] Here, referring to FIG. 11, a dividing process of a comparative example will be described. This comparative example is an example in which the pattern structures 6 formed on the first main surface 2a of adjacent element regions 3 are not symmetrical. Specifically, the maximum height of the pattern structure 6 within a predetermined distance (see D1 and D2 in FIG. 2) from the planned dividing line 4 is lower in the element region 3 on the right side of the figure than in the element region 3 on the left side of the figure (in this example, in the element region 3 on the right side of the figure, no pattern structure is formed within a predetermined distance from the planned dividing line 4, and the height of the pattern structure 6 is "0"). As shown in FIG. 11, in the comparative example in which the pattern structure 6 is asymmetrical, when the break bar 22 is pressed against the first main surface 2a of the semiconductor wafer 2 via the protective tape 14, a difference occurs in the load applied to each of the adjacent element regions 3. A relatively large load is applied to the element region 3 with a higher maximum height of the pattern structure 6 within a predetermined distance from the planned dividing line 4. Such a load difference may cause chipping in the element region 3 with a higher maximum height of the pattern structure 6.

[0028] As shown in FIG. 2, in this embodiment, in adjacent element regions 3, pattern structures 6 within a predetermined distance D1, D2 from the planned division line 4 are configured symmetrically with respect to the planned division line 4. Therefore, as shown in FIG. 9, when the break bar 22 is pressed against the first main surface 2a of the semiconductor wafer 2 via the protective tape 14, an equal load is applied to each of the adjacent element regions 3. As a result, the occurrence of chipping is suppressed in the division process of this embodiment. In this embodiment, the size of the predetermined distance D1 is twice the width W2 of the corresponding second scribe line 12y, and the size of the predetermined distance D2 is twice the width W1 of the corresponding first scribe line 12x. If the pattern structures 6 within the predetermined distances D1, D2, which are twice the scribe line widths W1, W2, are symmetrical, the load difference becomes sufficiently small, and the occurrence of chipping can be suppressed. The range of the element region 3 to which the load is applied by the break bar 22 depends on the radius of curvature of the tip of the break bar 22, the thickness of the protective tape 14, and the amount of pressing of the break bar 22 into the protective tape 14. Therefore, the predetermined distances D1 and D2 may be "the radius of curvature of the tip of the break bar 22" + "the thickness of the protective tape 14" - "the amount of pressing of the break bar 22 into the protective tape 14."

[0029] Other features of the technology disclosed in this specification will be summarized below.

[0030] In the manufacturing method disclosed in the present specification, a crack forming step is performed before the dividing step, in which grooves and cracks 5 are formed in the semiconductor wafer 2 by pressing a scribing wheel 18 against the second main surface 2b of the semiconductor wafer 2. The stress generated inside the semiconductor wafer 2 when forming the grooves and cracks 5 in the semiconductor wafer 2 remains as residual stress even after the semiconductor wafer 2 is divided. Therefore, in the semiconductor device 1 manufactured by the manufacturing method disclosed in the present specification, the residual stress in the second main surface 2b of the semiconductor substrate 2 is higher than the residual stress in the first main surface 2a. Even if such residual stress exists on the second main surface 2b of the semiconductor substrate 2, the effect on the electrical characteristics of the semiconductor device 1 is small. Instead of forming the fragile parts including the grooves and cracks 5 using the scribing wheel 18, the fragile parts may be formed by, for example, laser irradiation.

[0031] The pattern structure 6 in the real element region 3A is different from the pattern structure 6 in the test element region 3B. Therefore, in the conventional structure, the pattern structure 6 within the predetermined distance D1, D2 in the real element region 3A is different from the pattern structure 6 within the predetermined distance D1, D2 in the test element region 3B, and the pattern structure 6 within the predetermined distance D1, D2 between the adjacent real element region 3A and the test element region 3B is asymmetric. In the technology disclosed in this specification, the pattern structure 6 within the predetermined distance D1, D2 in the test element region 3B is designed to be the same as the pattern structure 6 within the predetermined distance D1, D2 in the real element region 3A. As a result, the pattern structure 6 within the predetermined distance D1, D2 between the adjacent real element region 3A and the test element region 3B is symmetric, and the occurrence of chipping is suppressed. Note that the maximum height of the pattern structure 6 within the predetermined distance D1, D2 in the test element region 3B may be higher than the maximum height of the pattern structure 6 within the predetermined distance D1, D2 in the real element region 3A adjacent to the test element region 3B. In this case, chipping occurs preferentially in the test element region 3B, so that chipping occurring in the actual element region 3A can be suppressed.

[0032] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness alone or in various combinations.

[0033] (Feature 1) A semiconductor device (1), a semiconductor substrate (2) having a first main surface (2a), a second main surface (2b) opposite to the first main surface, and side surfaces (3a, 3b, 3c, 3d) extending between the first main surface and the second main surface, the side surfaces including a first side surface (3a) and a second side surface (3b) opposite to each other in a first direction parallel to the first main surface and the second main surface, and a third side surface (3c) and a fourth side surface (3d) opposite to each other in a second direction parallel to the first main surface and the second main surface and perpendicular to the first direction, the side surfaces being cleavage planes; a convex pattern structure (6) provided on the first main surface of the semiconductor substrate, the pattern structure within a first predetermined distance (D1) from the first side along the first direction and the pattern structure within the first predetermined distance from the second side along the first direction are symmetrical with respect to a line extending in the second direction, A semiconductor device, wherein the pattern structure within a second predetermined distance (D2) from the third side along the second direction and the pattern structure within the second predetermined distance from the fourth side along the second direction are symmetrical with respect to a line extending in the first direction.

[0034] (Feature 2) the first predetermined distance is twice a scribe line width (W2) measured from the side to the pattern structure along the first direction; 2. The semiconductor device according to feature 1, wherein the second predetermined distance is twice a scribe line width (W1) measured from the side to the pattern structure along the second direction.

[0035] (Feature 3) 3. The semiconductor device according to feature 1 or 2, wherein the second main surface of the semiconductor substrate has a higher residual stress than the first main surface.

[0036] (Feature 4) 4. The semiconductor device according to any one of features 1 to 3, wherein the pattern structure within the first predetermined distance and the second predetermined distance is a protective film (7).

[0037] (Feature 5) 5. The semiconductor device according to any one of Features 1 to 4, wherein the material of the semiconductor substrate is silicon carbide.

[0038] (Feature 6) A method for manufacturing a semiconductor device (1), comprising the steps of: a pattern structure forming step of forming a convex pattern structure (6) on a first main surface of a semiconductor wafer (2) having a first main surface (2a) and a second main surface (2b), the pattern structure being formed in each of a plurality of element regions (3) arranged in a matrix in the semiconductor wafer; a dividing step of dividing the semiconductor wafer along a plurality of first scribe lines (12x) extending in a first direction parallel to the first main surface and the second main surface and a plurality of second scribe lines (12y) extending in a second direction parallel to the first main surface and the second main surface and perpendicular to the first direction, the dividing step being performed by pressing a dividing member (22) against the plurality of first scribe lines and the plurality of second scribe lines to divide the semiconductor wafer, thereby forming a plurality of individual semiconductor devices; It is equipped with Each of the plurality of individual semiconductor devices comprises a semiconductor substrate having side surfaces (3a, 3b, 3c, 3d) extending between the first main surface and the second main surface, the side surfaces including a first side surface (3a) and a second side surface (3b) opposed to each other in the first direction, and a third side surface (3c) and a fourth side surface (3d) opposed to each other in the second direction; the pattern structure within a first predetermined distance (D1) from the first side along the first direction and the pattern structure within the first predetermined distance from the second side along the first direction are symmetrical with respect to a line extending in the second direction, A method for manufacturing a semiconductor device, wherein the pattern structure within a second predetermined distance (D2) from the third side along the second direction and the pattern structure within the second predetermined distance from the fourth side along the second direction are symmetrical with respect to a line extending in the first direction.

[0039] (Feature 7) the first predetermined distance is twice a scribe line width (W2) measured from the side to the pattern structure along the first direction; 7. The method of claim 6, wherein the second predetermined distance is twice a scribe line width (W1) measured from the side to the pattern structure along the second direction.

[0040] (Feature 8) The method for manufacturing a semiconductor device according to feature 6 or 7, further comprising, prior to the dividing step, a crack forming step of forming cracks (5) in the semiconductor wafer by pressing a pressing member (18) against each of the plurality of first scribe lines and the plurality of second scribe lines on the second main surface of the semiconductor wafer.

[0041] (Feature 9) 9. The method for manufacturing a semiconductor device according to any one of features 6 to 8, further comprising a bonding step of bonding a protective tape to the first main surface side of the semiconductor wafer prior to the dividing step.

[0042] (Feature 10) 10. The method for manufacturing a semiconductor device according to any one of features 6 to 9, wherein the pattern structure within the first predetermined distance and the second predetermined distance is a protective film (7).

[0043] (Feature 11) 11. The method for producing a semiconductor device according to any one of Features 6 to 10, wherein a material of the semiconductor wafer is silicon carbide.

[0044] (Feature 12) The plurality of element regions in the semiconductor wafer include an actual element region (3A) and a test element region (3B); 12. The method for manufacturing a semiconductor device according to any one of features 6 to 11, wherein a height of the pattern structure within the first predetermined distance and the second predetermined distance of the test element region is the same as or higher than a height of the pattern structure within the first predetermined distance and the second predetermined distance of the actual element region adjacent to the test element region.

[0045] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0046] 1: semiconductor device, 2: semiconductor substrate, semiconductor wafer, 3: element region, 4: planned division line, 6: pattern structure, 12x: first scribe line, 12y: second scribe line, D1: first predetermined distance, D2: second predetermined distance, W1, W2: scribe line width

Claims

1. A semiconductor device (1), A semiconductor substrate (2) having a first main surface (2a), a second main surface (2b) opposite to the first main surface, and side surfaces (3a, 3b, 3c, 3d) extending between the first main surface and the second main surface, the side surfaces including a first side surface (3a) and a second side surface (3b) opposite to each other in a first direction parallel to the first main surface and the second main surface, and a third side surface (3c) and a fourth side surface (3d) opposite to each other in a second direction parallel to the first main surface and the second main surface and perpendicular to the first direction, the side surfaces being cleavage planes; A convex pattern structure (6) provided on the first main surface of the semiconductor substrate; It is equipped with the pattern structure within a first predetermined distance (D1) from the first side along the first direction and the pattern structure within the first predetermined distance from the second side along the first direction are symmetrical with respect to a line extending in the second direction, A semiconductor device, wherein the pattern structure within a second predetermined distance (D2) from the third side along the second direction and the pattern structure within the second predetermined distance from the fourth side along the second direction are symmetrical with respect to a line extending in the first direction.

2. the first predetermined distance is twice a scribe line width (W2) measured from the side to the pattern structure along the first direction; 2. The semiconductor device of claim 1, wherein the second predetermined distance is twice a scribe line width (W1) measured from the side to the pattern structure along the second direction.

3. The semiconductor device according to claim 1 , wherein the second main surface of the semiconductor substrate has a higher residual stress than the first main surface.

4. 2. The semiconductor device according to claim 1, wherein the pattern structure within the first predetermined distance and the second predetermined distance is a protective film (7).

5. 5. The semiconductor device according to claim 1, wherein the material of the semiconductor substrate is silicon carbide.

6. A method for manufacturing a semiconductor device (1), comprising the steps of: a pattern structure forming step of forming a convex pattern structure (6) on a first main surface of a semiconductor wafer (2) having a first main surface (2a) and a second main surface (2b), the pattern structure being formed in each of a plurality of element regions (3) arranged in a matrix in the semiconductor wafer; a dividing step of dividing the semiconductor wafer along a plurality of first scribe lines (12x) extending in a first direction parallel to the first main surface and the second main surface and a plurality of second scribe lines (12y) extending in a second direction parallel to the first main surface and the second main surface and perpendicular to the first direction, the dividing step being performed by pressing a dividing member (22) against the plurality of first scribe lines and the plurality of second scribe lines to divide the semiconductor wafer, thereby forming a plurality of individual semiconductor devices; It is equipped with Each of the plurality of individual semiconductor devices comprises a semiconductor substrate having side surfaces (3a, 3b, 3c, 3d) extending between the first main surface and the second main surface, the side surfaces including a first side surface (3a) and a second side surface (3b) opposed to each other in the first direction, and a third side surface (3c) and a fourth side surface (3d) opposed to each other in the second direction; the pattern structure within a first predetermined distance (D1) from the first side along the first direction and the pattern structure within the first predetermined distance from the second side along the first direction are symmetrical with respect to a line extending in the second direction, A method for manufacturing a semiconductor device, wherein the pattern structure within a second predetermined distance (D2) from the third side along the second direction and the pattern structure within the second predetermined distance from the fourth side along the second direction are symmetrical with respect to a line extending in the first direction.

7. the first predetermined distance is twice a scribe line width (W2) measured from the side to the pattern structure along the first direction; 7. The method of claim 6, wherein the second predetermined distance is twice a scribe line width (W1) measured from the side to the pattern structure along the second direction.

8. 7. The method for manufacturing a semiconductor device according to claim 6, further comprising, prior to the dividing step, a crack forming step of forming cracks (5) in the semiconductor wafer by pressing a pressing member (18) against each of the plurality of first scribe lines and the plurality of second scribe lines on the second main surface of the semiconductor wafer.

9. 7. The method for manufacturing a semiconductor device according to claim 6, further comprising a step of attaching a protective tape to said first main surface side of said semiconductor wafer before said dividing step.

10. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the pattern structure within the first and second predetermined distances is a protective film (7).

11. The method for manufacturing a semiconductor device according to claim 6 , wherein the material of the semiconductor wafer is silicon carbide.

12. The plurality of element regions in the semiconductor wafer include an actual element region (3A) and a test element region (3B), A method for manufacturing a semiconductor device according to any one of claims 6 to 11, wherein a height of the pattern structure within the first predetermined distance and the second predetermined distance of the test element region is the same as or higher than a height of the pattern structure within the first predetermined distance and the second predetermined distance of the actual element region adjacent to the test element region.

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