Operational amplifier and semiconductor device

Abstract

To provide an operational amplifier capable of appropriately controlling an idling current of an output circuit, and a semiconductor device.SOLUTION: Operational amplifiers 1 and 2 comprise: input circuits 10 and 20 including PMOS input differential pairs 100 and 200, to which a first input voltage and a second input voltage are inputted, and NMOS input differential pairs 102 and 202, to which the first input voltage and the second input voltage are inputted, and configured to switch input differential pairs to be operated between the PMOS input differential pairs 100 and 200 and the NMOS input differential pairs 102 and 202; current generation circuits 140, 240 and 300 each for generating a reference current; and output circuits 16 and 28 in which an idling current which is increased in response to an increase of the reference current flows and by which output voltages corresponding to output signals of the PMOS input differential pairs and the NMOS input differential pairs are generated. In a case where a reduction condition of the idling current is satisfied, the current generation circuits 140, 240 and 300 are configured to make the reference current larger than that in a case where the reduction condition is not satisfied.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to an operational amplifier and a semiconductor device. [Background technology]

[0002] An operational amplifier is used to amplify the difference between two input voltages. Patent Document 1 describes an operational amplifier that includes a PMOS input differential pair composed of P-channel MOS (Metal Oxide Semiconductor) transistors, an NMOS input differential pair composed of N-channel MOS transistors, and an output stage. This operational amplifier outputs an output voltage from the output stage according to two input voltages input to the PMOS input differential pair and the NMOS input differential pair. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-132357 A

[0004] [overview] However, the inventors have come to recognize the following problem: An idling current for stabilizing the output voltage flows through the output stage of the operational amplifier. If this idling current decreases, the output voltage may not be sufficiently stabilized.

[0005] The present disclosure has been made in light of the above circumstances, and one of its exemplary objectives is to provide an operational amplifier and a semiconductor device capable of appropriately adjusting the idling current of an output circuit.

[0006] An embodiment of the present disclosure is an operational amplifier. The operational amplifier includes an input circuit including a PMOS input differential pair to which a first input voltage and a second input voltage are input, and an NMOS input differential pair to which the first input voltage and the second input voltage are input, and configured so that an operating input differential pair can be switched between the PMOS input differential pair and the NMOS input differential pair, a current generating circuit that generates a reference current, and an output circuit through which an idling current that increases with an increase in the reference current flows and which generates an output voltage according to the output signals of the PMOS input differential pair and the NMOS input differential pair. The current generating circuit is configured so that the reference current is larger when a condition for lowering the idling current is satisfied than when the condition for lowering the idling current is not satisfied.

[0007] Another aspect of the present disclosure is a semiconductor device including the operational amplifier described above.

[0008] Any combination of the above components and conversion of the expressions of the present disclosure between methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of an operational amplifier according to one embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic circuit diagram of an operational amplifier according to the reference technology. [Diagram 3] FIG. 3 is a schematic circuit diagram of an operational amplifier according to one embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram showing the results of simulating the frequency characteristics of the operational amplifier according to this embodiment and the operational amplifier according to the reference technique. [Diagram 5] FIG. 5 is a diagram showing the results of simulating the frequency characteristics of the operational amplifier according to this embodiment and the operational amplifier according to the reference technique. [Figure 6] FIG. 6 is a block diagram of an operational amplifier according to the second embodiment. [Figure 7]FIG. 7 is a circuit diagram of an input circuit and a current generating circuit according to the second embodiment. [Figure 8] FIG. 8 is a circuit diagram of a current generating circuit, a control circuit, and an output circuit according to the second embodiment. [Figure 9] FIG. 9 is a circuit diagram of a current generating circuit, a control circuit, and an output circuit according to the third embodiment. [Figure 10] FIG. 10 is a block diagram of a gain stage according to the fourth embodiment. [Figure 11] FIG. 11(a) is a circuit diagram of a first current generating circuit according to the fourth embodiment, and FIG. 11(b) is a circuit diagram of a second current generating circuit according to the fourth embodiment. [Figure 12] FIG. 12 is a circuit diagram of a control circuit and an output circuit according to the fourth embodiment.

[0010] [Detailed Description] (overview) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be a comprehensive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0011] According to one embodiment, an operational amplifier includes an input circuit including a PMOS input differential pair to which a first input voltage and a second input voltage are input, and an NMOS input differential pair to which the first input voltage and the second input voltage are input, the input circuit being configured to be switchable between the PMOS input differential pair and the NMOS input differential pair as an operating input differential pair, a current generating circuit that generates a reference current, and an output circuit through which an idling current that increases with an increase in the reference current flows and that generates an output voltage according to the output signals of the PMOS input differential pair and the NMOS input differential pair. The current generating circuit is configured so that when a condition for lowering the idling current is satisfied, the reference current is larger than when the condition for lowering the idling current is not satisfied.

[0012] According to this configuration, when the idling current decreases, the reference current can be increased. Since the idling current increases in response to an increase in the reference current, the idling current can be appropriately adjusted.

[0013] In one embodiment, the lowering condition may be that the common voltage of the first input voltage and the second input voltage is higher than a predetermined voltage. Since the common voltage can be used in conjunction with other applications (such as switching an operating input differential pair in an input circuit), the operational amplifier can be realized with a simpler configuration.

[0014] In one embodiment, the input circuit may be configured such that the input differential pair to be operated is switched depending on the common voltage of the first input voltage and the second input voltage. The lowering condition may be that the common voltage is at a voltage at which the NMOS input differential pair is operated. This allows the operational amplifier to be realized with a simpler configuration.

[0015] In one embodiment, the input circuit may further include a tail current source that supplies a current for operating the PMOS input differential pair and the NMOS input differential pair. The current generating circuit may include a reference current source that supplies a first reference current, and may be configured such that when the PMOS input differential pair is operating, the reference current is the first reference current, and when the NMOS input differential pair is operating, the reference current is a current obtained by adding the first reference current to the second reference current. The second reference current may be a current obtained by copying the current supplied by the tail current source using a current mirror circuit.

[0016] In one embodiment, the output circuit may be configured with a first output transistor configured with a P-channel MOS transistor and a second output transistor configured with an N-channel MOS transistor, connected in a push-pull configuration. The current generating circuit may further include a first reference transistor configured with a P-channel MOS transistor through which a reference current flows, and a second reference transistor configured with an N-channel MOS transistor through which a reference current flows. The first output transistor, the second output transistor, the first reference transistor, and the second reference transistor may be provided such that a gate-source voltage of the first output transistor is equal to a gate-source voltage of the first reference transistor, and a gate-source voltage of the second output transistor is equal to a gate-source voltage of the second reference transistor.

[0017] A semiconductor device according to one embodiment includes the above operational amplifier.

[0018] According to this configuration, when the idling current decreases, the reference current can be increased. Since the idling current increases in response to an increase in the reference current, the idling current can be appropriately adjusted.

[0019] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0020] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0021] Similarly, "a state in which component C is connected (provided) between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0022] (First embodiment) 1 is a block diagram of an operational amplifier 1 according to an embodiment of the present disclosure. The operational amplifier 1 amplifies the difference between a first input voltage V+ and a second input voltage V- to generate an output voltage Vout1. The operational amplifier 1 according to this embodiment can be mounted on various semiconductor devices (such as a semiconductor integrated circuit).

[0023] The operational amplifier 1 according to the present embodiment includes an input circuit 10, a switching circuit 12, a gain stage 14, an output circuit 16, a non-inverting input terminal INP, an inverting input terminal INN, a first power supply terminal VDD, a second power supply terminal VSS, and an output terminal OUT.

[0024] A first input voltage V+ is input to the non-inverting input terminal INP, and a second input voltage V- is input to the inverting input terminal INN. The first input voltage V+ and the second input voltage V- are supplied to the input circuit 10 and the switching circuit 12. An upper power supply voltage Vdd is input to the first power supply terminal VDD. A lower power supply voltage Vss (ground voltage, etc.) is input to the second power supply terminal VNN (for example, a ground terminal, etc.). The upper power supply voltage Vdd and the lower power supply voltage Vss are supplied to the input circuit 10, the gain stage 14, and the output circuit 16. The difference between the first input voltage V+ and the second input voltage V- is amplified via the input circuit 10, the gain stage 14, and the output circuit 16, and an output voltage Vout1 is output from the output terminal OUT.

[0025] The switching circuit 12 detects a common voltage (hereinafter also referred to as an "input common voltage") between the first input voltage V+ and the second input voltage V-. The switching circuit 12 according to this embodiment generates enable signals EN1 and EN2 in response to the detection result of the input common voltage, and controls the operations of the input circuit 10 and the gain stage 14. The operation of the switching circuit 12 will be described in detail later with reference to FIG. 3.

[0026] Before describing the details of the operational amplifier 1 according to this embodiment, an operational amplifier according to the reference technology will be described. Fig. 2 is a schematic circuit diagram of an operational amplifier 9 according to the reference technology. In the operational amplifier 9 according to the reference technology, the switching circuit 12 and the gain stage 14 of the operational amplifier 1 according to this embodiment are replaced with a switching circuit 92 and a gain stage 94 according to the reference technology, respectively. In Fig. 2, the same reference symbols are used for configurations that are substantially the same as those shown in Fig. 1.

[0027] The input circuit 10 has a PMOS input differential pair 100, an NMOS input differential pair 102, a first tail current source 104, and a second tail current source 106. The input circuit 10 is configured so that the operating input differential pair can be switched between the PMOS input differential pair 100 and the NMOS input differential pair 102.

[0028] The PMOS input differential pair 100 has transistors MP1 and MP2, each of which is a P-channel MOS transistor. The sources of the transistors MP1 and MP2 are connected to each other, and the gate of the transistor MP2 is connected to the non-inverting input terminal INP. The drains of the transistors MP1 and MP2 are connected to the gain stage 94, and an output signal of the PMOS input differential pair 100 is input to the gain stage 94. The first tail current source 104 is supplied with a power supply voltage Vdd and is provided so as to be able to supply a tail current Itp1 to the sources of the transistors MP1 and MP2.

[0029] The NMOS input differential pair 102 has transistors MN1 and MN2, each of which is an N-channel MOS transistor. The sources of the transistors MN1 and MN2 are connected to each other. The drains of the transistors MN1 and MN2 are connected to the gain stage 94, and the output signal of the NMOS input differential pair 102 is input to the gain stage 94. The gate of the transistor MN1 is connected to the non-inverting input terminal INP, and the gate of the transistor MN2 is connected to the inverting input terminal INN in common with the gate of the transistor MP1. The second tail current source 106 is supplied with the lower power supply voltage Vss and is provided so as to be able to supply a tail current Itn1 to the sources of the transistors MN1 and MN2.

[0030] The switching circuit 92 is configured to switch the operating input differential pair between a PMOS input differential pair 100 and an NMOS input differential pair 102 according to the input common voltages of the first input voltage V+ and the second input voltage V-. The switching circuit 92 controls the on / off of the first tail current source 104 and the second tail current source 106 by inputting an inverted signal of an enable signal EN9 to the first tail current source 104 and inputting the enable signal EN9 to the second tail current source 106.

[0031] For example, when the input common voltage is equal to or lower than a predetermined voltage, the switching circuit 92 generates an enable signal EN9 so that the first tail current source 104 is turned on and the second tail current source 106 is turned off. As a result, the first tail current source 104 supplies a tail current Itp1 to the PMOS input differential pair 100, and the PMOS input differential pair 100 operates. When the input common voltage is higher than a predetermined voltage, the switching circuit 92 generates an enable signal EN9 so that the first tail current source 104 is turned off and the second tail current source 106 is turned on. As a result, the second tail current source 106 supplies a tail current Itn1 to the NMOS input differential pair 102, and the NMOS input differential pair 102 operates. In this way, the operating input differential pair is switched between the PMOS input differential pair 100 and the NMOS input differential pair 102 according to the input common voltage.

[0032] The gain stage 94 controls the operation of the output circuit 16 in response to the output signal of the input circuit 10. The gain stage 94 is also configured to perform class AB output control and control the idling current flowing through the output circuit 16, and specifically, generates a reference current Iref9 for the idling current Iid9 flowing through the output circuit 16. The function of generating the reference current Iref9 is realized by a current generating circuit 940 included in the gain stage 94. The current generating circuit 940 includes a reference current source 902, which generates the reference current Iref9.

[0033] The output circuit 16 generates an output voltage Vout1 according to the output signals of the PMOS input differential pair 100 and the NMOS input differential pair 102. The output voltage Vout1 swings around the output common voltage. The output circuit 16 has a first output transistor MP3 configured with a P-channel MOS transistor and a second output transistor MN3 configured with an N-channel MOS transistor.

[0034] The first output transistor MP3 and the second output transistor MN3 are push-pull connected. Specifically, the first output transistor MP3 is provided such that its source is connected to the first power supply terminal VDD, its gate is connected to the current generating circuit 940, and its drain is connected to the drain of the second output transistor MN3. The second output transistor MN3 is provided such that its source is connected to the second power supply terminal VSS, its gate is connected to the current generating circuit 940, and its drain is connected to the output terminal OUT. The operations of the first output transistor MP3 and the second output transistor MN3 correspond to the output signal of the input circuit 10 and are controlled by the current generating circuit 940.

[0035] When the output voltage Vout1 is higher than the upper threshold voltage, the first output transistor MP3 operates, and when the output voltage Vout1 is lower than the lower threshold voltage, the second output transistor MN3 operates. When the output voltage Vout1 is equal to or lower than the upper threshold voltage and equal to or higher than the lower threshold voltage, both the first output transistor MP3 and the second output transistor MN3 operate.

[0036] An idling current Iid9 that increases with an increase in the reference current Iref9 flows through the output circuit 16. Specifically, the idling current Iid9 flows through the first output transistor MP3 and the second output transistor MN3. The output circuit 16 and the gain stage 94 are configured such that, when the source-drain voltage VdsP1 of the first output transistor MP3 is sufficiently high (saturation region), a current that is N (a value greater than N:1) times the reference current Iref9 flows through the first output transistor MP3 as the idling current Iid1. Also, the output circuit 16 and the gain stage 94 are configured such that, when the source-drain voltage VdsN1 of the second output transistor MN3 is sufficiently high (saturation region), a current that is N times the reference current Iref9 flows through the second output transistor MN3 as the idling current Iid1.

[0037] When the input common voltage increases, the output common voltage also increases. In particular, when the NMOS input differential pair 102 is operating, the input common voltage and the output common voltage are higher than when the PMOS input differential pair 100 is operating, and the source-drain voltage VdsP9 of the first output transistor MP3 becomes lower. At this time, the idling current Iid9 may be smaller than N times the reference current Iref9 (Iid9 < Iref9 × N). Therefore, in the operational amplifier 9 according to the related art, when the input common voltage is high to such an extent that the NMOS input differential pair 102 operates, a sufficient idling current Iid9 may not flow, and the stability of the output voltage Vout1 may decrease.

[0038] Also, when the PMOS input differential pair 100 is operating, the output common voltage is lower than when the NMOS input differential pair 102 is operating. At this time, when the source-drain voltage VdsN1 of the second output transistor MN3 decreases in response to the decrease in the output common voltage, the idling current Iid9 may become lower than N times the reference current Iref9. However, generally, an N-channel MOS transistor is less affected by a decrease in the source-drain voltage on the drain current than a P-channel MOS transistor. For this reason, the influence of the decrease in the output common voltage on the idling current Iid9 is smaller than the influence of the increase in the output common voltage on the idling current Iid9.

[0039] FIG. 3 is a schematic circuit diagram of the operational amplifier 1 according to the present embodiment. In FIG. 3, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0040] The gain stage 14 according to the present embodiment controls the operation of the output circuit 16 in response to the output signal of the input circuit 10. The gain stage 14 is configured to perform AB-class output control and control the idling current Iid1 flowing through the output circuit 16. Specifically, a reference current Iref for the idling current Iid1 flowing through the output circuit 16 is generated. The function of generating the reference current Iref is realized by a current generation circuit 140 included in the gain stage 14.

[0041] The current generating circuit 140 generates the reference current Iref, and is configured so that when the condition for lowering the idling current Iid1 is satisfied, the reference current Iref is larger than when the condition for lowering the idling current Iid1 is not satisfied. The condition for lowering the idling current Iid1 is that the idling current Iid1 has lowered to a certain degree (for example, to 90%, 80%, 70% of the desired current) from a desired current (for example, a current N times the reference current Iref), or that a parameter related to the idling current Iid1 has changed so that the idling current Iid1 is lowered to a certain degree from the desired current. The parameter related to the idling current Iid1 is, for example, an input common voltage, an output common voltage, a source-drain voltage VdsP1 of the first output transistor MP3, and a source-drain voltage VdsN1 of the second output transistor MN3. In this embodiment, the condition for lowering the idling current Iid1 is that the input common voltages of the first input voltage V+ and the second input voltage V- are higher than a predetermined voltage. In this embodiment, when this drop condition is met, the NMOS input differential pair 102 operates.

[0042] The current generating circuit 140 according to this embodiment includes a first reference current source 142, a second reference current source 144, and a switch 146. The first reference current source 142 and the second reference current source 144 are connected in parallel, and the second reference current source 144 and the switch 146 are connected in series. The current generating circuit 140 is configured such that, when the switch 146 is off, the first reference current Iref1 supplied by the first reference current source 142 becomes the reference current Iref (Iref=Iref1). Furthermore, when the switch 146 is on, the current generating circuit 140 is configured such that the current obtained by adding the second reference current IrefN1 supplied by the second reference current source 144 to the first reference current Iref1 becomes the reference current Iref (Iref=Iref1+IrefN1).

[0043] The switching circuit 12 can use the enable signal EN1 to switch the input differential pair operating in the input circuit 10 in the same manner as the switching circuit 92 according to the reference technology. The switching circuit 12 uses the enable signal EN2 to control the on / off of the switch 146.

[0044] The switching circuit 12 according to this embodiment can control the on / off of the switch 146 according to the input common voltage. Specifically, when the input common voltage is at a voltage at which the PMOS input differential pair 100 operates, the switching circuit 12 turns off the switch 146. Also, when the input common voltage is at a voltage at which the NMOS input differential pair 102 operates, the switching circuit 12 turns on the switch 146.

[0045] The switching circuit 12 can switch the switch 146 on and off when switching the input differential pair operating in the input circuit 10. For example, when switching the operating input differential pair from the PMOS input differential pair 100 to the NMOS input differential pair 102, the switching circuit 12 switches the switch 146 from off to on. When switching the operating input differential pair from the NMOS input differential pair 102 to the PMOS input differential pair 100, the switching circuit 12 switches the switch 146 from on to off.

[0046] When the PMOS input differential pair 100 is operating, the reference current Iref of the current generating circuit 140 is Iref=Iref1, and when the NMOS input differential pair 102 is operating, the reference current Iref is Iref=Iref1+IrefN1. When the NMOS input differential pair 102 is operating, the output common voltage is higher than when the PMOS input differential pair 100 is operating. For this reason, the source-drain voltage VdsP1 of the first output transistor MP3 drops, and the idling current Iid1 may become smaller than N times the reference current Iref. However, according to the operational amplifier 1 of this embodiment, the idling current Iid1 can be increased by increasing the reference voltage Iref from Iref1 to Iref1+IrefN1. In this way, the idling current Iid1 can be appropriately adjusted to stabilize the output voltage Vout1.

[0047] After the switch 146 is turned on, the PMOS input differential pair 100 operates, and if the source-drain voltage of the first output transistor MP3 is sufficiently large, the switch 146 can be turned off to set the reference current to Iref1. This makes it possible to prevent the generation of unnecessarily large reference current Iref and idling current Iid1.

[0048] The configuration and operation of the operational amplifier 1 according to this embodiment have been described above. According to the operational amplifier 1 according to this embodiment, the current generating circuit 140 is configured to make the reference current Iref larger when the condition for lowering the idling current Iid1 is satisfied than when the condition for lowering the idling current Iid1 is not satisfied. Therefore, when the condition for lowering is satisfied, the reference current Iref is increased, the idling current Iid1 is appropriately adjusted, and the output voltage Vout1 can be stabilized.

[0049] Moreover, according to the operational amplifier 1 of this embodiment, the lowering condition is that the input common voltage is higher than a predetermined voltage. This allows the common voltage to be used in conjunction with other applications (such as switching the input differential pair operating in the input circuit), making it possible to realize the operational amplifier 1 with a simpler configuration.

[0050] Furthermore, according to the operational amplifier 1 of this embodiment, the operating input differential pair is configured to be switched according to the input common voltage, and the lowering condition is that the common voltage is at a voltage at which the NMOS input differential pair 102 operates. Therefore, the switching of the operating input differential pair and the switching of the reference voltage Iref can be performed simultaneously, so that the operational amplifier 1 can be realized with a simpler configuration.

[0051] 4 and 5 are diagrams showing the results of simulating the frequency characteristics of the operational amplifier 1 according to the present embodiment and the operational amplifier 9 according to the reference technique.

[0052] The simulation result of the operational amplifier 9 according to the reference technology shown in FIG. 4 is obtained by setting the reference current Iref9 so that the idling current Iid9 is 604 μA when the PMOS input differential pair 100 is operating, and the idling current Iid9 is 469 μA when the NMOS input differential pair 102 is operating. The simulation result of the operational amplifier 1 according to the present embodiment is obtained by setting the current generating circuit 140 so that the idling current Iid1 is 604 μA when the PMOS input differential pair 100 is operating, and the idling current Iid1 is 1400 μA when the NMOS input differential pair 102 is operating. In FIG. 4, the gain characteristic is shown on the upper side, and the phase characteristic is shown on the lower side. The horizontal axis is frequency (Hz), and the vertical axis is gain (dB) and phase (deg).

[0053] If the output impedance of the operational amplifier is ro and the idling current flowing through the output circuit of the operational amplifier is Ids, ro is proportional to the inverse of Ids, and the larger the idling current Ids, the smaller the output impedance ro becomes. The smaller the output impedance ro, the smaller the second pole frequency f 2nd-pole The frequency is shifted to the higher frequency side, and the phase margin of the operational amplifier is improved. Therefore, by increasing the idling current Ids, the phase margin of the operational amplifier can be improved.

number

[0054] A simulation result of the operational amplifier 9 according to the reference technology showed a unity gain frequency of 8.2 MHz and a phase margin of 61.4 deg. In contrast, a simulation result of the operational amplifier 1 according to the present embodiment showed a unity gain frequency of 8.6 MHz and a phase margin of 69.3 deg. Therefore, it was confirmed that the gain characteristics and phase margin can be improved according to the operational amplifier 1 according to the present embodiment.

[0055] The simulation result for the operational amplifier 9 according to the reference technology shown in Fig. 5 is obtained by setting the reference current in the same manner as the simulation result shown in Fig. 4. The simulation result for the operational amplifier 1 according to the present embodiment is obtained by setting the current generating circuit 140 so that the idling current Iid1 is 604 μA when the PMOS input differential pair 100 is operating and the idling current Iid1 is 665 μA when the NMOS input differential pair 102 is operating. In Fig. 5, the gain characteristic is shown on the upper side, and the phase characteristic is shown on the lower side. The horizontal axis is frequency (Hz), and the vertical axis is gain (dB) and phase (deg).

[0056] In a simulation result of the operational amplifier 1 according to this embodiment, the unity gain frequency was 8.3 MHz and the phase margin was 64.5 deg. In this way, it was confirmed that the gain characteristics and the phase margin can be improved even when the current generating circuit 140 is set so that the idling current Iid1 when the NMOS input differential pair 102 is operating is 665 μA.

[0057] Second embodiment Fig. 6 is a block diagram of an operational amplifier 2 according to the second embodiment. In Fig. 6, the same components as those shown in Fig. 1 are denoted by the same reference numerals, and their description will be omitted as appropriate. The operational amplifier 2 according to the second embodiment includes an input circuit 20, a gain stage 24, an output circuit 28, a non-inverting input terminal INP, a non-inverting input terminal INN, a first power supply terminal VDD, a second power supply terminal VSS, and an output terminal OUT. The difference between the first input voltage V+ and the second input voltage V- is amplified via the input circuit 20, the gain stage 24, and the output circuit 28, and an output voltage Vout2 is output from the output terminal OUT.

[0058] The non-inverting input terminal INP and the inverting input terminal INN are connected to the input circuit 20. The first power supply terminal VDD and the second power supply terminal VSS are connected to the input circuit 20, the gain stage 24 and the output circuit . The output terminal OUT is connected to the output circuit .

[0059] The gain stage 24 according to the second embodiment controls the operation of the output circuit 28 in response to the output signal of the input circuit 20. The gain stage 24 is configured to perform class AB output control and control the idling current flowing through the output circuit 28. The gain stage 24 according to the second embodiment includes a current generating circuit 240 and a control circuit 250.

[0060] The current generating circuit 240 is configured to generate a reference current for the idling current flowing through the output circuit 28. The current generating circuit 240 is configured to make the reference current larger when a condition for lowering the idling current flowing through the output circuit 28 is satisfied than when the condition for lowering the idling current is not satisfied. In this embodiment, the condition for lowering is that the input common voltage is at a voltage at which the NMOS input differential pair 202 operates. The control circuit 250 is configured to control the idling current flowing through the output circuit 28 based on the reference current generated by the current generating circuit 240.

[0061] Fig. 7 is a circuit diagram of an input circuit 20 and a current generating circuit 240 according to the second embodiment. As shown in Fig. 7, the input circuit 20 has a PMOS input differential pair 200, an NMOS input differential pair 202, a tail current source 204, transistors MP24, MN23 to MN25, and a detection circuit 210. The input circuit 20 is configured so that the operating input differential pair can be switched between the PMOS input differential pair 200 and the NMOS input differential pair 202.

[0062] The PMOS input differential pair 200 has transistors MP21 and MP22, each of which is composed of a P-channel type MOS transistor. The source of the transistor MP21 is connected to a tail current source 204 in common with the source of the transistor MP22. The gate of the transistor MP21 is connected to the non-inverting input terminal INP. The drains of the transistors MP21 and MP22 are connected to the control circuit 250 as the output of the PMOS input differential pair 200. As a result, the output signal of the PMOS input differential pair 200 is output from the drain of the PMOS input differential pair 200 to the control circuit 250.

[0063] The tail current source 204 receives the upper current power supply Vdd and supplies a tail current Itp2. A current It1_1 corresponding to the tail current Itp2 supplied by the tail current source 204 flows through the source of the PMOS input differential pair 200.

[0064] The NMOS input differential pair 202 has transistors MN21 and MN22, each of which is constituted by an N-channel MOS transistor. The sources of the transistors MN21 and MN22 are connected to each other, and the drains of the transistors MN21 and MN22 are connected to the control circuit 250 as the output of the NMOS input differential pair 202. As a result, the output signal of the NMOS input differential pair 202 is output from the drain of the NMOS input differential pair 202 to the control circuit 250. The gate of the transistor MN22 is connected to the non-inverting input terminal INP, and the gate of the transistor MN21 is connected to the inverting input terminal INN in common with the gate of the transistor MP22.

[0065] The transistors MN23 to MN25 are each formed of an N-channel MOS transistor. The transistors MN23 to MN25 and a transistor MN26 (described later) form a current mirror circuit. Specifically, the transistor MN23 forms a current mirror pair with each of the transistors MN24 to MN26.

[0066] The lower power supply voltage Vss is supplied to the sources of the transistors MN23 to MN25. The gate of the transistor MN23 is connected to the drain of the transistor MN23 in common with the gates of the transistors MN24 and MN25. The drain of the transistor MN24 is connected to the sources of the transistors MN21 and MN22.

[0067] The transistor MP24 is a P-channel MOS transistor. The transistor MP24 and a transistor MP25 (described later) form a current mirror circuit. The source of the transistor MP24 is supplied with the upper power supply voltage Vdd. The gate of the transistor MP24 is connected in common with the drain of the transistor MP24 and to the drain of the transistor MN25.

[0068] The detection circuit 210 is a circuit for detecting the input common voltage of the first input voltage V+ and the second input voltage V-. The detection circuit 210 has a transistor MP23 configured as a P-channel MOS transistor. The transistor MP23 is provided such that a bias voltage Vrcom is supplied to its gate, its source is connected to the tail current source 204, and its drain is connected to the drain of the transistor MN23. A current It1_2 corresponding to the tail current Itp2 supplied by the tail current source 204 flows through the transistor MP23.

[0069] The current generating circuit 240 has transistors MP25-MP27, MN26-MP28, a first reference current source 242, and a second reference current source 246. The current generating circuit 240 is configured such that, when the input common voltage is at a voltage at which the PMOS input differential pair 200 operates, the reference current becomes the first reference current Ir2 and the first reference current Ir3 supplied by the first reference current source 242 and the second reference current source 246, respectively, and, when the input common voltage is at a voltage at which the NMOS input differential pair 202 operates, the reference current becomes a current obtained by adding the second reference current to the first reference current. The second reference current is a current obtained by copying the current supplied by the tail current source 204 using a current mirror circuit.

[0070] The transistors MP25 to MP27 are each composed of a P-channel type MOS transistor. The transistor MP25 is provided so that the upper power supply voltage Vdd is supplied to the source and the gate is connected to the gate of the transistor MP24. The transistor MP26 is a first reference transistor, and is provided so that the upper power supply voltage Vdd is supplied to the source and the gate is connected to the drain. The transistor MP27 is provided so that the source is connected to the drain of the transistor MP26 and the gate is connected in common with the drain to the first reference current source 242 and the control circuit 250. A reference current Iref2 (drain current) flows through the transistors MP26 and MP27. The reference current Iref2 is used for the idling current of the output circuit 28, and is the sum of the first reference current Ir2 supplied by the first reference current source 242 and the second reference current IrN2 flowing through the transistor MN26 (Iref2=Ir2+IrN2).

[0071] The transistors MN26 to MN28 are each composed of an N-channel MOS transistor. The transistor MN26 is provided so that the lower power supply voltage Vss is supplied to the source, the gate is connected to the gate of the transistor MN23, and the drain is connected to the drain of the transistor MP27. The transistor MN28 is a second reference transistor, and is provided so that the lower power supply voltage Vss is supplied to the source and the gate is connected to the drain. The transistor MN27 is provided so that the source is connected to the drain of the transistor MN28, and the gate and the drain are commonly connected to the drain of the transistor MP25, the second reference current source 246, and the control circuit 250. A reference current Iref3 flows through the transistors MN27 and MN28. The reference current Iref3 is used for the idling current of the output circuit 28, and is the sum of the first reference current Ir3 supplied by the second reference current source 246 and the second reference current IrN4 flowing through the transistor MP25 (Iref3=Ir3+IrN4). Here, the first reference current Ir3 is equal to the first reference current Ir2 (Ir3=Ir2).

[0072] The above describes the configurations of the input circuit 20 and the current generating circuit 240. Here, the operations of the input circuit 20 and the current generating circuit 240 will be described.

[0073] When the input common voltage is sufficiently lower than the bias voltage Vrcom, the entire tail current Itp2 flows through the PMOS input differential pair 200 (It1_1=Itp2), and the current It1_2 does not flow through the transistor MP23 (It1_2=0). At this time, the PMOS input differential pair 200 operates. When the PMOS input differential pair 200 operates, the second reference current IrN2 does not flow through the transistor MN26 (IrN2=0). Therefore, the reference current Iref2 is equal to the first reference current Ir2 supplied by the first reference current source 242 (Iref2=Ir2). Also, since the current IrN3 does not flow through the transistor MP24, the second reference current IrN4 does not flow through the transistor MP25. Therefore, the reference current Iref3 is equal to the first reference current Ir3 supplied by the second reference current source 246 (Iref3=Ir3).

[0074] When the input common voltage increases to about the bias voltage Vrcom, a current I1_2 starts to flow through the transistor MP23. The current I1_2 is copied by the first current mirror circuit 206, and a current Itn2 is supplied to the drain of the NMOS input differential pair 202. As the input common voltage approaches the upper power supply voltage Vdd, the current Itn2 supplied to the NMOS input differential pair 202 increases. In this way, the operating input differential pair is switched from the PMOS input differential pair 200 to the NMOS input differential pair 202.

[0075] When the NMOS input differential pair 202 is operating, a second reference current IrN2 obtained by copying the current It1_2 supplied by the tail current source 204 flows through the transistor MN26. Therefore, the reference current Iref2 is a current obtained by adding the second reference current IrN2 to the first reference current Ir2 (Iref2=Ir2+IrN2). A current IrN3 obtained by copying the current It1_2 flows through the transistor MP24. Furthermore, a second reference current IrN4 obtained by copying the current IrN3 flows through the transistor MP25. Therefore, the reference current Iref3 is a current obtained by adding the first reference current Ir3 to the second reference current IrN4 (Iref3=Ir3+IrN4). Here, the second reference current IrN4 is substantially equal to the second reference current IrN2. In this way, the input differential pair that operates in response to a change in the input common voltage is switched between the PMOS input differential pair 200 and the NMOS input differential pair 202, and the magnitudes of the reference currents Iref2 and Iref3 are switched.

[0076] Fig. 8 is a circuit diagram of a current generating circuit 240, a control circuit 250, and an output circuit 28 according to the second embodiment. Since the second reference current IrN2 switches in response to the operation of the transistor MN26, Fig. 8 shows the transistor MN26 replaced with a first variable current source 243. Furthermore, since the second reference current IrN4 switches in response to the operation of the transistor MP25, Fig. 8 shows the transistor MP25 replaced with a second variable current source 247.

[0077] The control circuit 250 has transistors MP30-MP35, MN30-MN35. The transistors MP30-MP35 are each formed of a P-channel MOS transistor. The transistors MN30-MN35 are each formed of an N-channel MOS transistor.

[0078] The transistor MP30 is provided so that the upper power supply voltage Vdd is supplied to its source and the drain is connected to the source of the transistor MP31. The transistor MP33 is provided so that the upper power supply voltage Vdd is supplied to its source and the drain is connected to the source of the transistor MP34. A bias voltage Vbp2 is supplied to the gates of the transistors MP30 and MP33.

[0079] The transistor MP31 is provided such that its drain is connected to the source of the transistor MP32 and the drain of the transistor MN30. The drain of the transistor MP34 is connected to the source of the transistor MP35 and the drain of the transistor MN33. A bias voltage Vbp1 is supplied to each gate of the transistors MP31 and MP34. The output of the NMOS input differential pair 202 (specifically, the drain of the transistor MN21) is connected between the transistors MP30 and MP31. The output of the NMOS input differential pair 202 (specifically, the drain of the transistor MN22) is connected between the transistors MP33 and MP34.

[0080] The transistor MP32 is provided such that its gate is connected to the gate of the transistor MP27 and its drain is connected to the drain of the transistor MN31. The transistor MN30 is provided such that its gate is connected to the gate of the transistor MN27 and its source is connected to the drain of the transistor MN31.

[0081] The transistor MP35 is provided such that its gate is connected to the gate of the transistor MP27 and its drain is connected to the drain of the transistor MN34. The transistor MN33 is provided such that its gate is connected to the gate of the transistor MN27 and its drain is connected to the drain of the transistor MN34.

[0082] The transistor MN31 is provided so that its source is connected to the drain of the transistor MN32. The transistor MN34 is provided so that its source is connected to the drain of the transistor MN35. A bias voltage Vbn1 is supplied to the gates of the transistors MN31 and MN34.

[0083] The transistors MN32 and MN35 form a current mirror circuit. The transistor MN32 is provided so that the lower power supply voltage Vss is supplied to its source and its gate is connected to the drain of the transistor MN31. The transistor MN35 is provided so that the lower power supply voltage Vss is supplied to its source and its gate is connected to the gate of the transistor MN32. The output of the PMOS input differential pair 200 (specifically, the drain of the transistor MP22) is connected between the transistors MN31 and MN32. The output of the PMOS input differential pair 200 (specifically, the drain of the transistor MP21) is connected between the transistors MN34 and MN35.

[0084] The output circuit 28 generates an output voltage Vout2 according to the output signals of the NMOS input differential pair 202 and the PMOS input differential pair 200. An idling current Iid2 that increases according to an increase in the reference currents Iref2, Iref3 generated by the current generating circuit 240 flows through the output circuit 28. The output circuit 28 according to the second embodiment is configured similarly to the output circuit 16 according to the first embodiment. The output circuit 28 has a first output transistor MP36 configured by a P-channel MOS transistor and a second output transistor MN36 configured by an N-channel MOS transistor.

[0085] The first output transistor MP36 is provided so that its source is supplied with the upper power supply voltage Vdd, its gate is connected to the drain of the transistor MP34, and its drain is connected to the drain of the second output transistor MN36. The second output transistor MN36 is provided so that its source is supplied with the lower power supply voltage Vss, and its gate is connected to the drain of the transistor MN34. An output terminal OUT is connected between the first output transistor MP36 and the second output transistor MN36.

[0086] Since the gate voltage of transistors MP27 and MP35 is common, when the gate-source voltage of transistor MP26 is VgsP1, the gate-source voltage of transistor MP27 is VgsP2, the gate-source voltage of the first output transistor MP36 is VgsP3, and the gate-source voltage of transistor MP35 is VgsP4, the following equation holds: VgsP1+VgsP2=VgsP3+VgsP4...(1)

[0087] In this embodiment, VgsP1=VgsP3, VgsP2=VgsP4...(2) The sizes of the transistors MP25, MP26, MP35 and the first output transistor MP36 are designed so that

[0088] Since the gate voltage of transistors MN27 and MN33 is common, when the gate-source voltage of transistor MN28 is VgsN1, the gate-source voltage of transistor MN27 is VgsN2, the gate-source voltage of second output transistor MN36 is VgsN3, and the gate-source voltage of transistor MN33 is VgsN4, the following equation holds: VgsN1+VgsN2=VgsN3+VgsN4...(3)

[0089] In this embodiment, VgsN1=VgsN3, VgsN2=VgsN4...(4) The sizes of the transistors MN27, MN28, MN33 and the second output transistor MN36 are designed so that

[0090] The drain current (saturation current) Ids of a MOS transistor is given by the following equation: Ids = (β / 2) × (Vgs-Vt) 2 β=(W / L)×μCox where Vgs is the gate-source voltage, Vt is the threshold voltage, W is the channel width, L is the channel length, μ is the carrier mobility, and Cox is the unit capacitance of the gate oxide.

[0091] Regarding the reference current Iref2 and the idling current Iid2, the following equations (5) and (6) hold when the types and W / L of the transistor MP26 and the first output transistor MP36 are matched. Iref2=Np_ref1×[(W / L)×(μCox / 2)×(Vgs-Vt) 2 ]···(5) Iid2=Np_out1×[(W / L)×(μCox / 2)×(Vgs-Vt) 2 ]···(6) Np_ref1 is an arbitrary coefficient (integer) depending on the size of the transistor MP26, and Np_out1 is an arbitrary coefficient (integer) depending on the size of the output transistor MP36.

[0092] The relationship between the reference current Iref2 and the idling current Iid2 can be set by the ratio of these coefficients by canceling elements other than the coefficients Np_ref1 and Np_out1 as shown in the following equation. Iref2:Iid2=Np_ref1:Np_out1 Iid2×Np_ref1=Iref2×Np_out1···(7)

[0093] The sizes of transistors MP27 and MP35 are designed so that VgsP2=VgsP4 as shown in the above formula (2). Specifically, the sizes of both transistors MP27 and MP35 are designed according to the magnitude of the current flowing through each of them. For example, when an equal current (Iref2) flows through both transistors, both transistors are designed with the same W / L. On the other hand, when different currents flow through both transistors, both transistors are designed with different W / L.

[0094] Regarding the reference current Iref3 and the idling current Iid2, by matching the types and W / L of the transistor MN28 and the second output transistor MN36, the following equations (8) and (9) hold. Iref3=Nn_ref1×[(W / L)×(μCox / 2)×(Vgs-Vt) 2 ]···(8) Iid2=Nn_out1×[(W / L)×(μCox / 2)×(Vgs-Vt) 2 ]···(9) Nn_ref is an arbitrary coefficient (integer) depending on the size of the transistor MN28, and Nn_out is an arbitrary coefficient (integer) depending on the size of the output transistor MN36.

[0095] The relationship between the reference current Iref3 and the idling current Iid2 can be set by the ratio of these coefficients by canceling elements other than the coefficients Nn_ref1 and Nn_out1 as shown in the following equation. Iref3:Iid2=Nn_ref1:Nn_out1 Iid2×Nn_ref1=Iref3×Nn_out1···(10)

[0096] The sizes of transistors MN27 and MN33 are designed so that VgsN2=VgsN4 as shown in equation (4) above. Specifically, the sizes of both transistors MN27 and MN33 are designed according to the magnitude of the current flowing through each of them. For example, when an equal current (Iref3) flows through both transistors, both transistors are designed with the same W / L. On the other hand, when different currents flow through both transistors, both transistors are designed with different W / L.

[0097] From equations (7) and (10), the following equation holds: Iid2 = Iref2 × (Np_out1 / Np_ref1) =Iref3×(Nn_out1 / Nn_ref1)···(11) Here, the reference current Iref2 is substantially equal to the reference current Iref3. Also, the transistors MP26, MN28, the first output transistor MP36, and the second output transistor MN36 are configured so that Np_out1 / Np_ref1 is equal to Nn_out1 / Nn_ref1. According to the formula (11), the idling current Iid2 can be appropriately adjusted by controlling the reference currents Iref2 and Iref3.

[0098] According to the operational amplifier 2 of this embodiment, when the condition for lowering the idling current Iid2 is satisfied, the current generating circuit 240 makes the reference currents Iref2 and Iref3 larger than when the condition for lowering the idling current Iid2 is not satisfied. When the input common voltage is at the voltage at which the NMOS input differential pair 202 operates, the reference currents Iref2 and Iref3 are larger than when the input common voltage is not at the voltage at which the NMOS input differential pair 202 operates (i.e., when the input common voltage is at the voltage at which the PMOS input differential pair 200 operates). Specifically, when the PMOS input differential pair 200 operates, the reference currents Iref2 and Iref3 are the first reference currents Ir2 and Ir3. When the operating input differential pair switches from the PMOS input differential pair 200 to the NMOS input differential pair 202, the second reference currents IrN2 and IrN4 are added to the reference currents Iref2 and Iref3. As a result, the reference currents Iref2 and Iref3 increase, and the idling current Iid2 is appropriately adjusted, making it possible to stabilize the output voltage Vout2.

[0099] Third embodiment In the third embodiment, the configuration of the control circuit of the gain stage is different from that of the second embodiment. The operational amplifier according to the third embodiment has a configuration in which the control circuit of the operational amplifier according to the second embodiment is replaced with the control circuit according to the third embodiment. Fig. 9 is a circuit diagram of a current generating circuit 240, a control circuit 252, and an output circuit 28 according to the third embodiment. In Fig. 9, the same reference numerals are used for configurations that are substantially the same as those shown in Fig. 8, and descriptions thereof will be omitted as appropriate.

[0100] The gain stage 25 according to the third embodiment has a current generating circuit 240 and a control circuit 252. The control circuit 252 according to the third embodiment differs from the second embodiment mainly in the connection of the gates of the transistors MP30, MP33, MN32, and MN35.

[0101] The transistors MP30 and MP33 configure a current mirror circuit. The gate of the transistor MP30 is connected to the drain of the transistor MP31. The gate of the transistor MP33 is connected to the gate of the transistor MP30. A bias voltage Vbn2 is supplied to the gates of the transistors MN32 and MN35.

[0102] Even when the control circuit 252 is configured as in the third embodiment, the idling current Iid3 flowing through the output circuit 28 is expressed by the following equation, similarly to the second embodiment. Iid3 = Iref2 × (Np_out1 / Np_ref1) =Iref3×(Nn_out1 / Nn_ref1)···(12)

[0103] By controlling the reference currents Iref2 and Iref3, the idling current Iid3 can be appropriately adjusted and the output voltage Vout3 can be stabilized.

[0104] (Fourth embodiment) The fourth embodiment differs from the second embodiment mainly in the configuration of the gain stage. The operational amplifier according to the fourth embodiment may have a configuration in which gain stage 24 of the operational amplifier 2 according to the second embodiment is replaced with the gain stage according to the fourth embodiment.

[0105] 10 is a block diagram of a gain stage 30 according to the fourth embodiment. The gain stage 30 according to the fourth embodiment has a current generating circuit 300 and a control circuit 360. The current generating circuit 300 according to the present embodiment is configured to generate a reference current, and has a first current generating circuit 320 and a second current generating circuit 340. The control circuit 360 is configured to control the idling current flowing through the output circuit 28 based on the reference current generated by the current generating circuit 300.

[0106] Fig. 11(a) is a circuit diagram of the first current generating circuit 320, and Fig. 11(b) is a circuit diagram of the second current generating circuit 340. In Fig. 11(a) and Fig. 11(b), components that are substantially the same as those shown in Fig. 8 are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0107] 11(a), the first current generating circuit 320 has a first reference current source 242, a first variable current source 243, a transistor MP40, and an amplifier 322. The first reference current source 242 and the first variable current source 243 are configured similarly to the first reference current source 242 and the first variable current source 243 according to the second embodiment.

[0108] The transistor MP40 is a first reference transistor and is configured as a P-channel MOS transistor. The transistor MP40 is provided so that the upper power supply voltage Vdd is supplied to its source, the gate is connected to the output terminal of the amplifier 322, and the drain is connected to the first reference current source 242 and the first variable current source 243. The amplifier 322 is provided so that a voltage (Vdd / 2) that is half the upper power supply voltage Vdd is supplied to its inverting input terminal, the non-inverting input terminal is connected to the drain of the transistor MP40, and the output terminal is connected to the control circuit 360.

[0109] A reference current Iref4 flows through the transistor MP40. The reference current Iref4 is the sum of a first reference current Ir2 supplied by the first reference current source 242 and a second reference current IrN2 supplied by the first variable current source 243 (Iref4=Ir2+IrN2).

[0110] When the gate-source voltage of the transistor MP40 is VgsP5, the output voltage Vrefp of the amplifier 322 is expressed as follows: Vrefp=Vdd-VgsP5 It is expressed as:

[0111] 11(b), the second current generating circuit 340 has a second reference current source 246, a second variable current source 247, a transistor MN40, and an amplifier 342. The second reference current source 246 and the second variable current source 247 are configured similarly to the second reference current source 246 and the second variable current source 247 according to the second embodiment.

[0112] The transistor MN40 is a second reference transistor and is configured as an N-channel MOS transistor. The transistor MN40 is provided so that the lower power supply voltage Vss is supplied to its source, the gate is connected to the output terminal of the amplifier 342, and the drain is connected to the second reference current source 246 and the second variable current source 247. The amplifier 342 is provided so that a voltage (Vdd / 2) that is half the upper power supply voltage Vdd is supplied to its inverting input terminal, the non-inverting input terminal is connected to the drain of the transistor MN40, and the output terminal is connected to the control circuit 360.

[0113] A reference current Iref5 flows through the transistor MN40. The reference current Iref5 is the sum of a first reference current Ir3 supplied by the second reference current source 246 and a second reference current IrN4 supplied by the second variable current source 247 (Iref5=Ir3+IrN4).

[0114] When the gate-source voltage of the transistor MN40 is VgsN5, the output voltage Vrefn of the amplifier 342 is expressed as follows: Vrefn=Vss+VgsP5 It is expressed as:

[0115] 12 is a circuit diagram of a control circuit 360 and an output circuit 28 according to the fourth embodiment. The output circuit 28 according to the fourth embodiment has substantially the same configuration as the output circuit 28 according to the second embodiment.

[0116] The control circuit 360 according to the fourth embodiment has transistors MP41 to MP47, MN41 to MN47, and amplifiers 272 and 274. The transistors MP41 to MP47 are configured as P-channel MOS transistors. The transistors MN41 to MN47 are configured as N-channel MOS transistors.

[0117] The transistor MP41 is provided so that the upper power supply voltage Vdd is supplied to its source and the drain is connected to the source of the transistor MP42. The transistor MP44 is provided so that the upper power supply voltage Vdd is supplied to its source and the drain is connected to the sources of the transistors MP45 and MP47. A bias voltage Vbp5 is supplied to the gates of the transistors MP41 and MP44. The output of the NMOS input differential pair 202 (specifically, the drain of the transistor MN21) is connected between the transistors MP41 and MP42.

[0118] The drain of the transistor MP42 is connected to the source of the transistor MP43. The drain of the transistor MP45 is connected to the source of the transistor MP46. The drain of the transistor MP47 is connected to the drain of the transistor MN46 and the gate of the first output transistor MP36. The output of the NMOS input differential pair 202 (specifically, the drain of the transistor MN22) is connected between the transistors MP44 and MP45. A bias voltage Vbp4 is supplied to the gates of the transistors MP42, MP45, and MP47.

[0119] The drain of transistor MP43 is connected to transistors MN41 and MN42. The drain of transistor MP46 is connected to the drain of transistor MN47 and the gate of the second output transistor MN36. The source of transistor MN46 is connected to the drain of transistor MN44. A bias voltage Vbp3 is supplied to the gates of transistors MP43 and MP46, and a bias voltage Vbn3 is supplied to the gate of transistor MN46.

[0120] The transistors MN43 and MN45 form a current mirror circuit. The transistor MN43 is provided so that a lower power supply voltage Vss is supplied to its source, its gate is connected to the drain of the transistor MP43 in common with the gate of the transistor MN45, and its drain is connected to the drains of the transistors MN41 and MN42. The transistor MN45 is provided so that a lower power supply voltage Vss is supplied to its source, and its drain is connected to the sources of the transistors MN44 and MN47. The output of the PMOS input differential pair 200 (specifically, the drain of the transistor MP22) is connected between the transistor MN43 and the transistors MN41 and MN42. The output of the PMOS input differential pair 200 (specifically, the drain of the transistor MP21) is connected between the transistor MN45 and the transistors MN44 and MN47.

[0121] The amplifier 272 is provided such that its inverting input terminal is connected to the gate of the first output transistor MP36, its non-inverting input terminal is supplied with the output voltage Vrefp of the amplifier 322 in the first current generating circuit 320, and its output terminal is connected to the gates of the transistors MN42 and MN47. The amplifier 274 is provided such that its inverting input terminal is connected to the gate of the second output transistor MN36, its non-inverting input terminal is supplied with the output voltage Vrefn of the amplifier 342 in the second current generating circuit 340, and its output terminal is connected to the gates of the transistors MN41 and MN44.

[0122] According to the gain stage 30 and output circuit 28 of this embodiment, the gate-source voltage VgsP5 of the transistor MP40 in the first current generating circuit 320 is equal to the gate-source voltage VgsP6 of the first output transistor MP36 in the output circuit 28 (VgsP5=VgsP6). Also, the gate-source voltage VgsN5 of the transistor MN40 in the second current generating circuit 340 is equal to the gate-source voltage VgsN6 of the second output transistor MN36 in the output circuit 28 (VgsN5=VgsN6).

[0123] For the transistor MP40 and the first output transistor MP36, coefficients (integers) according to the transistor sizes are designated as Np_ref2 and Np_out2, respectively. For the transistor MN40 and the second output transistor MN36, coefficients (integers) according to the transistor sizes are designated as Nn_ref2 and Nn_out2, respectively. As in the second embodiment, the idling current Iid4 can be set by the size ratio between the transistor MP40 and the first output transistor MP36 or the size ratio between the transistor MN40 and the second output transistor MN36, and the idling current Iid4 flowing through the output circuit 28 is expressed by the following equation. Iid4 = Iref4 × (Np_out2 / Np_ref2) =Iref5×(Nn_out2 / Nn_ref2)···(13)

[0124] In addition, in the formula (13), the reference current Iref4 is substantially equal to the reference current Iref5, and Np_out2 / Np_ref2 is equal to Nn_out2 / Nn_ref2.

[0125] According to the fourth embodiment, by controlling the reference currents Iref4 and Iref5, it is possible to appropriately adjust the idling current Iid4 and stabilize the output voltage Vout4.

[0126] (Modification) In the above embodiment, an example has been described in which the reference current is controlled depending on whether the operating input differential pair is a PMOS input differential pair or an NMOS input differential pair. However, the present invention is not limited to this, and the reference current may be controlled regardless of the operating input differential pair. For example, the input common voltage, the output common voltage, the source-drain voltage of the first output transistor, and the idling current may be detected, and the reference current may be controlled based on the detection results.

[0127] For example, when the output common voltage is higher than a predetermined voltage, the reference voltage may be set higher than when the output common voltage is lower than the predetermined voltage. Also, when the source-drain voltage of the first output transistor is lower than a predetermined voltage, the reference voltage may be set higher than when the source-drain voltage is equal to or higher than the predetermined voltage. Furthermore, when the idling current is lower than a predetermined current, the reference voltage may be set higher than when the idling current is equal to or higher than the predetermined current. This makes it possible to suppress a decrease in the idling current and stabilize the output voltage.

[0128] In the above embodiment, an example in which the reference current is controlled in two stages has been mainly described. However, the current generating circuit may be configured to control the reference current in three or more stages. This allows the idling current to be controlled more flexibly. For example, when the input common voltage is at a voltage at which the NMOS input differential pair operates, the reference current is made larger than when the input common voltage is at a voltage at which the PMOS input differential pair operates. Furthermore, when the input common voltage is at a voltage at which the NMOS input differential pair operates, the current generating circuit may be configured to control the reference current in two or more stages.

[0129] In the above embodiment, an example has been described in which the reference current is controlled so as to suppress a decrease in the idling current caused by a decrease in the source-drain voltage of the first output transistor constituted by a P-channel MOS transistor. However, the idling current may also decrease when the source-drain voltage of the second output transistor constituted by an N-channel MOS transistor decreases. Therefore, when the source-drain voltage of the second output transistor decreases to such an extent that a sufficient idling current does not flow, the reference current may be increased.

[0130] The condition for lowering the idling current may be that the input common voltage is at a voltage at which the PMOS input differential pair operates and is lower than a predetermined voltage. This makes it possible to appropriately adjust the idling current and stabilize the output voltage even when the source-drain voltage of the second output transistor formed of an N-channel MOS transistor drops.

[0131] (supplement) Although the embodiments according to the present disclosure have been described using specific terms, this description is merely an example to aid understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. In addition to the embodiments, embodiments, examples, and modifications not described here are also included in the scope of the present invention. Furthermore, one or more components included in the operational amplifiers according to the first to fourth embodiments can be combined with one or more elements of an operational amplifier according to another embodiment.

[0132] (Additional Note) One aspect of the technology disclosed in this specification can be understood as follows.

[0133] (Claim 1) an input circuit including a PMOS input differential pair to which a first input voltage and a second input voltage are input, and an NMOS input differential pair to which the first input voltage and the second input voltage are input, the input circuit being configured so that an operating input differential pair can be switched between the PMOS input differential pair and the NMOS input differential pair; a current generating circuit for generating a reference current; an output circuit through which an idling current flows, the idling current increasing in accordance with an increase in the reference current, and which generates an output voltage corresponding to an output signal of the PMOS input differential pair and the NMOS input differential pair; the current generating circuit is configured such that, when a condition for lowering the idling current is satisfied, the reference current is larger than when the condition for lowering the idling current is not satisfied. Operational amplifier.

[0134] (Claim 2) the lowering condition is that a common voltage of the first input voltage and the second input voltage is higher than a predetermined voltage; 2. The operational amplifier of claim 1.

[0135] (Claim 3) the input circuit is configured such that an operating input differential pair is switched in response to a common voltage of the first input voltage and the second input voltage; The lowering condition is that the common voltage is at a voltage at which the NMOS input differential pair operates. 2. The operational amplifier of claim 1.

[0136] (Claim 4) the input circuit further includes a tail current source that supplies a current for operating the PMOS input differential pair and the NMOS input differential pair; the current generating circuit has a reference current source that supplies a first reference current, and is configured such that, when the PMOS input differential pair is operating, the reference current becomes the first reference current, and, when the NMOS input differential pair is operating, the reference current becomes a current obtained by adding a second reference current to the first reference current; The second reference current is a current obtained by copying the current supplied by the tail current source using a current mirror circuit. 4. The operational amplifier according to claim 1.

[0137] (Claim 5) the output circuit is configured by a first output transistor configured by a P-channel MOS transistor and a second output transistor configured by an N-channel MOS transistor being push-pull connected; the current generating circuit further includes a first reference transistor configured with a P-channel MOS transistor and through which the reference current flows, and a second reference transistor configured with an N-channel MOS transistor and through which the reference current flows; the first output transistor, the second output transistor, the first reference transistor and the second reference transistor are provided such that a gate-source voltage of the first output transistor is equal to a gate-source voltage of the first reference transistor, and a gate-source voltage of the second output transistor is equal to a gate-source voltage of the second reference transistor. 5. The operational amplifier according to claim 1.

[0138] (Claim 6) 6. A semiconductor device comprising the operational amplifier according to claim 1. [Explanation of symbols]

[0139] 1,2 operational amplifier, 10,20 input circuit, 12 switching circuit, 14,24,25,30 gain stage, 16,28 output circuit, 100,200 PMOS input differential pair, 102,202 NMOS input differential pair, 104 first tail current source, 106 second tail current source, 140,240,300 current generating circuit, 142 first reference current source, 144 second reference current source, 146 switch, 204 tail current source, 242 first reference current source, 243 first variable current source, 246 second reference current source, 247 second variable current source, 250,252,360 control circuit, 320 first current generating circuit, 340 second current generating circuit, 322,343 Amplifiers, MP1, MP2, MP21-MP27, MP30-MP35, MP40-MP47, MN1, MN2, MN21-MN28, MN30-MN35, MN40-MN47 transistors, MP3, MP36 first output transistors, MN3, MN36 second output transistors.

Claims

1. an input circuit including a PMOS input differential pair to which a first input voltage and a second input voltage are input, and an NMOS input differential pair to which the first input voltage and the second input voltage are input, the input circuit being configured so that an operating input differential pair can be switched between the PMOS input differential pair and the NMOS input differential pair; a current generating circuit for generating a reference current; an output circuit through which an idling current flows, the idling current increasing in response to an increase in the reference current, and which generates an output voltage corresponding to an output signal of the PMOS input differential pair and the NMOS input differential pair; the current generating circuit is configured such that, when a condition for lowering the idling current is satisfied, the reference current is larger than when the condition for lowering the idling current is not satisfied. Operational amplifier.

2. the lowering condition is that a common voltage of the first input voltage and the second input voltage is higher than a predetermined voltage; 2. The operational amplifier of claim 1.

3. the input circuit is configured such that an operating input differential pair is switched in response to a common voltage of the first input voltage and the second input voltage; The lowering condition is that the common voltage is at a voltage at which the NMOS input differential pair operates.

2. The operational amplifier of claim 1.

4. the input circuit further includes a tail current source that supplies a current for operating the PMOS input differential pair and the NMOS input differential pair; the current generating circuit has a reference current source that supplies a first reference current, and is configured such that, when the PMOS input differential pair is operating, the reference current becomes the first reference current, and, when the NMOS input differential pair is operating, the reference current becomes a current obtained by adding a second reference current to the first reference current; The second reference current is a current obtained by copying the current supplied by the tail current source using a current mirror circuit.

4. The operational amplifier of claim 3.

5. the output circuit is configured by a first output transistor configured by a P-channel MOS transistor and a second output transistor configured by an N-channel MOS transistor being push-pull connected; the current generating circuit further includes a first reference transistor configured with a P-channel MOS transistor and through which the reference current flows, and a second reference transistor configured with an N-channel MOS transistor and through which the reference current flows, the first output transistor, the second output transistor, the first reference transistor and the second reference transistor are provided such that a gate-source voltage of the first output transistor is equal to a gate-source voltage of the first reference transistor, and a gate-source voltage of the second output transistor is equal to a gate-source voltage of the second reference transistor.

2. The operational amplifier of claim 1.

6. A semiconductor device comprising the operational amplifier according to any one of claims 1 to 5.

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