Antenna, array antenna, semiconductor chip, and wireless device

Abstract

To provide an antenna, array antenna, semiconductor chip, and wireless device that can be reduced in size.SOLUTION: An antenna according to the present disclosure includes: a semiconductor substrate; a first wiring layer which is formed on a main surface of the semiconductor substrate; an insulating layer which is made of an insulating film laminated on the first wiring layer; and a second wiring layer which is laminated on the insulating layer. The antenna further includes: a first ground pattern which is formed in the first wiring layer so as to cover a part of a first region of the main surface of the semiconductor substrate; and a second ground pattern which is formed in the second wiring layer such that a part of the outer periphery of the first ground pattern overlaps with a part of the outer periphery thereof when viewed from above, and a portion overlapping with the first ground pattern is electrically connected to first signal wiring extending from an integrated circuit. The first ground pattern and the second ground pattern are formed so as to be apart from each other as heading toward an end region of the semiconductor substrate from an overlapping region of the first ground pattern and the second ground pattern when viewed from above.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to an antenna, an array antenna, a semiconductor chip, and a wireless device. [Background technology]

[0002] Antennas used for large-capacity communication using millimeter waves or sub-terahertz waves need to be designed to have a small structural size in order to realize high-frequency communication, but there is a limit to how small an antenna can be, and mounting is becoming difficult. In addition, the power loss when power is supplied from the chip to the antenna through the signal line increases as the frequency of the wireless signal increases. A solution to this problem is disclosed in, for example, Patent Document 1.

[0003] In Patent Document 1, an antenna is formed on a semiconductor chip, which enables further miniaturization of the antenna and also reduces power loss. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2011 / 078061 Summary of the Invention [Problem to be solved by the invention]

[0005] There is a continuing demand for miniaturization of antennas used for large-capacity communications using millimeter waves or sub-terahertz waves, without being limited to the antenna structure disclosed in Patent Document 1.

[0006] One object of the present disclosure is to provide an antenna, an array antenna, a semiconductor chip, and a wireless device that solve the above-mentioned problems. [Means for solving the problem]

[0007] An antenna according to a first aspect of the present disclosure is an antenna comprising at least a semiconductor substrate, a first wiring layer formed on a main surface of the semiconductor substrate, an insulating layer made of an insulating film laminated on the first wiring layer, and a second wiring layer laminated on the insulating layer, the antenna having a first ground pattern formed in the first wiring layer so as to cover a part of a first region of the main surface of the semiconductor substrate, and a second ground pattern formed in the second wiring layer so as to overlap a part of an outer periphery of the first ground pattern with a part of an outer periphery of the first ground pattern in a top view and to be electrically connected to a first signal wiring extending from an integrated circuit, the first ground pattern and the second ground pattern being formed so as to diverge from an overlapping region of the first ground pattern and the second ground pattern in a top view toward an edge region of the semiconductor substrate. Effect of the Invention

[0008] According to the present disclosure, it is possible to provide an antenna, an array antenna, a semiconductor chip, and a wireless device that can be made compact. [Brief description of the drawings]

[0009] [Figure 1] 1 is a top view showing a configuration example of a semiconductor chip on which an antenna according to the present disclosure is mounted; [Diagram 2] 3A and 3B are a top view and a cross-sectional view showing a more detailed configuration example of a region in which a microstrip line is formed of an antenna according to the present disclosure. [Diagram 3] 3A and 3B are a top view and a cross-sectional view showing a more detailed configuration example of a region in which a slot line is formed of an antenna according to the present disclosure. [Figure 4] 11 is a top view showing a configuration example of a semiconductor chip on which a modified example of an antenna according to the present disclosure is mounted; FIG. [Diagram 5] 1 is a top view showing a configuration example of a wireless device to which a semiconductor chip according to the present disclosure is applied; [Figure 6] 1 is a side view showing a configuration example of a wireless device to which a semiconductor chip according to the present disclosure is applied; [Figure 7] FIG. 2 is a diagram showing a 3D analysis result of the electric field strength of an antenna according to the present disclosure. [Figure 8] 1 is a diagram showing an analysis result of the electric field strength of an antenna according to the present disclosure when attached to a printed circuit board. [Figure 9] FIG. 13 is a diagram showing an analysis result of the electric field strength of an antenna according to the present disclosure when not attached to a printed circuit board. [Figure 10] 1 is a top view showing a configuration example of a semiconductor chip on which an antenna according to the present disclosure is mounted; [Figure 11] 1 is a top view showing a configuration example of a wireless device to which a semiconductor chip according to the present disclosure is applied; [Figure 12] 1 is a diagram showing an analysis result of the electric field strength of an antenna according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Embodiment 1> FIG. 1 is a top view showing a configuration example of a semiconductor chip 1 on which an antenna 10 according to the present disclosure is mounted. FIG. 2 is a top view and a cross-sectional view showing a more detailed configuration example of a region 1a of the antenna 10 in which a microstrip line is formed. The upper view of FIG. 2 shows a top view of the region 1a, and the lower view of FIG. 2 shows a cross-sectional view of the II-II part of the top view of the region 1a. Note that the insulating film 103a formed on the insulating layer M2 is omitted in the top view of FIG. 2. FIG. 3 is a top view and a cross-sectional view showing a more detailed configuration example of a region 1b of the antenna 10 in which a slot line is formed. The upper view of FIG. 3 shows a top view of the region 1b, and the lower view of FIG. 3 shows a cross-sectional view of the III-III part of the top view of the region 1b. Note that the insulating film 103b formed on the insulating layer M2 is omitted in the top view of FIG. 3.

[0011] 1 to 3, the semiconductor chip 1 includes at least a semiconductor substrate 101, a first wiring layer M1 formed on the main surface of the semiconductor substrate 101, an insulating layer M2 laminated on the first wiring layer M1, and a second wiring layer M3 laminated on the insulating layer M2. In this embodiment, a case where three layers M1 to M3 are provided on the main surface of the semiconductor substrate 101 will be described as an example, but the present invention is not limited thereto, and four or more layers may be provided.

[0012] The semiconductor substrate 101 is formed of a semiconductor material such as silicon or gallium arsenide. The first wiring layer M1 is a layer on which a ground pattern is formed. The ground pattern is a metal film such as copper having a predetermined shape connected to the ground. The insulating layer M2 is a layer on which an insulating film is formed. The second wiring layer M3 is a layer on which mainly signal wiring is formed. In the second wiring layer M3, a ground pattern for forming a slot line, which will be described later, is also formed.

[0013] A region 1c in which the integrated circuit 90 is disposed, a region (second region) 1a in which a microstrip line is formed, and a region (first region) 1b in which a slot line is formed are provided on the main surface of the semiconductor substrate 101. The antenna 10 is composed of the microstrip line formed in the region 1a and the slot line formed in the region 1b.

[0014] 1 and 2, the structure of the region 1a where the microstrip line is formed will be described. In the region 1a, a ground pattern (third ground pattern) 102a is formed in the first wiring layer M1 so as to cover the entire main surface of the region 1a among the main surface of the semiconductor substrate 101. An insulating film 103a is formed in the insulating layer M2 so as to cover the ground pattern 102a. In the second wiring layer M3, a signal wiring 104a is formed, which extends from the region 1c where the integrated circuit 90 is disposed to the region 1b where the slot line is formed. The signal wiring 104a formed in the region 1a plays a role as a microstrip line that transmits a wireless signal received from the signal wiring SL1 of the integrated circuit 90 to the slot line formed in the region 1b.

[0015] Next, the structure of the region 1b in which the slot line is formed will be described with reference to Fig. 1 and Fig. 3. In the region 1b, a ground pattern (first ground pattern) 102b is formed in the first wiring layer M1 so as to cover a part of the main surface of the region 1b among the main surface of the semiconductor substrate 101. An insulating film 103b is formed in the insulating layer M2 so as to cover the entire main surface of the region 1b including the ground pattern 102b. In the second wiring layer M3, a ground pattern (second ground pattern) 104b is formed so that a part of the outer periphery of the ground pattern 102b overlaps with a part of the outer periphery when viewed from above (as viewed in the z-axis direction) and the part overlapping with the ground pattern 102b is electrically connected to the signal wiring 104a in the region 1a. A gap SL2 formed between the ground pattern 102b and the ground pattern 104b serves as a slot line for transmitting a radio signal received from the signal wiring 104a in the region 1a.

[0016] 1, the ground pattern 102a formed in the first wiring layer M1 in the region 1a and the ground pattern 104b formed in the second wiring layer M3 in the region 1b are electrically connected by a via 112 near the boundary line P2 between the regions 1a and 1b. In addition, in top view, a gap 111 is provided between a connection point X1 between the signal wiring 104a and the ground pattern 104b and a connection point (a region where the via 112 is formed) between the ground pattern 102a and the ground pattern 104b. The length of the gap 111 in the x-axis direction is, for example, ¼ wavelength of a wireless signal.

[0017] Here, the ground patterns 102b and 104b are formed so as to be more separated from the overlapping portion of the ground patterns 102b and 104b in top view toward the chip end E1 region of the semiconductor substrate 101. In other words, the ground patterns 102b and 104b are formed so that the gap SL2 becomes larger (the interval L1 between the outer peripheries of the ground patterns 102b and 104b in the x-axis direction becomes longer) toward the end region from the center of the semiconductor chip 1. As a result, when power is supplied to the slot line, an electric field is generated in the gap SL2, and a magnetic field is generated in the vertical direction (z-axis direction) of the semiconductor chip, so that the slot line can function as an antenna. In other words, the slot line formed in the region 1b not only functions as a transmission line for transmitting a wireless signal received from the signal wiring 104a formed in the region 1a, but also functions as an antenna for radiating the wireless signal from the chip end E1 to the external space.

[0018] In this manner, the antenna 10 according to the present disclosure is formed on the semiconductor chip 1 such that the gap portion of the slot line gradually becomes larger from the center of the chip to the end of the chip. As a result, the antenna 10 can realize a small wireless device capable of large-capacity communication using millimeter waves or sub-terahertz waves. Furthermore, the antenna 10 can shorten the transmission path compared to when it is provided outside the semiconductor chip 1, so that the power loss can be reduced and the number of parts can be reduced.

[0019] In the present embodiment, the antenna 10 is configured by a microstrip line formed in the region 1a of the semiconductor chip 1 and a slot line formed in the region 1b of the semiconductor chip 1, but is not limited thereto. As long as the antenna 10 can radiate a radio signal from the integrated circuit 90 to the external space, it may be configured by only a slot line formed in the region 1b of the semiconductor chip 1, as shown in FIG.

[0020] (Example of wireless device 100 to which semiconductor chip 1 is applied) Fig. 5 is a top view showing an example of the configuration of a wireless device 100 to which the semiconductor chip 1 is applied, and Fig. 6 is a side view showing an example of the configuration of a wireless device 100 to which the semiconductor chip 1 is applied.

[0021] Since the semiconductor chip 1 is made of a dielectric material, the electromagnetic field pattern generated by the antenna 10 formed on the semiconductor chip 1 tends to be asymmetric between the vertically upward direction (positive direction of the z-axis) and the vertically downward direction (negative direction of the z-axis) of the chip. When the semiconductor substrate 101 is thick, the electromagnetic field pattern generated by the antenna 10 formed on the semiconductor chip 1 also tends to be asymmetric between the vertically upward direction and the vertically downward direction of the chip. Although it depends on the thickness of the semiconductor substrate 101 and the operating frequency, the electromagnetic waves are basically biased toward the semiconductor substrate 101 side (downward direction of the chip) which has a high dielectric constant, so the radiation direction of the electromagnetic waves from the antenna 10 may not be directed forward (positive direction of the y-axis) of the chip end E1.

[0022] Therefore, in the wireless device 100, the semiconductor chip 1 is provided on a ground layer 40 formed on the printed circuit board 30. As a result, the ground layer 40 acts as a reflector of electromagnetic waves, so that the antenna 10 provided on the semiconductor chip 1 can radiate a wireless signal in a desired direction.

[0023] Furthermore, in the wireless device 100, the semiconductor chip 1 is arranged so as to protrude from an end of the printed circuit board 30. By adjusting the amount of protrusion of the semiconductor chip 1, the pattern of the electromagnetic field generated by the antenna 10 can be adjusted to a desired pattern.

[0024] For example, it is preferable to reduce the amount of overhang because the electromagnetic waves are more likely to be biased toward the semiconductor substrate 101 side (vertically downward direction of the chip) as the thickness of the semiconductor substrate 101 increases. On the other hand, it is preferable to increase the amount of overhang because the electromagnetic waves are less likely to be biased toward the semiconductor substrate 101 side as the thickness of the semiconductor substrate 101 decreases.

[0025] Also, for example, the higher the operating frequency, the more susceptible it is to the effects of electromagnetic wave bias, so it is preferable to reduce the amount of overhang, whereas the lower the operating frequency, the less susceptible it is to the effects of electromagnetic wave bias, so it is preferable to increase the amount of overhang.

[0026] FIG. 7 is a diagram showing a 3D analysis result of the electric field strength of the antenna 10 of the semiconductor chip 1 attached to the printed circuit board 30. FIG. 8 is a diagram showing the analysis result of the electric field strength of the antenna 10 of the semiconductor chip 1 attached to the printed circuit board 30, as viewed from the top surface and side surface of the chip. FIG. 9 is a diagram showing the analysis result of the electric field strength of the antenna 10 of the semiconductor chip 1 not attached to the printed circuit board 30, as viewed from the top surface and side surface of the chip. In the example of FIG. 7 to FIG. 9, the design frequency is 150 GHz, and the thickness of the semiconductor substrate 101 of the semiconductor chip 1 is 200 um. The solid line portion in FIG. 8 and FIG. 9 represents the intensity of the electric field radiated from the antenna 10. Also, the scale drawn from the center to the outer periphery in FIG. 8 and FIG. 9 represents the antenna gain.

[0027] 9, the electromagnetic field pattern generated by the antenna 10 of the semiconductor chip 1 not attached to the printed circuit board 30 does not have symmetry in the vertically upward direction (positive z-axis direction) and vertically downward direction (negative z-axis direction) of the chip in front of the chip end E1 (positive y-axis direction). In other words, the antenna 10 of the semiconductor chip 1 not attached to the printed circuit board 30 may not be able to radiate a wireless signal in a desired direction. However, if the thickness of the semiconductor substrate 101 is small, the bias of the electromagnetic wave toward the semiconductor substrate 101 side is small, so that even the antenna 10 of the semiconductor chip 1 not attached to the printed circuit board 30 can radiate a wireless signal in a desired direction.

[0028] 7 and 8, the electromagnetic field pattern generated by the antenna 10 of the semiconductor chip 1 attached to the printed circuit board 30 has symmetry in the vertically upward and downward directions of the chip in front of the chip end portion E1. In other words, the antenna 10 of the semiconductor chip 1 attached to the printed circuit board 30 can radiate a wireless signal in a desired direction.

[0029] <Embodiment 2> FIG. 10 is a top view showing a configuration example of a semiconductor chip 2 on which an antenna (array antenna) 20 according to the present disclosure is mounted.

[0030] As shown in Fig. 10, the semiconductor chip 2 includes an antenna 20. The antenna 20 is composed of a plurality of antenna elements 10a having the same structure as the antenna 10. In the example of Fig. 10, the antenna 20 is composed of four antenna elements 10a. The four antenna elements 10a are arranged in an array on one semiconductor substrate so that the radiation direction of electromagnetic waves is the same.

[0031] In addition, the ground pattern formed on the first wiring layer M1 of a certain antenna element 10a and the ground pattern formed on the first wiring layer M1 of another adjacent antenna element 10a are continuous (electrically connected). In addition, the ground pattern formed on the second wiring layer M3 of a certain antenna element 10a and the ground pattern formed on the first wiring layer M1 of another adjacent antenna element 10a are electrically connected by vias or the like.

[0032] In this way, the antenna 20 of the present disclosure is equipped with an array of multiple antenna elements 10a having the same structure as the antenna 10, and is therefore able to radiate more directional radio signals forward (in the positive y-axis direction) from the chip end.

[0033] In the present embodiment, the semiconductor chip 2 is described as having four antenna elements 10a arranged in an array, each having the same structure as the antenna 10, but is not limited thereto. The semiconductor chip 2 may have two or more antenna elements 10a arranged in an array, each having the same structure as the antenna 10.

[0034] In addition, in the present embodiment, the case where the multiple antenna elements 10a are provided on one semiconductor substrate (chip) has been described as an example, but the present invention is not limited to this. The multiple antenna elements 10a may be provided separately on multiple semiconductor substrates. Therefore, for example, four semiconductor chips 1 may be provided in an array.

[0035] (An example of a wireless device 200 to which the semiconductor chip 2 is applied) Fig. 11 is a top view showing a configuration example of a wireless device 200 to which a semiconductor chip 2 is applied. As shown in Fig. 11, in the wireless device 200, the semiconductor chip 2 is provided on a ground layer 40 formed on a printed circuit board 30. As a result, the ground layer 40 acts as a reflector of electromagnetic waves, so that the antenna 20 provided on the semiconductor chip 2 can radiate a wireless signal in a desired direction.

[0036] Furthermore, in wireless device 200, semiconductor chip 2 is disposed so as to protrude from an end of printed circuit board 30. By adjusting the amount of protrusion of semiconductor chip 2, the pattern of the electromagnetic field generated by antenna 20 can be adjusted to a desired pattern.

[0037] Fig. 12 is a diagram showing the analysis results of the electric field strength of the antenna 10 of the semiconductor chip 1 attached to the printed circuit board 30, viewed from the top of the chip. As shown in Fig. 12, the electromagnetic field pattern generated by the antenna 20 of the semiconductor chip 2 attached to the printed circuit board 30 has stronger directionality in front of the chip end due to spatial synthesis of the four antenna elements.

[0038] As described above, the antenna according to the present disclosure is formed on a semiconductor chip such that the gap of the slot line gradually becomes larger from the center of the chip to the end of the chip. As a result, the antenna according to the present disclosure can realize a small wireless device capable of large-capacity communication using millimeter waves or sub-terahertz waves. Furthermore, the antenna according to the present disclosure can shorten the transmission path compared to when the antenna is provided outside the semiconductor chip, thereby reducing power loss and the number of parts.

[0039] Furthermore, a semiconductor chip equipped with an antenna as disclosed herein can be provided on the ground layer of a printed circuit board so as to extend beyond the edge of the printed circuit board, thereby enabling the electromagnetic field pattern of the antenna to be adjusted to a desired pattern.

[0040] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-mentioned embodiments. Various modifications that can be understood by a person skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be appropriately combined with other embodiments.

[0041] Each drawing is merely an example for describing one or more embodiments. Each drawing may relate not only to one particular embodiment, but to one or more other embodiments. As can be understood by those skilled in the art, various features or steps described with reference to any one drawing may be combined with features or steps shown in one or more other drawings to create an embodiment not explicitly shown or described, for example. Not all features or steps shown in any one drawing are necessary to describe an exemplary embodiment, and some features or steps may be omitted. The order of steps described in any drawing may be changed as appropriate.

[0042] A part or all of the above-described embodiments can be described as, but is not limited to, the following supplementary notes.

[0043] (Appendix 1) A semiconductor substrate; a first wiring layer formed on a main surface of the semiconductor substrate; an insulating layer formed of an insulating film laminated on the first wiring layer; A second wiring layer laminated on the insulating layer; An antenna comprising at least a first ground pattern formed in the first wiring layer so as to cover a part of a first region of a main surface of the semiconductor substrate; a second ground pattern formed in the second wiring layer such that, in a top view, a part of an outer periphery of the first ground pattern overlaps with a part of an outer periphery of the first ground pattern and such that a part of the second ground pattern overlapping with the first ground pattern is electrically connected to a first signal wiring extending from an integrated circuit; having the first ground pattern and the second ground pattern are formed so as to become increasingly separated from an overlapping region of the first ground pattern and the second ground pattern toward an end region of the semiconductor substrate when viewed from above. antenna.

[0044] (Appendix 2) a second region is further provided on the main surface of the semiconductor substrate between the integrated circuit formation region and the first region; a third ground pattern formed in the first wiring layer so as to cover the second region; a second signal wiring formed in the second wiring layer so as to connect the first signal wiring and a portion of the second ground pattern that overlaps with the first ground pattern in a top view; Further equipped with 2. The antenna described in claim 1.

[0045] (Appendix 3) a via hole electrically connecting the second ground pattern and the third ground pattern at a boundary between the first region and the second region; 6. An antenna as described in claim 2.

[0046] (Appendix 4) When viewed from above, a gap is formed between the second ground pattern and the third ground pattern. 4. An antenna as described in claim 3.

[0047] (Appendix 5) a length of the gap from a connection point between the second signal wiring and the second ground pattern to a connection point between the second ground pattern and the third ground pattern is ¼ wavelength of a radio signal; 5. An antenna as described in claim 4.

[0048] (Appendix 6) A plurality of antenna elements arranged in an array, Each of the plurality of antenna elements is an antenna as described in Supplementary Note 1. Array antenna.

[0049] (Appendix 7) An antenna as described in Appendix 1; an integrated circuit formed on the semiconductor substrate; A semiconductor chip comprising:

[0050] (Appendix 8) A printed circuit board; A ground layer formed on the printed circuit board; the semiconductor chip according to claim 7 provided on the ground layer so as to protrude from an end of the printed circuit board; A wireless device comprising:

[0051] (Appendix 9) An array antenna according to claim 6; an integrated circuit formed on the semiconductor substrate; A semiconductor chip comprising:

[0052] (Appendix 10) A printed circuit board; A ground layer formed on the printed circuit board; the semiconductor chip according to claim 9, which is provided on the ground layer so as to protrude from an end of the printed circuit board; A wireless device comprising: [Explanation of symbols]

[0053] 1. Semiconductor chip 1a Microstrip line formation area 1b Slot line formation region 1c Integrated circuit formation area 2. Semiconductor chips 10 Antennas 10a Antenna element 20 Antenna 30 Printed Circuit Board 40 Ground Layer 90 Integrated Circuits 100 Radio equipment 101 Semiconductor substrate 102a Grand Pattern 102b Grand Pattern 103a Insulating film 103b Insulating film 104a Signal wiring 104b Grand Pattern 111 void 112 Via 200 Radio equipment

Claims

1. A semiconductor substrate; a first wiring layer formed on a main surface of the semiconductor substrate; an insulating layer formed of an insulating film and laminated on the first wiring layer; A second wiring layer laminated on the insulating layer; An antenna comprising at least a first ground pattern formed in the first wiring layer so as to cover a part of a first region of the main surface of the semiconductor substrate; a second ground pattern formed in the second wiring layer such that, in a top view, a part of an outer periphery of the first ground pattern overlaps with a part of an outer periphery of the first ground pattern and such that a part of the second ground pattern overlapping with the first ground pattern is electrically connected to a first signal wiring extending from an integrated circuit; having the first ground pattern and the second ground pattern are formed so as to become increasingly separated from an overlapping region of the first ground pattern and the second ground pattern toward an end region of the semiconductor substrate when viewed from above. antenna.

2. a second region is further provided on the main surface of the semiconductor substrate between the integrated circuit formation region and the first region; a third ground pattern formed in the first wiring layer so as to cover the second region; a second signal wiring formed in the second wiring layer so as to connect the first signal wiring to a portion of the second ground pattern that overlaps with the first ground pattern in a top view; Further equipped with 2. The antenna of claim 1.

3. a via hole electrically connecting the second ground pattern and the third ground pattern at a boundary between the first region and the second region; 3. The antenna of claim 2.

4. When viewed from above, a gap is formed between the second ground pattern and the third ground pattern.

4. The antenna of claim 3.

5. a length of the gap from a connection point between the second signal wiring and the second ground pattern to a connection point between the second ground pattern and the third ground pattern is a quarter wavelength of a radio signal; 5. The antenna of claim 4.

6. A plurality of antenna elements arranged in an array, Each of the plurality of antenna elements is an antenna as claimed in claim 1. Array antenna.

7. An antenna according to claim 1; an integrated circuit formed on the semiconductor substrate; A semiconductor chip comprising:

8. A printed circuit board; A ground layer formed on the printed circuit board; 8. The semiconductor chip according to claim 7, which is provided on the ground layer so as to protrude from an end of the printed circuit board; A wireless device comprising:

9. An array antenna according to claim 6; an integrated circuit formed on the semiconductor substrate; A semiconductor chip comprising:

10. A printed circuit board; A ground layer formed on the printed circuit board; 10. The semiconductor chip according to claim 9, which is provided on the ground layer so as to protrude from an end of the printed circuit board; A wireless device comprising:

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