Electronic device and manufacturing method of the same

Abstract

To improve the performance of an electronic device.SOLUTION: A terminal TM1 of an electronic device, contains: a metal layer ML2 formed by an aluminum; and a metal layer ML3 that is arranged onto the metal layer ML2, bonded to a cap film CP1, and formed by titanium. The cap film CP1 is formed by titanium, and contains a metal film MF1 bonded to the metal layer ML3. The metal film MF1 contains: a contact part CPc that covers a whole of a part exposed from an insulation layer 16 in an open part 16H1 of an insulation layer 16 from the metal layer ML3 of the terminal TM1; and a peripheral edge part CPp that is on an outside of the open part 16H1, and arranged so as to continuously surround a circumference of the contact part CPc in a plan surface view. The insulation layer 16 is interposed between the peripheral edge part CPp of the metal film MF1 and the terminal TM1.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to electronic devices and methods for manufacturing the same. [Background technology]

[0002] There is an electronic device in which electronic components are mounted on a plurality of electrodes arranged on a substrate. For example, JP 2014-197619 A (Patent Document 1) describes an electronic device in which LED (Light Emitting Diode) elements are mounted on a plurality of electrodes arranged on a substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-197619 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the case of an electronic device in which an electronic component is mounted on a terminal formed on a substrate, bump electrodes may be formed on the substrate to facilitate connection between the electrodes of the electronic component and the terminals on the substrate. According to the study by the inventors of the present application, when an electronic device on which an electronic component is mounted is observed, it has been found that voids may be formed around the bump electrodes.

[0005] An object of the present invention is to provide a technique for improving the performance of electronic devices. [Means for solving the problem]

[0006] An electronic device according to an embodiment includes a first substrate, a first terminal disposed on the first substrate, an inorganic insulating layer made of an inorganic material, a first insulating layer covering the first terminal, a first opening formed in the first insulating layer, a first cap film connected to the first terminal at the first opening, and a first bump electrode electrically connected to the first terminal via the first cap film. The first terminal includes a first metal layer made of aluminum, and a second metal layer made of titanium disposed on the first metal layer in close contact with the first metal layer and bonded to the first cap film at the first opening. The first cap film includes a first metal film made of titanium and bonded to the second metal layer at the first opening. The first metal film includes a contact portion covering the entire portion of the second metal layer of the first terminal that is exposed from the first insulating layer at the first opening, and a peripheral portion that is located outside the first opening and is disposed so as to continuously surround the periphery of the contact portion in a plan view. The first insulating layer is interposed between the peripheral edge portion of the first metal film and the first terminal.

[0007] A method for manufacturing an electronic device according to another embodiment includes the steps of (a) forming a first terminal on a first substrate, (b) forming a first insulating layer made of an inorganic material so as to cover the first terminal, (c) forming a first opening in the first insulating layer to expose a portion of the first terminal from the first insulating layer, (d) forming a first cap film so as to cover the first opening, and (e) forming a bump electrode on the first cap film. The step (a) includes the steps of (a1) forming a first metal layer made of aluminum, and (a2) forming a second metal layer made of titanium on the first metal layer so as to be in close contact with the first metal layer. The step (d) includes the step of (d1) forming a first metal film made of titanium and bonded to the second metal layer in the first opening. The first metal film includes a contact portion covering the entire portion of the second metal layer of the first terminal that is exposed from the first insulating layer in the first opening, and a peripheral portion that is located outside the first opening and is disposed so as to continuously surround the periphery of the contact portion in a plan view. The first insulating layer is interposed between the peripheral portion of the first metal film and the first terminal. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing an example of the configuration of a micro LED display device, which is an embodiment of an electronic device. [Diagram 2] 2 is a circuit diagram showing a configuration example of a circuit in the periphery of the pixel shown in FIG. 1. [Diagram 3] 2 is an enlarged transparent plan view showing an example of a peripheral structure of LED elements arranged in each of a plurality of pixels of the display device shown in FIG. [Figure 4] FIG. 4 is an enlarged cross-sectional view taken along line AA in FIG. [Diagram 5] 4 is an enlarged plan view showing one of the terminals shown in FIG. 3. FIG. [Figure 6] FIG. 6 is an enlarged cross-sectional view taken along line BB in FIG. 5. [Figure 7] FIG. 7 is an enlarged cross-sectional view showing a study example for FIG. 6. [Figure 8] FIG. 7 is an enlarged cross-sectional view showing another study example for FIG. 6. [Figure 9] 7 is an enlarged cross-sectional view showing, on an enlarged scale, another terminal of the two terminals shown in FIG. 4 that is different from that shown in FIG. 6. [Figure 10] FIG. 1 is an explanatory diagram showing an example of a process flow of a method for manufacturing a display device, which is an embodiment of an electronic device. [Figure 11] FIG. 11 is an enlarged cross-sectional view showing an insulating layer forming step in FIG. [Figure 12] 11 is an enlarged cross-sectional view showing the opening forming step of FIG. 10. FIG. [Figure 13] 11 is an enlarged cross-sectional view showing the first metal film forming step shown in FIG. 10. FIG. [Figure 14] 11 is an enlarged cross-sectional view showing the second metal film forming step shown in FIG. 10. FIG. [Figure 15] 11 is an enlarged cross-sectional view showing a third metal film forming step shown in FIG. 10. FIG. [Figure 16] 11 is an enlarged cross-sectional view showing a fourth metal film forming step shown in FIG. 10. FIG. [Figure 17] FIG. 7 is an enlarged cross-sectional view showing a modification of FIG. 6. [Figure 18] FIG. 10 is an enlarged cross-sectional view showing a modification of FIG. [Figure 19] 11 is an explanatory diagram showing an example of a process flow of a manufacturing method of a display device which is a modified example of the display device shown in FIG. [Figure 20] 20 is an enlarged cross-sectional view showing the seed layer formation step shown in FIG. 19. [Figure 21] 20 is an enlarged cross-sectional view showing the resist film forming step shown in FIG. 19. [Figure 22] 20 is an enlarged cross-sectional view showing the second metal layer formation step shown in FIG. 19. [Diagram 23] 20 is an enlarged cross-sectional view showing the third metal layer formation step shown in FIG. 19. [Figure 24] 20 is an enlarged cross-sectional view showing a bump electrode forming step shown in FIG. 19. [Diagram 25] 20 is an enlarged cross-sectional view showing a resist film removing step shown in FIG. 19. [Figure 26]20 is an enlarged cross-sectional view showing the seed layer removing step shown in FIG. 19. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. Note that the disclosure is merely an example, and those who are skilled in the art can easily come up with appropriate modifications while maintaining the gist of the invention, which are naturally included in the scope of the present invention. In addition, in order to make the explanation clearer, the drawings may show the width, thickness, shape, etc. of each part in a schematic manner compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same or related symbols, and detailed explanations may be omitted as appropriate.

[0010] In the following embodiments, a micro LED display device equipped with a plurality of micro LED elements and a bump electrode array device before the micro LED elements are mounted will be described as examples of electronic devices in which a bump electrode array for mounting a plurality of electronic components is arranged.

[0011] In this application, when describing the materials constituting a specific component, the expression "component A is made of B" may be used. This means that "among the materials constituting component A, the material that is contained in the largest amount by weight is B." Therefore, component A may contain no impurities and may be made up purely of B, or it may contain materials other than B as impurities.

[0012] <Electronic equipment> First, a configuration example of a micro LED display device, which is one aspect of the electronic device of the present embodiment, will be described. FIG. 1 is a plan view showing a configuration example of a display device, which is one embodiment. In FIG. 1, the boundary between the display area DA and the peripheral area PFA, the control circuit 5, the driving circuit 6, and the multiple pixels PIX are each indicated by a two-dot chain line. FIG. 2 is a circuit diagram showing a configuration example of a circuit around the pixel shown in FIG. 1. Note that the pixel circuit PC shown in FIG. 2 shows an example of an equivalent circuit corresponding to one pixel PIX shown in FIG. 1.

[0013] FIG. 1 shows an X direction and a Y direction. The X direction and the Y direction intersect with each other. In the example described below, the X direction is perpendicular to the Y direction. In the following, the XY plane including the X direction and the Y direction will be described as a plane parallel to the display surface of the display device. In the following description, unless otherwise specified, the term "planar view" means a view of a plane parallel to the XY plane. In addition, as described later, the normal direction to the XY plane will be described as the "Z direction" or thickness direction. The X direction, the Y direction, and the Z direction are directions that intersect with each other, and more specifically, are directions that are perpendicular to each other.

[0014] In the explanation of this specification, it may be stated that "A" is "covered" by "B." "A is covered by B" means that A entirely overlaps with B in a planar view of the above-mentioned XY plane. "A is covered by B" can also be rephrased as "A entirely overlaps with B in the thickness direction (Z direction)" as described above.

[0015] 1, the display device DSP1 of the present embodiment has a display area DA, a peripheral area PFA surrounding the periphery of the display area DA in a frame shape, and a plurality of pixels PIX arranged in a matrix within the display area DA. The display device DSP1 also has a substrate 10, a control circuit 5 formed on the substrate 10, and a drive circuit 6 formed on the substrate 10.

[0016] The control circuit 5 is a control circuit that controls the driving of the display function of the display device DSP1. For example, the control circuit 5 is a driver IC (Integrated Circuit) mounted on the substrate 10. In the example shown in FIG. 1, the control circuit 5 is arranged along one of the four short sides of the substrate 10. In addition, in the example of the present embodiment, the control circuit 5 includes a signal line driving circuit (video driver) that drives the video signal lines VL (see FIG. 2) connected to the multiple pixels PIX. However, the position and configuration example of the control circuit 5 are not limited to the example shown in FIG. 1, and there are various modified examples. For example, in FIG. 1, a circuit board such as a flexible board may be connected to the position shown as the control circuit 5, and the above-mentioned driver IC may be mounted on the circuit board. In addition, for example, the signal line driving circuit that drives the video signal lines VL may be formed separately from the control circuit 5.

[0017] The driving circuit (scanning driver) 6 is a circuit that drives the scanning signal lines GLB, GLR, and GLS (see FIG. 2) of the multiple pixels PIX. The driving circuit 6 drives the multiple scanning signal lines based on a control signal from the control circuit 5. In the example shown in FIG. 1, the driving circuit 6 is arranged along each of two long sides of the four sides of the substrate 10. In the example shown in FIG. 1, the display area DA is arranged between the two driving circuits 6 in a plan view. However, the position and configuration example of the driving circuit 6 are not limited to the example shown in FIG. 1, and there are various modified examples. For example, in FIG. 1, a circuit board such as a flexible board may be connected to the position shown as the control circuit 5, and the above-mentioned driving circuit 6 may be mounted on the circuit board.

[0018] Next, a configuration example of a pixel circuit PC that drives the pixel PIX shown in Fig. 1 will be described with reference to Fig. 2. Note that Fig. 2 representatively illustrates one pixel circuit PC that drives one pixel. Each of the multiple pixels PIX shown in Fig. 1 includes a circuit similar to the pixel circuit PC shown in Fig. 2. The pixel circuit PC is a voltage signal type circuit that controls the light emission state of an LED element (inorganic light emitting diode element, diode element) 20 in response to a video signal Vsg supplied from a control circuit 5 (see Fig. 1).

[0019] 2, the pixel PIX includes an LED element 20. The LED element 20 is the above-mentioned micro light-emitting diode. The LED element 20 has an anode electrode 20EA (see FIG. 3 described later) and a cathode electrode 20EC (see FIG. 3 described later).

[0020] The display device DSP1 has multiple types of wiring in the display area DA. These wirings include multiple scanning signal lines GLS, GLR, and GLB, multiple video signal lines VL, multiple power lines PL1, multiple power lines PL2, and multiple reset lines RSL.

[0021] The scanning signal lines GLS, GLR, GLB extend in the X direction and are connected to the driving circuit 6. For example, as shown in Fig. 1, among the pixels PIX arranged in the Y direction, the scanning signal lines GLS, GLR, GLB for driving the even-numbered pixels PIX are connected to one driving circuit 6, and the scanning signal lines GLS, GLR, GLB for driving the odd-numbered pixels PIX are connected to the other driving circuit 6. As another example, there is a case where any one of the scanning signal lines GLS, GLR, GLB is connected to one driving circuit 6 and the remaining is connected to the other driving circuit 6, for example, the scanning signal lines GLS, GLR are all connected to one driving circuit 6 and the scanning signal lines GLB are all connected to the other driving circuit 6.

[0022] The video signal line VL, the power lines PL1 and PL2, and the reset line RSL extend in the Y direction. The video signal line VL is connected to a control circuit 5 (see FIG. 1). A video signal Vsg and an initialization signal are supplied to the video signal line VL from the control circuit 5. A high potential Pvdd is supplied to the power line PL1 from the control circuit 5. A low potential Pvss lower than the high potential Pvdd is supplied to the power line PL2 from the control circuit 5. A reset signal Vrs is supplied to the reset line RSL from the control circuit 5.

[0023] The control circuit 5 outputs a start pulse signal and a clock signal (not shown) to the drive circuit 6. The drive circuit 6 includes a plurality of shift register circuits, and sequentially transfers the start pulse signal to the next-stage shift register circuit in response to the clock signal, and sequentially supplies scanning signals to the scanning signal lines GLS, GLR, and GLB.

[0024] The pixel circuit PC controls the LED element 20 in response to a video signal Vsg supplied to a video signal line VL. To achieve such control, the pixel circuit PC in this embodiment has a reset transistor (switching element) RST, a pixel selection transistor (switching element) SST, an output transistor (switching element) BCT, a drive transistor (switching element) DRT, a storage capacitance Cs, and an auxiliary capacitance Cad. The auxiliary capacitance Cad is an element provided to adjust the amount of light emission current, and may not be necessary in some cases.

[0025] The reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT are switching elements made of thin film transistors (TFTs). The conductivity type of the thin film transistors is not particularly limited, and for example, all of the transistors may be made of N-channel TFTs, or at least one of them may be made of P-channel TFTs.

[0026] In this embodiment, the reset transistor RST, the pixel selection transistor SST, the output transistor BCT, and the drive transistor DRT are formed in the same process and in the same layer structure, and have a bottom gate structure using polycrystalline silicon for the semiconductor layer. As another example, the reset transistor RST, the pixel selection transistor SST, the output transistor BCT, and the drive transistor DRT may have a top gate structure. Note that an oxide semiconductor, a polycrystalline GaN semiconductor, or the like may be used for the semiconductor layer.

[0027] The reset transistor RST, the pixel selection transistor SST, the output transistor BCT, and the drive transistor DRT each have a source electrode, a drain electrode, and a gate electrode. The gate electrode of each transistor can be referred to as a control electrode. The source electrode and the drain electrode of each transistor can be referred to simply as electrodes.

[0028] The drive transistor DRT and the output transistor BCT are connected in series between the power supply line PL1 and the power supply line PL2 with the LED element 20. The high potential Pvdd supplied to the power supply line PL1 is set to, for example, 10 V, and the low potential Pvss supplied to the power supply line PL2 is set to, for example, 1.5 V.

[0029] The drain electrode of the output transistor BCT is connected to the power supply line PL1. The source electrode of the output transistor BCT is connected to the drain electrode of the drive transistor DRT. The gate electrode of the output transistor BCT is connected to the scanning signal line GLB. The output transistor BCT is turned on and off by a control signal Gsb provided to the scanning signal line GLB. Here, on represents a conductive state, and off represents a non-conductive state. The output transistor BCT controls the light emitting time of the LED element 20 based on the control signal Gsb.

[0030] A source electrode of the drive transistor DRT is connected to one electrode (here, the anode electrode 20EA) of the LED element 20. The other electrode (here, the cathode electrode 20EC) of the LED element 20 is connected to the power supply line PL2. The drive transistor DRT outputs a drive current to the LED element 20 according to the video signal Vsg.

[0031] The source electrode of the pixel selection transistor SST is connected to the video signal line VL. The drain electrode of the pixel selection transistor SST is connected to the gate electrode of the drive transistor DRT. The gate electrode of the pixel selection transistor SST is connected to the scanning signal line GLS that functions as a gate wiring for signal writing control. The pixel selection transistor SST is turned on and off by a control signal Gss supplied from the scanning signal line GLS, and switches between connection and disconnection between the pixel circuit PC and the video signal line VL. That is, when the pixel selection transistor SST is turned on, the video signal Vsg or the initialization signal of the video signal line VL is supplied to the gate electrode of the drive transistor DRT.

[0032] The source electrode of the reset transistor RST is connected to the reset wiring RSL. The drain electrode of the reset transistor RST is connected to the source electrode of the drive transistor DRT and the anode of the LED element 20. The gate electrode of the reset transistor RST is connected to the scanning signal line GLR that functions as a reset control gate wiring. The reset transistor RST is turned on and off by a control signal Grs supplied from the scanning signal line GLR. By switching the reset transistor RST on, the potential of the source electrode of the drive transistor DRT and the anode of the LED element 20 can be reset by a reset signal Vrs of the reset wiring RSL. In other words, the reset wiring RSL is a wiring for resetting the voltage of the LED element 20.

[0033] The storage capacitor Cs is connected between the gate electrode and source electrode of the drive transistor DRT, and the auxiliary capacitor Cad is connected between the source electrode of the drive transistor DRT and the power line PL2.

[0034] The control signals Gss, Grs, and Gsb are sequentially supplied to the scanning signal lines GLS, GLR, and GLB of each line (a series of pixels PIX arranged in the X direction) by the drive circuit 6 based on the above-mentioned start pulse signal and clock signal. Also, based on the signal supplied from the control circuit 5 shown in FIG. 2, the control circuit 5 sequentially supplies the video signal Vsg and the initialization signal to each video signal line VL. The charge held in the holding capacitor Cs is initialized with the supply of the initialization signal as the video signal Vsg is supplied.

[0035] In the configuration as described above, the pixel circuit PC is driven by the control signals Gss, Grs, and Gsb supplied to the scanning signal lines GLS, GLR, and GLB, and the LED element 20 emits light with a luminance corresponding to the video signal Vsg of the video signal line VL.

[0036] <Peripheral Structure of LED Element> Next, the peripheral structure of the LED element arranged in the pixel PIX shown in FIG. 1 will be described. FIG. 3 is a transparent enlarged plan view showing an example of the peripheral structure of the LED element arranged in each of a plurality of pixels of the display device shown in FIG. 1. FIG. 4 is an enlarged cross-sectional view taken along the line A-A of FIG. 3.

[0037] In FIG. 3, the conductor pattern and the cap films CP1 and CP2 arranged in the wiring layer WL4 shown in FIG. 4 are shown by solid lines. In FIG. 3, the outlines of the LED element 20 and the electrodes provided in the LED element 20 are shown by two-dot chain lines. Also, each of the pixels PIXA, PIXB, and PIXC shown in FIG. 3 has the same structure. For this reason, in FIG. 4, the structure of the pixel PIXA (see FIG. 3) is shown as a representative example, but the pixels PIXB and PIXC shown in FIG. 3 also have the same cross-sectional structure.

[0038] In the following description, the terms "terminal TM1" and "terminal TM2" are used, but "terminal" means a conductor pattern including a terminal portion for electrically connecting an external device and can be read as "terminal pattern" and applied accordingly.

[0039] Furthermore, the pixel circuit PC shown in Fig. 2 is a circuit corresponding to each of the pixels PIXA, PIXB, and PIXC shown in Fig. 3. Therefore, each of the pixels PIXA, PIXB, and PIXC shown in Fig. 3 includes the reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT described with reference to Fig. 2. Similarly, each of the pixels PIXA, PIXB, and PIXC shown in Fig. 3 includes the storage capacitance Cs and auxiliary capacitance Cad described with reference to Fig. 2.

[0040] As shown in Fig. 4, the display device DSP1 has a substrate structure SUB1 and an LED element (inorganic light emitting diode element) 20 mounted on the substrate structure SUB1. The substrate structure SUB1 of the display device DSP1 has a plurality of insulating layers arranged between a plurality of wiring layers. The LED element 20 is mounted on a wiring layer WL4 that is arranged in the uppermost layer of the plurality of wiring layers.

[0041] The substrate structure SUB1 of the display device DSP1 has a substrate 10. The substrate 10 has a surface 10f and a surface 10b opposite to the surface 10f. A plurality of wiring layers and a plurality of insulating layers are laminated on the surface 10f of the substrate 10. The substrate 10 is, for example, a glass substrate made of glass. However, there are various modifications to the material constituting the substrate 10, and for example, a resin substrate made of resin may be used.

[0042] The substrate structure SUB1 has a transistor as a switching element. In Fig. 4, a drive transistor DRT is illustrated as an example of a switching element arranged on the substrate 10. However, the reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT described with reference to Fig. 2 are arranged on the substrate 10 (specifically, on the insulating layer 11). Each of the reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT shown in Fig. 2 has a similar structure to the drive transistor DRT shown in Fig. 4 described later.

[0043] As shown in Fig. 3, the display device DSP1 has a plurality of LED elements 20. Fig. 3 illustrates, among the plurality of LED elements 20 included in the display device, an LED element 20A, an LED element 20B arranged next to the LED element 20A, and an LED element 20C arranged next to the LED element 20B.

[0044] As shown in Fig. 4, the LED element 20 has a surface 20f and a surface 20b opposite to the surface 20f. The LED element 20 also has a plurality of electrodes (two in Fig. 3) arranged on the surface 20f. The plurality of electrodes included in the LED element 20 include an anode electrode 20EA and a cathode electrode 20EC. The anode electrode 20EA is electrically connected to a terminal TM1 via a bump electrode 30. The cathode electrode 20EC is electrically connected to a terminal TM2 via a bump electrode 31.

[0045] The terminals TM1 and TM2 are conductor patterns that include portions of the conductor patterns of the substrate structure SUB1 that function as “terminals” for electrically connecting the LED element 20 to the substrate structure SUB1. The terminals TM1 and TM2 are each disposed on the substrate 10.

[0046] The display device DSP1 displays an image by driving each of the multiple LED elements 20 mounted on the substrate structure SUB1.

[0047] 4, the multiple wiring layers included in the display device DSP1 include a wiring layer WL4, a wiring layer WL3, a wiring layer WL2, and a wiring layer WL1 that are stacked in this order from the wiring layer WL4 toward the substrate 10. The multiple insulating layers included in the display device DSP1 include insulating layers 11, 12, 13, 14, 15, and 16 that are stacked in this order from the top of the surface 10f of the substrate 10.

[0048] The insulating layer 11 is an underlying layer for the thin-film transistor, and is an inorganic insulating layer made of an inorganic material. The wiring layer WL1 is disposed on the insulating layer 11 and is covered with an insulating layer 12. The conductor pattern formed on the wiring layer WL1 includes the gate electrode EG shown in FIG. 4 and the scanning signal lines GLB, GLS, and GLR described with reference to FIG. 2. The insulating layer 12 is also an inorganic insulating layer made of an inorganic material. A portion of the insulating layer 12 disposed between the gate electrode EG and the semiconductor layer 50 of the transistor functions as a gate insulating film.

[0049] The drive transistor DRT including the gate electrode EG has a semiconductor layer 50, a gate electrode EG, a source electrode ES, and a drain electrode ED. In the example shown in FIG. 4, a thin film transistor having a bottom gate structure is shown as an example, but as described above, a top gate structure may also be used. The gate electrode EG is disposed on an insulating layer 11. The semiconductor layer 50 is disposed on an insulating layer 12. A part of the semiconductor layer 50 corresponds to a source region, and a source electrode ES is connected to the source region. Another part of the semiconductor layer 50 corresponds to a drain region, and a drain electrode ED is connected to the drain region. The region between the source region and the drain region functions as a channel region.

[0050] The wiring layer WL2 is disposed on an insulating layer 13 that covers the drive transistor DRT. The insulating layer 13 is an inorganic insulating layer made of an inorganic material. The conductor pattern formed on the wiring layer WL2 includes wirings connected to each of the multiple transistors. For example, as shown in FIG. 4, the wiring pattern MW1 connected to the source electrode ES of the drive transistor DRT is included in the wiring layer WL2. In addition, the conductor pattern formed on the wiring layer WL2 includes the video signal line VL, the power line PL1, the power line PL2, and the reset line RSL shown in FIG. 2.

[0051] The wiring layer WL2 is electrically connected to the conductor pattern MP1 via a contact hole CH3 formed in the insulating layer 14, and includes a wiring pattern MW1 electrically connected to the electrode (source electrode ES) of the drive transistor DRT.

[0052] The insulating layer 14 covering the wiring layer WL2 and the insulating layer 15 laminated on the insulating layer 14 are each an organic insulating film made of an organic material. The insulating layer 14 is an insulating layer disposed between the wiring layer WL2 and the wiring layer WL3. The insulating layer 15 is an insulating layer disposed between the wiring layer WL3 and the wiring layer WL4. As shown in FIG. 4, contact holes are used for the electrical connection between the wiring layer WL2 and the wiring layer WL3, and between the wiring layer WL3 and the wiring layer WL4. The organic insulating layer has superior characteristics for filling an opening (e.g., a contact hole) compared to an inorganic insulating layer. In other words, in the case of an organic insulating layer, even if there is an opening in the base, it is easy to flatten the upper surface. For this reason, the insulating layer 14 and the insulating layer 15 in which a large number of contact holes are formed are each made of an organic material. An example of the organic material constituting the insulating layer 14 and the insulating layer 15 is an acrylic resin.

[0053] 4 shows contact holes CH1, CH2, and CH3 among the many contact holes provided in the substrate structure SUB1. Contact hole CH1 is an opening for connecting terminal TM1 and conductor pattern MP1 of wiring layer WL3. Contact hole CH2 is an opening for connecting terminal TM2 and conductor pattern MP2 of wiring layer WL3. Contact hole CH3 is an opening for connecting conductor pattern MP1 of wiring layer WL3 and wiring pattern MW1 of wiring layer WL2.

[0054] The wiring layer WL3 includes a conductor pattern MP1 electrically connected to the terminal TM1 through a contact hole CH1 formed in the insulating layer 15, and a conductor pattern MP2 made of the same metal as the conductor pattern MP1 and electrically connected to the terminal TM2 through a contact hole CH2 formed in the insulating layer 15.

[0055] The conductor pattern MP1 has a flat portion connected to the terminal TM1 at the bottom surface of the contact hole CH1 and a contact portion embedded in the contact hole CH3 and connected to the wiring layer WL2. As shown in Fig. 3, the conductor pattern MP2 is a large-area pattern that extends across multiple pixels PIX.

[0056] The conductor pattern MP1, the conductor pattern MP2, the terminal TM1, and the terminal TM2 shown in Fig. 4 are each made of, for example, the same metal material. Although details will be described later, in this embodiment, the conductor pattern MP1, the conductor pattern MP2, the terminal TM1, and the terminal TM2 are each a laminated film of a titanium layer made of titanium, an aluminum layer made of aluminum, and a titanium layer made of titanium.

[0057] The wiring layer WL4 is the uppermost wiring layer among the multiple wiring layers, and includes a terminal (conductor pattern) TM1 electrically connected to the anode electrode 20EA of the LED element 20A and a terminal (conductor pattern) TM2 electrically connected to the cathode electrode 20EC of the LED element 20A.

[0058] The wiring layer WL4 is covered with an insulating layer 16 made of an inorganic material. The insulating layer 16 is an inorganic insulating layer made of, for example, silicon nitride or silicon oxide. The terminals TM1 and TM2 are each covered with the insulating layer 16.

[0059] In detail, the terminal TM1 has a terminal portion (which can be said to be a flat portion) connected to the cap film CP1 at the opening of the insulating layer 16, and a contact portion embedded in the contact hole CH1 and connected to the wiring layer WL3. The contact portion is covered by the insulating layer 16. Similarly, the terminal TM2 has a terminal portion connected to the cap film CP2 at the opening of the insulating layer 16, and a contact portion embedded in the contact hole CH2 and connected to the wiring layer WL3. The contact portion is covered by the insulating layer 16. Each of the terminals TM1 and TM2 is an external terminal of the substrate structure SUB1.

[0060] An opening 16H1 is partially formed in the insulating layer 16. The terminal TM1 disposed on the wiring layer WL4 is connected to the cap film CP1 at the opening 16H1 formed in the insulating layer 16. Similarly, the terminal TM2 disposed on the wiring layer WL4 is connected to the cap film CP2 at the opening 16H2 formed in the insulating layer 16.

[0061] Specifically, the cap film CP1 and the terminal TM1 are joined at the bottom of the opening 16H1. The cap film CP2 and the terminal TM2 are joined at the bottom of the opening 16H2. The bottom of the opening 16H1 refers to a portion of the opening 16H1 that penetrates the insulating layer 16, in other words, a portion of the terminal TM1 that is exposed from the insulating layer 16.

[0062] Although details will be described later, each of the cap film CP1 and the cap film CP2 includes a titanium film made of titanium. The titanium film is disposed at the bonding interface with the terminal TM1 or the terminal TM2.

[0063] The bump electrode 30 is electrically connected to the terminal TM1 via the cap film CP1. The bump electrode 31 is electrically connected to the terminal TM2 via the cap film CP2. The anode electrode 20EA of the LED element 20A is electrically connected to the terminal TM1 via the bump electrode 30 and the cap film CP1. The cathode electrode 20EC of the LED element 20A is electrically connected to the terminal TM2 via the bump electrode 31 and the cap film CP2.

[0064] Each of the bump electrodes 30 and 31 is made of, for example, tin.

[0065] <Cap film and bump electrodes> Fig. 5 is an enlarged plan view showing one of the terminals shown in Fig. 3. Fig. 6 is an enlarged cross-sectional view taken along line BB in Fig. 5. In Fig. 5, the metal film MF1 arranged in the lowermost layer of the metal films included in the cap film CP1 shown in Fig. 6 is shown by a solid line. In Fig. 5, the outline of the metal film MF4 arranged in the uppermost layer of the metal films included in the cap film CP1 shown in Fig. 6 and the outline of the bump electrode 30 are shown by a two-dot chain line. In Fig. 5, the outline of the terminal TM1 is shown by a dotted line.

[0066] As shown in FIG. 6, the terminal TM1 has metal layers ML1, ML2, and ML3 stacked in this order on an insulating layer 15 made of an organic material. The metal layer ML1 is made of titanium. The metal layer ML1 is disposed on the insulating layer 15 in close contact with the insulating layer 15. The metal layer ML2 is made of aluminum. The metal layer ML2 is disposed on the metal layer ML1 in close contact with the metal layer ML3. The metal layer ML3 is made of titanium. The metal layer ML3 is disposed on the metal layer ML2 in close contact with the metal layer ML2. The metal layer ML3 is joined to the cap film CP1 at the bottom of the opening 16H1.

[0067] The metal layer ML2 is a main conductive layer of the terminal TM1 which is a conductive pattern. Therefore, the thickness of the metal layer ML2 (for example, 500 nm) is thicker than the thickness of the metal layer ML1 (for example, 50 nm) and the thickness of the metal layer ML3 (for example, 50 nm).

[0068] Aluminum constituting the metal layer ML2 is suitable as a material for forming wiring patterns and terminal patterns because of its high electrical conductivity and ease of pattern processing. However, from the viewpoint of suppressing damage to the wiring pattern caused by stress accompanying thermal expansion of the wiring pattern or electromigration, it is preferable that a titanium film is disposed so as to adhere closely to the metal layer ML3. The example shown in FIG. 6 shows an embodiment in which the metal layer ML2 is sandwiched between the metal layer ML1 and the metal layer ML3. However, as a modified example, there is a case in which the metal layer ML1 is not provided.

[0069] The cap film CP1 includes a metal film MF1 made of titanium and joined to the metal layer ML3 at the bottom of the opening 16H1. In the example shown in Fig. 6, the cap film CP1 has metal films MF2, MF3, and MF4 stacked on the metal film MF1. The details of the metal films MF2, MF3, and MF4 will be described later.

[0070] The metal film MF1 has a contact portion CPc that covers the entire portion of the metal layer ML3 of the terminal TM1 shown in FIG. 6 that is exposed from the insulating layer 16 at the bottom of the opening 16H1. The metal film MF1 is located outside the opening 16H1 and includes a peripheral portion CPp that is disposed so as to continuously surround the periphery of the contact portion CPc in a plan view, as shown in FIG. 5. "Continuously surrounding the periphery of the contact portion CPc in a plan view" means that the peripheral portion CPp is not divided midway, as shown in FIG. 6. In a cross-sectional view, the metal film MF1 has a portion that extends along the side surface of the opening 16H1 between the contact portion CPc and the peripheral portion CPp. Therefore, the contact portion CPc and the peripheral portion CPp are spaced apart.

[0071] As shown in Fig. 6, an insulating layer 16 is interposed between the peripheral portion CPp of the metal film MF1 and the terminal TM1. Hereinafter, a description will be given with reference to Fig. 7 and Fig. 8 showing a study example of Fig. 6. Fig. 7 and Fig. 8 are each an enlarged cross-sectional view showing a study example of Fig. 6.

[0072] 7, the structure of the terminal TM3 differs from that of the terminal TM1 shown in FIG 6. Moreover, the structure of the cap film CP3 of the display device DSP2 differs from that of the cap film CP1 shown in FIG 6.

[0073] The terminal TM3 shown in Fig. 7 is a laminated film having a metal layer ML1 made of titanium and a metal layer ML2 made of aluminum. Of the laminated metal layers, the metal layer ML2 is disposed at the bonding interface with the cap film CP3. The cap film CP3 shown in Fig. 7 is also a laminated film having a metal film MF3 made of copper and a metal film MF4 made of nickel. Of the laminated metal films, the metal film MF3 is disposed at the bonding interface with the terminal TM3. That is, in the case of the study example shown in Fig. 7, aluminum and copper are bonded at the bonding interface between the terminal TM3 and the cap film CP3.

[0074] In the manufacturing process of the display device DSP2, the process of forming the cap film CP3 on the terminal TM3 is performed as follows. That is, after the terminal TM3 is formed, an insulating layer 16 is formed so as to cover the terminal TM3. Next, an opening is formed so that a part of the terminal TM3 is exposed from the insulating layer 16. Next, the aluminum oxide film formed on the surface of the metal layer ML2 exposed from the opening of the insulating layer 16 is removed. As a method for removing the aluminum oxide film, for example, so-called zincate treatment can be used.

[0075] Next, the metal film MF3 of the cap film CP3 is formed by electroplating on the surface of the metal layer ML2 exposed from the opening of the insulating layer 16. According to the study by the inventors of the present application, it was found that a part of the metal layer ML2 is eroded by the plating solution for copper plating in the plating process for forming the metal film MF3. From the viewpoint of reducing the resistance of the part electrically connecting the bump electrode 30 and the terminal TM3, it is preferable that the thickness of the metal film MF3 made of copper is thick.

[0076] However, as described above, a part of the metal layer ML2 is eroded by the plating solution for copper plating, and the thicker the metal film MF3 is, the more the erosion progresses, and a cavity (void) 32 occurs between the insulating layer 16 and the metal layer ML2 as shown in FIG. 7. When a temperature cycle load is applied during the manufacturing process of the display device DSP2 or to the completed display device DSP2, the gas (e.g., air) in the cavity 32 expands and contracts repeatedly. Therefore, stress is applied to the members around the cavity 32. Depending on the level of this stress, the insulating layer 16 may be destroyed, or the connection interface between the terminal TM3 and the cap film CP3 may peel off. In other words, in the case of the display device DSP2, there is a concern that the occurrence of the cavity 32 may reduce the reliability of electrical connection around the bump electrode 30.

[0077] Next, the display device DSP3 shown in FIG. 8 has a cap film CP4 whose structure differs from that of the cap film CP1 shown in FIG.

[0078] In the case of the display device DSP3, a metal layer ML3 made of titanium is disposed at the bonding interface with the cap film CP4. Therefore, in the process of forming the metal film MF3 made of copper, it is possible to prevent a part of the metal layer ML2 from being eroded by the plating solution for copper plating. In addition, the following method can be applied as a method for forming the metal film MF3.

[0079] That is, first, a copper seed layer is formed by sputtering on the surface of the insulating layer 16 and on the surface of the terminal TM1 exposed from the insulating layer 16 at the opening. Next, a resist mask (not shown) is formed so as to cover the copper seed layer, and then an opening is formed in the resist mask by photolithography. Next, a copper film is grown on the copper seed layer exposed from the resist mask at the opening of the resist mask by, for example, an electroplating method. After that, a metal film MF4 made of nickel and a bump electrode 30 made of tin are formed on the copper film by utilizing the opening of the resist mask. After that, the resist mask and the copper seed layer are removed in the portions not overlapping with the bump electrode 30, thereby obtaining the bump structure of the display device DSP3 shown in FIG. 8.

[0080] However, in the case of the display device DSP3, dissimilar metals are bonded at the bonding interface between the terminal TM1 and the cap film CP4, so it is necessary to thoroughly remove the titanium oxide film or to perform a process to remove contaminants such as carbon before forming the metal film MF3 of the cap film CP4.

[0081] The following method can be exemplified as a process for removing the titanium oxide film or contaminants such as carbon. That is, a process gas (e.g., argon gas) is introduced into a vacuum chamber in which a substrate to be processed is placed. In this state, a glow discharge occurs by applying a voltage to a portion of the substrate to be processed (terminal TM1 in this study) and plasma generated by the glow discharge collides with the portion to be processed. The energy of this collision makes it possible to remove the titanium oxide film, carbon, etc. Hereinafter, this method will be referred to as a reverse sputtering method.

[0082] In the reverse sputtering method, the energy of the plasma colliding with the processed object can be adjusted by adjusting the applied power and the pressure of the process gas. The display device DSP3 uses the reverse sputtering method as a pre-processing for joining different metals, so it is necessary to collide plasma with a relatively high energy. For this reason, as shown in the enlarged view of FIG. 8, a cavity (void) 32 may occur between the insulating layer 16 and the metal layer ML3.

[0083] Furthermore, as described above, when the metal film MF3 is formed using a copper seed layer, the copper seed layer is removed by etching in the process of removing the copper seed layer around the bump electrode 30. At this time, depending on the degree of etching, there is a concern that a part of the metal film MF3 may be etched and a part of the metal layer ML3 of the terminal TM1 may be exposed. In this case, the gap formed between the metal film MF3 and the insulating layer 16 may cause a decrease in the electrical connection reliability of the display device DSP3, similar to the cavity 32 described with reference to FIG.

[0084] In light of the above, the display device DSP1 shown in FIG. 6 is superior to the display device DSP2 shown in FIG. 7 and the display device DSP3 shown in FIG. 8 in the following points.

[0085] First, the terminal TM1 of the display device DSP1 has a metal layer ML3 made of titanium disposed at the bonding interface with the cap film CP1. Therefore, even if an electroplating method is used in the step of forming the cap film CP1 and the step of forming the metal film MF3 made of copper, it is possible to prevent a part of the metal layer ML2 from being eroded by the plating solution for copper plating.

[0086] In addition, the cap film CP1 has a metal film MF1 made of the same titanium as the metal layer ML3 at the bonding interface with the terminal TM1, which can reduce damage to the metal layer ML3 in a pretreatment process (a process for removing the titanium oxide film) performed before the process for forming the metal film MF1.

[0087] For example, even if the metal film MF1 is formed in a state where a titanium oxide film is formed on the surface of the metal film MF1, the bonding strength can be increased. Also, if the titanium oxide film is thick, a reverse sputtering process may be performed. However, since it is not necessary to completely remove the titanium oxide film in the manufacturing process of the display difference DSP1, it is possible to adjust the plasma to collide with the terminal TM1 with energy that does not cause the cavity 32 shown in FIG. 8 to be formed. As a result, the generation of the cavity 32 shown in FIG. 7 and FIG. 8 can be prevented.

[0088] As described above, the metal film MF1 has a contact portion CPc that covers the entire portion of the metal layer ML3 of the terminal TM1 shown in Fig. 6 that is exposed from the insulating layer 16 at the bottom of the opening 16H1. The metal film MF1 is located outside the opening 16H1 and includes a peripheral portion CPp that is disposed so as to continuously surround the periphery of the contact portion CPc in a plan view as shown in Fig. 5. In other words, the bottom of the opening 16H1 and its periphery are covered with the metal film MF1 made of titanium.

[0089] Therefore, when the metal film MF3 is formed by using a copper seed layer, even if a large amount of the copper film is removed in the step of removing the copper seed layer, no gap is generated between the insulating layer 16 and the metal film MF1.

[0090] In this way, the display device DSP1 of this embodiment is superior to the display device DSP2 shown in FIG. 7 and the display device DSP3 shown in FIG. 8 in that it can prevent a decrease in connection reliability caused by the occurrence of the cavity 32 (or the gap described above) shown in FIG. 7 and FIG. 8.

[0091] 6, the thickness TF1 of the metal film MF1 of the cap film CP1 is greater than the thickness TL3 of the metal layer ML3 of the terminal TM1. From the viewpoint of suppressing damage to the metal film MF1, it is preferable to increase the thickness of the metal film MF1 disposed at the bottom layer of the cap film CP1.

[0092] The cap film CP1 has a metal film MF2 laminated on the metal film MF1. The metal film MF2 is made of aluminum. Although not shown, as a modification of the example shown in Fig. 6, there is a case where only the metal film MF1 is used as the cap film CP1, and a bump electrode 30 is formed on the metal film MF1. Alternatively, as a modification, as described later, there is a case where a metal film MF3 made of copper is laminated on the metal film MF1 so as to be in close contact with it.

[0093] 6, by interposing a metal film MF2 made of aluminum between a metal film MF3 made of copper and a metal film MF1 made of titanium, the metal film MF3 can be formed directly on the metal film MF2 by electroplating. The metal film MF2 is made of a metal having a higher electrical conductivity than the titanium constituting the metal film MF1. Therefore, the impedance of the path electrically connecting the bump electrode 30 and the terminal TM1 can be reduced compared to the case where only the metal film MF1 is used as the cap film CP1.

[0094] The thickness TF1 of the metal film MF1 of the cap film CP1 is thinner than the thickness TF2 of the metal film MF2 of the cap film CP1. As described above, from the viewpoint of reducing the impedance of the path electrically connecting the bump electrode 30 and the terminal TM1, it is preferable that the thickness TF2 of the metal film MF2 is thicker than the thickness TF1 of the metal film MF1.

[0095] 6, the cap film CP1 has a metal film MF3 laminated on the metal film MF2. The metal film MF3 is made of copper, and covers the entire metal film MF1 and the metal film MF2. Copper has a higher electrical conductivity than aluminum. Therefore, by interposing the metal film MF3 made of copper between the bump electrode 30 and the terminal TM1, the impedance of the path electrically connecting the bump electrode 30 and the terminal TM1 can be further reduced.

[0096] 6, the cap film CP1 further includes a metal film MF4 laminated on the metal film MF3. A portion of the metal film MF1 is exposed from the metal film MF2. The metal film MF4 is made of nickel and covers the entire metal film MF3.

[0097] By forming the metal film MF4 made of nickel on the uppermost layer of the cap film CP1, the bonding strength between the bump electrode 30 made of tin and the cap film CP1 can be improved.

[0098] Moreover, the terminal TM2 shown in Fig. 4 is similar to the terminal TM1 shown in Fig. 6, except that the terminal TM2 is formed at a position overlapping with the contact hole CH2 as shown in Fig. 9. Fig. 9 is an enlarged cross-sectional view showing, on an enlarged scale, another terminal of the two terminals shown in Fig. 4, which is different from that shown in Fig. 6.

[0099] 9, a portion of the terminal TM2 is connected to the conductor pattern MP2 disposed on the wiring layer WL3. More specifically, the terminal TM2 is joined to the conductor pattern MP2 at the bottom of a contact hole CH2 formed in the insulating layer 15.

[0100] Each of the terminal TM2 and the conductor pattern MP2 has a metal layer ML1, a metal layer ML2, and a metal layer ML3 laminated in this order on an insulating layer 15 made of an organic material. The metal layer ML1 is made of titanium. The metal layer ML1 of the terminal TM2 is disposed on the insulating layer 15 in close contact with the insulating layer 15. The metal layer ML2 is made of aluminum. The metal layer ML2 is disposed on the metal layer ML1 in close contact with the metal layer ML3. The metal layer ML3 is made of titanium. The metal layer ML3 is disposed on the metal layer ML2 in close contact with the metal layer ML2. The metal layer ML3 of the terminal TM2 is bonded to the cap film CP2 at the bottom of the opening 16H2. The metal layer ML1 of the terminal TM2 is bonded to the metal layer ML3 of the conductor pattern MP2 at the bottom of the contact hole CH2.

[0101] The metal layers ML1, ML2, and ML3 of the terminal TM2 are similar to the metal layers ML1, ML2, and ML3 of the terminal TM1 described with reference to FIG. 6, respectively, and therefore will not be described again.

[0102] The cap film CP2 includes a metal film MF1 made of titanium and joined to the metal layer ML3 at the bottom of the opening 16H2. In the example shown in Fig. 9, the cap film CP2 has metal films MF2, MF3, and MF4 laminated on the metal film MF1. The metal films MF1, MF2, MF3, and MF4 of the cap film CP2 are similar to the metal films MF1, MF2, MF3, and MF4 described with reference to Fig. 6, respectively, and therefore will not be described again.

[0103] However, the cap film CP2 differs from the cap film CP1 shown in FIG. 6 in that a part of the metal film MF1 (and a part of the metal film MF2) is embedded in the contact hole CH2.

[0104] <Electronic device manufacturing method> Next, a method for manufacturing the display device shown in Fig. 4 will be described as a method for manufacturing the electronic device of this embodiment. Fig. 10 is an explanatory diagram showing an example of a process flow of a method for manufacturing a display device, which is one embodiment of the electronic device. As shown in Fig. 10, the method for manufacturing the electronic device of this embodiment includes a substrate structure preparation step, a bump electrode formation step, and an electronic component mounting step. Note that the electronic component mounting step can be omitted when the substrate structure before mounting the electronic components is shipped as a semi-finished product.

[0105] In the substrate structure preparing step, a substrate structure SUB1 is prepared in a state before the bump electrodes 30 and 31 shown in Fig. 4 are formed. As shown in Fig. 10, the substrate structure preparing step includes a terminal forming step, an insulating layer forming step, an opening forming step, and a cap film forming step.

[0106] Although not shown in FIG. 10, the substrate structure preparation step includes the following steps performed before the terminal formation step. That is, in the substrate structure preparation step, first, a substrate 10 made of glass or resin is prepared (substrate preparation step). The substrate structure preparation step includes a wiring layer lamination step in which the members shown in FIG. 2 or FIG. 4 are laminated on the substrate 10. In the wiring layer lamination step, an insulating layer 11, a wiring layer WL1, an insulating layer 12, a semiconductor element (for example, a drive transistor DRT shown in FIG. 4), an insulating layer 13, a wiring layer WL2, an insulating layer 14, a wiring layer WL3, and an insulating layer 15 are laminated in this order on the surface 10f of the substrate 10. A contact hole CH1 and a contact hole CH2 are formed in the insulating layer 15.

[0107] <Terminal formation process> In the example shown in FIG. 10, the terminal forming step includes a first metal layer forming step, a second metal layer forming step, and a third metal layer forming step.

[0108] In the first metal layer formation step, a metal layer ML1 is formed, which is located at the bottom layer of the terminal TM1 shown in Fig. 6 or the bottom layer of the terminal TM2 shown in Fig. 9. As already described, the metal layer ML1 is a metal layer made of titanium, and is formed so as to adhere closely to the insulating layer 15.

[0109] At the bottom of each of the contact holes CH1 and CH2 shown in Fig. 4, the metal layer ML1 (see Fig. 9) is joined to the conductor pattern (the conductor pattern MP1 or the conductor pattern MP2 shown in Fig. 4) formed on the wiring layer WL3. After the contact holes CH1 and CH2 are formed, if an oxide film is formed on the outermost surface (uppermost layer) of the wiring layer WL3, a process for removing this oxide film (for example, oxide film removal by reverse sputtering) may be performed.

[0110] As shown in Fig. 9, each of the conductor patterns MP1 and MP2 formed on the wiring layer WL3 has a metal layer ML3 made of titanium formed on the outermost surface (uppermost layer). Therefore, a titanium film is bonded to the bonding interface between the conductor pattern MP1 and the terminal TM1 and the bonding interface between the conductor pattern MP2 and the terminal TM2 shown in Fig. 4. Therefore, it is not necessary to completely remove the titanium oxide film. Therefore, even if the oxide film is removed by the reverse sputtering method, the plasma can be adjusted to collide with the wiring layer WL3 with energy that does not form the cavity 32 (see Fig. 32) already described.

[0111] Next, in the second metal layer formation step, the metal layer ML2 constituting the terminal TM1 shown in FIG. 6 or the terminal TM2 shown in FIG. 9 is formed. As already explained, the metal layer ML2 is a metal layer made of aluminum, and is formed so as to adhere to the metal layer ML1. Note that, as a modification of the present embodiment, when the metal layer ML1 is not formed, the first metal layer formation step shown in FIG. 10 is omitted. In this case, the metal layer ML2 made of aluminum is formed so as to adhere to the insulating layer 15.

[0112] Next, in the third metal layer formation step, a metal layer ML3 is formed which constitutes the terminal TM1 shown in Fig. 6 or the terminal TM2 shown in Fig. 9. As already described, the metal layer ML3 is a metal layer made of titanium, and is formed so as to adhere closely to the metal layer ML2.

[0113] <Insulating layer formation process> Next, in the insulating layer forming step shown in Fig. 10, an insulating layer 16 is formed as shown in Fig. 11. Fig. 11 is an enlarged cross-sectional view showing the insulating layer forming step of Fig. 10.

[0114] In the insulating layer forming step, the insulating layer 16 is formed so as to cover each of the terminals TM1 and TM2. As described above, the insulating layer 16 is an inorganic insulating film such as silicon nitride. Therefore, the planarization characteristics of the insulating layer 16 with respect to irregularities are lower than those of the insulating layer 15 which is an organic insulating film. As a result, the insulating layer 16 has an upper surface with irregularities following the irregularities of the wiring layer WL4 formed on the insulating layer 15.

[0115] <Opening formation process> 10, openings 16H1 and 16H2 are formed in insulating layer 16 as shown in Fig. 12. Fig. 12 is an enlarged cross-sectional view showing the opening formation step of Fig. 10.

[0116] In the opening forming step, an opening 16H1 is formed to expose a portion of the terminal TM1 from the insulating layer 16. In the opening forming step, an opening 16H2 is formed to expose a portion of the terminal TM2 from the insulating layer 16.

[0117] The method for forming the openings 16H1 and 16H2 is, for example, the following method. First, a resist mask (not shown) is formed, and then openings are formed in the resist mask at positions overlapping with regions where the openings 16H1 and 16H2 are to be formed, using photolithography. Next, the insulating layer 16 exposed from the resist mask at the openings is removed by etching. This forms the openings 16H1 and 16H2. Thereafter, the resist mask is removed to obtain the insulating layer 16 shown in FIG. 12.

[0118] <Cap film formation process> Next, in the cap film formation process shown in FIG. 10, the cap film CP1 (see FIG. 6) and the cap film CP2 (see FIG. 9) described with reference to each of FIGS. 4 to 9 are formed. Below, a method for forming the cap film CP1 connected to the terminal TM1 is described as a representative example. However, the cap film CP2 connected to the terminal TM2 shown in FIG. 9 can be formed by a method similar to that described below. In the description of each process below, the "terminal TM1" can be replaced with the "terminal TM2", the "cap film CP1" with the "cap film CP2", and the "opening 16H1" with the "opening 16H2". Note that the cap film CP1 and the cap film CP2 are formed by the same process, and therefore can be formed collectively.

[0119] In the example shown in FIG. 10, the cap film forming step includes a first metal film forming step, a second metal film forming step, a third metal film forming step, and a fourth metal film forming step.

[0120] In the first metal film formation step, a metal film MF1 made of titanium is formed so as to be joined to the metal layer ML3 of the terminal TM1 at the bottom of the opening 16H1 as shown in Fig. 13. Fig. 13 is an enlarged cross-sectional view showing the first metal film formation step shown in Fig. 10.

[0121] 13, first, a resist film 40 is formed so as to cover the insulating layer 16, and then an opening is formed in the resist film 40 in a region where the metal film MF1 is to be formed. The region where the metal film MF1 is to be formed includes the entire opening 16H1 and its surrounding region.

[0122] Next, the metal film MF1 is selectively formed using the resist film 40 as a mask. A sputtering method can be given as an example of a method for forming the metal film MF1. When the metal film MF1 is formed by the sputtering method, the metal film MF1 is also formed on the resist film 40, but the metal film MF1 formed on the resist film 40 can be removed together with the resist film 40.

[0123] As already explained, a titanium film is bonded to the bonding interface between the terminal TM1 and the metal film MF1. Therefore, the titanium oxide film may not be completely removed from the bonding interface. Therefore, even if the oxide film is removed by the reverse sputtering method, the plasma can be adjusted so that it collides with the terminal TM1 with an energy that does not form the cavity 32 (see FIG. 32) as already explained.

[0124] The metal film MF1 has a contact portion CPc that covers the entire portion of the metal layer ML3 of the terminal TM1 that is exposed from the insulating layer 16 at the bottom of the opening 16H1. The metal film MF1 includes a peripheral portion CPp that is located outside the opening 16H1. As described with reference to FIG. 5, the peripheral portion CPp is formed so as to continuously surround the periphery of the contact portion CPc in a plan view.

[0125] As shown in FIG. 13, in this step, the metal film MF1 is preferably formed so that the thickness TF1 is greater than the thickness TL3 of the metal layer ML3.

[0126] In the second metal film formation step shown in Fig. 10, a metal film MF2 made of aluminum is formed on the metal film MF1 so as to be in close contact with the metal film MF1, as shown in Fig. 14. Fig. 14 is an enlarged cross-sectional view showing the second metal layer formation step shown in Fig. 10.

[0127] 14, a metal film MF2 is laminated in a state where a metal film MF1 is formed in the opening of a resist film 40. A sputtering method can be given as an example of a method for forming the metal film MF2. When the metal film MF2 is formed by a sputtering method, the metal film MF2 is also formed on the resist film 40, but the metal film MF2 formed on the resist film 40 can be removed together with the resist film 40.

[0128] This process is performed in a state in which the resist film 40 remains. Therefore, the side surface of the metal film MF1 that is in close contact with the resist film 40 is exposed from the metal film MF2.

[0129] In the third metal film forming step described later, the metal film MF2 is corroded by the copper plating solution and becomes thinner, so it is preferable that the metal film MF2 is formed thick in advance. In the example shown in Fig. 14, the thickness TF2 of the metal film MF2 is thicker than the thickness TF1 of the metal film MF1.

[0130] After the second metal film forming step shown in Fig. 10 and before the third metal film forming step, a step of removing the resist film 40 shown in Fig. 14 and a step of removing the oxide film formed on the metal film MF2 shown in Fig. 14 are included. For example, an etching process can be used as a method for removing the resist film 40. In the step of removing the oxide film of the metal film MF2, a zincate process can be used.

[0131] In the third metal film formation step shown in Fig. 10, a metal film MF3 made of copper is formed on the metal film MF2 so as to be in close contact with the metal film MF2, as shown in Fig. 15. Fig. 15 is an enlarged cross-sectional view showing the third metal layer formation step shown in Fig. 10.

[0132] The metal film MF3 is formed by electroplating. In electroplating, a metal film is selectively formed on the surface of the member to be plated by contacting the member to be plated with a plating solution while an electric current is applied to the member to be plated. During this process, the metal film MF2 made of aluminum is eroded by the copper plating solution, and the thickness TF2 of the metal film MF2 becomes thinner.

[0133] In the present embodiment, the entire opening 16H1 of the insulating layer 16 is covered with the metal film MF1. Therefore, even if the metal film MF2 is partially or entirely eroded by the plating liquid in the third metal film forming step, it is possible to prevent the plating liquid from coming into contact with the terminal TM1.

[0134] Furthermore, as described with reference to FIG. 14, by previously increasing the thickness TF2 of the metal film MF2, it is possible to prevent the entire metal film MF2 from being eroded by the plating liquid.

[0135] In the present embodiment, in the process of forming the copper metal film MF3 by electroplating, measures are taken to prevent the metal film MF2 from being lost due to the plating solution. Therefore, the copper metal film MF3 can be formed thick. As a result, the resistance of the portion electrically connecting the bump electrode 30 and the terminal TM3 shown in FIG. 6 can be reduced.

[0136] As shown in Fig. 15, this step is performed in a state where the resist film 40 (see Fig. 14) has been removed. Furthermore, a metal film formed by electroplating grows isotropically on the surface of the metal film in contact with the plating liquid. Therefore, the metal film MF3 is formed so as to entirely cover the metal films MF1 and MF2.

[0137] In the fourth metal film formation step shown in Fig. 10, a metal film MF4 made of nickel is formed on the metal film MF3 so as to be in close contact with the metal film MF3, as shown in Fig. 16. Fig. 16 is an enlarged cross-sectional view showing the fourth metal layer formation step shown in Fig. 10.

[0138] The metal film MF4 is formed by electroplating. Therefore, the metal film MF4 is formed so as to cover the entire metal film MF3. The metal film MF4 made of nickel is formed so as to cover the entire metal film MF3 made of copper, thereby improving the bonding strength between the cap film CP1 and the bump electrode 30 (see FIG. 5).

[0139] Through the above steps, the cap film CP1 is obtained.

[0140] <Bump electrode formation process> Next, in the bump electrode forming process shown in FIG. 10, the bump electrode 30 and the bump electrode 31 (see FIG. 9) described with reference to each of FIGS. 4 to 9 are formed. In the following, a method for forming the bump electrode 30 connected to the cap film CP1 shown in FIG. 6 is described as a representative example. However, the bump electrode 31 connected to the cap film CP2 shown in FIG. 9 can be formed in a similar manner to the following description. In the following description of each process, the "terminal TM1" can be replaced with the "terminal TM2", the "cap film CP1" with the "cap film CP2", the "opening 16H1" with the "opening 16H2", and the "bump electrode 30" with the "bump electrode 31". Note that the bump electrode 30 and the bump electrode 31 are formed by the same process, and therefore can be formed at the same time.

[0141] In the bump electrode formation process, as shown in Fig. 6, the bump electrode 30 is formed on the cap film CP1. In this embodiment, the bump electrode 30 is formed by electroplating while current is applied to the terminal TM1. The bump electrode 30 is made of, for example, tin (solder). When the bump electrode 30 is formed by electroplating, the bump electrode 30 can be selectively formed on the portion of the cap film CP1 that is in contact with the plating liquid. This makes it unnecessary to prepare a new large-scale exposure device such as a large stepper.

[0142] By this step, the bump electrode 30 can be formed so as to cover the opening 16H1 of the insulating layer 16. The cap film CP1 is interposed between the bump electrode 30 and the terminal TM1.

[0143] There are cases where the substrate structure SUB1 (see FIG. 4) before electronic components are mounted is shipped as a semi-finished product. In this case, the electronic component mounting process shown in FIG. 10 is omitted, and the substrate structure SUB1 shown in FIG. 6 is prepared for shipping after necessary inspection and packaging. That is, the substrate structure SUB1 as an electronic device is obtained by the bump electrode formation process in FIG. 10.

[0144] Next, in the electronic component mounting process shown in FIG. 10, after the bump electrode forming process, the bump electrodes 30 and 31 are electrically connected to the electronic components (LED element 20 in the example of FIG. 4) as shown in FIG. 4. In this process, the bump electrodes 30 and 31 are softened by, for example, irradiating them with a laser. As a result, the bump electrodes 30 are connected to the anode electrodes 20EA of the LED element 20, and the bump electrodes 31 are connected to the cathode electrodes 20EC of the LED element. Note that, before this process, a solder film may be formed in advance on each of the anode electrodes 20EA and cathode electrodes 20EC of the LED element 20 shown in FIG. 4. In this case, the bump electrodes 30 and 31 made of solder can be easily integrated with the solder film formed on the electrodes.

[0145] <Modification of the cap film> Next, modified examples of the cap film will be described. Fig. 17 is an enlarged cross-sectional view showing a modified example of Fig. 6. Fig. 18 is an enlarged cross-sectional view showing a modified example of Fig. 9.

[0146] The display device DSP4 shown in FIGS. 17 and 18 differs from the display device DSP1 shown in FIGS. 6 and 9 in the following points.

[0147] First, each of the cap films CP1 and CP2 of the display device DSP4 has a three-layer structure including a metal film MF1 made of titanium, a metal film MF2 made of copper, and a metal film MF3 made of nickel.

[0148] Moreover, each of the cap films CP1 and CP2 of the display device DSP4 has a part (specifically, a side surface) exposed from the bump electrode 30 or the bump electrode 31.

[0149] In the example shown in FIGS. 17 and 18, a portion of the metal film MF1 is exposed from the metal film MF2 and the metal film MF3.

[0150] The manufacturing method of the display device DSP4 shown in FIG. 17 and FIG. 18 is different from the manufacturing method of the display device DSP1 (see FIG. 4) described with reference to FIG. 10 to FIG. 16 in the following respects. FIG. 19 is an explanatory diagram showing an example of a process flow of a manufacturing method of a display device which is a modified example of FIG. 10. Note that the terminal forming process shown in FIG. 19 is the same as the terminal forming process described with reference to FIG. 10, so the first metal layer forming process, the second metal layer forming process, and the third metal layer forming process described in FIG. 10 are omitted from the illustration. The manufacturing method shown in FIG. 19 is different from the manufacturing method described with reference to FIG. 10 in the cap film forming process. In addition, the manufacturing method shown in FIG. 19 is different from the manufacturing method described with reference to FIG. 10 in that a resist film removing process and a seed layer removing process are provided after the bump electrode forming process and before the electronic component mounting process.

[0151] 10 will be described below. A method for forming a cap film CP1 connected to the terminal TM1 shown in FIG. 17 and a method for forming a bump electrode 30 connected to the cap film CP1 will be described below as representative examples. However, the cap film CP2 connected to the terminal TM2 shown in FIG. 18 can be formed in a similar manner to the following description. In the following description of each process, the "terminal TM1" can be replaced with the "terminal TM2", the "cap film CP1" with the "cap film CP2", the "opening 16H1" with the "opening 16H2", and the "bump electrode 30" with the "bump electrode 31".

[0152] The cap film forming step shown in FIG. 19 includes a first metal film forming step, a seed layer forming step, a resist film forming step, a second metal film forming step, and a third metal film forming step.

[0153] In the first metal film formation step, a metal film MF1 made of titanium is formed so as to be joined to the metal layer ML3 of the terminal TM1 at the bottom of the opening 16H1, similarly to the example described with reference to Fig. 13. Note that in the present modification, the resist film 40 shown in Fig. 13 is removed after the first metal film formation step and before the seed layer formation step.

[0154] In the seed layer formation step shown in Fig. 19, as shown in Fig. 20, a seed layer (copper seed layer) MS1 made of copper is formed on the metal film MF1 and on the insulating layer 16 so as to be in close contact with the metal film MF1 and the insulating layer 16. Fig. 20 is an enlarged cross-sectional view showing the seed layer formation step shown in Fig. 19.

[0155] As shown in Fig. 20, the seed layer formation step is performed in a state where the resist film 40 shown in Fig. 13 has been removed. The seed layer MS1 is a metal thin film made of copper and is formed by a sputtering method. Therefore, as shown in Fig. 20, in this step, the seed layer MS1 is formed so as to entirely cover the insulating layer 16 and the metal film MF1.

[0156] In the present modified example, the metal film MF1 made of titanium and the seed layer MS1 made of copper are bonded together. For this reason, it is preferable to perform the above-mentioned reverse sputtering process as a process for removing the titanium oxide film formed on the surface of the metal film MF1 or a process for removing dirt such as carbon. As described above, the reverse sputtering process is a process in which plasma is collided with the processing target portion.

[0157] In this modification, the portion (contact portion CPc) of the terminal TM1 exposed from the insulating layer 16 at the opening 16H1 is entirely covered with the metal film MF1. Therefore, even if strong energy is applied to the metal film MF1 by the reverse sputtering method, it is possible to prevent the cavity 32 described with reference to Fig. 8 from being formed. From the viewpoint of preventing the metal film MF1 from being burned away by the reverse sputtering method, it is preferable that the thickness TF1 of the metal film MF1 is thicker than the thickness TL3 of the metal layer ML3 of the terminal TM1, as shown in Fig. 17.

[0158] In the resist film formation step shown in Fig. 19, as shown in Fig. 21, a resist film 41 is formed so as to cover the seed layer MS1, and then an opening is formed in the resist film 41. Fig. 21 is an enlarged cross-sectional view showing the resist film formation step shown in Fig. 19. At least a part of the portion of the seed layer MS1 that is located at a position overlapping with the metal film MF1 is exposed from the resist film 41.

[0159] In the second metal film formation step shown in Fig. 19, a metal film MF2 made of copper is formed on the seed layer MS1 so as to be in close contact with the seed layer MS1 as shown in Fig. 22. Fig. 22 is an enlarged cross-sectional view showing the second metal layer formation step shown in Fig. 19.

[0160] In this process, the metal film MF2 is formed by, for example, electroplating. In the case of electroplating, it is possible to make the metal film thicker than by sputtering. Therefore, as shown in FIG. 17, the thickness TF2 of the metal film MF2 is thicker than the thickness MF1 of the metal film MF1.

[0161] 22, this step is performed in a state where a resist film 41 is formed on the insulating layer 16. Therefore, the metal film MF2 is selectively formed on a portion of the surface of the seed layer MS1 that is exposed from the resist film 41 in the opening of the resist film 41. Also, as shown in FIG. 17, a portion of the metal film MF1 is exposed from the metal film MF2.

[0162] In the third metal film formation step shown in Fig. 19, a metal film MF3 made of nickel is formed on the metal film MF2 so as to be in close contact with the metal film MF2, as shown in Fig. 23. Fig. 23 is an enlarged cross-sectional view showing the third metal layer formation step shown in Fig. 19.

[0163] In this step, the metal film MF3 is formed by, for example, an electroplating method. As in the second metal film forming step, this step is performed in a state in which a resist film 41 is formed on the insulating layer 16. Therefore, as shown in FIG. 17, a portion of the metal film MF1 is exposed from the metal film MF3.

[0164] Next, in the bump electrode formation step shown in Fig. 19, a bump electrode 30 is formed on the cap film CP1 as shown in Fig. 24. Fig. 24 is an enlarged cross-sectional view showing the bump electrode formation step shown in Fig. 19. In this modification, the bump electrode 30 is formed by electroplating while a current is applied to the terminal TM1. The bump electrode 30 is made of, for example, tin (solder).

[0165] This step is performed in a state where a resist film 41 is formed on the insulating layer 16, similarly to the above-described second metal film forming step and third metal film forming step. Therefore, as shown in FIG. 17, each of the metal films MF1 and MF2 is partially exposed from the bump electrode 30.

[0166] Next, in the resist film removing step shown in Fig. 19, the resist film 41 (see Fig. 24) is removed as shown in Fig. 25. Fig. 25 is an enlarged cross-sectional view showing the resist film removing step shown in Fig. 19. The resist film 41 is removed by, for example, etching.

[0167] Next, in the seed layer removal step shown in Fig. 19, a portion of the seed layer MS1 is removed as shown in Fig. 26. Fig. 26 is an enlarged cross-sectional view showing the seed layer removal step shown in Fig. 19. The seed layer MS1 is removed by etching. Note that it is preferable to select an etchant used in the seed layer removal step that has a higher etching rate for copper than for titanium.

[0168] In this case, a part of the metal film MF2 is etched together with the seed layer MS1. However, since the thickness of the metal film MF2 can be made sufficiently thicker than the thickness of the seed layer MS1, it is possible to prevent the entire metal film MF2 from being removed in this process.

[0169] Furthermore, a metal film MF1 made of titanium is adhered to the opening 16H1 (see FIG. 20) of the insulating layer 16. This makes it possible to prevent a cavity from being formed in the opening due to infiltration of the etching liquid into the opening.

[0170] Note that the portion of the seed layer MS1 that is interposed between the metal film MF2 and the metal film MF1 remains. However, the seed layer MS1 and the metal film MF2 are both metal films made of copper, and the boundary between them may not be clear. Therefore, the remaining portion of the seed layer MS1 that is not removed in this process can be regarded as a part of the metal film MF2, as shown in FIG.

[0171] Although the embodiment and the representative modified examples have been described above, the above-described technology can be applied to various modified examples other than the modified examples exemplified. For example, the modified examples described above may be combined with each other.

[0172] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds, deletes, or modifies the design of the above-mentioned embodiments, or adds, omits, or modifies the conditions of steps, are also included in the scope of the present invention as long as they include the gist of the present invention. [Industrial Applicability]

[0173] The present invention can be used in electronic devices such as display devices. [Explanation of symbols]

[0174] 5 Control circuit 6 Drive circuit 10 Substrate 10b,10f side 11, 12, 13, 14, 15, 16 Insulating layer 16H1,16H2 opening 20, 20A, 20B, 20C LED elements (light-emitting elements, electronic components) 20b,20f side 20EA Anode Electrode 20EC Cathode Electrode 30,31 Bump electrode 32 Void 40,41 Resist film 50 Semiconductor layer BCT Output transistor (switching element) Cad Auxiliary Capacity CH1, CH2, CH3 contact holes CP1, CP2, CP3, CP4 cap membrane CPc Contact Part CPp Periphery Cs retention capacity DA display area DRT Drive transistor (switching element) DSP1,DSP2,DSP3,DSP4 Display device ED drain electrode EG Gate electrode ES source electrode GLB,GLR,GLS scanning signal line Grs, Gsb, Gss control signal MF1,MF2,MF3,MF4 Metal film ML1,ML2,ML3 Metal layer MP1, MP2 conductor pattern MS1 seed layer (copper seed layer) MW1 Wiring pattern PC pixel circuit PFA surrounding area PIXA, PIXB, PIXC pixels PL1,PL2 power line Pvdd high potential Pvss low potential RSL Reset wiring RST Reset transistor (switching element) SST Pixel selection transistor (switching element) SUB1 Substrate structure SW Switching element TM1, TM2, TM3 terminals (conductor patterns) VL Video signal line Vrs Reset signal Vsg Video signal WL1,WL2,WL3,WL4 wiring layers

Claims

1. A first substrate; A first terminal disposed on the first substrate; a first insulating layer made of an inorganic material and covering the first terminal; a first opening formed in the first insulating layer; a first cap film connected to the first terminal in the first opening; a first bump electrode electrically connected to the first terminal via the first cap film; having The first terminal is a first metal layer comprising aluminum; a second metal layer made of titanium disposed on the first metal layer, the second metal layer being in close contact with the first metal layer and bonded to the first cap film at the first opening; Including, the first cap film includes a first metal film made of titanium and bonded to the second metal layer in the first opening; The first metal film is a contact portion covering an entire portion of the second metal layer of the first terminal that is exposed from the first insulating layer in the first opening; a peripheral portion that is located outside the first opening and that is disposed so as to continuously surround the periphery of the contact portion in a plan view; Including, the first insulating layer is interposed between the peripheral portion of the first metal film and the first terminal.

2. In claim 1, the first cap film further includes a second metal film laminated on the first metal film, The electronic device, wherein the second metal film is made of aluminum or copper.

3. In claim 2, the first cap film further includes a third metal film laminated on the second metal film, the second metal film is made of aluminum; The third metal film is made of copper and covers the entire first metal film and the entire second metal film.

4. In claim 3, the first cap film further includes a fourth metal film laminated on the third metal film, a portion of the first metal film is exposed from the second metal film; The fourth metal film is made of nickel and covers the entire third metal film.

5. In claim 2, the first cap film further includes a third metal film laminated on the second metal film, the second metal film is made of copper; The electronic device, wherein the third metal film is made of nickel.

6. In claim 5, A portion of the first metal film is exposed from the second metal film and the third metal film.

7. In any one of claims 1 to 6, An electronic device, wherein a thickness of the first metal film of the first cap film is greater than a thickness of the second metal layer of the first terminal.

8. In any one of claims 2 to 6, An electronic device, wherein a thickness of the first metal film of the first cap film is thicker than a thickness of the second metal layer of the first terminal and is thinner than a thickness of the second metal film.

9. In any one of claims 1 to 6, the first terminal further includes a third metal layer comprised of titanium; The first metal layer is disposed over and in intimate contact with the third metal layer.

10. In claim 9, The third metal layer is disposed on and in intimate contact with a second insulating layer made of an organic material.

11. (a) forming a first terminal on a first substrate; (b) forming a first insulating layer made of an inorganic material so as to cover the first terminal; (c) forming a first opening in the first insulating layer to expose a portion of the first terminal from the first insulating layer; (d) forming a first cap film to cover the first opening; (e) forming a bump electrode on the first cap film; Including, The step (a) comprises: (a1) forming a first metal layer comprising aluminum; (a2) forming a second metal layer made of titanium on the first metal layer so as to be in close contact with the first metal layer; Including, The step (d) comprises: (d1) forming a first metal film made of titanium and bonded to the second metal layer in the first opening; The first metal film is a contact portion covering an entire portion of the second metal layer of the first terminal that is exposed from the first insulating layer in the first opening; a peripheral portion that is located outside the first opening and that is disposed so as to continuously surround the periphery of the contact portion in a plan view; Including, The method for manufacturing an electronic device, wherein the first insulating layer is interposed between the peripheral portion of the first metal film and the first terminal.

12. In claim 11, The method for manufacturing an electronic device, wherein the step (d) further comprises the step of (d2) laminating a second metal film made of aluminum or copper on the first metal film.

13. In claim 12, the second metal film is made of aluminum; The step (d) further includes a step (d3) of laminating a third metal film made of copper on the second metal film, The method for manufacturing an electronic device, wherein the third metal film is formed so as to entirely cover the first metal film and the second metal film.

14. In claim 13, The step (d) further includes a step (d4) of laminating a fourth metal film made of nickel on the third metal film, The fourth metal film is formed so as to cover the entirety of the third metal film.

15. In claim 12, the second metal film is made of copper; The method for manufacturing an electronic device, wherein the step (d) further comprises the step of (d3) laminating a third metal film made of nickel on the second metal film.

16. In claim 15, A portion of the first metal film is exposed from the second metal film and the third metal film.

17. In any one of claims 11 to 16, A method for manufacturing an electronic device, wherein in the step (d1), the first metal film of the first cap film is formed to have a thickness greater than a thickness of the second metal layer of the first terminal.

Images