Semiconductor device

Abstract

To provide a semiconductor device that reduces inductance and impedance of a GaN HEMT device.SOLUTION: A semiconductor device 10 comprises two or more semiconductor layers 12 and a substrate 11. A curent flow direction of at least one of the semiconductor layers 12 is opposite to current flow directions of the remaining semiconductor layers 12.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Documents 1 and 2 disclose techniques relating to GaN-based semiconductor elements having a drain electrode, a source electrode, and a gate electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-066398 A [Patent Document 2] JP 2011-066390 A Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional GaN HEMT devices, current flows in only one direction. Therefore, in single-structure GaN HEMT devices, the current flows in only one direction, which can lead to an increase in inductance and high impedance. Therefore, a device that reduces the increase in inductance and has low impedance is desired. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment includes two or more GaN-based semiconductor layers and a substrate, and at least one of the GaN-based semiconductor layers has a current flow direction opposite to that of the remaining GaN-based semiconductor layers. Effect of the Invention

[0006] According to a semiconductor device according to one aspect of the present disclosure, the inductance and impedance of a GaN HEMT device can be reduced. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram showing a semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a schematic diagram showing the semiconductor element according to the first embodiment. [Diagram 3] FIG. 3 is a schematic diagram showing a semiconductor device according to a first modification of the first embodiment. [Figure 4] FIG. 4 is a schematic diagram showing a semiconductor device according to a second modification of the first embodiment. [Diagram 5] FIG. 5 is a schematic diagram showing a semiconductor element according to the second embodiment. [Figure 6] FIG. 6 is a schematic diagram showing a semiconductor element according to the third embodiment. [Figure 7] FIG. 7 is a schematic diagram showing a semiconductor element according to the fourth embodiment. [Figure 8] FIG. 8 is a schematic diagram showing a semiconductor element according to the fifth embodiment. [Figure 9] FIG. 9 is a schematic diagram showing a semiconductor device according to the sixth embodiment. [Figure 10] FIG. 10 is a schematic diagram showing a semiconductor element according to the seventh embodiment. [Figure 11] FIG. 11 is a schematic diagram showing a conventional semiconductor device. [Figure 12] FIG. 12 is a schematic diagram showing a conventional semiconductor element. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A semiconductor device according to an embodiment will be described below. The embodiment will be described below with reference to the drawings, but the present invention is not limited to the embodiment. The components of the multiple embodiments described below can be combined as appropriate. In addition, some components may not be used.

[0009] [First embodiment] (Semiconductor element) FIG. 1 is a schematic diagram showing a semiconductor element according to a first embodiment. FIG. 2 is a schematic diagram showing a semiconductor element according to a first embodiment. In FIG. 2, the direction of current flow is indicated by a thick arrow. The same applies to the following figures. The stacking direction of the semiconductor element 1 is the up-down direction. The up-down direction is the z-axis direction. One direction perpendicular to the stacking direction is the y-axis direction. The direction perpendicular to both the stacking direction and the one direction is the x-axis direction. In the embodiment, the y-axis direction is the direction in which current flows. In the following description, the semiconductor element 1 is described as having a TMBS structure as an example. The semiconductor element 1 includes a substrate 11, a semiconductor layer 21, a back electrode 31, a Schottky electrode 41, an insulating film 51, and a field plate 61.

[0010] The semiconductor device 10 is a GaN HEMT (High Electron Mobility Transistor). The semiconductor device 10 includes a substrate 11 and a semiconductor layer (GaN-based semiconductor layer) 12. The semiconductor device 10 includes a source 13, a drain 14, and a gate 15 on a surface 12a of the semiconductor layer 12.

[0011] The substrate 11 is formed of, for example, GaN, sapphire, SiC, Si, AlGaN, a QST (Qromis Substrate Technology) substrate (product name), a bonded substrate, or the like.

[0012] The semiconductor layer 12 is a GaN-based semiconductor layer. The semiconductor layer 12 is provided on the surface 11a of the substrate 11. The semiconductor layer 12 grows by epitaxial growth from the surface 11a of the substrate 11. The semiconductor layer 12 has legs 121 on the surface 11a of the substrate 11.

[0013] At least two semiconductor layers 12 are provided on the surface 11a of the substrate 11. The semiconductor layers 12 are provided in a striped pattern. The semiconductor layers 12 extend along the y direction.

[0014] The HEMT element is disposed on the surface 12a of the semiconductor layer 12 so that a current flows along the y direction, which is the extension direction of the HEMT element. The HEMT element includes a source 13, a drain 14, and a gate 15.

[0015] The source 13 is provided on the surface 12 a of the semiconductor layer 12 .

[0016] The drain 14 is provided on the surface 12 a of the semiconductor layer 12 .

[0017] The gate 15 is provided on the surface 12 a of the semiconductor layer 12 .

[0018] In this manner, a HEMT element is provided on the surface 12a of each semiconductor layer 12 of the semiconductor element 10. In each HEMT element of the semiconductor element 10, a current flows from the drain 14 to the source 13. In at least one semiconductor layer 12, the direction of current flow is opposite to that of the remaining semiconductor layers 12. In the embodiment, in the HEMT elements on each semiconductor layer 12 of the semiconductor element 10, the drain 14 serving as a drain electrode and the source 13 serving as a source electrode are alternately arranged. In other words, the HEMT elements on each semiconductor layer 12 arranged side by side along the x direction are arranged with their orientations rotated by 180° alternately in the yz plane. In the semiconductor element 10, the directions of current flow on the semiconductor layers 12 adjacent to each other along the x direction are alternate, in other words, opposite to each other.

[0019] The semiconductor layers 12 in which the current flows in a predetermined direction and the semiconductor layers 12 in which the current flows in a direction opposite to the predetermined direction are arranged alternately one by one. In other words, in the embodiment, the HEMT elements are arranged alternately one by one. The HEMT element adjacent in the +x direction of the HEMT element arranged in the direction in which the current flows in the +y direction and the HEMT element adjacent in the -x direction both have a current flowing in the -y direction. The HEMT element adjacent in the +x direction of the HEMT element adjacent in the x direction of the HEMT element arranged in the direction in which the current flows in the -y direction both have a current flowing in the +y direction.

[0020] 1 and 2, on the surface 12a of the leftmost semiconductor layer 12, the source 13, the gate 15, and the drain 14 are arranged in this order along the y-axis direction. On the surface 12a of the semiconductor layer 12 immediately to the right of the leftmost semiconductor layer 12, the drain 14, the gate 15, and the source 13 are arranged in this order along the y-axis direction.

[0021] (Action and Effects) In the semiconductor elements 10, the directions of current flow in the semiconductor layers 12 adjacent to each other along the x direction are opposite to each other. As a result, according to the embodiment, the inductances generated in the adjacent semiconductor elements 10 interfere with each other and cancel each other out, thereby realizing a reduction in the inductance of the GaN HEMT device as a whole. Also, a reduction in the impedance of the GaN HEMT device can be realized.

[0022] [Modification 1 of the first embodiment] 3 is a schematic diagram showing a semiconductor device according to Modification 1 of the first embodiment. In this modification, the semiconductor device 10 differs from the first embodiment in the semiconductor layer 12. The semiconductor layer 12 has a mesa structure 123.

[0023] The semiconductor layer 12 formed of ELO-GaN has a defect 122 above the mask opening A. For this reason, when a HEMT element is fabricated above the mask opening A, there is a risk of degradation of element performance, such as an increase in leakage current and the occurrence of current collapse. To avoid this, the semiconductor layer 12 is subjected to mesa processing above the mask opening A to provide a mesa structure 123. In other words, the mesa structure 123 is located above the mask opening A.

[0024] The mesa structure 123 is provided on the surface 12a of the semiconductor layer 12. The mesa structure 123 provides two HEMT elements on one leg portion 121. Here, the portion separated by the mesa structure 123 is referred to as a semiconductor layer 124. Two semiconductor layers 124 are provided on one leg portion 121.

[0025] (effect) As described above, in the embodiment, the mesa structure 123 is formed on the mask opening A of the semiconductor layer 12. According to the embodiment, the influence of the defects 122 can be suppressed.

[0026] [Modification 2 of the First Embodiment] 4 is a schematic diagram showing a semiconductor device according to Modification 2 of the first embodiment. In this modification, the semiconductor device 10 has a semiconductor layer 12 that is different from that of the first embodiment.

[0027] The semiconductor layer 12 is provided integrally on the surface 11a of the substrate 11. The surface 12b of the semiconductor layer 12 is provided on the surface 11a of the substrate 11. In the present modified example 2, the semiconductor layer 12 is not limited to an epitaxially grown GaN-based semiconductor layer. For example, the semiconductor layer 12 may be provided by bonding. The semiconductor layer 12 may be formed of SiC, sapphire, AlN, GaAs, diamond, Ga2O3, or the like.

[0028] The semiconductor layer 12 is provided with a mesa structure 123. As a result, the semiconductor layer 12 is divided into a plurality of semiconductor layers 124 by the mesa structure 123. A HEMT element is provided on the divided semiconductor layers 124.

[0029] (effect) As described above, according to the embodiment, a similar element structure can be provided not only on the epitaxially grown GaN-based semiconductor layer 12 but also on a normal substrate.

[0030] [Second embodiment] 5 is a schematic diagram showing a semiconductor device according to a second embodiment, in which the arrangement of the HEMT devices is different from that of the first embodiment.

[0031] Next to one semiconductor layer 12 in which the current flows in a predetermined direction, a plurality of semiconductor layers 12 in which the current flows in a direction opposite to the predetermined direction are arranged side by side. In the semiconductor element 10, next to one HEMT element in which the current flows in a predetermined direction in the x direction, a plurality of HEMT elements in which the current flows in a direction opposite to the predetermined direction are arranged. This is repeated alternately in the x direction. In the embodiment, when a current flows in the +y-axis direction in a HEMT element on a certain semiconductor layer 12, the HEMT elements on n adjacent semiconductor layers 12 in the x-axis direction are arranged so that a current flows in the -y-axis direction. Here, n is a natural number equal to or greater than 1.

[0032] (effect) As described above, according to the embodiment, the inductances generated by the adjacent semiconductor elements 10 interfere with each other and cancel each other out, thereby reducing the inductance of the GaN HEMT device as a whole. Also, the impedance of the GaN HEMT device can be reduced.

[0033] [Third embodiment] 6 is a schematic diagram showing a semiconductor device according to a third embodiment, which differs from the second embodiment in the arrangement of the HEMT devices.

[0034] A plurality of semiconductor layers 12 in which a current flows in a predetermined direction and a plurality of semiconductor layers 12 in which a current flows in a direction opposite to the predetermined direction are arranged alternately. The semiconductor elements 10 have a current flow direction on the semiconductor layer 12 that alternates for each plurality of semiconductor elements 10 along the x direction. In the embodiment, the HEMT elements on n semiconductor layers 12 are arranged such that when a current flows in the +y-axis direction in the HEMT elements on the adjacent n semiconductor layers 12 in the x-axis direction, a current flows in the -y-axis direction in the HEMT elements on the adjacent n semiconductor layers 12. Here, n is a natural number equal to or greater than 1.

[0035] (effect) As described above, according to the embodiment, the inductances generated by the adjacent semiconductor elements 10 interfere with each other and cancel each other out, thereby reducing the inductance of the GaN HEMT device as a whole. Also, the impedance of the GaN HEMT device can be reduced.

[0036] [Fourth embodiment] 7 is a schematic diagram showing a semiconductor device according to a fourth embodiment. This embodiment differs from the first embodiment in the semiconductor layer 12.

[0037] The length of the semiconductor layer 12 in the y-axis direction is several times the length of the semiconductor layer 12 in the first embodiment. A plurality of sets of drains 14, sources 13, and gates 15 are arranged on a surface 12a of the semiconductor layer 12. In a HEMT element provided on one semiconductor layer 12, a plurality of drain-gate-source terminals are provided.

[0038] In the semiconductor elements 10, the direction of current flow on the semiconductor layer 12 alternates for each of the plurality of semiconductor elements 10 along the x direction.

[0039] (effect) As described above, according to the embodiment, a plurality of drain-gate-source terminals can be provided in a HEMT element provided on one semiconductor layer 12. This makes it possible to improve the area utilization efficiency.

[0040] Furthermore, the inductances generated by the adjacent semiconductor elements 10 interfere with each other and cancel each other out, thereby reducing the inductance of the GaN HEMT device as a whole and also reducing the impedance of the GaN HEMT device.

[0041] [Fifth embodiment] 8 is a schematic diagram showing a semiconductor element according to the fifth embodiment. The semiconductor element 10 is the same as the fifth embodiment in that the drain terminals are aligned.

[0042] The semiconductor layers 12 aligned in a direction perpendicular to the current flow direction are arranged so that the positions of the drain 14, the source 13, and the gate 15 are aligned. In the semiconductor layers 12 aligned in the x-axis direction, the positions of the drain terminal, the gate terminal, and the source terminal are aligned.

[0043] (effect) As described above, according to the embodiment, the wiring of each terminal can be efficiently connected.

[0044] [Sixth embodiment] 9 is a schematic diagram showing a semiconductor device according to a sixth embodiment. In the semiconductor device 10, semiconductor layers 12 having different widths are arranged in the x-axis direction. For example, in the sixth embodiment, HEMT elements on n semiconductor layers 12 are combined into one HEMT element.

[0045] (effect) As described above, according to the embodiment, the wiring of each terminal can be efficiently connected.

[0046] [Seventh embodiment] 10 is a schematic diagram showing a semiconductor device according to the seventh embodiment. In a semiconductor device 10, wide semiconductor layers 12 are arranged in the x-axis direction.

[0047] (effect) As described above, according to the embodiment, the wiring of each terminal can be efficiently connected.

[0048] The embodiments disclosed in the present application can be modified without departing from the spirit and scope of the invention. Furthermore, the embodiments disclosed in the present application and their modifications can be combined as appropriate.

[0049] Although specific embodiments have been described in order to fully and clearly disclose the technology of the appended claims, the appended claims should not be limited to the above-described embodiments, but should be construed to embody all modifications and alternative configurations that may be made by those skilled in the art within the scope of the basic subject matter presented in this specification. [Explanation of symbols]

[0050] 10 Semiconductor elements 12 Semiconductor layer (GaN-based semiconductor layer) 13 Source 14 Drain 15 Gate

Claims

1. Two or more semiconductor layers; A substrate; Equipped with At least one of the semiconductor layers has a current flow direction opposite to that of the remaining semiconductor layers. Semiconductor element.

2. The semiconductor layer has a mesa structure. The semiconductor device according to claim 1 .

3. the mesa structure is located over a mask opening; The semiconductor device according to claim 2 .

4. A drain, a source, and a gate are disposed on the surface of the semiconductor layer. The semiconductor device according to claim 1 .

5. The semiconductor layers in which a current flows in a predetermined direction and the semiconductor layers in which a current flows in a direction opposite to the predetermined direction are arranged alternately one by one. The semiconductor device according to claim 1 .

6. Next to one of the semiconductor layers in which a current flows in a predetermined direction, a plurality of the semiconductor layers in which a current flows in a direction opposite to the predetermined direction are arranged side by side. The semiconductor device according to claim 1 .

7. The semiconductor layer in which a current flows in a predetermined direction and the semiconductor layer in which a current flows in a direction opposite to the predetermined direction are arranged alternately in a plurality of layers. The semiconductor device according to claim 1 .

8. A plurality of pairs of drains, sources, and gates are arranged on the surface of the semiconductor layer. The semiconductor device according to claim 1 .

9. The semiconductor layers arranged in a direction perpendicular to the direction of current flow are arranged so that the drain position, the source position, and the gate position are aligned. The semiconductor device according to claim 8.

10. The semiconductor layer is a GaN-based semiconductor layer. A semiconductor device according to any one of claims 1 to 9.

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