Wiring board and semiconductor device

Abstract

To suppress bridge failure of soldering from being caused.SOLUTION: A wiring board has an insulation layer and a connection terminal formed on a surface of the insulation layer. The connection terminal has a metal pad embedded in the insulation layer and a plating layer exposed from the surface of the insulation layer and covering an end surface of the pad. The pad has a cave-in recessed to a position below the surface of the insulation layer, and the plating layer also has a cave-in recessed toward the end surface on the opposite side from the surface contacting the end surface of the pad.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board and a semiconductor device. [Background technology]

[0002] In general, a wiring board on which a semiconductor chip is mounted has connection terminals for connecting to the semiconductor chip. The connection terminals are formed, for example, on the outermost layer of the wiring board, and the semiconductor chip is joined to the connection terminals formed on the outermost layer of the wiring board by using solder.

[0003] Specifically, a pad made of a metal such as copper is embedded in the insulating layer that forms the outermost layer of the wiring board to form a connection terminal. The end face of the pad in the connection terminal is a flat surface exposed from the surface of the insulating layer and is flush with the surface of the insulating layer. Solder is then supplied to this connection terminal, and the connection terminal of the wiring board and the electrode of the semiconductor chip are joined via the solder. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-104774 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the connection terminals of the wiring board described above, the end faces of the pads exposed from the surface of the insulating layer may be covered with a plating layer made of a metal such as nickel for the purpose of improving the wettability of the solder, etc. The plating layer is formed by, for example, an electroless plating method.

[0006] However, there is a problem that a connection terminal whose end face is covered with a plating layer may cause a bridge failure in which the solder connects to a neighboring connection terminal when the connection terminal is joined to a semiconductor chip. That is, when the plating layer of the connection terminal is formed by electroless plating, a metal such as nickel is isotropically deposited and grows on the end face of the pad, and the plating layer protrudes upward in a spherical shape from the end face of the pad. Therefore, when solder is supplied to the connection terminal for joining the semiconductor chip, the solder may flow outward along the spherical plating layer and extend to the side of the connection terminal. As a result, adjacent connection terminals may easily become conductive through the solder, which may cause a bridge failure.

[0007] The disclosed technology has been made in view of the above, and has an object to provide a wiring board and a semiconductor device that can suppress the occurrence of solder bridge defects. [Means for solving the problem]

[0008] In one embodiment, the wiring board disclosed in the present application has an insulating layer and a connection terminal formed on the surface of the insulating layer. The connection terminal has a metal pad embedded in the insulating layer and a plating layer covering an end face of the pad exposed at the surface of the insulating layer. The end face of the pad is recessed in a concave shape to a position lower than the surface of the insulating layer, and the surface of the plating layer opposite to the surface in contact with the end face of the pad is recessed in a concave shape toward the end face. Effect of the Invention

[0009] According to one aspect of the wiring board disclosed in the present application, it is possible to suppress the occurrence of solder bridging defects. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing the configuration of a wiring board according to a first embodiment. [Diagram 2]FIG. 2 is a flowchart showing the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a diagram showing a specific example of a core substrate forming step. [Figure 4] FIG. 4 is a diagram showing a specific example of the build-up process. [Diagram 5] FIG. 5 is a diagram showing a specific example of the solder resist layer forming step. [Figure 6] FIG. 6 is a diagram showing a specific example of a connection terminal forming step. [Figure 7] FIG. 7 is a diagram showing a specific example of a semiconductor chip mounting process. [Figure 8] FIG. 8 is a flowchart showing a connection terminal forming step according to the first embodiment. [Figure 9] FIG. 9 is an enlarged view of a portion of the wiring layer. [Figure 10] FIG. 10 is a diagram showing a specific example of the first insulating layer forming step. [Figure 11] FIG. 11 is a diagram showing a specific example of the seed layer forming step. [Figure 12] FIG. 12 is a diagram showing a specific example of a resist layer forming step. [Figure 13] FIG. 13 is a diagram showing a specific example of an electrolytic plating process. [Figure 14] FIG. 14 is a diagram showing a specific example of the resist layer removing step. [Figure 15] FIG. 15 is a diagram showing a specific example of the second insulating layer laminating step. [Figure 16] FIG. 16 is a diagram showing a specific example of the second insulating layer polishing step. [Figure 17] FIG. 17 is a diagram showing a specific example of the pad polishing process. [Figure 18] FIG. 18 is a diagram showing a specific example of the plating layer forming step. [Figure 19] FIG. 19 is a diagram showing a configuration of a wiring board according to a modified example of the first embodiment. [Figure 20] FIG. 20 is a diagram showing the configuration of a wiring board according to the second embodiment. [Figure 21] FIG. 21 is a flowchart showing a connection terminal forming step according to the second embodiment. [Figure 22] FIG. 22 is a diagram showing a specific example of the outermost insulating layer forming step. [Figure 23] FIG. 23 is a diagram showing a specific example of the seed layer forming step. [Figure 24] FIG. 24 is a diagram showing a specific example of an electrolytic plating process. [Diagram 25] FIG. 25 is a diagram showing a specific example of a metal layer polishing step. [Figure 26] FIG. 26 is a diagram showing a specific example of the plating layer forming step. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the wiring board and semiconductor device disclosed in the present application will be described in detail with reference to the drawings. Note that the disclosed technology is not limited to the embodiments.

[0012] (First embodiment) Fig. 1 is a diagram showing a configuration of a wiring board 100 according to a first embodiment. Fig. 1 shows a schematic cross section of the wiring board 100. The wiring board 100 shown in Fig. 1 can be used, for example, as a substrate for a semiconductor device on which a semiconductor chip is mounted.

[0013] The wiring board 100 has a laminated structure, and includes a core substrate 110, a multilayer wiring structure 120, an outermost insulating layer 130, and a solder resist layer 140. In the following description, the solder resist layer 140 is the bottom layer and the outermost insulating layer 130 is the top layer as shown in Fig. 1, but the wiring board 100 may be used, for example, upside down, or in any position.

[0014] Core substrate 110 has wiring layers 113 formed by plating on both sides of base material 111, which is a plate-like insulator. The wiring layers 113 on both sides are connected by through-wires 112 as necessary.

[0015] The multilayer wiring structure 120 is formed by stacking layers including an insulating insulating layer 121 and a conductive wiring layer 122. The insulating layer 121 is formed using an insulating resin such as an epoxy resin or a polyimide resin. The wiring layer 122 is formed using a metal such as copper. In FIG. 1, two layers are stacked in the multilayer wiring structure 120 above the core substrate 110, and two layers are stacked in the multilayer wiring structure 120 below the core substrate 110, but the number of stacked layers may be one layer or three or more layers.

[0016] The outermost insulating layer 130 is a layer that covers the wiring layer 122 on the surface of the multilayer wiring structure 120. The outermost insulating layer 130 is formed using an insulating photosensitive resin such as an acrylic resin or a polyimide resin. The outermost insulating layer 130 may be formed using an insulating non-photosensitive resin such as an epoxy resin.

[0017] The outermost insulating layer 130 has a two-layer structure and includes a first insulating layer 131 and a second insulating layer 132. The first insulating layer 131 covers the wiring layer 122 on the surface of the multilayer wiring structure 120. The second insulating layer 132 is laminated adjacent to and above the first insulating layer 131.

[0018] The outermost insulating layer 130 side of the wiring board 100 is a surface on which electronic components such as semiconductor chips are mounted. At the position where the semiconductor chip is to be mounted, an opening 133 is formed in the first insulating layer 131 of the outermost insulating layer 130. When the outermost insulating layer 130 is formed using a photosensitive resin, the opening 133 can be formed by exposure and development. When the outermost insulating layer 130 is formed using a non-photosensitive resin, the opening 133 can be formed by laser processing.

[0019] A connection terminal 150 that connects the wiring layer 122 of the multilayer wiring structure 120 and an electrode of the semiconductor chip is formed in the opening 133 of the first insulating layer 131 of the outermost insulating layer 130. The connection terminal 150 is a protruding electrode formed to protrude from the surface 132a of the outermost insulating layer 130, and has a pad 151 and a plating layer 152.

[0020] The pad 151 is an electrode that is the main body of the connection terminal 150, and is embedded in the outermost insulating layer 130 (that is, the first insulating layer 131 and the second insulating layer 132). The pad 151 is formed in the opening 133 of the first insulating layer 131 by, for example, electrolytic plating of copper (Cu) to connect to the wiring layer 122 of the multilayer wiring structure 120, and protrudes upward from the opening 133 of the first insulating layer 131, and the protruding portion is embedded in the second insulating layer 132. An end face (upper surface) of the pad 151 is exposed on the surface 132a of the outermost insulating layer 130, that is, the surface 132a of the second insulating layer 132. The end face of the pad 151 is recessed in a concave shape to a position lower than the surface 132a of the second insulating layer 132, and the periphery of the end face of the pad 151 is higher than the center.

[0021] The plating layer 152 is a metal layer that covers the end faces of the pads 151 exposed on the surface 132a of the second insulating layer 132. The plating layer 152 can be formed by electroless plating using a metal such as nickel (Ni) as a material.

[0022] In this embodiment, since the plating layer 152 is formed along the concave end face of the pad 151, the upper surface of the plating layer 152 is concavely recessed toward the concave end face of the pad 151. As a result, the periphery of the upper surface of the plating layer 152 is higher than the center. Therefore, when solder for joining a semiconductor chip is supplied to the connection terminal 150, the solder is captured by the concave end face of the plating layer 152, and the solder is less likely to flow outward from the plating layer 152. As a result, adjacent connection terminals 150 are less likely to be conductive via the solder, and the occurrence of bridge defects due to solder can be suppressed.

[0023] Furthermore, in this embodiment, the periphery of the end face of the pad 151 is located on the same plane as the surface 132a of the second insulating layer 132. As a result, the end face of the pad 151 and the surface 132a of the second insulating layer 132 located around the end face of the pad 151 are continuously covered with the plating layer 152. This improves the adhesion strength between the plating layer 152 and the end face of the pad 151, and makes it possible to suppress peeling of the plating layer 152 from the end face of the pad 151.

[0024] In this embodiment, the peripheral edge of the end face of the pad 151 contacts the second insulating layer 132. This improves the adhesion strength between the pad 151 and the second insulating layer 132, and prevents the pad 151 from peeling off from the second insulating layer 132.

[0025] Here, the case where the periphery of the end face of the pad 151 is located on the same plane as the surface 132a of the second insulating layer 132 has been described, but the periphery of the end face of the pad 151 may be located at a position lower than the surface 132a of the second insulating layer 132. As a result, the height of the end face of the pad 151 from the surface 132a of the second insulating layer 132 is lower than when the periphery of the end face of the pad 151 is located on the same plane as the surface 132a of the second insulating layer 132. Therefore, the upper surface of the plating layer 152 is recessed deeper in a concave shape toward the concave end face of the pad 151, and when solder for joining a semiconductor chip is supplied to the connection terminal 150, the outward flow of the solder from the plating layer 152 is more unlikely to occur. As a result, the adjacent connection terminals 150 are less likely to be conductive via the solder, and the occurrence of bridge defects due to solder can be more effectively suppressed.

[0026] The solder resist layer 140 is a layer that covers the wiring layer 122 on the surface of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 140 is a layer made of an insulating photosensitive resin such as an acrylic resin or a polyimide resin, and is one of the insulating layers. The solder resist layer 140 may be formed using an insulating non-photosensitive resin such as an epoxy resin.

[0027] The solder resist layer 140 side of the wiring board 100 is the surface to be connected to external components and devices. At the positions where external connection terminals for electrically connecting to external components and devices are to be formed, openings 141 are formed in the solder resist layer 140, and the wiring layer 122 of the multilayer wiring structure 120 is exposed through the openings 141. External connection terminals such as solder balls are formed in the openings 141. When the solder resist layer 140 is formed using a photosensitive resin, the openings 141 can be formed by exposure and development. When the solder resist layer 140 is formed using a non-photosensitive resin, the openings 141 can be formed by laser processing.

[0028] Next, a method for manufacturing a semiconductor device having the wiring substrate 100 configured as described above will be described with a specific example with reference to Fig. 2. Fig. 2 is a flowchart showing the method for manufacturing the semiconductor device according to the first embodiment.

[0029] First, a core substrate 110 that becomes a support member of the wiring substrate 100 is formed (step S101). Specifically, as shown in FIG. 3, for example, a through-wire 112 that penetrates the substrate 111, which is a plate-shaped insulator, is formed, and a wiring layer 113 of metal such as copper or copper alloy is formed on both sides of the substrate 111 by, for example, copper foil or copper plating. FIG. 3 is a diagram showing a specific example of a core substrate forming step. The wiring layers 113 on both sides of the substrate 111 are connected by through-wires 112 formed by plating of metal such as copper or copper alloy as necessary. As the substrate 111, for example, a reinforcing material such as glass woven fabric impregnated with insulating resin such as epoxy resin can be used. As the reinforcing material, glass nonwoven fabric, aramid woven fabric, or aramid nonwoven fabric can be used in addition to glass woven fabric. As the insulating resin, polyimide resin or cyanate resin can be used in addition to epoxy resin. Also, the through-wire 112 may be a through hole that is filled with a thermosetting resin such as epoxy resin.

[0030] Then, a multilayer wiring structure 120 is formed on the upper and lower surfaces of the core substrate 110 by a build-up method (step S102). Specifically, as shown in Fig. 4, for example, an insulating layer 121 is formed on the upper and lower surfaces of the core substrate 110, and a wiring layer 122 is formed on the surface of the insulating layer 121. Fig. 4 is a diagram showing a specific example of the build-up process. The insulating layer 121 is formed using an insulating resin such as an epoxy resin or a polyimide resin. Also, the wiring layer 122 is formed by plating a metal such as copper.

[0031] Between wiring layer 113 and wiring layer 122 of core substrate 110, or between wiring layers 122 of adjacent layers, vias 123 formed by plating with a metal such as copper are connected as necessary. Insulating layer 121 and wiring layer 122 may be laminated in multiple layers on the upper and lower surfaces of core substrate 110, respectively.

[0032] When the multilayer wiring structure 120 is formed, the wiring layer 122 on the surface of the multilayer wiring structure 120 is covered with the solder resist layer 140 (step S103). For example, the wiring layer 122 on the surface of the multilayer wiring structure 120 laminated on the lower surface of the core substrate 110 is covered with the solder resist layer 140.

[0033] Then, as shown in Fig. 5, for example, openings 141 are formed in the solder resist layer 140 on the side to be connected to an external component or device at positions where external connection terminals are to be provided. Fig. 5 is a diagram showing a specific example of a solder resist layer forming step. The wiring layer 122 on the surface of the multilayer wiring structure 120 is exposed at the bottom of the openings 141. When a photosensitive resin is used as the solder resist layer 140, the openings 141 can be formed by exposure and development. When a non-photosensitive resin is used as the solder resist layer 140, the openings 141 can be formed by laser processing.

[0034] Then, the wiring layer 122 on the surface of the multilayer wiring structure 120 is covered with the outermost insulating layer 130, and the connection terminal 150 protruding from the surface 132a of the outermost insulating layer 130 is formed (step S104). That is, as shown in FIG. 6, for example, the connection terminal 150 is formed having a pad 151 embedded in the outermost insulating layer 130 and a plating layer 152 covering an end face of the pad 151 exposed on the surface 132a of the outermost insulating layer 130. FIG. 6 is a diagram showing a specific example of the connection terminal forming step. The pad 151 is formed in the opening 133 of the first insulating layer 131 by electrolytic plating of copper (Cu), for example. The plating layer 152 can be formed by electroless plating of a metal such as nickel (Ni), for example. In the connection terminal 150, the end face (upper face) of the pad 151 is concavely recessed to a position lower than the surface 132a of the outermost insulating layer 130, and the upper face of the plating layer 152 is concavely recessed toward the concave end face of the pad 151. The process of forming the connection terminal 150 will be described in detail later.

[0035] When the connection terminal 150 is formed on the outermost insulating layer 130 side, an external connection terminal is formed on the solder resist layer 140 side (step S105). Then, a semiconductor chip is mounted on the outermost insulating layer 130 side (step S106), and the connection terminal 150 and the electrode of the semiconductor chip are connected. Specifically, for example, as shown in FIG. 7, an external connection terminal such as a solder ball 170 is formed in the opening 141 of the solder resist layer 140. Also, the semiconductor chip 200 is mounted above the connection terminal 150, and the electrode 210 of the semiconductor chip 200 is joined to the connection terminal 150 by the solder 210a supplied to the plating layer 152. At this time, since the upper surface of the plating layer 152 is recessed in a concave shape toward the concave end surface of the pad 151, the supplied solder 210a is captured by the concave upper surface of the plating layer 152, and the outflow of the solder 210a to the outside of the plating layer 152 is less likely to occur. As a result, adjacent connection terminals 150 are less likely to be electrically connected to each other via the solder 210a, making it possible to suppress the occurrence of bridge defects due to the solder 210a. Figure 7 shows a specific example of a semiconductor chip mounting process.

[0036] Then, the joints between the electrodes 210 and the connection terminals 150 are sealed with underfill resin 230, completing a semiconductor device in which the semiconductor chip 200 is mounted on the wiring substrate 100. The order of the step of forming the external connection terminals and the step of mounting the semiconductor chip may be reversed. That is, after the semiconductor chip 200 is mounted on the wiring substrate 100, external connection terminals such as solder balls 170 may be formed in the openings 141 of the solder resist layer 140.

[0037] Next, the step of forming the connection terminal 150 will be described more specifically with reference to Fig. 8. Fig. 8 is a flowchart showing the step of forming the connection terminal according to the first embodiment. Here, a case will be described in which an outermost insulating layer 130 and the connection terminal 150 are formed on the uppermost wiring layer 122 of the multilayer wiring structure 120, as shown in Fig. 9, for example. Fig. 9 is an enlarged view of a portion of the wiring layer 122.

[0038] When the multilayer wiring structure 120 is laminated on the upper surface of the core substrate 110, the uppermost wiring layer 122 of the multilayer wiring structure 120 is covered with a first insulating layer 131 (step S201). An opening 133 is formed in the first insulating layer 131, for example, as shown in FIG. 10. FIG. 10 is a diagram showing a specific example of the first insulating layer forming step. When the outermost insulating layer 130 is formed using a photosensitive resin, the opening 133 can be formed by exposure and development. When the outermost insulating layer 130 is formed using a non-photosensitive resin, the opening 133 can be formed by laser processing. The wiring layer 122 is exposed at the bottom of the opening 133. The thickness of the first insulating layer 131 is, for example, about 20 to 40 μm.

[0039] In this state, a seed layer is formed on the surface of first insulating layer 131 (step S202). That is, as shown in Fig. 11, for example, seed layer 301 is formed on the entire surface of first insulating layer 131 and wiring layer 122 exposed in opening 133 by, for example, electroless copper plating or copper sputtering. Fig. 11 is a diagram showing a specific example of the seed layer formation step. The thickness of seed layer 301 is, for example, about 0.01 to 0.40 µm.

[0040] After the seed layer 301 is formed, a resist layer serving as a mask for electrolytic plating is formed on the surface of the seed layer 301 (step S203). That is, a dry film resist (DFR) made of a photosensitive resin is laminated on the seed layer 301. Then, the laminated DFR is exposed and developed according to the positions of the connection terminals 150, thereby forming a resist layer 302 on the seed layer 301 except for the positions where the connection terminals 150 are to be formed, as shown in FIG. 12, for example. FIG. 12 is a diagram showing a specific example of the resist layer formation step.

[0041] Then, for example, electrolytic plating is performed to form pads 151 on seed layer 301 (step S204). Specifically, for example, electrolytic copper plating is performed using a copper sulfate plating solution, whereby copper is deposited in the portions where resist layer 302 is not formed, and pads 151 are formed on seed layer 301, as shown in Fig. 13. At this time, openings 133 are filled with pads 151. Fig. 13 is a diagram showing a specific example of the electrolytic plating process.

[0042] When the pad 151 is formed, the resist layer 302 is removed (step S205). For example, caustic soda or an amine-based alkaline stripping solution is used to remove the resist layer 302. Flash etching is also performed to remove the seed layer 301 from the unplated portion. As a result, as shown in FIG. 14, for example, the pad 151 is formed, which protrudes from the opening 133 of the first insulating layer 131 and connects to the wiring layer 122 via the seed layer 301. FIG. 14 is a diagram showing a specific example of the resist layer removal step. The thickness of the pad 151 (height from the upper surface of the first insulating layer 131) can be, for example, about 3 to 20 μm.

[0043] After the resist layer 302 is removed, a second insulating layer 132 that covers the pads 151 is laminated on the first insulating layer 131 (step S206), as shown in Fig. 15. Fig. 15 is a diagram showing a specific example of the second insulating layer laminating step. The thickness of the second insulating layer 132 is, for example, about 10 to 45 µm.

[0044] Then, the entire second insulating layer 132 is polished from the surface 132a onwards by, for example, chemical mechanical polishing (CMP) (step S207). Specifically, as shown in FIG. 16, the second insulating layer 132 is polished until the surface 132a of the second insulating layer 132 is flush with the end surface (upper surface) 151a of the pad 151, and the end surface 151a of the pad 151 is exposed on the surface 132a of the second insulating layer 132. Through the steps up to this point, the outermost insulating layer 130 having the first insulating layer 131 and the second insulating layer 132 is obtained, and the pad 151 embedded in the outermost insulating layer 130 (i.e., the first insulating layer 131 and the second insulating layer 132) is obtained. FIG. 16 is a diagram showing a specific example of the second insulating layer polishing step.

[0045] After the second insulating layer 132 is polished, the end surface 151a of the pad 151 exposed on the surface 132a of the second insulating layer 132 is polished by, for example, CMP (step S208). Specifically, the end surface of the pad 151 is polished by CMP using a chemical polishing liquid such as hydrogen peroxide solution. As a result, as shown in FIG. 17, the end surface 151a of the pad 151 exposed on the surface 132a of the second insulating layer 132 is recessed in a concave shape to a position lower than the surface 132a of the second insulating layer 132. FIG. 17 is a diagram showing a specific example of the pad polishing step. The periphery of the end surface 151a of the pad 151 is located on the same plane as the surface 132a of the second insulating layer 132. The end surface 151a of the pad 151 is in contact with the second insulating layer 132 at its periphery. The deepest part of the end surface 151a of the pad 151 may be located below the upper surface of the first insulating layer 131. In other words, the pad 151 may have an end surface 151 a that is recessed to a position closer to the wiring layer 122 than the surface of the first insulating layer 131 .

[0046] After polishing the pad 151, a plating layer 152 is formed covering an end surface 151a of the pad 151 by electroless plating using a metal such as nickel (Ni) as a material (step S209), for example, as shown in FIG. 18. This forms a connection terminal 150 that is connected to the uppermost wiring layer 122 of the multilayer wiring structure 120 and has the pad 151 and the plating layer 152. FIG. 18 is a diagram showing a specific example of the plating layer formation step. The thickness of the plating layer 152 can be, for example, about 1 μm to 10 μm.

[0047] In the formation of the plating layer 152, a metal such as nickel is isotropically deposited and grows on the end surface 151a of the pad 151. Therefore, the plating layer 152 is formed along the concavely recessed end surface 151a of the pad 151, and the upper surface 152a of the plating layer 152 is recessed concavely toward the concave end surface 151a of the pad 151. As a result, when the semiconductor chip 200 is mounted, the solder 210a supplied to the plating layer 152 of the connection terminal 150 is captured by the concavely recessed upper surface 152a of the plating layer 152, and the outflow of the solder 210a to the outside of the plating layer 152 is unlikely to occur. As a result, the adjacent connection terminals 150 are unlikely to be electrically connected to each other via the solder 210a, and the occurrence of bridge defects due to the solder 210a can be suppressed.

[0048] In addition, in the formation of the plating layer 152, a metal such as nickel is deposited and grown not only on the end face 151a of the pad 151 but also on the surface 132a of the second insulating layer 132 located around the end face 151a of the pad 151. Here, since the periphery of the end face 151a of the pad 151 is located on the same plane as the surface 132a of the second insulating layer 132, the plating layer 152 is formed on the surface 132a of the second insulating layer 132 beyond the periphery of the end face 151a of the pad 151. Therefore, the plating layer 152 is formed across the second insulating layer 132 and the pad 151 in a plan view. In other words, the side surface of the plating layer 152 is located outward from the periphery of the end face 151a of the pad 151. As a result, the end face 151a of the pad 151 and the surface 132a of the second insulating layer 132 located around the end face of the pad 151 are continuously covered with the plating layer 152. This improves the adhesion strength between the plating layer 152 and the end surface of the pad 151, making it possible to suppress peeling of the plating layer 152 from the end surface 151a of the pad 151.

[0049] As described above, the wiring board (for example, wiring board 100) according to the first embodiment has an insulating layer (for example, outermost insulating layer 130) and a connection terminal (for example, connection terminal 150) formed on the surface (for example, surface 132a) of the insulating layer. The connection terminal has a metal pad (for example, pad 151) embedded in the insulating layer and a plating layer (for example, plating layer 152) covering an end face (for example, end face 151a) of the pad exposed on the surface of the insulating layer. The end face of the pad is recessed in a concave shape to a position lower than the surface of the insulating layer, and the surface of the plating layer opposite to the surface in contact with the end face of the pad (for example, upper surface 152a) is recessed in a concave shape toward the end face. This makes it possible to suppress the occurrence of bridge defects due to solder (for example, solder 210a).

[0050] The end face of the pad may have a rim that is flush with the surface of the insulating layer, thereby making it possible to suppress peeling of the plating layer from the end face of the pad.

[0051] The end face of the pad may have a rim that is located lower than the surface of the insulating layer, thereby making it possible to further prevent the occurrence of solder bridging defects.

[0052] The end face of the pad may be in contact with the insulating layer at its periphery, thereby making it possible to prevent the pad from peeling off from the insulating layer.

[0053] The insulating layer may have a first insulating layer (for example, first insulating layer 131) and a second insulating layer (for example, second insulating layer 132) laminated on the first insulating layer. The first insulating layer may cover the wiring layer (for example, wiring layer 122) and have an opening (for example, opening 133) that penetrates to the wiring layer. The pad may be formed in the opening of the first insulating layer to connect to the wiring layer and protrude from the opening of the first insulating layer, and the protruding portion may be embedded in the second insulating layer. As a result, since the insulating layer has a two-layer structure, the adhesive strength between the pad and the insulating layer can be improved.

[0054] (Modification of the first embodiment) 19 is a diagram showing the configuration of a wiring board 100 according to a modified example of the first embodiment. In this modified example, the same components as those in the first embodiment are given the same reference numerals, and redundant explanations will be omitted.

[0055] As shown in FIG. 19, the wiring board 100 according to the modification is different from the first embodiment in that the connection terminal 150 has a surface treatment layer 153. The surface treatment layer 153 is a metal layer that covers the upper surface and side surface of the plating layer 152. Specifically, the surface treatment layer 153 has a palladium (Pd) layer and a gold (Au) layer in this order from the side closer to the plating layer 152 made of nickel (Ni), although not shown in the figure. The Pd layer and the Au layer can be formed by, for example, electrolytic plating or electroless plating. The thickness of the Pd layer and the Au layer can be, for example, about 0.01 to 0.5 μm. As the surface treatment layer 153, a single Au layer may be used instead of the Pd / Au layer.

[0056] In forming the surface treatment layer 153, palladium and gold are isotropically deposited and grown on the upper surface and side surfaces of the plating layer 152. Therefore, the surface treatment layer 153 is formed along the concave upper surface of the plating layer 152, and the upper surface of the surface treatment layer 153 is concavely depressed toward the concave upper surface of the plating layer 152.

[0057] In the modified example, the upper and side surfaces of the plating layer 152 are covered with the surface treatment layer 153, thereby improving the wettability of the solder 210a, for example, when the electrode 210 of the semiconductor chip 200 is joined to the connection terminal 150 by the solder 210a.

[0058] Second embodiment 20 is a diagram showing the configuration of a wiring board 100 according to the second embodiment. In the second embodiment, the same components as those in the first embodiment are given the same reference numerals, and redundant explanations will be omitted.

[0059] 20, the wiring board 100 according to the second embodiment differs from the first embodiment in the structure of the outermost insulating layer 130 and the structure of the pads 151 of the connection terminals 150. Specifically, the outermost insulating layer 130 has a single-layer structure and covers the wiring layer 122 on the surface of the multilayer wiring structure 120. The thickness of the outermost insulating layer 130 is, for example, about 20 to 40 μm. An opening 133 is formed in the outermost insulating layer 130 at a position where a semiconductor chip is to be mounted.

[0060] The pad 151 is an electrode that is the main body of the connection terminal 150, and is embedded in the outermost insulating layer 130. The pad 151 is formed in the opening 133 of the first insulating layer 131 by, for example, electrolytic plating of copper (Cu), and is connected to the wiring layer 122 of the multilayer wiring structure 120. An end face (upper face) of the pad 151 is exposed on the surface 130a of the outermost insulating layer 130. The end face of the pad 151 is recessed in a concave shape to a position lower than the surface 130a of the outermost insulating layer 130, and the periphery of the end face of the pad 151 is higher than the center.

[0061] In this embodiment, similarly to the first embodiment, the plating layer 152 is formed along the concave end face of the pad 151, so that the upper surface of the plating layer 152 is concave toward the concave end face of the pad 151. This makes it possible to suppress the occurrence of bridge defects due to solder.

[0062] Furthermore, in this embodiment, the outermost insulating layer 130 has a single-layer structure and is therefore thinner than an outermost insulating layer 130 having a two-layer structure. This can facilitate the thinning of the wiring board 100.

[0063] Next, a process for forming the connection terminal 150 will be described with reference to Fig. 21. Fig. 21 is a flowchart showing the process for forming the connection terminal according to the second embodiment. Here, a case will be described in which the outermost insulating layer 130 and the connection terminal 150 are formed on the uppermost wiring layer 122 of the multilayer wiring structure 120, as shown in Fig. 9, for example.

[0064] When the multilayer wiring structure 120 is laminated on the upper surface of the core substrate 110, the uppermost wiring layer 122 of the multilayer wiring structure 120 is covered with the outermost insulating layer 130 (step S301). An opening 133 is formed in the outermost insulating layer 130, for example, as shown in FIG. 22. FIG. 22 is a diagram showing a specific example of the outermost insulating layer forming step. When the outermost insulating layer 130 is formed using a photosensitive resin, the opening 133 can be formed by exposure and development. When the outermost insulating layer 130 is formed using a non-photosensitive resin, the opening 133 can be formed by laser processing. The wiring layer 122 is exposed at the bottom of the opening 133. The thickness of the outermost insulating layer 130 is, for example, about 20 to 40 μm.

[0065] In this state, a seed layer is formed on the surface 130a of the outermost insulating layer 130 (step S302). That is, as shown in Fig. 23, for example, a seed layer 301 is formed on the entire surface of the surface 130a of the outermost insulating layer 130 and the wiring layer 122 exposed in the opening 133 by, for example, electroless copper plating or copper sputtering. Fig. 23 is a diagram showing a specific example of the seed layer formation step. The thickness of the seed layer 301 is, for example, about 0.01 to 0.40 µm.

[0066] Then, for example, electrolytic plating is performed to form a metal layer 151A on the seed layer 301 (step S303). Specifically, for example, electrolytic copper plating is performed using a copper sulfate plating solution to deposit copper on the entire upper surface of the seed layer 301, and as shown in Fig. 24, for example, a metal layer 151A is formed on the entire upper surface of the seed layer 301. At this time, the metal layer 151A fills the inside of the opening 133 and extends around the opening 133 on the surface 130a of the outermost insulating layer 130. Fig. 24 is a diagram showing a specific example of the electrolytic plating process.

[0067] When the metal layer 151A is formed, the entire upper surface of the metal layer 151A is polished by, for example, CMP (step S304). Specifically, the metal layer 151A is polished by CMP using a chemical polishing liquid such as hydrogen peroxide until the surface 130a of the outermost insulating layer 130 is exposed. As a result, the part of the metal layer 151A located on the surface 130a of the outermost insulating layer 130 is polished and the metal layer 151A remains inside the opening 133, and for example, as shown in FIG. 25, a pad 151 connected to the wiring layer 122 via the seed layer 301 is formed. FIG. 25 is a diagram showing a specific example of the metal layer polishing step. The seed layer 301 on the surface 130a of the outermost insulating layer 130 is polished and removed together with the metal layer 151A on the surface 130a of the outermost insulating layer 130.

[0068] In addition, in the process of polishing the metal layer 151A, in parallel with the formation of the pad 151, the end face (upper face) 151a of the pad 151 exposed on the surface 130a of the outermost insulating layer 130 is further polished downward from the surface 130a of the outermost insulating layer 130. As a result, the end face 151a of the pad 151 is recessed in a concave shape to a position lower than the surface 130a of the outermost insulating layer 130. The periphery of the end face 151a of the pad 151 is located on the same plane as the surface 130a of the outermost insulating layer 130. In addition, the periphery of the end face 151a of the pad 151 is in contact with the second insulating layer 132 via the seed layer 301. Through the process up to this point, the pad 151 embedded in the outermost insulating layer 130 is obtained.

[0069] After the pad 151 is formed, the surface 130a of the outermost insulating layer 130 is polished by, for example, CMP (step S305) to remove the residue of the metal layer 151A remaining on the surface 130a of the outermost insulating layer 130. Thereafter, a plating layer 152 covering the end surface 151a of the pad 151 is formed by electroless plating using a metal such as nickel (Ni) (step S306), for example, as shown in FIG. 26. This forms a connection terminal 150 that is connected to the uppermost wiring layer 122 of the multilayer wiring structure 120 and has the pad 151 and the plating layer 152. FIG. 26 is a diagram showing a specific example of the plating layer forming step. The thickness of the plating layer 152 can be, for example, about 1 μm to 10 μm.

[0070] In the formation of the plating layer 152, a metal such as nickel is isotropically deposited and grows on the end surface 151a of the pad 151. Therefore, the plating layer 152 is formed along the concavely recessed end surface 151a of the pad 151, and the upper surface 152a of the plating layer 152 is recessed concavely toward the concave end surface 151a of the pad 151. As a result, when the semiconductor chip 200 is mounted, the solder 210a supplied to the plating layer 152 of the connection terminal 150 is captured by the concavely recessed upper surface 152a of the plating layer 152, and the outflow of the solder 210a to the outside of the plating layer 152 is unlikely to occur. As a result, the adjacent connection terminals 150 are unlikely to be electrically connected to each other via the solder 210a, and the occurrence of bridge defects due to the solder 210a can be suppressed.

[0071] In addition, in the formation of the plating layer 152, a metal such as nickel is deposited and grown not only on the end face 151a of the pad 151 but also on the surface 130a of the outermost insulating layer 130 located around the end face 151a of the pad 151. Here, since the periphery of the end face 151a of the pad 151 is located on the same plane as the surface 130a of the outermost insulating layer 130, the plating layer 152 is formed on the surface 130a of the outermost insulating layer 130 beyond the periphery of the end face 151a of the pad 151. Therefore, the plating layer 152 is formed across the outermost insulating layer 130 and the pad 151 in a plan view. In other words, the side surface of the plating layer 152 is located outward from the periphery of the end face 151a of the pad 151. As a result, the end face 151a of the pad 151 and the surface 130a of the outermost insulating layer 130 located around the end face of the pad 151 are continuously covered with the plating layer 152. This improves the adhesion strength between the plating layer 152 and the end surface of the pad 151, making it possible to suppress peeling of the plating layer 152 from the end surface 151a of the pad 151.

[0072] In the second embodiment, an insulating layer (for example, outermost insulating layer 130) covers a wiring layer (for example, wiring layer 122) and has an opening (for example, opening 133) that penetrates to the wiring layer. A pad (for example, pad 151) is formed in the opening of the insulating layer and connected to the wiring layer. This results in a single-layered insulating layer, which can suppress the occurrence of solder bridging defects and facilitates the thinning of the wiring board.

[0073] (Modification of the second embodiment) In the wiring board 100 according to the second embodiment, similarly to the first embodiment, the upper surface and side surfaces of the plating layer 152 may be covered with a surface treatment layer 153 (see FIG. 19). This can improve the wettability of the solder 210a when, for example, the electrode 210 of the semiconductor chip 200 is joined to the connection terminal 150 by the solder 210a. [Explanation of symbols]

[0074] 100 Wiring board 110 Core Board 111 Base material 112 Through Wiring 113 Wiring layer 120 Multilayer wiring structure 121 Insulating layer 122 wiring layer 123 Beer 130 Outermost insulating layer 130a surface 131 First insulating layer 132 Second insulating layer 132a surface 133 Opening 140 Solder resist layer 141 Opening 150 Connection terminal 151 Pad 151a End face 151A Metal layer 152a top surface 153 Surface treatment layer 170 Balls 200 Semiconductor Chips 210 electrode 230 Underfill resin 301 Seed layer 302 Resist layer

Claims

1. An insulating layer; a connection terminal formed on a surface of the insulating layer; having The connection terminal is a metal pad embedded in the insulating layer; a plating layer covering the end faces of the pads exposed on the surface of the insulating layer; having The end surface of the pad is The insulating layer is recessed in a concave shape to a position lower than the surface of the insulating layer, The plating layer is The surface opposite to the surface in contact with the end surface of the pad is recessed in a concave shape toward the end surface. A wiring board comprising:

2. The end surface of the pad is A periphery that is flush with the surface of the insulating layer.

2. The wiring board according to claim 1.

3. The end surface of the pad is A periphery located below the surface of the insulating layer 2. The wiring board according to claim 1.

4. The end surface of the pad is The insulating layer is in contact with the periphery.

2. The wiring board according to claim 1.

5. The plating layer is Made of nickel 2. The wiring board according to claim 1.

6. The plating layer is The insulating layer is formed across the pad in a plan view.

2. The wiring board according to claim 1.

7. The insulating layer is A first insulating layer; a second insulating layer laminated on the first insulating layer; having The first insulating layer is a conductive layer that covers the wiring layer and has an opening that penetrates to the wiring layer; The pad is a first insulating layer that is formed in an opening of the first insulating layer and is connected to the wiring layer, and that protrudes from the opening of the first insulating layer and is embedded in the second insulating layer at the protruding portion; 2. The wiring board according to claim 1.

8. The insulating layer is a conductive layer that covers the wiring layer and has an opening that penetrates to the wiring layer; The pad is The insulating layer is formed in an opening portion thereof and is connected to the wiring layer.

2. The wiring board according to claim 1.

9. The connection terminal is a surface treatment layer that covers the surface of the plating layer opposite to the surface that contacts the end surface of the pad and the side surface; 2. The wiring board according to claim 1, further comprising:

10. A wiring board; A semiconductor chip mounted on the wiring board; having The wiring board includes: An insulating layer; a connection terminal formed on a surface of the insulating layer; having The connection terminal is a metal pad embedded in the insulating layer; a plating layer covering an end surface of the pad exposed on a surface of the insulating layer; having The end surface of the pad is The insulating layer is recessed in a concave shape to a position lower than the surface of the insulating layer, The plating layer is a surface opposite to a surface in contact with the end surface of the pad is recessed in a concave shape toward the end surface; The semiconductor chip comprises: The semiconductor chip is mounted above the connection terminal, and electrodes of the semiconductor chip are joined to the connection terminals by solder supplied to the plating layer. A semiconductor device comprising:

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