Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of suitably inhibiting crack extension, and a method of manufacturing the same.SOLUTION: A semiconductor device comprises an upper substrate 20 that is arranged on a lower substrate 10, and an interlayer dielectric film 22 that is provided on the upper substrate 20. The interlayer dielectric film 22 includes a plurality of cavities Ga, Gb, Gc and Gd provided at different heights. The plurality of cavities Ga, Gb, Gc and Gd are arranged in a staircase pattern. Crack extension during dicing can be suitably inhibited by the plurality of cavities Ga, Gb, Gc and Gd.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] When manufacturing semiconductor devices such as photodetectors by dicing a wafer, cracks may occur in the chips or chipping may occur due to the cracks. If the cracks extend to the guard ring or pixels in the chip, the quality of the semiconductor device may deteriorate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-120870 A [Patent Document 2] International Application Publication No. WO2021 / 100579 Summary of the Invention [Problem to be solved by the invention]

[0004] In order to prevent cracks from propagating during dicing, it is possible to form a cavity in the chip before dicing. This makes it possible to prevent the crack from propagating by the cavity. However, if the stress that propagates the crack is large, the cavity may not be able to sufficiently prevent the crack from propagating.

[0005] In view of this, the present disclosure provides a semiconductor device capable of suitably suppressing the propagation of cracks, and a manufacturing method thereof. [Means for solving the problem]

[0006] A semiconductor device according to a first aspect of the present disclosure includes a first substrate and an insulating film provided on the first substrate, the insulating film including a plurality of cavities provided at different heights, the plurality of cavities being arranged in a stepped manner. This makes it possible to suitably suppress the propagation of cracks by the cavities. For example, it is possible to cause the cracks to propagate so as to reach the upper surface of the insulating film before reaching a guard ring or a pixel.

[0007] In the first aspect, the cavities may be provided at positions that do not overlap with one another in a plan view, which makes it possible, for example, to gradually tilt the direction in which a crack propagates.

[0008] In addition, in the first aspect, one of the cavities may be provided between a first wiring and a second wiring in one wiring layer provided in the insulating film in a plan view. This makes it possible to extend a crack between the first wiring and the second wiring, for example. Furthermore, it is possible to form the cavity as part of a process of forming these wirings.

[0009] In addition, in this first aspect, the plurality of cavities may include first to Nth cavities provided at first to Nth heights (N is an integer of 2 or more), respectively, and the first to Nth cavities may be arranged in a staircase shape with N steps. This makes it possible, for example, to suitably suppress the extension of a crack by the first to Nth cavities.

[0010] The semiconductor device on the first side may further include first to Nth wiring layers provided at the first to Nth heights in the insulating film, and the first to Nth cavities may be provided in the first to Nth wiring layers, respectively. This makes it possible to control, for example, the direction in which a crack extends by the first to Nth cavities and the first to Nth wiring layers.

[0011] In addition, in this first aspect, the insulating film may include two or more cavities provided at the Kth height as a Kth cavity (K is an integer satisfying 1≦K≦N), and the two or more cavities may be arranged to form a ring in a planar view. This makes it possible to arrange, for example, the two or more cavities so as to surround a pixel or a guard ring in a planar view.

[0012] The semiconductor device according to the first aspect may further include a pixel region including a plurality of pixels and an extra-pixel region surrounding the pixel region in a plan view, and the plurality of cavities may be disposed in the extra-pixel region, which makes it possible to dispose the cavities so as to prevent cracks from extending to the pixels, for example.

[0013] In addition, in the first aspect, the extra-pixel region may include a guard ring surrounding the pixel region in a plan view, and the guard ring may be disposed between the pixel region and the cavities, which makes it possible to dispose the cavities so as to prevent cracks from extending to the guard ring, for example.

[0014] The semiconductor device according to the first aspect may further include a second substrate provided on the insulating film and having a slit, which allows, for example, a crack to escape to the slit.

[0015] In addition, in the first aspect, the slits may be provided at positions that do not overlap with the plurality of cavities in a plan view, which makes it possible, for example, to gradually tilt the direction in which a crack extends due to the cavities and the slits.

[0016] In addition, in the first aspect, the insulating film may include a first insulating film provided on the first substrate and a second insulating film provided on the first insulating film, and the cavities may be provided in the second insulating film. This makes it possible to preferably suppress the propagation of cracks by the cavities when, for example, bonding the first substrate and the second substrate together to manufacture a semiconductor device.

[0017] The semiconductor device of the first side further includes a wiring provided in the first insulating film, a first pad provided in the first insulating film and electrically connected to the wiring, and a second pad provided on the first pad in the second insulating film, and the wiring, the first pad, or the second pad may be provided at a position overlapping at least one of the cavities in a plan view. This makes it possible to suitably suppress the extension of cracks by the cavities, the wiring, and the pad, for example, when manufacturing a semiconductor device by bonding a first substrate and a second substrate together.

[0018] The semiconductor device on the first side may further include a first pad provided in the first insulating film and a second pad provided on the first pad in the second insulating film, the first pad or the second pad being provided at a position overlapping at least one of the cavities in a plan view. This makes it possible to suitably suppress the propagation of cracks by the cavities and the pads, for example, when manufacturing a semiconductor device by bonding a first substrate and a second substrate together.

[0019] The semiconductor device of the first side may further include wiring provided in the first insulating film, the wiring being provided at a position overlapping at least one of the cavities in a plan view. This makes it possible to preferably suppress the propagation of cracks by the cavities and wiring, for example, when manufacturing a semiconductor device by bonding a first substrate and a second substrate together.

[0020] A semiconductor device according to a second aspect of the present disclosure includes a first substrate and an insulating film provided on the first substrate, the insulating film including a first cavity and a second cavity provided at different heights, the first cavity and the second cavity being provided at different positions in a plan view. This makes it possible to effectively suppress the propagation of cracks by these cavities. For example, it is possible to cause cracks to propagate so as to reach the upper surface of the insulating film before reaching a guard ring or a pixel.

[0021] In the second aspect, the first cavity and the second cavity may be provided at positions that do not overlap with each other in a plan view, which makes it possible to tilt the direction in which a crack propagates, for example.

[0022] A method for manufacturing a semiconductor device according to a third aspect of the present disclosure includes forming an insulating film on a first substrate, and dicing the first substrate after the insulating film is formed, the insulating film being formed to include a plurality of cavities at different heights, the plurality of cavities being arranged in a stepped pattern. This makes it possible to suitably suppress the extension of cracks by these cavities. For example, it is possible to make the cracks extend so as to reach the upper surface of the insulating film before reaching a guard ring or a pixel.

[0023] In addition, in the third aspect, the insulating film may be formed to include a first insulating film and a second insulating film, the insulating film may be formed by forming the first insulating film on the first substrate, forming the second insulating film on the second substrate to include the cavities, bonding the first substrate and the second substrate together to sandwich the first insulating film and the second insulating film, and dicing the first substrate and the second substrate after the bonding. This makes it possible to preferably suppress the propagation of cracks by the cavities, for example, when manufacturing a semiconductor device by bonding the first substrate and the second substrate together.

[0024] In addition, in the third aspect, one of the cavities may be formed between a first wiring and a second wiring in one wiring layer provided in the insulating film in a plan view. This makes it possible to extend a crack between the first wiring and the second wiring, for example. Furthermore, it is possible to form the cavity as part of a process of forming these wirings.

[0025] In addition, in the third aspect, the one cavity included in the plurality of cavities may be formed by forming the first wiring and the second wiring in a first film of the insulating film, forming a first recess in the first film between the first wiring and the second wiring, and forming a second film of the insulating film such that the one cavity remains in the first recess. Thereby, for example, it becomes possible to form a cavity in the insulating film by leaving a cavity in the first recess. [Brief description of the drawings]

[0026] [Figure 1] 1 is a block diagram showing a configuration of a photodetector according to a first embodiment; [Diagram 2] 1 is a cross-sectional view showing a structure of a photodetector according to a first embodiment. [Diagram 3] 5A to 5C are cross-sectional views illustrating a method for manufacturing the photodetector of the first embodiment. [Figure 4] 5A to 5C are other cross-sectional views illustrating the method for manufacturing the photodetector of the first embodiment. [Diagram 5] FIG. 2 is a plan view illustrating a method for manufacturing the photodetector according to the first embodiment. [Figure 6] FIG. 1 is a plan view showing a structure of a photodetector according to a first embodiment. [Figure 7] FIG. 4 is another plan view showing the structure of the photodetector according to the first embodiment. [Figure 8] 10A and 10B are cross-sectional views for explaining a problem with a photodetector according to a comparative example of the first embodiment. [Figure 9] 1A and 1B are a cross-sectional view and an enlarged cross-sectional view for explaining a problem with a photodetector according to a comparative example of the first embodiment. [Figure 10] 1A and 1B are a cross-sectional view and an enlarged cross-sectional view for explaining advantages of the photodetector of the first embodiment; [Figure 11] 4 is a cross-sectional view (1 / 3) illustrating the method for manufacturing the photodetector of the first embodiment. FIG. [Figure 12] 5A to 5C are cross-sectional views (2 / 3) illustrating the method for manufacturing the photodetector of the first embodiment. [Figure 13]4 is a cross-sectional view (3 / 3) illustrating the method for manufacturing the photodetector according to the first embodiment. FIG. [Figure 14] 1 is a cross-sectional view showing a structure of a photodetector according to a first embodiment. [Figure 15] FIG. 11 is a cross-sectional view showing the structure of a photodetector according to a second embodiment. [Figure 16] FIG. 11 is a cross-sectional view showing the structure of a photodetector according to a third embodiment. [Figure 17] FIG. 13 is a cross-sectional view showing the structure of a photodetector according to a fourth embodiment. [Figure 18] FIG. 1 is a block diagram showing an example of the configuration of an electronic device. [Figure 19] FIG. 1 is a block diagram showing a configuration example of a mobile object control system. [Figure 20] 20 is a plan view showing a specific example of the setting position of the imaging unit in FIG. 19. [Figure 21] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 22] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0028] (First embodiment) FIG. 1 is a block diagram showing the configuration of a photodetector according to the first embodiment.

[0029] The photodetector of Fig. 1 is, for example, a solid-state imaging device such as a CMOS (Complementary Metal Oxide Semiconductor) type image sensor (CIS). The photodetector of Fig. 1 includes a pixel array 2 including a plurality of pixels 1, a control circuit 3, a vertical drive circuit 4, a plurality of column signal processing circuits 5, a horizontal drive circuit 6, an output circuit 7, a plurality of vertical signal lines (VSL) 8, and a horizontal signal line (HSL) 9. The photodetector of Fig. 1 is an example of a semiconductor device of the present disclosure.

[0030] Each pixel 1 includes a photodiode that functions as a photoelectric conversion unit and a MOS transistor that functions as a pixel transistor. The pixel transistor may be, for example, a transfer transistor, a reset transistor, an amplification transistor, a selection transistor, a conversion efficiency switching transistor, a switch transistor, or the like. These pixel transistors may be shared by several pixels 1. Each pixel 1 may further include a floating diffusion unit, a pixel memory, or the like.

[0031] The pixel array 2 includes a plurality of pixels 1 arranged in a two-dimensional array. The pixel array 2 also includes an effective pixel region that receives light, performs photoelectric conversion, and outputs a signal charge generated by the photoelectric conversion, and a black reference pixel region that outputs optical black that serves as a reference for the black level. In general, the black reference pixel region is arranged on the periphery of the effective pixel region.

[0032] The control circuit 3 generates various signals that serve as references for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, a master clock, etc. The signals generated by the control circuit 3 are, for example, clock signals and control signals, and are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0033] The vertical drive circuit 4 includes, for example, a shift register, and vertically scans each pixel 1 in the pixel array 2 on a row-by-row basis. The vertical drive circuit 4 further supplies a pixel signal based on the signal charge generated by each pixel 1 to a column signal processing circuit 5 through a vertical signal line 8.

[0034] The column signal processing circuit 5 is arranged, for example, for each column of pixels 1 in the pixel array 2, and performs signal processing for each column of signals output from one row of pixels 1 based on signals from the black reference pixel region. Examples of this signal processing include noise removal and signal amplification.

[0035] The horizontal drive circuit 6 includes, for example, a shift register, and supplies pixel signals from each column signal processing circuit 5 to a horizontal signal line 9 .

[0036] The output circuit 7 processes signals supplied from each column signal processing circuit 5 through a horizontal signal line 9, and outputs the processed signals.

[0037] FIG. 2 is a cross-sectional view showing the structure of the photodetector according to the first embodiment.

[0038] The photodetector of this embodiment has a laminated structure including a lower substrate 10 constituting a first floor and an upper substrate 20 constituting a second floor, as shown in Fig. 2. The lower substrate 10 and the upper substrate 20 are bonded to each other at the interface S.

[0039] The lower substrate 10 includes a substrate 11, an interlayer insulating film 12, a plurality of contact plugs 13, a wiring layer 14a, a plurality of via plugs 15a, a wiring layer 14b, a plurality of via plugs 15b, a wiring layer 14c, a plurality of via plugs 15c, a wiring layer 14d, a plurality of via plugs 15d, a wiring layer 14e, a plurality of via plugs 15e, a wiring layer 14f, a plurality of via plugs 16, and a wiring layer 17. The substrate 11 and the interlayer insulating film 12 are examples of the first substrate and the first insulating film of the present disclosure, respectively.

[0040] The upper substrate 20 includes a substrate 21, an interlayer insulating film 22, a plurality of contact plugs 23, a wiring layer 24a, a plurality of via plugs 25a, a wiring layer 24b, a plurality of via plugs 25b, a wiring layer 24c, a plurality of via plugs 25c, a wiring layer 24d, a filter layer 26, and a lens layer 27. The substrate 21 and the interlayer insulating film 22 are examples of the second substrate and the second insulating film of the present disclosure, respectively. The interlayer insulating films 12 and 22 are examples of the insulating film of the present disclosure.

[0041] FIG. 2 shows an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other. The X-axis and the Y-axis correspond to the lateral direction (horizontal direction), and the Z-axis corresponds to the longitudinal direction (vertical direction). The +Z-axis corresponds to the upward direction, and the -Z-axis corresponds to the downward direction. For example, the upper substrate 20 is disposed on the lower substrate 10, and the boundary surface S extends in the horizontal direction. The -Z-axis may or may not strictly coincide with the direction of gravity.

[0042] The photodetector of this embodiment further includes a pixel region R1 including a pixel array 2 (see FIG. 1), and an extra-pixel region R2 annularly surrounding the pixel region R1 in a plan view. FIG. 2 shows a cross section of the extra-pixel region R2. The extra-pixel region R2 includes a region R2a surrounding the pixel region R1, a region R2b surrounding the region R2a, and a region R2c surrounding the region R2b. Each of the regions R2a to R2c has an annular shape in a plan view, that is, has an annular shape when viewed from the Z direction. The region R2c faces a side surface (chip end) of a chip forming the photodetector of this embodiment.

[0043] With continued reference to FIG. 2, the structure of the photodetector of this embodiment will now be described in further detail.

[0044] [Substrate 11] The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. In Fig. 2, the X direction and the Y direction are parallel to the upper surface of the substrate 11, and the Z direction is perpendicular to the upper surface of the substrate 11. In Fig. 2, the upper surface of the substrate 11 is the front surface of the substrate 11, and the lower surface of the substrate 11 is the back surface of the substrate 11.

[0045] [Interlayer insulating film 12] The interlayer insulating film 12 is formed on the substrate 11. The contact plugs 13, the wiring layers 14a to 14f, the via plugs 15a to 15e, the via plug 16, and the wiring layer 17 are disposed in the interlayer insulating film 12. The interlayer insulating film 12 is, for example, a stacked insulating film including a SiO2 (silicon oxide) film and other insulating films.

[0046] [Contact Plug 13] The contact plugs 13 are formed on the substrate 11. The contact plugs 13 (not shown) in the pixel region R1 are electrically connected to, for example, a gate electrode, a source region, or a drain region of a transistor formed on the substrate 11. On the other hand, the contact plugs 13 in the regions R2a and R2b are, for example, dummy plugs that are not used for driving the photodetector.

[0047] [Wiring layers 14a to 14f] The wiring layers 14a to 14f are formed above the substrate 11 and are disposed at different heights. Each of the wiring layers 14a to 14f includes a plurality of wirings. Each of the wiring layers 14a to 14f is, for example, a metal layer including a Cu (copper) layer or an Al (aluminum) layer. The substrate 11 and the wiring layer 14a are electrically connected by a contact plug 13, and the wiring layer 14a and the wiring layer 14b are electrically connected by a via plug 15a. The wiring layer 14b and the wiring layer 14c are electrically connected by a via plug 15b, and the wiring layer 14c and the wiring layer 14d are electrically connected by a via plug 15c. The wiring layer 14d and the wiring layer 14e are electrically connected by a via plug 15d, and the wiring layer 14e and the wiring layer 14f are electrically connected by a via plug 15e.

[0048] The wiring layers 14a-14f include wiring in the pixel region R1 and the extra-pixel region R2. The wiring in the regions R2a and R2b is, for example, dummy wiring that is not used for driving the photodetector. On the other hand, the wiring in the region R2c constitutes, for example, a test circuit for testing the operation of the photodetector. FIG. 2 shows a groove H1 formed in the upper substrate 20 and the lower substrate 10 in the region R2c. The groove H1 is used to apply a probe to the test circuit. The groove H1 has, for example, a ring shape in a plan view.

[0049] [Via plugs 15a~15e] The via plugs 15a to 15e are formed on the wiring layers 14a to 14e, respectively. Each of the via plugs 15a to 15e is, for example, a metal layer including a W (tungsten) layer. The via plugs 15a to 15e in the regions R2a and R2b are, for example, dummy plugs.

[0050] [Via Plug 16] The via plugs 16 are formed on the wiring layer 14f. Each of the via plugs 16 is, for example, a metal layer including a W layer. The via plugs 16 in the region R2a are, for example, dummy plugs.

[0051] [Wiring layer 17] The wiring layer 17 is formed above the wiring layers 14a to 14f. The wiring layer 17 includes a plurality of wires. The wiring layer 17 is, for example, a metal layer including a Cu layer or an Al layer. The wiring layer 14f and the wiring layer 17 are electrically connected by a via plug 16.

[0052] The wiring layer 17 includes wiring in the pixel region R1 and the extra-pixel region R2. The wiring in the region R2a is, for example, a dummy wiring. On the other hand, the wiring in the region R2c constitutes, for example, a test circuit. In FIG. 2, the upper surface of the wiring layer 17 in the region R2c is exposed to the groove H1.

[0053] [Substrate 21] The substrate 21 is disposed above the substrate 11 and the interlayer insulating film 12. The substrate 21 is, for example, a semiconductor substrate such as a Si substrate. In FIG. 2, the X direction and the Y direction are parallel to the lower surface of the substrate 21, and the Z direction is perpendicular to the lower surface of the substrate 21. In FIG. 2, the lower surface of the substrate 21 is the front surface of the substrate 21, and the upper surface of the substrate 21 is the back surface of the substrate 21. FIG. 2 shows a slit H2 formed in the substrate 21 within the region R2b. The slit H2 has, for example, a ring shape in a plan view, and penetrates the substrate 21 in the Z direction.

[0054] [Interlayer insulating film 22] The interlayer insulating film 22 is formed under the substrate 21 and disposed on the interlayer insulating film 12. The boundary surface S includes the interface between the interlayer insulating film 12 and the interlayer insulating film 22. The contact plug 23, the wiring layers 24a to 24d, and the via plugs 25a to 25c are disposed in the interlayer insulating film 22. The interlayer insulating film 22 is, for example, a laminated insulating film including a SiO2 film and other insulating films. The photodetector of this embodiment is manufactured by forming the interlayer insulating film 12 and the like on the substrate 11, forming the interlayer insulating film 22 and the like on the substrate 21, and bonding the substrate 11 and the substrate 21 together so as to sandwich the interlayer insulating films 12 and 22. The substrates 11 and 21 are diced after this bonding.

[0055] [Contact Plug 23] The contact plugs 23 are formed under the substrate 21. The contact plugs 23 (not shown) in the pixel region R1 are electrically connected to, for example, a gate electrode, a source region, or a drain region of a transistor formed under the substrate 21. On the other hand, the contact plugs 23 in the region R2a are, for example, dummy plugs.

[0056] [Wiring layer 24a~24d] The wiring layers 24a to 24d are formed below the substrate 21 and are disposed at different heights. Each of the wiring layers 24a to 24d includes a plurality of wires. Each of the wiring layers 24a to 24d is, for example, a metal layer including an Al layer or a Cu layer. The substrate 21 and the wiring layer 24a are electrically connected by a contact plug 23, and the wiring layer 24a and the wiring layer 24b are electrically connected by a via plug 25a. The wiring layer 24b and the wiring layer 24c are electrically connected by a via plug 25b, and the wiring layer 24c and the wiring layer 24d are electrically connected by a via plug 25c.

[0057] The wiring layers 24a-24d include wirings in the pixel region R1 and the extra-pixel region R2. The wirings in the regions R2a-R2c are, for example, dummy wirings. In the region R2b, the wiring layers 24a-24d each include wirings Ia-Id located on the inner periphery side and wirings Ja-Jd located on the outer periphery side. Each of the wirings Ia-Id and wirings Ja-Jd has, for example, an annular shape in plan view. The wirings Ia-Id are an example of the first wiring of the present disclosure, and the wirings Ja-Jd are an example of the second wiring of the present disclosure. The interlayer insulating film 22 of this embodiment includes a cavity Ga between the wirings Ia and Ja, a cavity Gb between the wirings Ib and Jb, a cavity Gc between the wirings Ic and Jc, and a cavity Gd between the wirings Id and Jd. That is, the cavities Ga-Gd are formed in the wiring layers 24a-24d, respectively. 2, the cavities Ga to Gd are formed at different heights. The cavities Ga to Gd are, for example, air gaps formed in the interlayer insulating film 22.

[0058] The heights of the cavities Ga-Gd and the wiring layers 24a-24d may be regulated by any rule. In this embodiment, when a part of a cavity (or wiring layer) and a part of another cavity (or wiring layer) are located in the same XY cross section, these cavities are expressed as being located at the same height. On the other hand, when a cavity (or wiring layer) and another cavity (or wiring layer) do not include a part located in the same XY cross section, these cavities are expressed as being located at different heights. In FIG. 2, the heights of the cavities Ga-Gd decrease in the order of the cavities Ga-Gd, and the heights of the wiring layers 24a-24d decrease in the order of the wiring layers 24a-24d. Furthermore, the cavities Ga-Gd are located at the same height as the wiring layers 24a-24d, respectively. The cavities Ga-Gd are examples of the first to Nth cavities of the present disclosure, the wiring layers 24a-24d are examples of the first to Nth wiring layers of the present disclosure, and the heights of the cavities Ga-Gd and the wiring layers 24a-24d are examples of the first to Nth heights of the present disclosure, where N is an integer equal to or greater than 2, and is 4 in this example. Each of the cavities Ga-Gd is an example of the Kth cavity of the present disclosure (K is an integer satisfying 1≦K≦N).

[0059] The cavities Ga to Gd in this embodiment are arranged in a four-step staircase pattern. Therefore, in the XZ cross section shown in FIG. 2, the cavities Ga to Gd are arranged not on a straight line parallel to the Z direction but on a straight line inclined with respect to the Z direction. More specifically, the cavities Ga to Gd in this embodiment are arranged at positions where they do not overlap each other in a plan view. This makes the inclination of the steps formed by the cavities Ga to Gd gentle. Note that, as long as the cavities Ga to Gd are arranged in a step-like pattern, they may be arranged on a curved line instead of a straight line, or may be arranged at positions where they partially overlap each other in a plan view. The cavities Ga to Gd may be arranged at different positions from each other in a plan view in a manner where they are arranged at positions where they do not overlap each other in a plan view, or may be arranged at different positions from each other in a plan view in a manner where they are arranged at positions where they partially overlap each other in a plan view.

[0060] Moreover, the slit H2 in this embodiment is disposed at a position that does not overlap with the cavities Ga to Gd in a plan view. The slit H2 is further disposed at a position that does not overlap with the wirings Ia to Id and Ja to Jd in a plan view. FIG. 2 shows a region R2b' which is a part of the region R2b. The region R2b' has an annular shape in a plan view, similar to the regions R2a to R2c. In this embodiment, the slit H2 is disposed outside the region R2b', and the cavities Ga to Gd and the wirings Ia to Id and Ja to Jd are disposed within the region R2b'. As a result, the slit H2 is disposed at a position that does not overlap with the cavities Ga to Gd and the wirings Ia to Id and Ja to Jd in a plan view. In this embodiment, the width of the slit H2 (the dimension of the slit H2 in the X direction in FIG. 2) is 1.8 μm, and the width of the region R2b' (the dimension of the region R2b' in the X direction in FIG. 2) is 8.0 μm.

[0061] In this embodiment, the cavities Ga-Gd are arranged such that the higher the position of the cavity, the shorter the distance between the cavity and the pixel region R1. Therefore, the cavity Ga is arranged closest to the pixel region R1 among the cavities Ga-Gd, and the cavity Gd is arranged farthest from the pixel region R1 among the cavities Ga-Gd. In other words, the cavities Ga-Gd are arranged so that the higher the staircase, the closer they are to the pixel region R1. In this embodiment, the distance between the slit H2 and the pixel region R1 is shorter than the distance between each cavity and the pixel region R1.

[0062] In Fig. 2, the cavity Ga is disposed at a position overlapping with the wiring Ib. Furthermore, the cavity Gb is disposed at a position overlapping with the wiring Ic and Ja. Furthermore, the cavity Gc is disposed at a position overlapping with the wiring Id and Jb. Furthermore, the cavity Gd is disposed at a position overlapping with the wiring Jc. However, the cavities Ga-Gd may be disposed at positions where such overlap does not occur. Further details of the arrangement of the cavities Ga-Gd will be described later with reference to Figs. 6 and 7.

[0063] [Via plugs 25a~25c] The via plugs 25a-25c are formed under the wiring layers 24a-24d, respectively. Each of the via plugs 25a-25c is, for example, a metal layer including a W layer or a Cu layer. The via plugs 25a-25c in the regions R2a and R2c are, for example, dummy plugs. Note that the via plugs 25a-25c of this embodiment are not disposed in the region R2b. Therefore, the wirings Ia-Id, Ja-Jd of this embodiment are not in contact with the via plugs 25a-25c.

[0064] In region R2a, the wiring layers 24a-24d and the via plugs 25a-25c form a guard ring G. The guard ring G is arranged to prevent a predetermined substance (e.g., water) from entering the pixel region R1. The guard ring G has, for example, an annular shape surrounding the pixel region R1 in a plan view. In this embodiment, the guard ring G is arranged between the pixel region R1 and the cavities Ga-Gd (and the wirings Ia-Id, Ja-Jd).

[0065] [Filter layer 26] The filter layer 26 is formed on the substrate 21. The interlayer insulating film 22, the contact plugs 23, the wiring layers 24a-24d, and the via plugs 25a-25c are formed before bonding the substrates 11 and 21, whereas the filter layer 26 is formed after the bonding. The filter layer 26 in the pixel region R1 forms, for example, a color filter or an infrared filter for each pixel 1.

[0066] [Lens layer 27] The lens layer 27 is formed on the filter layer 26. The lens layer 27 is formed after the above-mentioned bonding, similar to the filter layer 26. The lens layer 27 in the pixel region R1 forms, for example, an on-chip lens of each pixel 1.

[0067] According to this embodiment, the cavities Ga to Gd can effectively suppress the propagation of cracks in the photodetector. For example, the cracks can be propagated so as to reach the upper surface of the interlayer insulating film 22 before reaching the guard ring G or the pixel region R1. Specifically, the cracks can be allowed to escape to the slit H2 without propagating to the guard ring G or the pixel region R1. Further details of the cracks will be described later.

[0068] FIG. 3 is a cross-sectional view illustrating the method for manufacturing the photodetector of the first embodiment.

[0069] Fig. 3 shows the lower substrate 10 and the upper substrate 20 before dicing. Each of the lower substrate 10 and the upper substrate 20 before dicing has a wafer-like shape in a plan view. As shown in Fig. 3, the lower substrate 10 and the upper substrate 20 before dicing include a plurality of chip regions Rc and scribe regions Rs located between these chip regions Rc. Each chip region Rc has the structure shown in Fig. 2 above.

[0070] The structure shown in FIG. 3 is fabricated, for example, by the following procedure. First, the interlayer insulating film 12, the contact plugs 13, the wiring layers 14a-14f, the via plugs 15a-15e, the via plugs 16, and the wiring layer 17 are formed on the substrate 11, and the interlayer insulating film 22, the contact plugs 23, the wiring layers 24a-24d, and the via plugs 25a-25c are formed on the substrate 21. At this time, the guard ring G, the cavities Ga-Gd, the wirings Ia-Id, Ja-Jd, etc. are also formed in the interlayer insulating film 22 of each chip region Rc. Next, the substrate 11 and the substrate 21 are bonded together so as to sandwich the interlayer insulating films 12 and 22. Next, the filter layer 26 and the lens layer 27 are formed on the substrate 21, the grooves H1 are formed in the upper substrate 20 and the lower substrate 10, and the slits H2 are formed in the substrate 21 of each chip region Rc. The grooves H1 of this embodiment are formed so as to straddle the scribe region Rs and the region R2c in each chip region Rc. Thereafter, a test is performed using a test circuit, and after the test, the lower substrate 10 and the upper substrate 20 are diced.

[0071] FIG. 4 is another cross-sectional view for illustrating the method for manufacturing the photodetector of the first embodiment.

[0072] Fig. 4 shows the lower substrate 10 and the upper substrate 20 during dicing. When dicing the lower substrate 10 and the upper substrate 20, the scribe region Rs is cut by a blade B as shown in Fig. 4. As a result, the lower substrate 10 and the upper substrate 20 are divided into a plurality of chips (chip regions Rc). Each of these chips becomes the photodetector of this embodiment.

[0073] FIG. 5 is a plan view for explaining the method of manufacturing the photodetector of the first embodiment.

[0074] Fig. 5 shows a plurality of chip regions Rc and scribe regions Rs in the lower substrate 10 and the upper substrate 20 before dicing. In Fig. 5, the planar shape of each chip region Rc is rectangular, and the planar shape of the scribe region Rs is mesh-shaped.

[0075] Each chip region Rc includes a pixel region R1 having a rectangular shape in a plan view and an extra-pixel region R2 having an annular shape in a plan view. Fig. 5 shows a plurality of I / O (Input / Output) pads provided in the extra-pixel region R2 of each chip region Rc. The dot hatching shown in Fig. 5 indicates the range in which the groove H1 is provided. The groove H1 before dicing has a mesh shape in a plan view and extends over the scribe region Rs and each chip region Rc.

[0076] FIG. 6 is a plan view showing the structure of the photodetector according to the first embodiment.

[0077] 6 shows the layout of the slit H2, cavities Ga-Gd, wirings Ia-Id, Ja-Jd, etc. in the region R2b. In Fig. 6, the slit H2, cavities Ga-Gd, and wirings Ia-Id, Ja-Jd are arranged in positions that do not overlap with each other in a plan view. This makes it possible to make the inclination of the steps formed by the cavities Ga-Gd more gentle than in the structure shown in Fig. 2.

[0078] The shapes of the cavities Ga to Gd, the wires Ia to Id, and the wires Ja to Jd will be described below using the cavity Ga, the wire Ia, and the wire Ja as examples. The following description is also applicable to the cavities Gb to Gd, the wires Ib to Id, and the wires Jb to Jd.

[0079] The interlayer insulating film 22 of this embodiment alternately includes a plurality of cavities Ga and a plurality of insulating films 22a between the wiring Ia and the wiring Ja. These insulating films 22a are part of the interlayer insulating film 22. The plurality of cavities Ga and the plurality of insulating films 22a are alternately arranged along the direction in which the wirings Ia and Ja extend. Therefore, the cavities Ga and the insulating films 22a are arranged to form a ring in a plan view.

[0080] 6 shows the width W1 of each of the wirings Ia and Ja, the width W2 of the region between the wirings Ia and Ja, the length L1 of each cavity Ga, and the length L2 of each insulating film 22a. The width W1 is, for example, 0.15 μm. The width W2 is, for example, 0.10 μm. The length L1 is, for example, 3.0 μm. The length L2 is, for example, 0.24 μm. The width of the wiring Ia and the width of the wiring Ja may be different from each other. Furthermore, the value of the length L1 may be different for each cavity Ga. Furthermore, the value of the length L2 may be different for each insulating film 22a.

[0081] The interlayer insulating film 22 of the present embodiment may include only one cavity Ga between the wiring Ia and the wiring Ja. In this case, it is preferable that the cavity Ga has an annular shape in a plan view.

[0082] FIG. 7 is another plan view showing the structure of the photodetector according to the first embodiment.

[0083] Fig. 7 is a schematic diagram showing the planar shapes of the cavity Ga, the wiring Ia, and the wiring Ja shown in Fig. 6. The following description is also applicable to the cavities Gb to Gd, the wiring Ib to Id, and the wiring Jb to Jd.

[0084] In FIG. 7, each of the wirings Ia and Ja has a ring shape in plan view. Therefore, the region between the wirings Ia and Ja also has a ring shape in plan view. The cavities Ga and the insulating films 22a arranged between the wirings Ia and Ja are alternately arranged along the direction in which the wirings Ia and Ja extend. Therefore, these cavities Ga and insulating films 22a are arranged to form a ring in plan view.

[0085] Hereinafter, a photodetector of a comparative example of this embodiment will be compared with the photodetector of this embodiment with reference to FIG. 8 and other figures.

[0086] FIG. 8 is a cross-sectional view for explaining a problem with a photodetector as a comparative example of the first embodiment.

[0087] Fig. 8 shows a cross section similar to that of Fig. 4. However, the interlayer insulating film 22 of this comparative example includes cavities Ga-Gd arranged in a non-stepped manner. Furthermore, the interlayer insulating film 22 of this comparative example includes a cavity Ga' provided between the cavities Ga and Gb, a cavity Gb' provided between the cavities Gb and Gc, and a cavity Gc' provided between the cavities Gc and Gd.

[0088] FIG. 9 is a cross-sectional view and an enlarged cross-sectional view for explaining a problem with a photodetector as a comparative example of the first embodiment.

[0089] FIG. 9A shows a cross section similar to that of FIG. 8. FIG. 9A further shows a crack C1 generated in the chip (lower substrate 10 and upper substrate 20) of this comparative example, and a portion C2 where chipping may occur due to the crack C1. Chipping is a phenomenon in which a part of the chip is separated from the chip by the crack C1. In FIG. 9A, when the crack C1 occurs so as to separate the chip, the portion C2 is separated from the chip. If the crack C1 extends to the guard ring G or the pixel region R1, or if chipping occurs over a wide range, the quality of the photodetector may deteriorate. If the crack C1 extends to the guard ring G, for example, the guard ring G may not be able to sufficiently suppress the intrusion of water. If the crack C1 extends to the pixel region R1, for example, the pixel 1 affected by the crack C1 may not operate normally. In FIG. 9A, the crack C1 extends to the guard ring G.

[0090] 9B shows an enlarged view of the cavities Ga-Gd of this comparative example. It is desirable that the cracks extend from the cavities Ga-Gd to the slits H2, as indicated by the reference symbol C1'. However, if the stress that causes the cracks to extend is large, the cracks may be more likely to extend horizontally than vertically, as indicated by the reference symbol C1. As a result, the cracks extend to the guard ring G or pixel region R1.

[0091] FIG. 10 is a cross-sectional view and an enlarged cross-sectional view for explaining the advantages of the photodetector of the first embodiment.

[0092] Fig. 10A shows a cross section similar to that of Fig. 4. Similarly to Fig. 9A, Fig. 10A also shows a crack C1 generated in the chip (lower substrate 10 and upper substrate 20) of this embodiment and a portion C2 where chipping may occur due to the crack C1. In this embodiment, the crack C1 extends from the cavities Ga-Gd to the slit H2. Fig. 10B shows an enlarged view of the cavities Ga-Gd of this embodiment.

[0093] In this embodiment, the cavities Ga to Gd are arranged in a stepped manner. Therefore, in the XZ cross section shown in FIG. 10A and FIG. 10B, the cavities Ga to Gd are arranged on a line inclined with respect to the Z direction, not on a line parallel to the Z direction. This makes it possible to make the cracks C1 easily extend in an oblique direction along the arrangement of the cavities Ga to Gd. That is, it becomes possible to guide the extension force of the cracks C1 in an oblique direction. In FIG. 10A and FIG. 10B, the cracks C1 reach the upper surface of the interlayer insulating film 22 before reaching the guard ring G, specifically, they reach the slit H2. According to this embodiment, it is possible to suppress the cracks C1 from extending to the guard ring G or the pixel region R1, thereby suppressing the deterioration of the quality of the photodetector due to the cracks C1 and chipping.

[0094] As shown in Figs. 10A and 10B, the cavities Ga to Gd of this embodiment have a cross-sectional shape of an inverted triangle. According to this embodiment, the crack C1 is allowed to extend from one cavity to another, thereby making it possible to attenuate the extension force of the crack C1. In general, the crack C1 is likely to be drawn into the apex of each cavity. Therefore, the crack C1 of this embodiment is likely to extend from the apex of one cavity to the apex of another cavity, which makes it easier to prevent the crack C1 from extending to the guard ring G or the pixel region R1. An example of a method for forming the cavities Ga to Gd having a cross-sectional shape of an inverted triangle will be described later with reference to Figs. 11 to 13.

[0095] In addition, the cavities Ga-Gd in this embodiment are disposed between the wirings Ia-Id and the wirings Ja-Jd, respectively. This also makes it easier for the cracks C1 to extend along the cavities Ga-Gd. This is because the wirings Ia-Id and Ja-Jd prevent the cracks C1 extending along the cavities Ga-Gd from extending toward the inner periphery of the wirings Ia-Id or toward the outer periphery of the wirings Ja-Jd.

[0096] In this embodiment, the cavities Ga-Gd are arranged at positions that do not overlap each other in a plan view. Therefore, the inclination of the steps formed by the cavities Ga-Gd is gentle. This makes it possible for the crack C1 to easily escape to the upper surface of the interlayer insulating film 22 because the angle at which the crack C1 propagates is not steep.

[0097] Moreover, the via plugs 25a-25c of this embodiment are not disposed within the region R2b as described above. Therefore, the wirings Ia-Id, Ja-Jd of this embodiment are not in contact with the via plugs 25a-25c. This makes it possible to prevent the via plugs 25a-25c from interfering with the propagation of the cracks C1 along the cavities Ga-Gd. This is because if the via plugs 25a-25c are disposed near the wirings Ia-Id, Ja-Jd, the via plugs 25a-25c may interfere with the propagation of the cracks C1.

[0098] 11 to 13 are cross-sectional views showing a method for manufacturing the photodetector of the first embodiment. Specifically, Fig. 11 to 13 show the procedure for forming the cavities Ga-Gd, the wirings Ia-Id, and the wirings Ja-Jd, taking the cavity Ga, the wiring Ia, and the wiring Ja as examples. The following procedure can also be applied to the cavities Gb-Gd, the wirings Ib-Id, and the wirings Jb-Jd.

[0099] First, a substrate 21 is prepared, and an insulating film 31, which is a part of an interlayer insulating film 22, is formed on the substrate 21 (FIG. 11A). The insulating film 31 is, for example, a SiO2 film. The insulating film 31 is an example of a first film of the present disclosure. In FIG. 11A, unlike FIG. 2 and the like, the upper surface of the substrate 21 is the front surface of the substrate 21, and the lower surface of the substrate 21 is the back surface of the substrate 21.

[0100] Next, wiring grooves Xa and Ya are formed in the insulating film 31 by lithography and RIE (Reactive Ion Etching), a wiring layer 24a is formed in and on the insulating film 31, and the upper surface of the wiring layer 24a is polished by CMP (Chemical Mechanical Polishing) (FIG. 11A). As a result, the wiring layer 24a outside the wiring grooves Xa and Ya is removed, and wirings Ia and Ib are formed in the wiring grooves Xa and Ya, respectively. The wiring layer 24a is formed by sequentially forming a barrier metal layer 41 and a wiring material layer 42 in and on the insulating film 31. The barrier metal layer 41 is a metal layer containing, for example, Ti (titanium) or Ta (tantalum). The wiring material layer 42 is, for example, a Cu layer.

[0101] Next, an insulating film 32, which is a part of the interlayer insulating film 22, is formed on the insulating film 31 and the wirings Ia and Ib (FIG. 11A). The insulating film 32 is, for example, a SiCN (silicon carbonitride) film.

[0102] Next, a resist layer 51 is formed on the insulating film 32, and the resist layer 51 is patterned (FIG. 11B). As a result, a part of the upper surface of the insulating film 32 is exposed from the resist layer 51.

[0103] Next, a groove Za is formed in the insulating films 32 and 31 by RIE using the resist layer 51 as a mask (FIG. 12A). The groove Za is formed, for example, between the wiring Ia and the wiring Ib, and is formed to have a ring shape in a plan view. As shown in FIG. 12A, the groove Za in this embodiment is formed so that the side surfaces of the wirings Ia and Ib are exposed in the groove Za. The groove Za may be formed by RIE using a hard mask layer instead of the resist layer 51. The groove Za may also be formed at a position where a part of the wirings Ia and Ib is etched. The groove Za is an example of a first recess in the present disclosure. The resist layer 51 is removed after the groove Za is formed.

[0104] Next, an insulating film 33, which is a part of the interlayer insulating film 22, is formed on the insulating films 32 and 31 (FIG. 12B). As a result, the insulating film 33 is formed on the upper surface of the insulating film 31, the side surfaces of the wirings Ia and Ib, and the upper surface of the insulating film 32. The insulating film 33 is, for example, a SiCN film.

[0105] Next, an insulating film 34, which is a part of the interlayer insulating film 22 and has low coverage, is formed on the insulating film 33 (FIG. 13A). Since the insulating film 34 has low coverage, it is formed so that a part of the groove Za remains as a cavity Ga between the wirings Ia and Ib. The insulating film 34 is, for example, a SiO2 film. The insulating film 34 is an example of the second film of the present disclosure. The cavity Ga in this embodiment is formed to have a roughly triangular cross-sectional shape. This is because the insulating film 34 generally does not easily enter the lower part of the groove Za, and generally does easily enter the upper part of the groove Za. More specifically, the cross-sectional shape of the cavity Ga is often shaped like a water drop. Note that the vertical orientation of the substrate 21 shown in FIG. 2 is opposite to the vertical orientation of the substrate 21 shown in FIG. 13A, so the cavity Ga shown in FIG. 2 has a roughly inverted triangular cross-sectional shape.

[0106] In the step of FIG. 13A, a part of the insulating film 34 that has entered the groove Za becomes the insulating films 22a shown in FIG. 6 and FIG. 7. As a result, a plurality of cavities Ga and a plurality of insulating films 22a are formed alternately in the groove Za along the extension direction of the groove Za. FIG. 13A shows one of these cavities Ga. The pitch between the cavities Ga may or may not be constant. Similarly, the pitch between the insulating films 22a may or may not be constant.

[0107] Next, the upper surface of the insulating film 34 is polished by CMP (FIG. 13B). As a result, the upper surface of the insulating film 34 is flattened.

[0108] In this manner, the cavity Ga, the wiring Ia, and the wiring Ja are formed in the interlayer insulating film 22. The materials of the insulating films 31 to 34 included in the interlayer insulating film 22 may be materials other than the above-mentioned materials. For example, the insulating films 31 and 34 may be formed of a material other than SiO2, and the insulating films 32 and 33 may be formed of a material other than SiCN.

[0109] FIG. 14 is a cross-sectional view showing the structure of the photodetector according to the first embodiment.

[0110] Fig. 14 shows three pixels 1 included in a pixel array 2 in a pixel region R1. The photodetector of this embodiment includes the above-mentioned substrate 21, filter layer 26, and lens layer 27. In Fig. 14, the above-mentioned substrate 11 and interlayer insulating films 12 and 22 are omitted from illustration. The photodetector of this embodiment further includes a plurality of n-type regions 21a in the substrate 21, a p-type region 21b in the substrate 21, a pixel isolation insulating film 61, and a light-shielding layer 62. The pixel isolation insulating film 61 includes an insulating film 61a and an insulating film 61b.

[0111] Each n-type region 21a is provided in a corresponding pixel 1. The photodiode PD in each pixel 1 is formed by a pn junction between the n-type region 21a and p-type region 21b in each pixel 1 or the like.

[0112] The pixel isolation insulating film 61 includes a lower portion formed inside the substrate 21 and an upper portion formed on the upper surface of the substrate 21. The lower portion is disposed between the n-type regions 21a of different pixels 1, and separates the pixels 1 from each other. The pixel isolation insulating film 61 is formed, for example, by sequentially forming insulating films 61a and 61b inside and on the substrate 21. The insulating film 61a is, for example, a metal oxide film that acts as a fixed charge film. The insulating film 61b is, for example, a SiO2 film.

[0113] The light-shielding layer 62 is formed on the pixel isolation insulating film 61 and has a function of blocking light. The light-shielding layer 62 has, for example, a mesh shape in a planar view. The light-shielding layer 62 is, for example, a metal layer including a W layer, an Al layer, or a Cu layer.

[0114] In addition, the pixel region R1 of this embodiment may include not only normal pixels but also dummy pixels as the pixels 1. The normal pixels are structures that function as pixels of a photodetector. On the other hand, the dummy pixels are structures that have the same or similar structure as the normal pixels but do not function as pixels of a photodetector.

[0115] As described above, the photodetector of this embodiment includes the cavities Ga-Gd arranged in a stepped pattern in the interlayer insulating film 22. Therefore, according to this embodiment, the cavities Ga-Gd can effectively suppress the propagation of cracks. For example, it is possible to cause the cracks to propagate so as to reach the upper surface of the interlayer insulating film 22 before reaching the guard ring G or the pixel region R1. Specifically, it is possible to allow the cracks to escape to the slits H2.

[0116] The structure and manufacturing method of the photodetector of this embodiment may be applied to semiconductor devices other than the photodetector. In this case, the pixel region R1 may be replaced with a device region including devices other than the pixel 1 and the pixel array 2, and the extra-pixel region R2 may be replaced with an extra-device region surrounding such a device region. This is the same in the second to fourth embodiments described later.

[0117] Second embodiment FIG. 15 is a cross-sectional view showing the structure of the photodetector according to the second embodiment.

[0118] The photodetector of this embodiment includes, in addition to the components of the photodetector of the first embodiment, wiring 17a in wiring layer 17, a plurality of via plugs 18, a plurality of metal pads 19, a plurality of via plugs 28, and a plurality of metal pads 29. Metal pad 19 is an example of a first pad of the present disclosure. Metal pad 29 is an example of a second pad of the present disclosure.

[0119] [Wire 17a] The wiring 17a is formed in the interlayer insulating film 12, and is included in the wiring layer 17. The wiring 17a is disposed above the wiring layers 14a to 14e in the region R2b. The wiring 17a is, for example, a dummy wiring.

[0120] [Via Plug 18] The via plugs 18 are formed on the wiring layer 17 in the interlayer insulating film 12. Each of the via plugs 18 is, for example, a metal layer including a W layer or a Cu layer. The photodetector of this embodiment includes via plugs 18 in the pixel region R1 and the extra-pixel region R2. FIG. 15 shows two of these via plugs 18.

[0121] 15 are disposed on the wiring 17a in the region R2b. These via plugs 18 are, for example, dummy plugs.

[0122] [Metal Pad 19] The metal pads 19 are formed on the via plugs 18 in the interlayer insulating film 12. Each of the metal pads 19 is, for example, a metal layer including a Cu layer. The via plugs 18 and the metal pads 19 may be formed of the same Cu layer by a dual damascene method. The photodetector of this embodiment includes metal pads 19 in the pixel region R1 and the extra-pixel region R2. FIG. 15 shows two of these metal pads 19. The photodetector of this embodiment may include a metal pad 19 arranged on the via plugs 18 and a metal pad 19 not arranged on the via plugs 18.

[0123] 15 are disposed on the via plug 18 in the region R2b. Therefore, these metal pads 19 are electrically connected to the wiring 17a. These metal pads 19 are, for example, dummy pads that are not used for driving the photodetector.

[0124] [Metal Pad 29] The metal pads 29 are formed in the interlayer insulating film 22 below the via plugs 28 and are disposed on the metal pads 19. Each of the metal pads 29 is, for example, a metal layer including a Cu layer. The via plugs 28 and the metal pads 29 may be formed of the same Cu layer by a dual damascene method. The photodetector of this embodiment includes metal pads 29 in the pixel region R1 and the extra-pixel region R2. FIG. 15 shows two of these metal pads 29. The photodetector of this embodiment may include a metal pad 29 disposed below the via plugs 28 and a metal pad 29 not disposed below the via plugs 28.

[0125] 15 are disposed on the metal pad 19 in the region R2b. Therefore, these metal pads 29 are electrically connected to the wiring 17a. These metal pads 29 are, for example, dummy pads. On the other hand, the metal pads 19 and 29 in the pixel region R1 are used, for example, to electrically connect a device in the lower substrate 10 and a device in the upper substrate 20.

[0126] [Viaplug28] The via plugs 28 are formed in the interlayer insulating film 22 below the wiring layer 27. Each of the via plugs 28 is, for example, a metal layer including a W layer or a Cu layer. The photodetector of this embodiment includes via plugs 28 in the pixel region R1 and the extra-pixel region R2. FIG. 15 shows two of these via plugs 28.

[0127] Two via plugs 28 shown in Fig. 15 are disposed on metal pads 29 in region R2b. These via plugs 28 are, for example, dummy plugs. In Fig. 15, one of the via plugs 28 is in contact with the wiring layer 27 (wiring Id), but the other via plug 28 is not in contact with the wiring layer 27. Note that both of these via plugs 28 may or may not be in contact with the wiring layer 27.

[0128] The photodetector of this embodiment does not necessarily have to include the via plug 28 in the region R2b.

[0129] Next, still referring to FIG. 15, the structure of the photodetector of this embodiment will be described in further detail.

[0130] As described above, the wiring 17a, the via plug 18, the metal pad 19, the metal pad 29, and the via plug 28 shown in FIG. 15 are arranged in the region R2b. More specifically, the wiring 17a is arranged at a position overlapping with the cavities Ga to Gd in a plan view. One of the two metal pads 19 and one of the two metal pads 29 are arranged at a position overlapping with the cavities Gc and Gd in a plan view. The remaining metal pads 19 and 29 may also be arranged at a position overlapping with at least one of the cavities Ga to Gd in a plan view. The remaining metal pads 19 and 29 are arranged at a position overlapping with the wiring Ia in a plan view.

[0131] According to this embodiment, like the wires Ia-Id and Ja-Jd, the wires 17a and metal pads 19, 29 in the region R2b can control the direction in which the cracks C1 extend. The wires 17a and metal pads 19, 29 in the region R2b can suppress the cracks C1 from extending in the inner circumferential direction, as shown in Fig. 15. To achieve this effect, it is desirable that the wires 17a and metal pads 19, 29 in the region R2b are disposed at positions overlapping with the cavities Ga-Gd or in the vicinity thereof in a plan view.

[0132] Moreover, according to this embodiment, by arranging the metal pads 19, 29 not only in the pixel region R1 but also in the extra-pixel region R2, it is possible to increase the strength of bonding between the lower substrate 10 and the upper substrate 20. Furthermore, according to this embodiment, by arranging the metal pads 19, 29 not only in the pixel region R1 but also in the extra-pixel region R2, it is possible to increase the uniformity of the coverage of the metal pads 19, 29 on the boundary surface S. This makes it possible to increase the flatness of the boundary surface S.

[0133] When manufacturing the photodetector of this embodiment, the wiring 17a, the via plug 18, and the metal pad 19 are formed in the interlayer insulating film 12 before bonding the substrate 11 and the substrate 21 together. Similarly, the via plug 28 and the metal pad 29 are formed in the interlayer insulating film 22 before bonding the substrate 11 and the substrate 21 together. The substrate 11 and the substrate 21 are bonded to each other such that each metal pad 19 is bonded to the corresponding metal pad 29. In this manner, the photodetector of this embodiment is manufactured.

[0134] According to this embodiment, as in the first embodiment, it is possible to suitably suppress the extension of the cracks by the cavities Ga to Gd. Moreover, according to this embodiment, it is possible to make the cracks extend in a suitable direction by the wiring 17a and the metal pads 19 and 29 in the region R2b.

[0135] Third embodiment FIG. 16 is a cross-sectional view showing the structure of the photodetector according to the third embodiment.

[0136] The photodetector of this embodiment has a structure in which the wiring 17a and the via plugs 18 and 28 are removed from the region R2b of the photodetector of the second embodiment. According to this embodiment, the metal pads 19 and 29 in the region R2b enable the crack to extend in a preferred direction.

[0137] (Fourth embodiment) FIG. 17 is a cross-sectional view showing the structure of the photodetector according to the fourth embodiment.

[0138] The photodetector of this embodiment has a structure in which the via plugs 18, 28 and the metal pads 19, 29 are removed from the region R2b of the photodetector of the second embodiment. According to this embodiment, the wiring 17a in the region R2b makes it possible to extend the crack in a suitable direction. Note that the shape of the crack C1 shown in FIG. 17 is different from the shape of the crack C1 shown in FIG. 15 due to the absence of the metal pads 19, 29 in the region R2b.

[0139] (Application example) 18 is a block diagram showing an example of the configuration of an electronic device. The electronic device shown in FIG.

[0140] Camera 100 includes optical section 101 including a lens group and the like, imaging device 102 which is a photodetector according to any one of the first to fourth embodiments, DSP (Digital Signal Processor) circuit 103 which is a camera signal processing circuit, frame memory 104, display section 105, recording section 106, operation section 107, and power supply section 108. DSP circuit 103, frame memory 104, display section 105, recording section 106, operation section 107, and power supply section 108 are connected to each other via bus line 109.

[0141] The optical unit 101 takes in incident light (image light) from a subject and forms an image on an imaging surface of the imaging device 102. The imaging device 102 converts the amount of incident light imaged on the imaging surface by the optical unit 101 into an electrical signal on a pixel-by-pixel basis and outputs the electrical signal.

[0142] The DSP circuit 103 performs signal processing on the pixel signals output by the imaging device 102. The frame memory 104 is a memory for storing one screen of a moving image or a still image captured by the imaging device 102.

[0143] The display unit 105 includes a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 102. The recording unit 106 records the moving images or still images captured by the imaging device 102 in a recording medium such as a hard disk or a semiconductor memory.

[0144] An operation unit 107, under the operation of a user, issues operation commands for various functions of the camera 100. A power supply unit 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display unit 105, recording unit 106, and operation unit 107 as operating power sources to these devices.

[0145] By using the photodetector according to any one of the first to fourth embodiments as the imaging device 102, it is possible to expect acquisition of a good image.

[0146] The optical detection device can be applied to various other products. For example, the optical detection device may be mounted on various moving objects such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0147] 19 is a block diagram showing a configuration example of a moving object control system, which is a vehicle control system 200.

[0148] The vehicle control system 200 includes a plurality of electronic control units connected via a communication network 201. In the example shown in Fig. 19, the vehicle control system 200 includes a drive system control unit 210, a body system control unit 220, an outside-vehicle information detection unit 230, an inside-vehicle information detection unit 240, and an integrated control unit 250. Fig. 19 further illustrates, as components of the integrated control unit 250, a microcomputer 251, an audio / video output unit 252, and an in-vehicle network I / F (Interface) 253.

[0149] The drivetrain control unit 210 controls the operation of devices related to the drivetrain of the vehicle according to various programs. For example, the drivetrain control unit 210 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0150] The body system control unit 220 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 220 functions as a control device for a smart key system, a keyless entry system, a power window device, various lamps (e.g., head lamps, back lamps, brake lamps, blinkers, fog lamps), etc. In this case, radio waves transmitted from a portable device that substitutes for a key or signals from various switches may be input to the body system control unit 220. The body system control unit 220 receives input of such radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.

[0151] The outside-vehicle information detection unit 230 detects information outside the vehicle equipped with the vehicle control system 200. For example, an imaging unit 231 is connected to the outside-vehicle information detection unit 230. The outside-vehicle information detection unit 230 causes the imaging unit 231 to capture an image outside the vehicle, and receives the captured image from the imaging unit 231. The outside-vehicle information detection unit 230 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received image.

[0152] The imaging unit 231 is an optical sensor that receives light and outputs an electrical signal according to the amount of the received light. The imaging unit 231 can output the electrical signal as an image, and can also output it as distance measurement information. The light received by the imaging unit 231 may be visible light, or may be invisible light such as infrared light. The imaging unit 231 includes a light detection device according to any one of the first to fourth embodiments.

[0153] The in-vehicle information detection unit 240 detects information about the inside of the vehicle equipped with the vehicle control system 200. For example, a driver state detection unit 241 that detects the state of the driver is connected to the in-vehicle information detection unit 240. For example, the driver state detection unit 241 includes a camera that captures an image of the driver, and the in-vehicle information detection unit 240 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 241, or may determine whether the driver is dozing. This camera may include any of the photodetectors of the first to fourth embodiments, and may be, for example, the camera 100 shown in FIG. 18.

[0154] The microcomputer 251 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 230 or the inside-vehicle information detection unit 240, and output a control command to the drive system control unit 210. For example, the microcomputer 251 can perform cooperative control aimed at realizing functions of an ADAS (Advanced Driver Assistance System), such as vehicle collision avoidance, impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, collision warning, lane departure warning, etc.

[0155] In addition, the microcomputer 251 can perform cooperative control for the purpose of automatic driving, in which the vehicle travels autonomously without being operated by the driver, by controlling the driving force generating device, the steering mechanism, or the braking device based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 230 or the inside vehicle information detection unit 240.

[0156] Furthermore, the microcomputer 251 can output a control command to the body system control unit 220 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 230. For example, the microcomputer 251 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 230, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0157] The audio / image output unit 252 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 19, an audio speaker 261, a display unit 262, and an instrument panel 263 are shown as such output devices. The display unit 262 may include, for example, an on-board display or a head-up display.

[0158] FIG. 20 is a plan view showing a specific example of the setting position of the imaging unit 231 in FIG.

[0159] 20 includes imaging units 301, 302, 303, 304, and 305 as the imaging unit 231. The imaging units 301, 302, 303, 304, and 305 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 300.

[0160] The imaging unit 301 provided on the front nose mainly acquires images of the front of the vehicle 300. The imaging unit 302 provided on the left side mirror and the imaging unit 303 provided on the right side mirror mainly acquire images of the sides of the vehicle 300. The imaging unit 304 provided on the rear bumper or the back door mainly acquires images of the rear of the vehicle 300. The imaging unit 305 provided on the upper part of the windshield inside the vehicle cabin mainly acquires images of the front of the vehicle 300. The imaging unit 305 is used to detect, for example, a leading vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, and the like.

[0161] FIG. 20 shows an example of the imaging ranges of the imaging units 301, 302, 303, and 304 (hereinafter referred to as "imaging units 301 to 304"). Imaging range 311 indicates the imaging range of the imaging unit 301 provided on the front nose. Imaging range 312 indicates the imaging range of the imaging unit 302 provided on the left side mirror. Imaging range 313 indicates the imaging range of the imaging unit 303 provided on the right side mirror. Imaging range 314 indicates the imaging range of the imaging unit 304 provided on the rear bumper or the back door. For example, the image data captured by the imaging units 301 to 304 are superimposed to obtain an overhead image of the vehicle 300 viewed from above. Hereinafter, the imaging ranges 311, 312, 313, and 314 are referred to as "imaging ranges 311 to 314".

[0162] At least one of the imaging units 301 to 304 may have a function of acquiring distance information. For example, at least one of the imaging units 301 to 304 may be a stereo camera including a plurality of imaging devices, or may be an imaging device having pixels for detecting a phase difference.

[0163] For example, the microcomputer 251 (FIG. 19) calculates the distance to each solid object in the imaging range 311-314 and the change in this distance over time (relative speed with respect to the vehicle 300) based on the distance information obtained from the imaging units 301-304. Based on these calculation results, the microcomputer 251 can extract, as a preceding vehicle, a solid object that is the closest solid object on the traveling path of the vehicle 300 and travels in approximately the same direction as the vehicle 300 at a predetermined speed (for example, 0 km / h or more). Furthermore, the microcomputer 251 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, according to this example, cooperative control can be performed for the purpose of automatic driving that travels autonomously without the driver's operation.

[0164] For example, the microcomputer 251 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 301 to 304, and can use the data for automatic obstacle avoidance. For example, the microcomputer 251 distinguishes obstacles around the vehicle 300 into obstacles that are visible to the driver of the vehicle 300 and obstacles that are difficult to see. Then, the microcomputer 251 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and there is a possibility of a collision, the microcomputer 251 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 261 or the display unit 262, or by performing forced deceleration or avoidance steering via the drive system control unit 210.

[0165] At least one of the imaging units 301 to 304 may be an infrared camera that detects infrared rays. For example, the microcomputer 251 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 301 to 304. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 301 to 304 as infrared cameras and a procedure of performing a pattern matching process on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 251 determines that a pedestrian is present in the captured images of the imaging units 301 to 304 and recognizes the pedestrian, the audio / image output unit 252 controls the display unit 262 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 252 may also control the display unit 262 to display an icon or the like indicating a pedestrian at a desired position.

[0166] FIG. 21 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0167] 21 shows a state in which an operator (doctor) 531 is performing surgery on a patient 532 on a patient bed 533 using an endoscopic surgery system 400. As shown in the figure, the endoscopic surgery system 400 is composed of an endoscope 500, other surgical tools 510 such as an insufflation tube 511 and an energy treatment tool 512, a support arm device 520 that supports the endoscope 500, and a cart 600 on which various devices for endoscopic surgery are mounted.

[0168] The endoscope 500 is composed of a lens barrel 501, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 532, and a camera head 502 connected to the base end of the lens barrel 501. In the illustrated example, the endoscope 500 is configured as a so-called rigid lens barrel having a rigid lens barrel 501, but the endoscope 500 may be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0169] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 501. A light source device 603 is connected to the endoscope 500, and light generated by the light source device 603 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 501, and is irradiated via the objective lens toward an observation target in a body cavity of a patient 532. The endoscope 500 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0170] An optical system and an image sensor are provided inside the camera head 502, and reflected light (observation light) from an observation target is collected on the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The image signal is transmitted to a camera control unit (CCU) 601 as RAW data.

[0171] The CCU 601 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 500 and the display device 602. Furthermore, the CCU 601 receives an image signal from the camera head 502, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0172] Under the control of the CCU 601 , the display device 602 displays an image based on an image signal that has been subjected to image processing by the CCU 601 .

[0173] The light source device 603 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 500 with irradiation light when imaging an operation site or the like.

[0174] The input device 604 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 400 via the input device 604. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 500.

[0175] The treatment tool control device 605 controls the driving of the energy treatment tool 512 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 606 feeds gas into the body cavity of the patient 532 via the insufflation tube 511 in order to secure the field of view of the endoscope 500 and the working space of the surgeon. The recorder 607 is a device capable of recording various information related to the surgery. The printer 608 is a device capable of printing various information related to the surgery in various formats such as text, image, or graph.

[0176] The light source device 603 that supplies irradiation light to the endoscope 500 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 603. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation target with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 502 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0177] Furthermore, the light source device 603 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 502 in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner and synthesizing the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0178] The light source device 603 may be configured to supply light of a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band light is irradiated compared to the irradiated light (i.e., white light) during normal observation, and a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast, so-called narrow band imaging is performed. Alternatively, the special light observation may be a fluorescent observation in which an image is obtained by fluorescence generated by irradiating excitation light. In the fluorescent observation, excitation light is irradiated to the body tissue and the fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and excitation light corresponding to the fluorescent wavelength of the reagent is irradiated to the body tissue to obtain a fluorescent image. The light source device 603 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0179] FIG. 22 is a block diagram showing an example of a functional configuration of the camera head 502 and the CCU 601 shown in FIG.

[0180] The camera head 502 has a lens unit 701, an imaging section 702, a drive section 703, a communication section 704, and a camera head control section 705. The CCU 601 has a communication section 711, an image processing section 712, and a control section 713. The camera head 502 and the CCU 601 are connected to each other by a transmission cable 700 so as to be able to communicate with each other.

[0181] Lens unit 701 is an optical system provided at a connection portion with lens barrel 501. Observation light taken in from the tip of lens barrel 501 is guided to camera head 502 and enters lens unit 701. Lens unit 701 is configured by combining multiple lenses including a zoom lens and a focus lens.

[0182] The imaging unit 702 is composed of an imaging element. The imaging element constituting the imaging unit 702 may be one (so-called single-plate type) or multiple (so-called multi-plate type). When the imaging unit 702 is composed of a multi-plate type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 702 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 531 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 702 is composed of a multi-plate type, the lens unit 701 may also be provided in multiple systems corresponding to each imaging element. The imaging unit 702 is, for example, a light detection device of any of the first to fourth embodiments.

[0183] Furthermore, the imaging section 702 does not necessarily have to be provided in the camera head 502. For example, the imaging section 702 may be provided inside the lens barrel 501, immediately behind the objective lens.

[0184] The driving section 703 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 701 by a predetermined distance along the optical axis under the control of the camera head control section 705. This allows the magnification and focus of the image captured by the imaging section 702 to be appropriately adjusted.

[0185] The communication unit 704 is configured by a communication device for transmitting and receiving various information to and from the CCU 601. The communication unit 704 transmits the image signal obtained from the imaging unit 702 to the CCU 601 via the transmission cable 700 as RAW data.

[0186] Furthermore, the communication unit 704 receives a control signal for controlling the driving of the camera head 502 from the CCU 601, and supplies the control signal to the camera head control unit 705. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing the image, and / or information specifying the magnification and focus of the captured image.

[0187] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by a user, or may be automatically set by the control unit 713 of the CCU 601 based on an acquired image signal. In the latter case, the endoscope 500 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0188] The camera head control unit 705 controls the driving of the camera head 502 based on a control signal received from the CCU 601 via the communication unit 704 .

[0189] The communication unit 711 is configured with a communication device for transmitting and receiving various information to and from the camera head 502. The communication unit 711 receives an image signal transmitted from the camera head 502 via the transmission cable 700.

[0190] Furthermore, the communication unit 711 transmits, to the camera head 502, a control signal for controlling the driving of the camera head 502. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0191] The image processing unit 712 performs various types of image processing on the image signal, which is RAW data sent from the camera head 502 .

[0192] The control unit 713 performs various controls related to the imaging of the operation site etc. by the endoscope 500 and the display of the captured image obtained by imaging the operation site etc. For example, the control unit 713 generates a control signal for controlling the driving of the camera head 502.

[0193] Further, the control unit 713 causes the display device 602 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 712. At this time, the control unit 713 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 713 can recognize surgical tools such as forceps, specific living body parts, bleeding, mist generated when the energy treatment tool 512 is used, etc., by detecting the shape and color of the edge of an object included in the captured image. When the control unit 713 causes the display device 602 to display the captured image, it may use the recognition result to superimpose various types of surgery support information on the image of the surgical site. By superimposing and presenting the surgery support information to the surgeon 531, the burden on the surgeon 531 can be reduced and the surgeon 531 can proceed with the surgery reliably.

[0194] The transmission cable 700 connecting the camera head 502 and the CCU 601 is an electrical signal cable corresponding to communication of electrical signals, an optical fiber corresponding to optical communication, or a composite cable of these.

[0195] Here, in the illustrated example, the communication is performed by wire using the transmission cable 700, but the communication between the camera head 502 and the CCU 601 may be performed wirelessly.

[0196] Although the embodiments of the present disclosure have been described above, these embodiments may be implemented with various modifications within the scope of the gist of the present disclosure. For example, two or more embodiments may be implemented in combination.

[0197] The present disclosure may also be configured as follows.

[0198] (1) A first substrate; an insulating film provided on the first substrate; the insulating film includes a plurality of cavities provided at different heights; The plurality of cavities are arranged in a stepped manner. Semiconductor device.

[0199] (2) The semiconductor device according to (1), wherein the plurality of cavities are provided at positions that do not overlap with each other in a planar view.

[0200] (3) The semiconductor device according to (1), wherein one of the cavities is provided, in a planar view, between a first wiring and a second wiring in a wiring layer provided in the insulating film.

[0201] (4) The plurality of cavities include first to Nth cavities provided at first to Nth heights (N is an integer of 2 or more), respectively; The first to Nth cavities are arranged in a staircase shape with N steps. The semiconductor device according to (1).

[0202] (5) The insulating film further includes first to Nth wiring layers provided at the first to Nth heights, respectively. The first to Nth cavities are provided in the first to Nth wiring layers, respectively. The semiconductor device according to (4).

[0203] (6) the insulating film includes two or more cavities provided at a K-th height as a K-th cavity (K is an integer satisfying 1≦K≦N); The two or more cavities are arranged to form a ring in a plan view. The semiconductor device according to (4).

[0204] (7) A pixel region including a plurality of pixels; an extra-pixel region surrounding the pixel region in a plan view, The plurality of cavities are disposed within the extra-pixel region. The semiconductor device according to (1).

[0205] (8) the extra-pixel region includes a guard ring that surrounds the pixel region in a plan view, the guard ring is disposed between the pixel region and the plurality of cavities; The semiconductor device according to (7).

[0206] (9) The semiconductor device according to (1), further comprising a second substrate provided on the insulating film and having a slit formed therein.

[0207] (10) The semiconductor device according to (9), wherein the slit is provided at a position that does not overlap with the plurality of cavities in a plan view.

[0208] (11) the insulating film includes a first insulating film provided on the first substrate and a second insulating film provided on the first insulating film; The cavities are provided in the second insulating film. The semiconductor device according to (1).

[0209] (12) A wiring provided in the first insulating film; a first pad provided in the first insulating film and electrically connected to the wiring; a second pad provided on the first pad within the second insulating film; The semiconductor device according to (11), wherein the wiring, the first pad, or the second pad is provided at a position overlapping with at least one of the plurality of cavities in a plan view.

[0210] (13) a first pad provided in the first insulating film; a second pad provided on the first pad within the second insulating film; The semiconductor device according to (11), wherein the first pad or the second pad is provided at a position overlapping with at least one of the plurality of cavities in a plan view.

[0211] (14) Further comprising a wiring provided in the first insulating film, The semiconductor device according to (11), wherein the wiring is provided at a position overlapping with at least one of the plurality of cavities in a plan view.

[0212] (15) A first substrate; an insulating film provided on the first substrate; the insulating film includes a first cavity and a second cavity provided at different heights; The first cavity and the second cavity are provided at different positions in a plan view. Semiconductor device.

[0213] (16) The semiconductor device according to (15), wherein the first cavity and the second cavity are provided at positions that do not overlap with each other in a plan view.

[0214] (17) forming an insulating film on a first substrate; dicing the first substrate after forming the insulating film; Including, the insulating film is formed to include a plurality of cavities provided at different heights; The plurality of cavities are arranged in a stepped manner. A method for manufacturing a semiconductor device.

[0215] (18) the insulating film is formed to include a first insulating film and a second insulating film; the insulating film is formed by forming the first insulating film on the first substrate, forming the second insulating film on a second substrate so as to include the plurality of cavities, and bonding the first substrate and the second substrate together so as to sandwich the first insulating film and the second insulating film; The first substrate and the second substrate are diced after the bonding. A method for manufacturing a semiconductor device according to (17).

[0216] (19) The method for manufacturing a semiconductor device according to (17), wherein one of the plurality of cavities is formed, in a planar view, between a first wiring and a second wiring in one wiring layer provided in the insulating film.

[0217] (20) The one cavity included in the plurality of cavities is forming the first wiring and the second wiring in a first film of the insulating film; forming a first recess in the first film between the first wiring and the second wiring; forming a second film of the insulating film so that the one cavity remains in the first recess; The method for manufacturing a semiconductor device according to (19), [Explanation of symbols]

[0218] 1: pixel; 2: pixel array; 3: control circuit; 4: vertical drive circuit, 5: column signal processing circuit, 6: horizontal drive circuit, 7: output circuit, 8: vertical signal line, 9: horizontal signal line, 10: lower substrate, 11: substrate, 12: interlayer insulating film, 13: contact plugs, 14a to 14f: wiring layers, 15a to 15e: via plugs, 16: via plugs, 17: wiring layer, 17a: wiring, 18: via plug, 19: metal pad, 20: Upper substrate, 21: Substrate, 21a: N-type region, 21b: P-type region, 22: interlayer insulating film, 22a: insulating film, 23: contact plug, 24a to 24d: wiring layers, 25a to 25c: via plugs, 26: filter layer, 27: lens layer, 28: via plug, 29: metal pad, 31: insulating film, 32: insulating film, 33: insulating film, 34: insulating film, 41: barrier metal layer, 42: wiring material layer, 51: resist layer, 61: pixel isolation insulating film, 61a: insulating film, 61b: insulating film, 62: light shielding layer

Claims

1. A first substrate; an insulating film provided on the first substrate; the insulating film includes a plurality of cavities provided at different heights; The plurality of cavities are arranged in a stepped manner. Semiconductor device.

2. The semiconductor device according to claim 1 , wherein the plurality of cavities are provided at positions that do not overlap each other in a plan view.

3. 2. The semiconductor device according to claim 1, wherein one of said plurality of cavities is provided between a first wiring and a second wiring in one wiring layer provided in said insulating film in a plan view.

4. the plurality of cavities include first to Nth cavities provided at first to Nth heights (N is an integer of 2 or more), respectively; The first to Nth cavities are arranged in a staircase shape of N steps. The semiconductor device according to claim 1 .

5. The insulating film further includes first to Nth wiring layers provided at the first to Nth heights, respectively; The first to Nth cavities are provided in the first to Nth wiring layers, respectively. The semiconductor device according to claim 4.

6. the insulating film includes two or more cavities provided at a K-th height as a K-th cavity (K is an integer satisfying 1≦K≦N); The two or more cavities are arranged to form a ring in a plan view. The semiconductor device according to claim 4.

7. A pixel region including a plurality of pixels; an extra-pixel region surrounding the pixel region in a plan view, The plurality of cavities are disposed within the extra-pixel region. The semiconductor device according to claim 1 .

8. the extra-pixel region includes a guard ring that surrounds the pixel region in a plan view, the guard ring is disposed between the pixel region and the plurality of cavities; The semiconductor device according to claim 7.

9. The semiconductor device according to claim 1 , further comprising a second substrate provided on said insulating film and having a slit formed therein.

10. The semiconductor device according to claim 9 , wherein the slit is provided at a position not overlapping with the plurality of cavities in a plan view.

11. the insulating film includes a first insulating film provided on the first substrate and a second insulating film provided on the first insulating film; The plurality of cavities are provided in the second insulating film. The semiconductor device according to claim 1 .

12. A wiring provided in the first insulating film; a first pad provided in the first insulating film and electrically connected to the wiring; a second pad provided on the first pad within the second insulating film; The semiconductor device according to claim 11 , wherein the wiring, the first pad, or the second pad is provided at a position overlapping with at least one of the plurality of cavities in a plan view.

13. a first pad provided in the first insulating film; a second pad provided on the first pad within the second insulating film; The semiconductor device according to claim 11 , wherein the first pad or the second pad is provided at a position overlapping with at least one of the plurality of cavities in a plan view.

14. The semiconductor device further includes a wiring provided in the first insulating film, The semiconductor device according to claim 11 , wherein the wiring is provided at a position overlapping at least one of the plurality of cavities in a plan view.

15. A first substrate; an insulating film provided on the first substrate; the insulating film includes a first cavity and a second cavity provided at different heights; The first cavity and the second cavity are provided at different positions in a plan view. Semiconductor device.

16. The semiconductor device according to claim 15 , wherein the first cavity and the second cavity are provided at positions not overlapping with each other in a plan view.

17. forming an insulating film on a first substrate; dicing the first substrate after forming the insulating film; Including, the insulating film is formed to include a plurality of cavities provided at different heights; The plurality of cavities are arranged in a stepped manner. A method for manufacturing a semiconductor device.

18. the insulating film is formed to include a first insulating film and a second insulating film; the insulating film is formed by forming the first insulating film on the first substrate, forming the second insulating film on the second substrate so as to include the plurality of cavities, and bonding the first substrate and the second substrate together so as to sandwich the first insulating film and the second insulating film; The first substrate and the second substrate are diced after the bonding. The method for manufacturing a semiconductor device according to claim 17.

19. 18. The method for manufacturing a semiconductor device according to claim 17, wherein one of the plurality of cavities is formed, in a plan view, between a first wiring and a second wiring in one wiring layer provided in the insulating film.

20. The one cavity included in the plurality of cavities is forming the first wiring and the second wiring in a first film of the insulating film; forming a first recess in the first film between the first wiring and the second wiring; forming a second film of the insulating film so that the one cavity remains in the first recess; The method for manufacturing a semiconductor device according to claim 19,

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