Vertical resonator type surface light-emitting laser chip structure for quick testing and formation method of the same

Abstract

To provide a vertical resonator type surface light-emitting laser chip structure for quick testing, and provide a formation method of the same.SOLUTION: A vertical resonator type surface light-emitting laser chip structure includes a probing region and a light emission region that are segmented by a first trench. The vertical resonator type surface light-emitting laser chip structure contains a substrate, an epitaxial layer, a cover layer, a first electrode, and a second electrode. The epitaxial layer is formed over an upper surface of the substrate. The cover layer is formed over the epitaxial layer. The first electrode is formed over the cover layer, and at a bottom part of the first trench and two side walls. The second electrode is formed at a lower surface of the substrate. The probing region includes a plurality of second trenches for dividing the probing region into a plurality of sub-regions. The epitaxial layer in the light emission region includes a first wet oxygen layer with an open. The epitaxial layer in each sub region of the probing region includes a second wet oxygen layer over a whole region of the corresponding sub region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a vertical cavity surface emitting laser chip structure, and more particularly to a vertical cavity surface emitting laser chip structure for rapid testing. [Background technology]

[0002] In recent years, vertical cavity surface emitting laser (VCSEL) elements have been widely used as light sources for electronic devices.

[0003] In the complete fabrication process of the vertical cavity surface emitting laser chip, an insulating layer is added to the structure to prevent leakage from the sidewalls and limit the current path from the probing region to the active layer, as shown in FIG. 1. FIG. 1 is a cross-sectional view of a conventional vertical cavity surface emitting laser chip structure 1. The vertical cavity surface emitting laser chip structure 1 includes a substrate 11, an epitaxial layer 12 (consisting of an N-type epitaxial layer 12N, a multiple quantum well layer 12M, and a P-type epitaxial layer 12P), a cover layer 13, an insulating layer 14, a first electrode 15, and a second electrode 16. The epitaxial layer 12 further includes a wet oxygen layer 121. The probing region R1 (left side of the dotted line) and the light emitting region R2 (right side of the dotted line) are separated by a trench 102. The complete fabrication process of the vertical cavity surface emitting laser chip usually takes many days because the insulating layer 14 needs to be formed. It is difficult to complete the validation of a newly developed epitaxial material in a short period of time and then realize subsequent development improvements and optimization.

[0004] In view of the above circumstances, how to shorten the number of days required for the manufacturing process of vertical-cavity surface-emitting laser chips and realize rapid testing of vertical-cavity surface-emitting laser chips has become an urgent issue in the industry. Summary of the Invention

[0005] The purpose of the present invention is to provide a vertical cavity surface emitting laser chip structure for rapid testing. By omitting the formation of an insulating layer, adding a trench in the probing area, forming a wet oxygen layer with a desired opening in the light emitting area, and forming a wet oxygen layer in the probing area, it is possible to prevent current from entering the active layer from the probing area and affecting the electrical characteristics. Therefore, compared with the complete manufacturing process of the vertical cavity surface emitting laser chip, the manufacturing process of the vertical cavity surface emitting laser chip according to the present invention can be shortened by several days, and the verification of the newly developed epitaxial can be completed in the shortest time, and the subsequent development improvement and optimization can be realized.

[0006] In order to achieve the above object, the present invention provides a vertical cavity surface emitting laser chip structure. The vertical cavity surface emitting laser chip structure has a probing region and a light emitting region. The probing region and the light emitting region are partitioned by a first trench. The vertical cavity surface emitting laser chip structure includes a substrate, an epitaxial layer, a cover layer, a first electrode, and a second electrode. The epitaxial layer is formed on a top surface of the substrate. The cover layer is formed on the epitaxial layer. The first electrode is formed on the cover layer and on a bottom and two side walls of the first trench. The second electrode is formed on a bottom surface of the substrate. The probing region has a plurality of second trenches partitioning the probing region into a plurality of sub-regions. The epitaxial layer in the light emitting region has a first wet oxygen layer having an opening. The epitaxial layer in each of the sub-regions of the probing region has a second wet oxygen layer over the entire area of ​​the corresponding sub-region. The vertical cavity surface emitting laser chip structure of the present invention employs the above structure, which can realize rapid testing of the vertical cavity surface emitting laser chip.

[0007] In an embodiment of the present invention, the substrate is a gallium arsenide (GaAs) substrate.

[0008] In an embodiment of the present invention, the epitaxial layer includes an N-type epitaxial layer formed on the top surface of the substrate, a multiple quantum well layer formed on the N-type epitaxial layer, and a P-type epitaxial layer formed on the multiple quantum well layer. The first wet oxygen layer is formed on the P-type epitaxial layer in the light emitting region. Each of the second wet oxygen layers is formed on the P-type epitaxial layer in a corresponding sub-region of the probing region. The first wet oxygen layer and each of the second wet oxygen layers are formed simultaneously in a wet oxidation process.

[0009] In an embodiment of the present invention, the epitaxial layer is formed by metalorganic chemical vapor deposition or molecular beam epitaxy using a III-V or II-VI semiconductor material.

[0010] In an embodiment of the present invention, the first trench and the second trench are formed simultaneously by a wet etching process or a dry etching process.

[0011] The present invention also provides a method for forming a vertical cavity surface emitting laser chip structure for rapid testing, the method includes the steps of: preparing a substrate, forming an epitaxial layer on a top surface of the substrate, forming a cover layer on the epitaxial layer, forming a first trench that divides the vertical cavity surface emitting laser chip structure into a probing region and a light emitting region, forming a plurality of second trenches that divide the probing region into a plurality of sub-regions, forming a first wet oxygen layer with an opening in the epitaxial layer in the light emitting region, forming a second wet oxygen layer in the epitaxial layer in each of the sub-regions of the probing region over the entire area of ​​the corresponding sub-region, forming a first electrode on the cover layer and on a bottom and two sidewalls of the first trench, and forming a second electrode on a bottom surface of the substrate.

[0012] In an embodiment of the present invention, the substrate is a gallium arsenide (GaAs) substrate.

[0013] In an embodiment of the present invention, the step of forming the epitaxial layer includes the steps of forming an N-type epitaxial layer on the top surface of the substrate, forming a multiple quantum well layer on the N-type epitaxial layer, and forming a P-type epitaxial layer on the multiple quantum well layer. The first wet oxygen layer is formed on the P-type epitaxial layer in the light emitting region. Each of the second wet oxygen layers is formed on the P-type epitaxial layer in a corresponding sub-region of the probing region. The first wet oxygen layer and each of the second wet oxygen layers are formed simultaneously in a wet oxidation process.

[0014] In an embodiment of the present invention, the epitaxial layer is formed by metalorganic chemical vapor deposition or molecular beam epitaxy using a III-V or II-VI semiconductor material.

[0015] In an embodiment of the present invention, the first trench and the second trench are formed simultaneously by a wet etching process or a dry etching process.

[0016] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below. [Brief description of the drawings]

[0017] [Figure 1] Cross-sectional view of a conventional vertical-cavity surface-emitting laser chip structure [Diagram 2] FIG. 1 is a cross-sectional view showing a vertical cavity surface emitting laser chip structure according to an embodiment of the present invention. [Diagram 3] 3 is a flow chart of a method for forming the vertical cavity surface emitting laser chip structure shown in FIG. [Figure 4A] FIG. 4 is a schematic diagram showing a structure corresponding to the flowchart of FIG. 3. [Figure 4B] FIG. 4 is a schematic diagram showing a structure corresponding to the flowchart of FIG. 3. [Figure 4C] FIG. 4 is a schematic diagram showing a structure corresponding to the flowchart of FIG. 3. [Figure 4D] FIG. 4 is a schematic diagram showing a structure corresponding to the flowchart of FIG. 3. [Figure 4E] FIG. 4 is a schematic diagram showing a structure corresponding to the flowchart of FIG. 3. [Figure 4F] FIG. 4 is a schematic diagram showing a structure corresponding to the flowchart of FIG. 3. [Figure 4G] FIG. 4 is a schematic diagram showing a structure corresponding to the flowchart of FIG. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The contents of the present invention will be described below through examples. The examples of the present invention are examples of embodiments, and are not intended to limit the present invention to the environments, applications, or specific aspects described in the examples. Therefore, the explanation of the examples is for explaining the present invention, but does not limit the present invention. In the embodiments and drawings, components that are not directly related to the present invention are omitted and not shown. The dimensional relationship between the components in the drawings is for ease of understanding, and does not limit the actual dimensions.

[0019] 2 shows a vertical cavity surface emitting laser chip structure 2 for rapid testing. The vertical cavity surface emitting laser chip structure 2 has a probing region R1 and a light emitting region R2. The probing region R1 and the light emitting region R2 are defined by a first trench 202. The vertical cavity surface emitting laser chip structure 2 includes a substrate 21, an epitaxial layer 22, a cover layer 23, a first electrode 24, and a second electrode 25.

[0020] The substrate 21 may be, but is not limited to, a gallium arsenide (GaAs) substrate. The epitaxial layer 22 is formed on the upper surface of the substrate 21. The epitaxial layer 22 is formed by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) using a III-V group semiconductor material or a II-VI group semiconductor material. For example, the epitaxial layer 22 may be formed by alternately stacking gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), and aluminum arsenide (AlAs). The energy gap of the epitaxial layer 22 is 1.3 to 2.5 eV.

[0021] The epitaxial layer 22 includes an N-type epitaxial layer 22N, a multiple quantum well layer 22M, and a P-type epitaxial layer 22P. The N-type epitaxial layer 22N is formed on the upper surface of the substrate 21. The multiple quantum well layer 22M is formed on the N-type epitaxial layer 22N. The P-type epitaxial layer 22P is formed on the multiple quantum well layer 22M.

[0022] The cover layer 23 is formed on the epitaxial layer 22. The first electrode 24 is formed on the cover layer 23 and on the bottom and two side walls of the first trench 202. The second electrode 25 is formed on the lower surface of the substrate 21. The first electrode 24 is a P-electrode (P-pad), and the second electrode 25 is an N-electrode (N-pad). The first electrode 24 and the second electrode 25 are made of a metal material such as gold (Au), titanium (Ti), or platinum (Pt).

[0023] The probing region R1 has a number of second trenches 204. The second trenches 204 divide the probing region R1 into a number of sub-regions SR1. The first trenches 202 and the second trenches 204 are formed simultaneously in a wet or dry etching process, i.e., in the same etching process according to a specific photomask pattern.

[0024] The epitaxial layer 22 in the light-emitting region R2 has a first wet oxygen layer 221 having an opening 22A. The epitaxial layer 22 in each sub-region SR1 of the probing region R1 has a second wet oxygen layer 222 over the entire area of ​​the corresponding sub-region SR1. In detail, as shown in FIG. 2, in the manufacturing process of the present invention, the first wet oxygen layer 221 having the opening 22A is formed in the light-emitting region R2, while the second wet oxygen layer 222 is also formed in the entire area of ​​the sub-regions SR1 of the probing region R1 as an insulating layer for blocking current, thereby preventing current from entering the active layer (i.e., the multiple quantum well layer 22M) from the probing region R1 and affecting the electrical characteristics. Therefore, compared with the complete manufacturing process of the vertical cavity surface-emitting laser chip, the manufacturing process of the vertical cavity surface-emitting laser chip according to the present invention can omit the formation of an insulating layer, thereby shortening the manufacturing process by several days, and completing the verification of the newly developed epitaxial in the shortest time, and realizing the subsequent development improvement and optimization.

[0025] 2, the first wet oxygen layer 221 is formed on the P-type epitaxial layer 22P in the light emitting region R2. Each second wet oxygen layer 222 is formed on the P-type epitaxial layer 22P in a corresponding sub-region SR1 of the probing region R1. The first wet oxygen layer 221 and each second wet oxygen layer 222 are formed simultaneously in a wet oxidation process.

[0026] A second embodiment of the present invention will now be described with reference to Figure 3 and Figures 4A to 4G. Figure 3 is a flow chart of a method for forming a vertical cavity surface emitting laser chip structure 2 for rapid testing. Figures 4A to 4G are schematic diagrams showing structures corresponding to the flow chart of Figure 3.

[0027] First, in step S301, substrate 21 is prepared (see FIG. 4A). Next, in step S303, epitaxial layer 22 is formed on the upper surface of substrate 21 (see FIG. 4B). In step S305, cover layer 23 is formed on epitaxial layer 22 (see FIG. 4C).

[0028] Then, in step S307, a first trench 202 is formed to divide the vertical cavity surface emitting laser chip structure 2 into a probing region R1 and a light emitting region R2, and a plurality of second trenches 204 are formed to divide the probing region R1 into a plurality of sub-regions SR1 (see FIG. 4D).

[0029] Next, in step S309, a first wet oxygen layer 221 is formed on the epitaxial layer 22 in the light emitting region R2, and a second wet oxygen layer 222 is formed on the epitaxial layer 22 in each sub-region SR1 of the probing region R1 (see FIG. 4E).

[0030] In step S311, a first electrode 24 is formed on the cover layer 23 and on the bottom and two side walls of the first trench 202 (see FIG. 4F). Then, in step S313, a second electrode 25 is formed on the lower surface of the substrate 21 (see FIG. 4G).

[0031] Specifically, in step S303, the step of forming the epitaxial layer 22 includes the steps of forming an N-type epitaxial layer 22N on the upper surface of the substrate 21, forming a multiple quantum well layer 22M on the N-type epitaxial layer 22N, and forming a P-type epitaxial layer 22P on the multiple quantum well layer 22M. Also, in step S309, a first wet oxygen layer 221 is formed in the P-type epitaxial layer 22P in the light emitting region R2, and each second wet oxygen layer 222 is formed in the P-type epitaxial layer 22P in the corresponding sub-region SR1 of the probing region R1.

[0032] The order of steps in the flowchart shown in Figure 3 is for illustrative purposes only and is not intended to limit the present invention. In other words, a person skilled in the art can appropriately change the order of these steps based on the disclosure of Figure 3 to form the vertical cavity surface emitting laser chip structure of Figure 2.

[0033] As mentioned above, the present invention provides a vertical cavity surface emitting laser chip structure for rapid testing, which can omit the formation of an insulating layer, so that compared with the complete manufacturing process of the vertical cavity surface emitting laser chip, the manufacturing process of the vertical cavity surface emitting laser chip of the present invention can be shortened by several days, and the verification of the newly developed epitaxial can be completed in the shortest time, and the subsequent development improvement and optimization can be realized.

[0034] The above examples are for explaining the embodiments of the present invention and for explaining the characteristic configuration of the present invention. The present invention is not limited to the above examples. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention is based on the claims. [Explanation of symbols]

[0035] 1 Vertical-cavity surface-emitting laser chip structure 11 Substrate 12 Epitaxial layer 12N N-type epitaxial layer 12M multi-quantum well layer 12P P-type epitaxial layer 13 Cover Layer 14 Insulating layer 15 1st electrode 16 2nd electrode 102 Trench 121 Wet oxygen layer 2 Vertical-cavity surface-emitting laser chip structure 21 Substrate 22 Epitaxial layer 22A opening 22N N-type epitaxial layer 22M multi-quantum well layer 22P P-type epitaxial layer 23 Cover Layer 24 1st electrode 25 2nd electrode 202 Trench No. 1 204 Second Trench 221 First wet oxygen layer 222 Second wet oxygen layer R1 Probing Region R2 Light-emitting area SR1 Subarea S301~S313 Steps

Claims

1. A vertical cavity surface emitting laser chip structure, the vertical cavity surface emitting laser chip structure having a probing region and a light emitting region defined by a first trench; A substrate; an epitaxial layer formed on an upper surface of the substrate; a cover layer formed on the epitaxial layer; a first electrode formed on the cover layer and on the bottom and two sidewalls of the first trench; a second electrode formed on a lower surface of the substrate; the probing region has a plurality of second trenches that divide the probing region into a plurality of sub-regions; the epitaxial layer in the light emitting region includes a first wet oxygen layer having an opening; the epitaxial layer in each of the sub-regions of the probing region having a second wet oxygen layer across the corresponding sub-region.

2. 2. The vertical cavity surface emitting laser chip structure of claim 1, wherein the substrate is a gallium arsenide (GaAs) substrate.

3. The epitaxial layer is an N-type epitaxial layer formed on an upper surface of the substrate; a multi-quantum well layer formed on the N-type epitaxial layer; a P-type epitaxial layer formed on the multiple quantum well layer; The first wet oxygen layer is formed on the P-type epitaxial layer in the light emitting region, and each of the second wet oxygen layers is formed on the P-type epitaxial layer in a corresponding one of the sub-regions of the probing region; 2. The vertical cavity surface emitting laser chip structure of claim 1, wherein the first wet oxygen layer and each of the second wet oxygen layers are formed simultaneously in a wet oxidation process.

4. 2. The vertical cavity surface emitting laser chip structure of claim 1, wherein the epitaxial layer is formed by metal organic chemical vapor deposition or molecular beam epitaxy using III-V group semiconductor material or II-VI group semiconductor material.

5. 2. The vertical cavity surface emitting laser chip structure of claim 1, wherein the first trench and the second trench are simultaneously formed by a wet etching process or a dry etching process.

6. 1. A method for forming a vertical cavity surface emitting laser chip structure for rapid testing, comprising: Providing a substrate; forming an epitaxial layer on an upper surface of the substrate; forming a cover layer over the epitaxial layer; forming a first trench that divides the vertical cavity surface emitting laser chip structure into a probing region and a light emitting region, and forming a plurality of second trenches that divide the probing region into a plurality of sub-regions; forming a first wet oxygen layer having an opening in the epitaxial layer in the light emitting region and forming a second wet oxygen layer in the epitaxial layer in each of the sub-regions in the probing region across a corresponding one of the sub-regions; forming a first electrode on the cover layer and on a bottom and two sidewalls of the first trench; forming a second electrode on a bottom surface of the substrate.

7. 7. The method of claim 6, wherein the substrate is a gallium arsenide (GaAs) substrate.

8. The step of forming the epitaxial layer includes: forming an N-type epitaxial layer on the top surface of the substrate; forming a multiple quantum well layer on the N-type epitaxial layer; forming a P-type epitaxial layer on the multiple quantum well layer; The first wet oxygen layer is formed on the P-type epitaxial layer in the light emitting region, and each of the second wet oxygen layers is formed on the P-type epitaxial layer in a corresponding one of the sub-regions of the probing region; 7. The method of claim 6, wherein the first wet oxygen layer and each of the second wet oxygen layers are formed simultaneously in a wet oxidation process.

9. 7. The method according to claim 6, wherein the epitaxial layer is formed by metal organic chemical vapor deposition or molecular beam epitaxy using a III-V group semiconductor material or a II-VI group semiconductor material.

10. 7. The method of claim 6, wherein the first trench and the second trench are formed simultaneously by a wet or dry etching process.

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