Constant voltage generation circuit

Abstract

To provide a constant voltage generation circuit that can improve the temperature characteristic of an output voltage.SOLUTION: The constant voltage generation circuit (11) comprises a selection section (3) configured to select a transistor section that is effective in at least one of a plurality of first transistor sections (1A) and a plurality of second transistor sections (2A).SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The present disclosure relates to a constant voltage generating circuit. [Background technology]

[0002] Conventionally, as one type of constant-voltage generating circuit, an ED type constant-voltage source that combines a depletion-type N-channel metal oxide semiconductor field effect transistor (MOSFET) and an enhancement-type N-channel MOSFET is widely known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 172001

[0004] [overview] Here, in the constant voltage generating circuit, there is room for improvement in the temperature characteristics of the output voltage.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a constant voltage generating circuit that can improve the temperature characteristics of the output voltage.

[0006] A constant voltage generating circuit according to an embodiment of the present disclosure includes: a first transistor stage having one or a plurality of first transistor sections connected in series, each of the first transistor sections being configured as a depletion-mode N-channel MOSFET; a second transistor stage having one or a plurality of second transistor sections connected in series, each of which is configured as an N-channel MOSFET, and connected to a low potential side of the first transistor stage; a selection unit configured to select a transistor unit to be enabled from at least one of the plurality of first transistor units and the plurality of second transistor units; an output terminal connected to a gate of the second transistor portion and configured to output an output voltage; Equipped with The gates of all the first transistor sections in the first transistor stage are connected to the source of the first transistor section on the lowest potential side. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a configuration of a constant voltage generating circuit according to a comparative example. [Diagram 2] FIG. 2 is a diagram illustrating a configuration of a constant voltage generating circuit according to an exemplary embodiment of the present disclosure. [Figure 3A] FIG. 3A is a diagram showing a first specific configuration example of the constant voltage generating circuit. [Figure 3B] FIG. 3B is a diagram showing a modification of the first configuration example. [Figure 4] FIG. 4 is a diagram illustrating an example of a table map. [Diagram 5] FIG. 5 is a diagram showing a schematic diagram of temperature characteristics. [Figure 6] FIG. 6 is a diagram illustrating an example of the temperature characteristic of the output voltage. [Figure 7] FIG. 7 is a diagram showing a second specific configuration example of the constant voltage generating circuit. [Figure 8] FIG. 8 is a diagram showing another example of the table map. [Figure 9] FIG. 9 is a diagram showing a configuration of a constant voltage generating circuit according to a modified example. [Figure 10] FIG. 10 is a diagram showing a configuration of a constant voltage generating circuit according to a modified example. [Figure 11] FIG. 11 is a flowchart showing an example of the soft start operation. [Figure 12] FIG. 12 is a waveform diagram showing an example of the behavior of the output voltage at the time of start-up. [Figure 13] FIG. 13 is a diagram showing a configuration of a constant voltage generating circuit according to a modified example. [Figure 14]FIG. 14 is a flowchart showing an example of the soft-start operation.

[0008] [Detailed Description] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <Comparative Example> FIG. 1 is a diagram showing a comparative example of a constant voltage generating circuit (basic configuration to be compared with the embodiments described later). The constant voltage generating circuit 1 of this comparative example is a so-called ED type reference voltage source. With reference to this diagram, the constant voltage generating circuit 1 includes a transistor M1 and a transistor M2. The transistor M1 is configured by a depletion type N-channel MOSFET. The transistor M2 is configured by an enhancement type N-channel MOSFET.

[0010] Note that the depletion type is one in which a drain current flows even when the gate-source voltage is 0 V. On the other hand, the enhancement type is one in which no drain current flows when the gate-source voltage is 0 V.

[0011] The drain of the transistor M1 is connected to an application terminal of the input voltage Vin. The source and back gate of the transistor M2 are connected to a ground terminal (an application terminal of the ground potential). The gate, source and back gate of the transistor M1 and the gate and drain of the transistor M2 are all connected to an output terminal Tout which is an application terminal of the output voltage Vout.

[0012] In the constant voltage generating circuit 1 of this comparative example, the gate and source of the transistor M1 are shorted. Therefore, the gate-source voltage Vgs1 of the transistor M1 is 0V. Therefore, the transistor M1 functions as a constant current source that generates a constant drain current Idd1. In other words, a constant bias current (=drain current Idd1) flows through the transistor M2. As a result, a constant output voltage Vout equivalent to the gate-source voltage Vgs2 of the transistor M2 is generated.

[0013] Here, assuming that the currents flowing through the transistors M1 and M2 operating in the saturation region are I1 and I2, respectively, the currents I1 and I2 are expressed by the following formulas (1a) and (1b).

[0014]

number

[0015] In the above formulas (1a) and (1b), μ1 and μ2 are the carrier mobilities of the transistors M1 and M2, respectively. Cox is the oxide film capacitance of the transistors M1 and M2, respectively. W1 and W2 are the gate widths of the transistors M1 and M2, respectively. L1 and L2 are the gate lengths of the transistors M1 and M2, respectively. Vth1 and Vth2 are the threshold voltages of the transistors M1 and M2, respectively.

[0016] In the constant voltage generating circuit 1, I1=I2 holds. Therefore, the output voltage Vout is expressed by the following equation (2).

[0017]

number

[0018] The threshold voltage Vth1 of the depletion-type transistor M1 is a negative value. Therefore, the above formula (2) can be expressed as the following formula (3).

[0019]

number

[0020] Therefore, the temperature characteristics of the threshold voltages Vth1 and Vth2 can be offset by appropriately designing the W / L of each of the transistors M1 and M2.

[0021] However, the constant voltage generating circuit 1 of this comparative example does not have a current capacity, and when a load (not shown) connected to the output terminal Tout requires a current capacity, the output voltage Vout decreases. One example of a load requiring a current capacity is a resistive voltage divider circuit.

[0022] <Constant voltage generating circuit according to the present disclosure> 2 is a diagram showing a configuration of a constant voltage generating circuit 11 according to an exemplary embodiment of the present disclosure. The constant voltage generating circuit 11 includes transistors M1 and M2 as in the comparative example, and also includes transistors M3 and M4. Here, differences in the configuration from the comparative example will be mainly described.

[0023] The transistor M3 is configured by a depletion-type N-channel MOSFET. The drain of the transistor M3 is connected to the drain of the transistor M1. The gate of the transistor M3 is connected to the source of the transistor M1. The source of the transistor M3 is connected to the gate of the transistor M2. The gate of the transistor M2 is connected to the output terminal Tout. The output voltage Vout is output from the output terminal Tout.

[0024] By providing such a transistor M3, a source follower is configured. A current can be supplied from the output terminal Tout to the load LD via the transistor M3, and the constant voltage generating circuit 11 can have a current capability without affecting the output voltage Vout.

[0025] Moreover, the transistor M4 is configured by a depletion type N-channel MOSFET. The drain of the transistor M4 is connected to the source of the transistor M3. The gate and source of the transistor M4 are shorted. The source of the transistor M4 is connected to the ground terminal. The constant current source CI is configured by such a transistor M4. The constant current source CI can also be regarded as an active load formed by an active element (transistor M4). When the load LD is not connected, the leakage current flowing through the transistor M3 at high temperatures is absorbed by the constant current source CI, thereby preventing the output voltage Vout from increasing.

[0026] In addition, the constant voltage generating circuit 11 according to this embodiment can be configured with depletion-type transistors M1, M3, and M4 and an enhancement-type transistor M2. In other words, it can be configured with two types of elements. This makes it possible to suppress the effects of element variations and simplify the element layout.

[0027] The transistor M2 may be a depletion type transistor with p-type impurities implanted in the gate. In this case, the transistors M1, M3, and M4 are depletion type transistors with n-type impurities implanted in the gate. The transistor M2 configured in this way can have a positive threshold voltage, and can be used instead of an enhancement type transistor. Furthermore, the transistors M1 to M4 have the same device structure (particularly the parts below the gate). This makes it possible to further suppress the effects of element variations. Also, the element layout can be simplified.

[0028] <Specific first configuration example> Fig. 3A is a diagram showing a first specific configuration example of the constant voltage generating circuit 11 described above. The constant voltage generating circuit 11 shown in Fig. 3A includes a first transistor stage 1, a second transistor stage 2, a selection section 3, and a selection signal generating section 4. The constant voltage generating circuit 11 also includes a third transistor section 1B on the high potential side of the first transistor stage 1. Note that Fig. 3A also shows the transistors M3 and M4 described above.

[0029] The first transistor stage 1 has first transistor sections 1A connected in series. The first transistor section 1A and the third transistor section 1B are each composed of a depletion type N-channel MOSFET. Each of the first transistor sections 1A is a single transistor, and in the example of FIG. 3A, five first transistor sections 1A are connected in series. The source and drain of each of the adjacent first transistor sections 1A are connected. The third transistor section 1B is connected between the application terminal of the input voltage Vin and the drain of the first transistor section 1A on the highest potential side (upper side). The third transistor section 1B is composed of, for example, a plurality of transistors connected in parallel. The drain of the third transistor section 1B is connected to the application terminal of the input voltage Vin, and the source of the third transistor section 1B is connected to the drain of the first transistor section 1A on the highest potential side. The gates of the first transistor section 1A and the third transistor section 1B are commonly connected to the source of the first transistor section 1A on the lowest potential side (lower side). The back gates of the first transistor portions 1A are commonly connected to the source of the first transistor portion 1A on the lowest potential side. The back gate of the first transistor portion 1B is connected to the source of the first transistor portion 1B.

[0030] Such a first transistor stage 1 corresponds to a transistor M1 (FIG. 2). For example, if the gate length of each of the first transistor sections 1A is 10 μm, the first transistor stage 1 corresponds to a transistor M1 having a gate length L1=10×5 μm. The third transistor section 1B generates a voltage that is higher than the voltage Vdep, which is the source voltage of the first transistor section 1A on the lowest potential side, by a voltage equivalent to the threshold voltage (negative value) of the third transistor section 1B, and is used to suppress the influence of fluctuations in the input voltage Vin.

[0031] It should be noted that the configuration of the first transistor stage 1 shown in FIG. 3 is merely an example, and the first transistor stage 1 may be composed of, for example, one first transistor portion 1A.

[0032] The second transistor stage 2 has second transistor sections 2A connected in series. Each of the second transistor sections 2A is composed of one transistor and is an enhancement type N-channel MOSFET. The drain of the second transistor section 2A on the highest potential side is connected to the source of the first transistor section 1A on the lowest potential side. The sources and drains of the adjacent second transistor sections 2A are connected. The source of the second transistor section 2A on the lowest potential side is connected to the ground terminal. The gates of the second transistor sections 2A are commonly connected to the output terminal Tout. The back gates of the second transistor sections 2A are commonly connected to the ground terminal. Any of the second transistor sections 2A may be configured by connecting multiple transistors in parallel. The number of second transistor sections 2A in the second transistor stage 2 is six in the example of FIG. 3, but may be any other number.

[0033] The selection unit 3 has a plurality of switches 3A. Each of the switches 3A is provided corresponding to each of the second transistor units 2A. The switches 3A are configured with an N-channel MOSFET. The drains of the switches 3A are connected to the drains of the second transistor units 2A, and the sources of the switches 3A are connected to the sources of the second transistor units 2A. When the switches 3A are turned on, the corresponding second transistor units 2A are bypassed and disabled. When the switches 3A are turned off, the corresponding second transistor units 2A are enabled.

[0034] The second transistor stage 2 functions as a transistor M2 (FIG. 2) having the sum of the gate lengths of the second transistor sections 2A enabled by the selection section 3. In the example of FIG. 3, the gate lengths of the six second transistor sections 2A are set to 1 μm, 2 μm, 4 μm, 8 μm, 16 μm, and 32 μm, respectively. n (n is an integer between 0 and m) The gate length is set to 2 μm (here m=5). 0 μm~2 0 +···+2 mThe gate length can be selected by the selection unit 3 (in the above example, from 1 μm to 63 μm).

[0035] The selection signal generating unit 4 generates a selection signal S1 for controlling the on / off state of each of the switches 3A in the selection unit 3. The selection signal generating unit 4 has a configuration consisting of an OR circuit 4A, an inverter 4B, and a set of a fuse 4C and a resistor 4D connected in series between the application terminal of the input voltage Vin and the ground terminal, the number of which corresponds to the number of the switches 3A (here, six). The selection signal S2 output from the node where the fuse 4C and the resistor 4D are connected is input to the first input terminal of the OR circuit 4A via the inverter 4B. The selection signal S3 is input to the second input terminal of the OR circuit 4A. The selection signal S3 is input from an electrode pad or a logic unit (not shown). The selection signal S1 output from the OR circuit 4A is input to the gate of the corresponding switch 3A. When the fuse 4C is not cut, the selection signal S2 is at a high level, and the output of the inverter 4B is at a low level. Therefore, when the fuse 4C is not cut, the level of the selection signal S1, which is the output of the OR circuit 4, can be selected by the selection signal S3. On the other hand, if the selection signal S3 is fixed at a low level, the level of the selection signal S1 can be selected depending on whether or not the fuse 4C is cut. Specifically, if the fuse 4C is not cut, the selection signal S1 is at a low level, and if the fuse 4C is cut, the selection signal S1 is at a high level. When the selection signal S1 is at a high level, the switch 3A is turned on, and when the selection signal S1 is at a low level, the switch 3A is turned off.

[0036] Next, a method for selecting the second transistor section 2A in the second transistor stage 2 in the constant voltage generating circuit 11 having the configuration shown in Fig. 3A will be described. The selection method is performed by an operator in the following steps.

[0037] First, in the first step, the second transistor section 2A to be enabled is selected by the switch 3A so that the gate length of the second transistor stage 2 is a predetermined reference value (e.g., 36 μm). At this time, the switch 3A is turned on or off by the selection signal S3 with the fuse 4C not cut. In this selected state, the output voltage Vout is measured when the temperature is a predetermined temperature T0 (e.g., room temperature).

[0038] In the second step, the drain current Idd1 flowing through the first transistor stage 1, i.e., the transistor M1 (FIG. 2), is measured in the above-mentioned selected state and temperature state. The drain current Idd1 is measured, for example, by applying a voltage higher than the output voltage Vout from the outside to the output terminal Tout, turning off the transistor M3, and measuring the drain current flowing through the transistor M4. Since the transistor M4 and the transistors in the first transistor stage 1 are both configured as depletion-type N-channel MOSFETs with their gates and sources shorted, they are subject to the same tendency of influence of manufacturing variations, and the drain current Idd1 flowing through the transistor M1 can be estimated based on the above-mentioned measured drain current. For example, the drain current Idd1 can be estimated from the ratio of the on-resistances of the transistors M1 and M4.

[0039] In a third step, the gate length L2 of the second transistor stage 2 is determined based on the output voltage Vout measured in step S1, the drain current Idd1 measured in step S2, and the table map.

[0040] Fig. 4 is a diagram showing an example of the table map. As shown in Fig. 4, in the table map, the vertical axis is the output voltage Vout, and the horizontal axis is the drain current Idd1, and characteristic lines (straight lines) for each gate length are defined. In the table map, the gate length of the characteristic line intersecting the point P specified by the measured drain current Idd1 and the measured output voltage Vout is determined as the gate length to be selected.

[0041] In the example table map of FIG. 4, point P specified by 150 nA which is the reference value of the drain current Idd1 and 900 mV which is the reference value of the output voltage Vout intersects with the characteristic line of the reference value of gate length=38 μm.

[0042] Here, as shown in FIG. 5, in the above formula (2),

number

[0043] Here, the current capabilities of the depletion-type transistor M1 and enhancement-type transistor M2 each vary due to manufacturing variations. Below, the typical current capability is represented as T (Typ), higher current capability as F (Fast), and lower current capability as S (Slow), and the combination of the current capabilities of the transistors M1 and M2 due to variations is represented as ENH / DEP. For example, if both the transistors M1 and M2 are typical values, ENH / DEP=T / T.

[0044] When ENH / DEP=T / T, the parameters in (A) above (mobility, gate width, gate length) become values ​​that correspond to the typical current capability, and point P, which represents the combination of Idd1 and Vout, is located on the characteristic line for L2=36μm, which is the reference value, as shown in Figure 4. In other words, with L2=36μm, the temperature characteristic of Vout becomes almost flat, as shown in Figure 5.

[0045] Here, if the current capabilities of transistors M1 and M2 vary in the same direction, such as ENH / DEP=S / S ​​or T / T, the parameters in (A) above also vary in the same direction. As a result, as shown in FIG. 4, point P is located at, for example, L2=37 μm or 35 μm, and the temperature characteristics become close to flat even if L2 remains at the reference value (36 μm).

[0046] Furthermore, when ENH / DEP=S / T or F / T, the value of Vout at point P will be higher or lower than when ENH / DEP=T / T, as shown in Figure 4. When ENH / DEP=S / T, the temperature characteristic of Vout will be a positive temperature characteristic, and when ENH / DEP=F / T, the temperature characteristic of Vout will be a negative temperature characteristic, and neither is a flat characteristic. Therefore, as shown in Figure 4, by adjusting L2, for example, L2=30μm when ENH / DEP=S / T, and L2=44μm when ENH / DEP=F / T, the temperature characteristic can be made closer to flat.

[0047] Furthermore, when ENH / DEP=T / F, the Idd1 value and Vout value at point P are higher than when ENH / DEP=T / T, as shown in FIG. 4. In this case, the temperature characteristic of Vout is a positive temperature characteristic, and the temperature characteristic can be made closer to flat by adjusting L2 to, for example, 30 μm, as shown in FIG. 4. Similarly, when ENH / DEP=T / S, the Idd1 value and Vout value at point P are lower than when ENH / DEP=T / T, as shown in FIG. 4. In this case, the temperature characteristic of Vout is a negative temperature characteristic, and the temperature characteristic can be made closer to flat by adjusting L2 to, for example, 46 μm, as shown in FIG. 4.

[0048] In this way, for example, by adjusting L2 to the value of L2 on the characteristic line at which point P representing the combination of Idd1 and Vout intersects in a table map such as that shown in FIG. 4, the temperature characteristic of Vout can be made closer to flat.

[0049] Then, in step 4, in order to select the second transistor section 2A to be enabled so that the gate length L2 in the second transistor stage 2 becomes the gate length determined above, the selection signal generation section 4 determines whether to cut or not cut each of the fuses 4C. When used as a product, the selection signal S3 is fixed to a low level.

[0050] Here, Fig. 6 is a diagram showing an example of the temperature characteristic of the output voltage Vout. In Fig. 6, the output voltage Vout is shown with a value obtained by setting the value of the output voltage Vout at a predetermined room temperature Tx to 1.0%. By adjusting the gate length L2 in the second transistor stage 2 as described above, for example, the positive temperature characteristic before correction (solid line) can be corrected as shown by the arrow, and the negative temperature characteristic before correction (dashed line) can be corrected as shown by the arrow. As a result, the output voltage Vout can be kept within ±α% in the temperature range WT shown by the dashed line frame in Fig. 6.

[0051] <Modification> FIG. 3B is a diagram showing a modified example of the configuration of the constant voltage generating circuit 11 shown in FIG. 3A described above. In the configuration shown in FIG. 3B, the selection section 3 is composed of a unit circuit 31. The unit circuit 31 is provided for each second transistor section 2A. As shown in FIG. 3B, the unit circuit 31 has a fuse 31A and a switch 31B. The fuse 31A and the switch 31B are connected in series between the drain and source of the second transistor section 2A. A selection signal SA is applied to the gate of the switch 31B. In a state where the fuse 31A is not cut, the switch 31B is turned on or off depending on the level of the selection signal SA, and the second transistor section 2A is disabled or enabled. In addition, if the level of the selection signal SA is fixed and the switch 31B is maintained in the on state, the second transistor section 2A can be enabled or disabled depending on whether or not the fuse 31A is cut. As a result, the gate length L2 of the second transistor stage 2 (transistor M2) can be set to a reference value by the selection signal SA in a state where the fuse 31A is not cut.

[0052] <Specific second configuration example> 7 is a diagram showing a specific second configuration example of the above-mentioned constant voltage generating circuit 11. Here, differences in configuration from the first configuration example (FIG. 3A) will be mainly described.

[0053] In the configuration shown in FIG. 7, a switch 3A in the selection unit 3 is provided corresponding to each of the first transistor sections 1A in the first transistor stage 1. That is, the switch 3A switches between enabled and disabled states of the corresponding first transistor section 1A. A selection signal S1 generated by the selection signal generation unit 4 is input to the gate of the switch 3A. The gate length of each of the first transistor sections 1A is set to a respective value. For example, a part of the first transistor section 1A may be composed of a plurality of transistors connected in parallel. For example, when a part of the first transistor sections 1A is configured to have one transistor with a gate length of 40 μm, one transistor with a gate length of 5 μm, and two transistors with a gate length of 5 μm connected in parallel, these first transistor sections 1A can be enabled to set L1=40+5+5 / 2=47.5 μm. As described above, the third transistor section 1B is used to suppress the influence of fluctuations in the input voltage Vin.

[0054] In addition, in the configuration of FIG. 7, a circuit for selecting the second transistor portion 2A in the second transistor stage 2 is not provided, and the gate length L2 in the second transistor stage 2 is fixed.

[0055] 7, the method of selecting the first transistor portion 1A in the first transistor stage 1 is similar to the above-described embodiment, and uses, for example, a table map as shown in Fig. 8. In the table map, a characteristic line of the gate length L1 is defined.

[0056] That is, when the gate length L1 in the first transistor section 1A is set as a reference value and the temperature is set to a predetermined temperature, the drain current Idd1 and the output voltage Vout are measured, and the gate length L1 is determined based on the measurement results and the table map. In the example of FIG. 8, the reference value of the gate length L1 is set to 47.5 μm. As shown in FIG. 8, in the table map, the lower the output voltage Vout is, the shorter the gate length L1 of the characteristic line becomes, which is the opposite relationship to the gate length L2 of the characteristic line shown in the table map of FIG. 4 described above.

[0057] In the configuration shown in Figure 3A or Figure 7, the on-resistance of switch 3A needs to be lower than the on-resistance of the transistor section to be selected. However, by providing switch 3A for first transistor stage 1 as in the configuration shown in Figure 7, the on-resistance of switch 3A can be made relatively high because the on-resistance of first transistor section 1A is relatively high, and the circuit area caused by switch 3A can be reduced.

[0058] On the other hand, in the configuration shown in FIG. 3A, since the selection unit 3 is provided on the low potential side, the operating voltage at the input voltage Vin can be made lower.

[0059] In the configuration of FIG. 7, the unit circuit 31 (FIG. 3B) may be applied to the configuration for selecting the first transistor portion 1A.

[0060] <Modification of the selection section> Fig. 9 is a diagram showing the configuration of a constant voltage generating circuit 11X according to a modified example of the configuration shown in Fig. 3A. In the constant voltage generating circuit 11X, a selection section 30 is provided.

[0061] The selection unit 30 has a plurality of switches 3B, a plurality of switches 3C, a plurality of switches 3D, and a plurality of switches 3E. The switch 3B is configured by an N-channel MOSFET, and the switch 3C is configured by a P-channel MOSFET. The switches 3B and 3C are connected in parallel to configure an analog switch. That is, the selection unit 30 is provided with a plurality of analog switches. Each of the multiple switches 3B and 3C (analog switches) is provided corresponding to each of the second transistor units 2A (enhancement type). The source of the switch 3B and the drain of the switch 3C are connected to the gate of the corresponding second transistor unit 2A. The drain of the switch 3B and the source of the switch 3C are connected to the application terminal of the output voltage Vout. The back gates of the switches 3B and 3C are connected to the ground terminal. The switch 3D is configured by an N-channel MOSFET. The switch 3E is configured by a P-channel MOSFET. The switches 3D and 3E are connected in parallel to configure an analog switch. A plurality of switches 3D, 3E (analog switches) are provided corresponding to the second transistor sections 2A, respectively. The source of the switch 3D and the drain of the switch 3E are connected to the gate of the corresponding second transistor section 2A. The drain of the switch 3D and the source of the switch 3E are connected to an application terminal of the input voltage Vin. The back gates of the switches 3D, 3E are connected to the ground terminal.

[0062] When one of the switches 3B, 3C (analog switches) and the switches 3D, 3E (analog switches) is in an on state, the other is in an off state according to a signal applied to each gate of the switches 3B, 3C, 3D, 3E. When the switches 3B, 3C are in an on state and the switches 3D, 3E are in an off state, the output voltage Vout is applied to the gate of the corresponding second transistor section 2A, and the second transistor section 2A is enabled. On the other hand, when the switches 3B, 3C are in an off state and the switches 3D, 3E are in an on state, the input voltage Vin is applied to the gate of the corresponding second transistor section 2A, and the second transistor section 2A is in a full on state and disabled. When the second transistor section 2A is disabled, a predetermined voltage higher than the output voltage Vout, not limited to the input voltage Vin, may be applied to the gate of the second transistor section 2A.

[0063] According to such a configuration of the selection section 30, it is possible to use the switches 3B, 3C, 3D, and 3E, which are smaller in size than the switch 3A shown in Fig. 3A, and it is possible to greatly reduce the circuit area. The reason why the analog switch is configured with the switches 3B and 3C or the switches 3D and 3E is that in order to turn on the switch 3B or 3D, an input voltage Vin of 2Vth or more, which is the sum of the Vth of the second transistor section 2A and the Vth of the switch 3B or 3D, is required, but by providing the switch 3C or 3E configured by a P-channel MOSFET, it is possible to turn on the switch 3C or 3E during reduced power and operate it at 1Vth.

[0064] Also, a switch may be provided for each of the plurality of first transistor sections 1A (depletion type) as shown in FIG. 7, for switching whether the voltage Vdep or the input voltage Vin is applied to the gate of the first transistor section 1A.

[0065] <Soft start function> FIG. 10 is a diagram showing the configuration of a constant voltage generating circuit 11Y according to a modified example of the configuration shown in FIG. 3A. The constant voltage generating circuit 11Y is provided with capacitors C1, C2, and C3. One end of the capacitor C1 is connected to the source of the third transistor section 1B, and the other end is connected to the ground terminal. One end of the capacitor C2 is connected to the application terminal of the voltage Vdep, and the other end is connected to the ground terminal. One end of the capacitor C3 is connected to the application terminal of the output voltage Vout, and the other end is connected to the ground terminal. The constant voltage generating circuit 11Y is also provided with a logic circuit 5 that controls the on / off of the switch 3A in the selection section 3. The logic circuit 5 functions as a soft start control section.

[0066] The constant voltage generating circuit 11Y has the following soft start function. The soft start function will be described with reference to the flowchart shown in Fig. 11. Note that Fig. 11 shows an operation in which all second transistor sections 2A (enhancement type) are enabled in a normal state as an example.

[0067] First, when the input voltage Vin is applied, all the switches 3A are turned on by the logic circuit 5 as an initial state (step S1). Therefore, all the second transistor sections 2A are disabled.

[0068] Then, the logic circuit 5 turns off the switch 3A corresponding to the second transistor portion 2A with a gate length of 1 μm, and enables the second transistor portion 2A (step S2). Thereafter, the logic circuit 5 similarly turns off the switches 3A corresponding to the second transistor portions 2A with gate lengths of 2 μm, 4 μm, 8 μm, 16 μm, and 32 μm in sequence, and enables the second transistor portions 2A in sequence (steps S3 to S7).

[0069] As a result, the Vgs of the enabled second transistor section 2A appear in the output voltage Vout in sequence, thereby achieving a soft start of the output voltage Vout. Also, by enabling the second transistor section 2A in sequence starting from the second transistor section 2A with the shortest gate length as described above, the second transistor section 2A with the smallest Vgs can be enabled in sequence, allowing a more effective soft start.

[0070] Here, Fig. 12 is a waveform diagram showing an example of the behavior of the output voltage Vout when the input voltage Vin is applied under each condition. The output voltage Vout_A shows the behavior when the capacitors C1, C2, and C3 described above are provided in the configuration of Fig. 3A and the capacitances of the capacitors C1, C2, and C3 are relatively small. The output voltage Vout_A overshoots the steady-state voltage of 0.9V and then converges to the steady-state voltage.

[0071] The output voltage Vout_B shows the behavior when the capacitances of the capacitors C1, C2, and C3 are relatively large when the capacitors C1, C2, and C3 are provided in the configuration of Fig. 3A. The output voltage Vout_B can suppress overshoot compared to the output voltage Vout_A, but the circuit area is larger.

[0072] The output voltage Vout_C shows the behavior when the capacitances of the capacitors C1, C2, and C3 are relatively small in the configuration having the soft start function of Fig. 10. In this way, the output voltage Vout_C can suppress overshoot while reducing the circuit area. Note that the output voltage Vout_D shows the behavior when the capacitances of the capacitors C1, C2, and C3 are relatively large in the configuration having the soft start function of Fig. 10.

[0073] Fig. 13 is a diagram showing the configuration of a constant voltage generating circuit 11Z according to a modified example of the configuration shown in Fig. 7. In this configuration, similarly to the configuration shown in Fig. 10 described above, capacitors C1, C2, and C3 are provided, and a logic circuit 5 that controls the on / off of a switch 3A is provided.

[0074] The constant voltage generating circuit 11Z has the following soft start function. The soft start function will be described with reference to the flowchart shown in Fig. 14. Note that Fig. 14 shows, as an example, an operation in a normal state in which, of first transistor sections 1A (depletion type) with gate lengths of 1.25 µm, 2.5 µm, 5 µm, 10 µm, 20 µm, and 40 µm, the first transistor sections 1A with gate lengths of 2.5 µm, 5 µm, and 40 µm are enabled.

[0075] First, when the input voltage Vin is applied, all the switches 3A are turned off by the logic circuit 5 as an initial state (step S11). Therefore, all the first transistor sections 1A are enabled.

[0076] Then, the logic circuit 5 turns on the switch 3A corresponding to the first transistor portion 1A having a gate length of 1.25 μm, thereby disabling the first transistor portion 1A (step S12). Thereafter, the logic circuit 5 similarly turns on the switches 3A corresponding to the first transistor portions 1A having gate lengths of 10 μm and 20 μm, thereby disabling the first transistor portions 1A, respectively (steps S13 and S14).

[0077] This allows for a soft start of the output voltage Vout to be achieved by gradually increasing the current flowing through the first transistor stage 1 from the initial state. Also, by disabling the first transistor sections 1A in order from the smallest gate length as described above, the first transistor sections 1A in order from the smallest resistance can be disabled, enabling a more effective soft start.

[0078] In the soft start of this embodiment, the second transistor section 2A or the first transistor section 1A may be switched between enabled and disabled using the above-mentioned switches 3B and 3C.

[0079] <Other> In addition to the above-mentioned embodiment, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-mentioned embodiment, but should be understood to include all modifications that fall within the meaning and scope equivalent to the scope of the claims.

[0080] <Additional Notes> As described above, the constant voltage generating circuit (11) according to one aspect of the present disclosure has: A first transistor stage (1) having one or a plurality of first transistor sections (1A) connected in series, each of which is configured as a depletion-mode N-channel MOSFET; a second transistor stage (2) having one or a plurality of second transistor sections (2A) connected in series, each of which is configured as an N-channel MOSFET, and connected to a low potential side of the first transistor stage; a selection unit (3) configured to select a transistor unit to be enabled from at least one of the plurality of first transistor units and the plurality of second transistor units; an output terminal (Tout) connected to the gate of the second transistor portion and configured to output an output voltage (Vout); Equipped with The gates of all the first transistor sections in the first transistor stage are connected to the sources of the first transistor sections on the lowest potential side (first configuration).

[0081] According to this configuration, the selection section selects the transistor section, thereby adjusting the gate length and improving the temperature characteristic of the output voltage.

[0082] In the first configuration, the selection section may have a switch (3A) configured to switch whether the transistor section is bypassed or not (second configuration).

[0083] In addition, the second configuration may further include a selection signal generating section (4) configured to generate a first selection signal (S1) to be output to the control terminal of the switch (third configuration).

[0084] Furthermore, in the above third configuration, the selection signal generating unit may have a fuse (4C) and a resistor (4D) connected in series between a power supply voltage (Vin) and a ground terminal, an inverter (4B) configured to receive a second selection signal (S2) output from a node to which the fuse and the resistor are connected, and an OR circuit (4A) including a first input terminal to which the output of the inverter is input and a second input terminal to which a third selection signal (S3) is input, and the first selection signal may be output from the OR circuit (fourth configuration).

[0085] In the first configuration, the selection unit (3) has a unit circuit (31) configured to switch whether to bypass the transistor unit, The unit circuit may have a fuse (31A) and a switch (31B) connected in series between the main electrodes (between the drain and source) of the transistor portion (2A) (fifth configuration).

[0086] In any one of the first to fifth configurations, the gate length of each of the transistor units selectable by the selection unit is 2 n Alternatively, the thickness may be 1 μm (sixth configuration), where n is an integer from 0 to m.

[0087] In any one of the first to sixth configurations, at least one of the transistor sections selectable by the selection section may be configured with transistors connected in parallel (seventh configuration).

[0088] Furthermore, in any of the first to seventh configurations, a third transistor section (1B) configured as a depletion-type N-channel MOSFET having a source connected to the drain of the first transistor section (1A) on the highest potential side, a gate connected to the gate of the first transistor section, and a drain connected to an application terminal for an input voltage (Vin) (eighth configuration).

[0089] In addition, in any of the above first to eighth configurations, a configuration may be made which further includes a MOS transistor (M3) configured as an N-channel MOSFET having a drain connected to the drain of the first transistor section on the highest potential side, a gate connected to the source of the first transistor section on the lowest potential side, and a source connected to the output terminal (ninth configuration).

[0090] In the ninth configuration, the MOS transistor may be of the depletion type (tenth configuration).

[0091] In addition, in the ninth or tenth configuration, the circuit may further include a constant current source (CI) connected to the source of the MOS transistor (eleventh configuration).

[0092] In the eleventh configuration, the constant current source may be configured as an active load having an active element (twelfth configuration).

[0093] In the twelfth configuration, the active element may be a depletion-type N-channel MOSFET (M4) whose gate and source are short-circuited (thirteenth configuration).

[0094] Further, one aspect of the present disclosure is a method for selecting the transistor unit by the selection unit in the constant voltage generating circuit of any one of the first to thirteenth configurations, comprising: a first step of measuring the output voltage; a second step of measuring a drain current through the first transistor stage; a third step of determining a gate length based on the measurement results of the output voltage and the drain current and a table map; Including, The table map has axes of the output voltage and the drain current, and a characteristic line for each gate length is defined in the table map (fourteenth configuration).

[0095] In the fourteenth configuration, the constant voltage generating circuit comprises: a first MOS transistor configured as an N-channel MOSFET having a drain connected to the drain of the first transistor section on the highest potential side, a gate connected to the source of the first transistor section on the lowest potential side, and a source connected to the output terminal; a second MOS transistor configured as a depletion-type N-channel MOSFET having a drain connected to the source of the third transistor and having a gate-source short-circuited; In the second step, a voltage higher than the measured output voltage may be applied from outside to the output terminal, and the drain current flowing through the second MOS transistor may be measured to estimate the drain current flowing through the first transistor stage (15th configuration).

[0096] In addition, in any of the first to thirteenth configurations, the selection unit (30) may be configured to have switches (3B, 3C) configured to switch the voltage to be applied to the gate of the transistor unit to enable or disable the transistor unit (a sixteenth configuration).

[0097] In the sixteenth configuration, the switch may be configured by connecting an N-channel MOSFET and a P-channel MOSFET in parallel (seventeenth configuration).

[0098] Furthermore, in any of the first to thirteenth, sixteenth, and seventeenth configurations, a configuration may be provided in which a soft-start control section (5) is configured to disable all of the second transistor sections (2A) as an initial state when the constant voltage generating circuit (11Y) is started up, and then sequentially enable the second transistor sections to be enabled (an eighteenth configuration).

[0099] In the eighteenth configuration, the soft-start control section may be configured to enable the second transistor sections in order starting from the second transistor section having the shortest gate length (a nineteenth configuration).

[0100] Furthermore, in any of the first to thirteenth, sixteenth, and seventeenth configurations, a configuration may be provided in which a soft-start control section (5) is configured to enable all of the first transistor sections (1A) as an initial state when the constant voltage generating circuit (11Z) is started, and then sequentially disable the first transistor sections to be disabled (a twentieth configuration).

[0101] In the twentieth configuration, the soft-start control section may be configured to disable the first transistor sections in order starting from the first transistor section having the shortest gate length (twenty-first configuration). [Industrial Applicability]

[0102] The present disclosure can be used in constant voltage generating circuits for various purposes. [Explanation of symbols]

[0103] 1 First transistor stage 1A 1st transistor section 1B 3rd transistor section 2 Second transistor stage 2A 2nd transistor section 3 Selection section 3A, 3B, 3C, 3D, 3E Switches 30 Selection section 31 Unit Circuit 31A fuse 31B Switch 4. Selection signal generator 4A OR circuit 4B Inverter 4C Fuse 4D resistance 5 Logic Circuits 11, 11X, 11Y, 11Z, 100 Constant voltage generation circuit C1, C2, C3 capacitors CI constant current source LD load M1~M4 Transistors Tout output end

Claims

1. a first transistor stage having one or a plurality of first transistor portions connected in series, each of the first transistor portions being configured as a depletion-mode N-channel MOSFET; a second transistor stage having one or a plurality of second transistor sections connected in series, the second transistor section being configured as an N-channel MOSFET, the second transistor stage being connected to a low potential side of the first transistor stage; a selection unit configured to select a transistor unit to be enabled from at least one of the plurality of first transistor units and the plurality of second transistor units; an output terminal connected to a gate of the second transistor portion and configured to output an output voltage; Equipped with A constant voltage generating circuit, wherein the gates of all the first transistor sections in the first transistor stage are connected to the sources of the first transistor sections on the lowest potential side.

2. The constant voltage generating circuit according to claim 1 , wherein the selection section includes a switch configured to switch whether the transistor section is bypassed or not.

3. The constant voltage generating circuit according to claim 2 , further comprising a selection signal generating unit configured to generate a first selection signal to be output to a control end of the switch.

4. The selection signal generation unit A fuse and a resistor connected in series between the power supply voltage and a ground terminal; an inverter configured to receive a second selection signal output from a node to which the fuse and the resistor are connected; an OR circuit including a first input terminal to which the output of the inverter is input and a second input terminal to which a third selection signal is input; having 4. The constant voltage generating circuit according to claim 3, wherein the first selection signal is output from the OR circuit.

5. the selection unit has a unit circuit configured to switch whether the transistor unit is bypassed or not, 2. The constant voltage generating circuit according to claim 1, wherein the unit circuit includes a fuse and a switch connected in series between main electrodes of the transistor portion.

6. The gate length of each of the transistor units selectable by the selection unit is 2 ｎ 2. The constant voltage generating circuit according to claim 1, wherein n is an integer from 0 to m.

7. 2. The constant voltage generating circuit according to claim 1, wherein at least one of the transistor sections selectable by the selection section is composed of transistors connected in parallel.

8. 2. The constant voltage generating circuit according to claim 1, further comprising a third transistor section configured as a depletion-type N-channel MOSFET having a source connected to the drain of the first transistor section on the highest potential side, a gate connected to the gate of the first transistor section, and a drain connected to an application terminal for an input voltage.

9. 2. The constant voltage generating circuit according to claim 1, further comprising a MOS transistor configured as an N-channel MOSFET having a drain connected to a drain of the first transistor section on the highest potential side, a gate connected to a source of the first transistor section on the lowest potential side, and a source connected to the output terminal.

10. 10. The constant voltage generating circuit according to claim 9, wherein the MOS transistor is a depletion type.

11. 10. The constant voltage generating circuit according to claim 9, further comprising a constant current source connected to the source of the MOS transistor.

12. The constant voltage generating circuit according to claim 11 , wherein the constant current source is configured as an active load having an active element.

13. 13. The constant voltage generating circuit according to claim 12, wherein the active element is a depletion-type N-channel MOSFET having a gate and a source shorted therebetween.

14. 14. A method for selecting the transistor unit by the selection unit in the constant voltage generating circuit according to claim 1, comprising the steps of: a first step of measuring the output voltage; a second step of measuring a drain current through the first transistor stage; a third step of determining a gate length based on the measurement results of the output voltage and the drain current and a table map; Including, The selection method, wherein the table map has axes of the output voltage and the drain current, and a characteristic line for each gate length is defined in the table map.

15. The constant voltage generating circuit includes: a first MOS transistor configured as an N-channel MOSFET having a drain connected to the drain of the first transistor section on the highest potential side, a gate connected to the source of the first transistor section on the lowest potential side, and a source connected to the output terminal; a second MOS transistor having a drain connected to the source of the first MOS transistor and configured as a depletion-type N-channel MOSFET with a gate and a source shorted; 15. The selection method according to claim 14, wherein in the second step, a voltage higher than the measured output voltage is applied from the outside to the output terminal, and a drain current flowing through the second MOS transistor is measured to estimate the drain current flowing through the first transistor stage.

16. The constant voltage generating circuit according to claim 1 , wherein the selection section includes a switch configured to switch a voltage to be applied to a gate of the transistor section in order to enable or disable the transistor section.

17. 17. The constant voltage generating circuit according to claim 16, wherein the switch is configured by connecting an N-channel MOSFET and a P-channel MOSFET in parallel.

18. 2. The constant voltage generation circuit according to claim 1, further comprising a soft-start control unit configured to disable all of the second transistor units as an initial state when the constant voltage generation circuit is started, and then sequentially enable the second transistor units to be enabled.

19. 20. The constant voltage generating circuit according to claim 18, wherein the soft-start control section sequentially enables the second transistor sections in ascending order of gate length.

20. 2. The constant voltage generation circuit according to claim 1, further comprising a soft-start control unit configured to enable all of the first transistor units as an initial state when the constant voltage generation circuit is started, and then sequentially disable the first transistor units to be disabled.

21. 21. The constant voltage generating circuit according to claim 20, wherein the soft-start control section sequentially disables the first transistor section having the shortest gate length.

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