Semiconductor device

Abstract

To provide a semiconductor device having a transistor with excellent electric characteristics, in a semiconductor device having an oxide semiconductor film.SOLUTION: Provided is a semiconductor device having a transistor. The transistor has a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. Each of the source electrode and the drain electrode has a first conductive film, a second conductive film provided on and in contact with the first conductive film, and a third conductive film provided on and in contact with the second conductive film. The second conductive film contains copper. The first conductive film and the third conductive film contain a material that suppresses diffusion of copper. An end part of the second conductive film has a region containing copper and silicon.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film, This relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. Therefore, the technical field of one embodiment of the present invention disclosed in the present specification more specifically relates to Examples of the semiconductor device include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, etc. Examples of the present invention include a device, an imaging device, a driving method thereof, or a manufacturing method thereof. This can be done.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (thin film transistor (TFT) or The technology of constructing a field effect transistor (FET) has been attracting attention. Transistors are widely used in electronic devices such as integrated circuits (ICs) and imaging devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor films that can be used in transistors. As another material, oxide semiconductors are attracting attention.

[0005] For example, a transistor is fabricated using an In-Ga-Zn oxide as an oxide semiconductor. A technique for doing this has been disclosed (see, for example, Patent Document 1).

[0006] In addition, aluminum has traditionally been widely used as a material for wiring and signal lines. However, in order to further reduce the resistance, development using copper (Cu) is actively underway. However, copper (Cu) has poor adhesion to the underlying film and is used as a semiconductor material for transistors. However, it has a drawback that it is likely to diffuse into the body film and deteriorate the transistor characteristics.

[0007] In addition, the ohmic electrode formed on the oxide semiconductor film containing indium can be made of A Cu-Mn alloy has been disclosed (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2007-96055 A [Patent Document 2] International Publication No. 2012 / 002573 Summary of the Invention [Problem to be solved by the invention]

[0009] According to the configuration described in Patent Document 2, a Cu-Mn alloy film is deposited on an oxide semiconductor film. Thereafter, the Cu-Mn alloy film is subjected to a heat treatment to bond the oxide semiconductor film and the Cu-Mn alloy film. Mn oxide is formed at the interface between the Cu-Mn alloy film and the Mn oxide. The oxygen diffuses toward the conductive film and preferentially bonds with the oxygen that constitutes the oxide semiconductor film. In addition, the region in the oxide semiconductor film that is reduced by Mn becomes an oxygen vacancy, and the carrier The Mn concentration increases and the film has high conductivity. By turning the Mn alloy into pure Cu, an ohmic electrode with low electrical resistance is obtained.

[0010] However, in the above-mentioned configuration, after the ohmic electrode is formed, For example, the effect of Cu diffusion from the oxide semiconductor film is not taken into consideration. After forming an electrode including a gold film, a heat treatment is performed to form an oxide semiconductor film and a Cu-Mn alloy. Mn oxide is formed at the bonding interface with the gold film. The formation of the Mn oxide reduces the oxidation This suppresses the diffusion of Cu from the Cu-Mn alloy film in contact with the oxide semiconductor film into the oxide semiconductor film. Even if the Cu-Mn alloy film is heated, the Mn in the film and the sides of the film may be removed and the pure Mn may be lost. Cu re-adheres to the surface of the oxide semiconductor film from the side or surface of the Cu film. .

[0011] For example, when a transistor using an oxide semiconductor film has a bottom gate structure, A part of the surface of the oxide semiconductor film is a so-called back channel side. When Cu is redeposited, the electrical characteristics of the transistor (e.g., on-current, field-effect mobility, There is also the problem of deterioration of the gate resistance, which is one of the reliability tests for transistors. There was a problem with the BT stress test, in which the transistor characteristics deteriorated.

[0012] In view of the above-described problems, in one embodiment of the present invention, a transistor including an oxide semiconductor film is provided with copper. Another object of the present invention is to provide a novel semiconductor device using a conductive film having a In one embodiment of the present invention, a conductive film containing copper is used for a transistor including an oxide semiconductor film. , and transistors with excellent electrical characteristics (e.g., on-current, field-effect mobility, frequency characteristics, etc.) Another object of the present invention is to provide a semiconductor device having A conductive film containing copper is used for a transistor including an oxide semiconductor film, and fluctuation in electrical characteristics is reduced. It is an object of the present invention to provide a semiconductor device having a transistor in which the noise generated by the semiconductor device is suppressed. In one embodiment of the present invention, a conductive film containing copper is used for a transistor including an oxide semiconductor film. It is an object of the present invention to provide a semiconductor device having a highly reliable transistor. Alternatively, in one embodiment of the present invention, a copper-containing transistor is provided in a transistor including an oxide semiconductor film. It is an object of the present invention to provide a semiconductor device using a conductive film, the manufacturing cost of which is reduced. In one embodiment of the present invention, a transistor including an oxide semiconductor film is provided with a conductive film having copper. Another object of the present invention is to provide a semiconductor device with high productivity by using a film. An object of one embodiment of the present invention is to provide a novel semiconductor device. An object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0013] Note that the above description of the object does not preclude the existence of other objects. It is not necessary to solve all of these problems. Problems other than those mentioned above can be solved by the description of the specification, etc. It is obvious from the description of the specification that other problems can be extracted. do. [Means for solving the problem]

[0014] One embodiment of the present invention is a semiconductor device including a transistor. a first insulating film on the gate electrode, and a second insulating film overlapping the gate electrode with the first insulating film sandwiched therebetween. a source electrode electrically connected to the oxide semiconductor film; A drain electrode electrically connected to the oxide semiconductor film, a source electrode on the oxide semiconductor film, and a second insulating film on the source electrode and the drain electrode, The ends of the source electrode and the drain electrode are made of copper and silicon, respectively. The semiconductor device has a region including

[0015] Another embodiment of the present invention is a semiconductor device including a transistor. The transistor has a gate electrode, a first insulating film on the gate electrode, and a gate insulating film sandwiched between the gate electrode and the first insulating film. An oxide semiconductor film having a region overlapping with an electrode and a source electrically connected to the oxide semiconductor film. a drain electrode electrically connected to the oxide semiconductor film; and a second insulating film on the source electrode and the drain electrode. The electrodes each have copper, and the ends of the source electrode and the drain electrode each have copper and silver. The semiconductor device has a region having a compound including a silicon.

[0016] In each of the above configurations, the end of the source electrode and the end of the drain electrode are each connected to the second insulating layer. It is preferred that the membrane has an area in contact with the membrane.

[0017] Another embodiment of the present invention is a semiconductor device including a transistor. The transistor has a gate electrode, a first insulating film on the gate electrode, and a gate insulating film sandwiched between the gate electrode and the first insulating film. An oxide semiconductor film having a region overlapping with an electrode and a source electrically connected to the oxide semiconductor film. a drain electrode electrically connected to the oxide semiconductor film; and a second insulating film on the source electrode and the drain electrode. The electrodes are each made of a first conductive film, a second conductive film in contact with the first conductive film, and a second conductive film and a third conductive film in contact with the upper surface of the first conductive film, the second conductive film having copper, and the first conductive film and the third conductive film having copper. The conductive film has a material that suppresses the diffusion of copper, and the end of the second conductive film is made of copper and silicon. The semiconductor device has a region including

[0018] Another embodiment of the present invention is a semiconductor device including a transistor. The transistor has a gate electrode, a first insulating film on the gate electrode, and a gate insulating film sandwiched between the gate electrode and the first insulating film. An oxide semiconductor film having a region overlapping with an electrode and a source electrically connected to the oxide semiconductor film. a drain electrode electrically connected to the oxide semiconductor film; and a second insulating film on the source electrode and the drain electrode. The electrodes are each made of a first conductive film, a second conductive film in contact with the first conductive film, and a second conductive film and a third conductive film in contact with the upper surface of the first conductive film, the second conductive film having copper, and the first conductive film and the third conductive film having copper. The conductive film has a material that suppresses the diffusion of copper, and the end of the second conductive film is made of copper and silicon. The semiconductor device has a region having a compound containing the compound.

[0019] In each of the above structures, it is preferable that an end portion of the second conductive film has a region in contact with the second insulating film. I wish.

[0020] In each of the above structures, the first conductive film and the third conductive film are made of titanium or tungsten. It is preferable that the first conductive film and the second conductive film have at least one of tantalum and molybdenum. The third conductive film has an oxide, and the oxide has at least one of In and Zn. It is preferable to do so.

[0021] In each of the above structures, the oxide semiconductor film is made of In, Zn, and M (M is Al, G In addition, the oxide semiconductor film preferably has a crystalline portion. It is preferable that the crystal portion has a c-axis orientation.

[0022] Another embodiment of the present invention is a display device including the semiconductor device of any of the above embodiments and a display element. Another aspect of the present invention is a display device having the display device of the above aspect and a touch sensor. Another aspect of the present invention is a semiconductor device according to any one of the above aspects. A display device according to the above embodiment, or a display module according to the above embodiment, and at least one of an operation key and a battery. It is an electronic device having a single function. Effect of the Invention

[0023] According to one embodiment of the present invention, a conductive film containing copper is formed on a transistor including an oxide semiconductor film. According to one embodiment of the present invention, a novel semiconductor device using an oxidized A conductive film containing copper is used for a transistor using a semiconductor film, and the electrical characteristics (e.g., To provide a semiconductor device having transistors with excellent characteristics (e.g., switching current, field-effect mobility, frequency characteristics, etc.) According to one embodiment of the present invention, a transistor including an oxide semiconductor film can be provided. The transistor has a copper-containing conductive film and a fluctuation in electrical characteristics is suppressed. According to one embodiment of the present invention, a semiconductor device including an oxide semiconductor film can be provided. A conductive film containing copper is used for the transistor to have high reliability. According to one embodiment of the present invention, a semiconductor device including an oxide semiconductor film can be provided. A semiconductor device in which a conductive film containing copper is used for a transistor, and manufacturing costs are reduced. According to one embodiment of the present invention, a transistor using an oxide semiconductor film can be provided. By using a conductive film containing copper for a transistor, a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. It is not necessary to have all of these effects. Effects other than these are described in the specification. The disclosure of the specification, drawings, claims, etc. is self-evident, and the disclosure of the specification, drawings, claims, etc. is self-evident. From this, it is possible to extract other effects. [Brief description of the drawings]

[0025] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 5] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 7]FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 8] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 9] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 10] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 11] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 19] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 20] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 21] FIG. 1 illustrates a range of atomic ratios of an oxide semiconductor according to one embodiment of the present invention. [Figure 22] A diagram explaining the InMZnO4 crystal. [Diagram 23] FIG. 1 is a band diagram of a stacked structure of oxide semiconductors. [Figure 24] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Diagram 25] Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Figure 26] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 27]Cross-sectional TEM image of a-like OS. [Figure 28] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 29] FIG. 1 is a top view illustrating one embodiment of a display device. [Diagram 30] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 31] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 32] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 33] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 34] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 35] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 36] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 37] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 38] 1A and 1B are graphs and circuit diagrams illustrating one embodiment of the present invention. [Figure 39] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 40] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 41] 1A to 1C are a block diagram, a circuit diagram, and waveform diagrams illustrating one embodiment of the present invention. [Diagram 42] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 43] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 44] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 45] FIG. 2 is a diagram illustrating a display module. [Diagram 46] 1A to 1C are diagrams illustrating electronic devices. [Figure 47] 1A to 1C are diagrams illustrating electronic devices. [Figure 48] FIG. 1 is a perspective view illustrating a display device. [Figure 49] 1A and 1B are a cross-sectional view and a circuit diagram illustrating a structure of a semiconductor device of one embodiment of the present invention. [Figure 50] FIG. 1 is a block diagram illustrating a configuration of a CPU according to one embodiment of the present invention. [Figure 51] FIG. 1 is a circuit diagram illustrating a configuration of a memory element according to one embodiment of the present invention. [Figure 52] FIG. 1 is a circuit diagram showing an example of an imaging device. [Figure 53] FIG. 1 is a diagram showing an example of the configuration of an imaging apparatus. [Figure 54] FIG. 2 is a view for explaining a STEM photograph of a sample in the embodiment. [Figure 55] FIG. 2 is a diagram illustrating the results of XPS analysis of a sample according to an embodiment. [Figure 56] FIG. 2 is a diagram illustrating the results of XPS analysis of a sample according to an embodiment. [Figure 57] 4 shows the Id-Vg characteristics of a transistor according to an embodiment. [Figure 58] 4 shows the Id-Vg characteristics of a transistor according to an embodiment. [Figure 59] FIG. 2 is a view for explaining a STEM photograph of a sample in the embodiment. [Figure 60] FIG. 13 is a diagram illustrating the results of EDX analysis of a sample according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above description, and the embodiments and details thereof are not limited to those described above without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the embodiments described below. The terms of the present disclosure are not to be construed as being limited to the content.

[0027] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily shown in order to facilitate understanding. The actual position, size, range, etc. may not be shown. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc.

[0028] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. In some cases, the order of steps or layers may not be indicated. For example, "first" may be replaced with "second" or " " can be appropriately replaced with "the third" etc. The ordinal numbers used to identify an aspect of the present invention may not match those used in the present invention. be.

[0029] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used. The relationship is used for convenience in describing the drawings. The terms change depending on the direction in which each component is depicted. It can be rephrased appropriately depending on the situation.

[0030] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, The reference numerals are used commonly among different drawings.

[0031] In addition, even when the term "semiconductor" is used in this specification, for example, If the electrical conductivity is low enough, the material may have the properties of an insulator. The boundary between "insulators" and "insulators" is unclear, and it may not be possible to strictly distinguish them. In some cases, the term "semiconductor" in the above can be replaced with "insulator." In some cases, the term "insulator" in the specification can be replaced with "semiconductor." In some cases, the term "insulator" in this specification can be rephrased as "semi-insulator." .

[0032] In addition, even when the term "semiconductor" is used in this specification, for example, If the electrical conductivity is high enough, it may have the properties of a "conductor". The boundary between the term "conductor" and the term "electrical conductor" is unclear, and it may not be possible to strictly distinguish between them. In some cases, the term "semiconductor" in the above can be replaced with "conductor." The term "conductor" in the specification etc. may be replaced with "semiconductor" in some cases.

[0033] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. In this specification and the like, the channel region is a region through which a current mainly flows. This refers to.

[0034] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably.

[0035] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). The source region or the channel region This refers to the distance between the drain (drain region or drain electrode) and the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one of the values, maximum The value may be the minimum or average value.

[0036] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the electrode (the area where the current flows) forms a channel. This refers to the length of the part of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. That is, The channel width of a transistor may not be determined to a single value. In the fine print, the channel width is any one of the values ​​in the region where the channel is formed, the maximum The value may be the minimum or average value.

[0037] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0038] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, voltage can be replaced with electric potential. be.

[0039] In this specification and the like, a silicon oxynitride film is a film having a composition containing more oxygen than nitrogen. It refers to a film with a high content of oxygen, preferably 55 atomic % to 65 atomic % and 1 % to 20 atomic %, silicon is 25 atomic % to 35 atomic %, hydrogen is 0.1 atomic % The silicon oxide nitride film is a film containing silicon dioxide in the range of 10 atomic % or more. The nitrogen content is preferably 55 atomic % or more and 65 atomic % or less. % or less, oxygen is 1 atomic % to 20 atomic %, silicon is 25 atomic % to 35 atomic % Hereinafter, this refers to a film containing hydrogen in a concentration range of 0.1 atomic % or more and 10 atomic % or less.

[0040] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to:

[0041] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that the two straight lines are arranged at an angle of -30° to 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it includes the case where the angle is between 85° and 95°. " refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0042] In addition, in this specification and the like, when the crystal is a trigonal or rhombohedral crystal, it is referred to as a hexagonal crystal system. represent.

[0043] (Embodiment 1) In this embodiment, a semiconductor device and a manufacturing method of the semiconductor device according to one embodiment of the present invention will be described. This will be described below with reference to FIGS. 1 to 20.

[0044] <1-1. Configuration example 1 of semiconductor device> FIG. 1A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. FIG. 1B is a cross-sectional view taken along the dashed line X1-X2 in FIG. FIG. 1C is a cross section taken along the dashed line Y1-Y2 in FIG. 1A. In FIG. 1A, for clarity, the components of the transistor 100 are shown. 1, some of the elements (such as the substrate 102 and the insulating film) are omitted.

[0045] The direction of the dashed line X1-X2 in FIG. 1A corresponds to the channel length of the transistor 100. The direction of the dashed line Y1-Y2 may be referred to as the channel width direction of the transistor 100. be.

[0046] The transistor 100 includes a conductive film 104 over a substrate 102, which functions as a gate electrode, and a An insulating film 106 on the plate 102 and the conductive film 104, and an insulating film 107 on the insulating film 106, The oxide semiconductor film 108 over the film 107 and a pair of oxide semiconductor films 108 electrically connected to the oxide semiconductor film 108 the conductive films 112a and 112b which function as electrodes, The insulating film 114 and the insulating film 116 on the insulating film 112a and the insulating film 112b, 8 and,

[0047] The oxide semiconductor film 108 is made of indium (In), zinc (Zn), and M (M is aluminum). Al, Ga, Y, or Sn) It is preferable to have the following:

[0048] In the transistor 100, the insulating films 106 and 107 are In the transistor 100, the pair of electrodes and The conductive films 112a and 112b function as a source electrode and a drain electrode. has a function as a drain electrode.

[0049] The conductive film 112a includes a conductive film 112a_1 and a conductive film 112a_2 in contact with the conductive film 112a_1. a conductive film 112a_3 in contact with the conductive film 112a_2; The film 112b is a conductive film 112b_1 and a conductive film 112b_2 in contact with the conductive film 112b_1. 2 and a conductive film 112b_3 on and in contact with the conductive film 112b_2. The conductive film 112a_2 has a region 112a_2a and a region 112a_2b. 2b_2 has a region 112b_2a and a region 112b_2b.

[0050] The conductive film 112a_2 and the conductive film 112b_2 each contain copper, and the region 112a_2 The conductive film 112a_1, the conductive film 112b_2, and the conductive film 112b_3 are made of copper and silicon. The conductive film 112a_3, the conductive film 112b_1, and the conductive film 112b_3 are each formed by diffusing copper. The region 112a_2b includes a material that suppresses the The region 112b_2b has a region in contact with the insulating film 114. The conductive film 112a_1 is located at the end of the insulating film 114. The conductive film 112b_1 has an area located outside the end of the conductive film 112a_2. , the conductive film 112a_ has a region located outside the end of the conductive film 112b_2. 3 covers the upper surface of the conductive film 112a_2, and the conductive film 112b_3 covers the upper surface of the conductive film 112b_2. Therefore, the conductive film 112a_2a covers the upper surface of the conductive film 112a_1, the region 112a _2b and a conductive film 112a_3. The conductive film 112b_2a is a conductive The structure is covered with a film 112b_1, a region 112b_2b, and a conductive film 112b_3. .

[0051] The regions 112a_2b and 112b_2b are made of copper silicide. Since copper silicide has a bond between copper and silicon, it is preferable to form a copper silicide having a higher conductivity than copper. The insulating film 114 is stable and has a function of suppressing copper from diffusing to the outside. When the region 112a_2b and the region 112b_2b include silicon, the region 112a_2b and the region 112b_2b include copper and silicon. This has the effect of increasing the adhesion between the conductive films 112a_2 and 112b_2 and the insulating film 114. It plays a key role.

[0052] In addition, the regions 112a_2b and 112b_2b may contain copper, silicon, and nitrogen. Alternatively, copper silicide nitride may be formed. 2b, 112b_2b have copper silicide nitride, so copper diffuses outward. This can be suppressed.

[0053] The conductive film 112a and the conductive film 112b are a conductive film 112a_2 containing copper and a conductive film 112b containing copper, respectively. By providing the film 112b_2, it is possible to reduce the resistance of the conductive films 112a and 112b. In addition, by configuring the conductive films 112a and 112b as described above, the copper element is 2a and 112b, particularly into the oxide semiconductor film 108. Therefore, a semiconductor device having a transistor with excellent electrical characteristics can be provided. It can be provided.

[0054] <1-2. Configuration example 2 of semiconductor device> Next, examples of a configuration different from that of the transistor 100 shown in FIGS. 2 to 11. Note that in the following FIGS. 2 to 11, transistor 1 If a part has the same function as 00, the hatch pattern will be the same and no code will be added. There is a match.

[0055] FIG. 2A is a top view of a transistor 100A which is a semiconductor device of one embodiment of the present invention. FIG. 2(B) corresponds to a cross-sectional view taken along the dashed line X1-X2 in FIG. 2(A). FIG. 2(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 2(A). Equivalent.

[0056] The transistor 100A includes a conductive film 100A functioning as a first gate electrode on a substrate 102. 4, an insulating film 106 on the substrate 102 and the conductive film 104, and an insulating film 107 on the insulating film 106. The oxide semiconductor film 108 over the insulating film 107 and the insulating film 108 electrically connected to the oxide semiconductor film 108 are The conductive films 112a and 112b function as a pair of electrodes connected to the oxide semiconductor film 108 and the and an insulating film 114 and an insulating film 116 on the conductive films 112a and 112b. The conductive film 112a is exposed through an opening 152c formed in the insulating films 114 and 116. , a conductive film electrically connected to one of the conductive films 112b (conductive film 112b in FIG. 2(B)). 120a, and a conductive film 120 that is provided on the insulating film 116 and functions as a second gate electrode. b, and an insulating film 118 on the insulating film 116 and the conductive films 120a and 120b.

[0057] In the transistor 100A, the insulating films 106 and 107 are the first insulating films of the transistor 100A. The insulating films 114 and 116 function as the gate insulating film of the transistor 100A. The insulating film 118 functions as a second gate insulating film of the transistor 100A. In this specification and the like, the insulating films 106 and 107 are The first gate insulating film and the insulating films 114 and 116 may be referred to as a second gate insulating film. In the transistor 100A, the conductive film 112a and the conductive film 112b function as a pair of electrodes. 112b has one function as a source electrode and the other function as a drain electrode. In addition, the conductive film 120a functions as a pixel electrode used in a display device.

[0058] ≪s-channel structure≫ The oxide semiconductor film 108 in the transistor 100A shown in FIG. The second gate insulating film is sandwiched between the conductive film 104 and the conductive film 120b. The length of the conductive film 104 in the channel length direction and the length of the conductive film 104 in the channel width direction are determined by the thickness of the oxide semiconductor film 104. The length of the film 108 in the channel length direction and the length of the film 108 in the channel width direction are both longer than the length of the film 108 in the channel length direction and the channel width direction. The length of the conductive film 120b in the channel length direction and the length of the conductive film 120b in the channel width direction are equal to or larger than the length of the oxide semiconductor film 1 The length in the channel length direction and the length in the channel width direction of the 08 are both longer than those of the 08. The entire oxide semiconductor film 108 is formed by sandwiching the first gate insulating film and the second gate insulating film therebetween. The conductive film 104 and the conductive film 120b are covered with each other.

[0059] In other words, in the channel width direction of the transistor 100A, the conductive film 104 and the conductive The film 120b is an oxide semiconductor film sandwiching a first gate insulating film and a second gate insulating film therebetween. The composition surrounds 108.

[0060] With such a structure, the oxide semiconductor film 108 of the transistor 100A The conductive film 104 and the conductive film 120b can electrically surround the conductive film 104 and the conductive film 120b. As in the transistor 100A, the electric field of the conductive film 104 and the conductive film 120b causes the channel region The device structure of the transistor is electrically surrounding the oxide semiconductor film in which the region is formed. This can be called an unded channel (s-channel) structure.

[0061] Since the transistor 100A has an s-channel structure, the conductive film 104 and the conductive The electric field for inducing a channel is effectively applied to the oxide semiconductor film 108 by the conductive film 120b. Therefore, the current driving capability of the transistor 100A is improved. It is possible to obtain high on-current characteristics. It is also possible to increase the on-current. Therefore, it is possible to miniaturize the transistor 100A. FIG. 1A shows a structure in which the oxide semiconductor film 108 is surrounded by the conductive film 104 and the conductive film 120b. This can increase the mechanical strength of the transistor 100A.

[0062] In addition, with the above structure, carriers can flow in the oxide semiconductor film 108. The region is a region on the first gate insulating film side of the oxide semiconductor film 108 and a region on the second gate insulating film side of the oxide semiconductor film 108. Since the second gate insulating film and the oxide semiconductor film 108 are included in the wide area, The amount of carrier movement in the transistor 100A increases. As a result, As the on-current increases, the field effect mobility increases. 10cm 2 / V·s or more. Note that the field effect mobility here is This is not an approximation of the mobility as a physical property, but an estimate of the current driving force in the saturation region of a transistor. It is an index and is the apparent field-effect mobility.

[0063] In addition, as in the transistor 100B shown in FIGS. 0b may be provided on the insulating film 118. In this case, the insulating films 114, 116, and 118 In the opening 152c provided in the The top view of the transistor 100B is shown in FIG. 3A is the same as the transistor 100A shown in FIG. FIG. 3B is a cross-sectional view of the cut surface taken along the dashed line Y1 in FIG. 2A. This corresponds to a cross-sectional view taken along the line -Y2. Since the transistor 100A is similar to the transistor 100A, the configuration of the transistor 100A is taken into consideration. That's good.

[0064] In addition, in a transistor 100C shown in FIG. In the embodiment, there is a region where the end of the conductive film 112a_1 and the end of the conductive film 112a_2 are aligned. Alternatively, there may be a region where the end of the conductive film 112b_1 and the end of the conductive film 112b_2 are aligned. is also good.

[0065] In addition, as in the case of a transistor 100D shown in FIGS. 4(A), 4(B), and 4(C), The conductive film 120b, which functions as an electrode, is disposed between the first gate insulating film (insulating films 106 and 107) and the and openings 152a, 152b provided in the second gate insulating film (insulating films 114, 116). In this case, the first gate electrode 104 may be connected to the conductive film 104 which functions as the first gate electrode. Note that FIG. 4A is a top view of a transistor 100D which is a semiconductor device of one embodiment of the present invention. FIG. 4B is a cross-sectional view taken along the dashed line X1-X2 in FIG. FIG. 4C corresponds to a cross-sectional view, and is a cross-section taken along dashed line Y1-Y2 shown in FIG. 4A. In addition, as another configuration of the transistor 100D, Since the configuration of the transistor 100A is the same as that of the transistor 100A, the configuration of the transistor 100A can be taken into consideration.

[0066] In the transistor 100D, the conductive film 104 and the conductive film 120b form a first gate insulator. The insulating film and the second gate insulating film are connected at openings 152a and 152b. Therefore, the side surface of the oxide semiconductor film 108 in the channel width direction is covered with the first gate insulating film and the second gate insulating film. The conductive film 104 faces the conductive film 120b with the gate insulating film interposed therebetween. The same potential is applied to the film 120b. This effectively enables the transistor 100D. The oxide semiconductor film 108 is electrically insulated by the electric field of the conductive film 104 and the conductive film 120b. In addition, the opening 152a and the opening 152b can be surrounded by either one of them. Alternatively, only the above-mentioned second electrode 14 may be provided.

[0067] In addition, as in the case of a transistor 100E shown in FIGS. 0b may be provided on the insulating film 118. In this case, the insulating films 114, 116, and 118 In the opening 152c provided in the One of the insulating films 106, 107, 114, 116, and 118 is electrically connected to the other of the insulating films 106, 107, 114, 116, and 118. In the openings 152a and 152b, a conductive film 120b that functions as a second gate electrode is formed. The conductive film 104 serving as the first gate electrode is electrically connected to the transistor 104. The top view of the transistor 100E is similar to that of the transistor 100D shown in FIG. 5(A) corresponds to a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 4(A); FIG. 5B is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. Other configurations of the transistor 100E are similar to those of the transistor 100D. For this reason, the configuration of the transistor 100D can be taken into consideration.

[0068] In addition, as in the transistor 100F shown in FIGS. 6(A), 6(B), and 6(C), The conductive film 120b, which functions as an electrode, is connected to the conductive film 112c, which functions as a connection electrode, via the conductive film 112c. The conductive film 104 functioning as the first gate electrode may be connected to the first gate electrode. FIG. 1A is a top view of a transistor 100F which is a semiconductor device of one embodiment of the present invention. FIG. 6B is a cross-sectional view taken along the dashed line X1-X2 in FIG. FIG. 6C is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. Equivalent.

[0069] The transistor 100F shown in FIGS. 6A, 6B, and 6C is provided over an insulating film 107. At the same time, the conductive layer is formed in an opening 151 provided in the first gate insulating film (insulating films 106 and 107). The conductive film 112c is electrically connected to the insulating film 104. The conductive film 120b is 6 and an opening provided in the second gate insulating film (insulating films 114 and 116). The point where the conductive film 112c is electrically connected to the transistor 152d is different from that of the transistor 100A. become.

[0070] In the transistor 100F, the conductive film 104 and the conductive film 120b are connected to the conductive film 112c. One of the side surfaces of the oxide semiconductor film 108 in the channel width direction is electrically connected to the first The first gate insulating film and the second gate insulating film are sandwiched between the first gate insulating film and the conductive film 112c. In addition, the conductive film 104 and the conductive film 120b are given the same potential. The oxide semiconductor film 108 included in the transistor 100F is It can be electrically surrounded by the electric field of b.

[0071] On the other hand, for example, in the transistor 100A and the transistor 100B, the conductive film 104 In the case where the conductive film 104 and the conductive film 120b are not connected to each other, Each of the electrodes can be given a different potential.

[0072] In addition, either the length in the channel length direction or the length in the channel width direction of the conductive film 120b or Both of them are longer than the length in the channel length direction and the length in the channel width direction of the oxide semiconductor film 108. They don't have to be long.

[0073] The conductive film 112c can be formed in the same process as the conductive films 112a and 112b. In this case, the conductive film 112c is connected to the conductive film 112c_1. and a conductive film 112c_3 in contact with the conductive film 112c_2. The conductive film 112c_2 has a region 112c_2a and a region 112c_2b. do.

[0074] The conductive film 112c_2 contains copper, and the region 112c_2b contains copper and silicon. The conductive film 112c_1 and the conductive film 112c_3 each contain a material that suppresses the diffusion of copper. The region 112c_2b is located at the end of the conductive film 112c_2 and is in contact with the insulating film 114. In addition, the end of the conductive film 112c_1 is outward from the end of the conductive film 112c_2. The conductive film 112c_3 has a region located on the upper surface of the conductive film 112c_2. Therefore, the conductive film 112c_2a covers the conductive film 112c_1, the region 112c_2b and is covered with a conductive film 112c_3.

[0075] The region 112c_2b is made of the same material as the regions 112a_2b and 112b_2b. It can be formed by a process.

[0076] With this structure, the resistance of the conductive film 112c can be reduced. Diffusion of an element to the outside of the conductive film 112c, particularly to the oxide semiconductor film 108 can be suppressed.

[0077] Other configurations of the transistor 100F are the same as those of the transistor 100A. Therefore, the configuration of the transistor 100A should be taken into consideration.

[0078] <1-3. Configuration example 3 of semiconductor device> 7A and 7B are cross-sectional views of a transistor 100G which is a semiconductor device of one embodiment of the present invention. 1A, the top view of the transistor 100G is the same as that of the transistor 100 shown in FIG. FIG. 7A is a cross-section taken along the dashed line X1-X2 in FIG. 7(B) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 1(A). This corresponds to a surface view.

[0079] In the transistor 100G, the oxide semiconductor film 108 is disposed on the conductive film 104 side. 108a, an oxide semiconductor film 108b on the oxide semiconductor film 108a, and an oxide semiconductor film 1 The transistor 108 differs from the transistor 100 in that the transistor 108 includes an oxide semiconductor film 108c over the oxide semiconductor film 108b. The oxide semiconductor film 108 has a three-layer structure. The structure of the transistor 100 is the same as that of the transistor 100, and the same effects are obtained. This section explains the composition of the system.

[0080] The oxide semiconductor films 108a, 108b, and 108c are each composed of In, Zn, and M (M is Al, Ga, Y, or Sn).

[0081] For example, in the oxide semiconductor film 108b, a region in which the atomic ratio of In is larger than the atomic ratio of M is The oxide semiconductor films 108a and 108c preferably have an oxide semiconductor region. It is preferable that the number of In atoms is less than that of the body film 108b.

[0082] the oxide semiconductor film 108b has a region in which the atomic ratio of In is higher than the atomic ratio of M; In this way, the field effect mobility of the transistor 100G can be increased. The field effect mobility of a 100G transistor is 10cm 2 / Vs, more preferably The field effect mobility of a 100G transistor is 30cm 2 / Vs can be exceeded.

[0083] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. A driver (especially a demux connected to the output terminal of a shift register of a gate driver) By using it in a semiconductor device or display device with a narrow frame (also called a narrow frame), Locations can be provided.

[0084] On the other hand, the oxide semiconductor film 108b has a region in which the atomic ratio of In is larger than the atomic ratio of M. In this case, the electrical characteristics of the transistor 100G are likely to vary when exposed to light. In the semiconductor device of one embodiment of the present invention, an oxide semiconductor is formed on the oxide semiconductor film 108b. The oxide semiconductor film 108c is formed on the oxide semiconductor film 108b. Since the oxide semiconductor film 108 has a region with a low atomic ratio of In, the oxide semiconductor film 108 has a larger Eg than the oxide semiconductor film 108b. Therefore, the stacked structure of the oxide semiconductor film 108b and the oxide semiconductor film 108c The oxide semiconductor film 108 can have high resistance to a negative bias stress test using light irradiation. It becomes Noh.

[0085] In addition, the oxide semiconductor film 108, particularly the channel region of the oxide semiconductor film 108b, Impurities such as hydrogen and moisture are problematic because they affect transistor characteristics. Therefore, in the channel region of the oxide semiconductor film 108b, hydrogen, moisture, and the like are The fewer the impurities, the more preferable. The oxygen vacancies that occur in the oxide semiconductor layer affect the transistor characteristics, which is a problem. When oxygen vacancies are formed in the channel region of the membrane 108b, hydrogen bonds to the oxygen vacancies, A carrier supply source is generated in the channel region of the oxide semiconductor film 108b. When the oxide semiconductor film 108b is formed, the electrical characteristics of the transistor 100G including the oxide semiconductor film 108b change. Typically, a shift in the threshold voltage occurs. In the panel region, the fewer the oxygen vacancies, the more preferable.

[0086] In view of this, in one embodiment of the present invention, an insulating film in contact with the oxide semiconductor film 108, specifically, In the present embodiment, the insulating films 114 and 116 formed above the oxide semiconductor film 108 contain excess oxygen. Oxygen or excess oxygen is introduced from the insulating films 114 and 116 to the oxide semiconductor film 108. By the movement, oxygen vacancies in the oxide semiconductor film can be reduced.

[0087] In addition, in the transistor 100H illustrated in FIGS. However, the oxide semiconductor film 108 has a two-layer structure including an oxide semiconductor film 108b and an oxide semiconductor film 108c. Note that the top view of the transistor 100H is the same as that of the transistor shown in FIG. 100, and FIG. 8(A) shows a cut-off between dashed lines X1-X2 shown in FIG. 1(A). FIG. 8B is a cross-sectional view of the cross section of the semiconductor device 100 shown in FIG. 1A along the dashed line Y1-Y2. The cross-sectional view of the cut surface corresponds to the cross-sectional view of the cut surface. Since the configuration of the transistor 100G is the same as that of the transistor 100G, the configuration of the transistor 100G can be taken into consideration.

[0088] In addition, as in the case of a transistor 100J shown in FIGS. 9(A) and 9(B), The oxide semiconductor film 108 has a conductive film 120b that functions as a gate insulating film. The transistor 100J may have a structure including the oxide semiconductor film 108c. The surface view is the same as that of the transistor 100A shown in FIG. 9(B) corresponds to a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 2( This corresponds to a cross-sectional view taken along the dashed line Y1-Y2 in FIG. The other configuration of the transistor 100J is the same as that of the transistor 100A. Please refer to the configuration of 100A.

[0089] In addition, as in a transistor 100K shown in FIG. In the embodiment, there is a region where the end of the conductive film 112a_1 and the end of the conductive film 112a_2 are aligned. Alternatively, there may be a region where the end of the conductive film 112b_1 and the end of the conductive film 112b_2 are aligned. is also good.

[0090] In addition, as in the transistor 100L shown in FIG. 20b may be provided over the insulating film 118. In addition, the transistor shown in FIG. As shown in FIG. 100M, in the conductive films 112a and 112b, an end of the conductive film 112a_1 and There may be a region where the end of the conductive film 112a_2 is aligned with the end of the conductive film 112b_1. There may be a region where the end of the conductive film 112b_2 is aligned.

[0091] Transistors such as 100J, 100K, 100L, 100M, s-channel By having the structure, the region in the oxide semiconductor film 108 where carriers flow is an oxide the first gate insulating film side of the oxide semiconductor film 108b and the second gate insulating film side of the oxide semiconductor film 108b. Since the area is large on the gate insulating film side and in the oxide semiconductor film 108, The amount of carrier movement in the transistor increases. As a result, the on-current of the transistor increases. As the temperature increases, the field effect mobility increases.

[0092] In addition, the oxide semiconductor film 108 included in the transistor 100 is a conductive film 11 The oxide semiconductor film in the region exposed from 2a and 112b becomes thin. In other words, the oxide semiconductor The embodiment shows a shape in which a part of the film has a recess. However, one embodiment of the present invention is not limited to this. Therefore, the oxide semiconductor film in a region exposed from the conductive films 112a and 112b does not become thin. It is not necessary to have a recess. An example of this case is shown in Fig. 11(A)(B). 11B) is a cross-sectional view showing an example of a semiconductor device. A transistor 100 in which the oxide semiconductor film 108 does not have a recess Cross-sectional view of 100N.

[0093] <1-4. Configuration example 4 of semiconductor device> FIG. 12(A) is a top view of the transistor 100P, and FIG. 12(B) is a 12(C) corresponds to a cross-sectional view taken along the dashed line X1-X2 in FIG. 12(C). 2(A) along dashed line Y1-Y2.

[0094] The transistor 100P shown in FIG. 12 includes a conductive film 104 on a substrate 102 and a and an insulating film 106 on the conductive film 104, an insulating film 107 on the insulating film 106, and The oxide semiconductor film 108, the insulating film 114 on the oxide semiconductor film 108, and the insulating film 114 through the insulating film 116 and the opening 151a provided in the insulating film 114 and the insulating film 116. The conductive film 112a electrically connected to the oxide semiconductor film 108, the insulating film 114, and the insulating film The insulating film 116 is electrically connected to the oxide semiconductor film 108 through an opening 151b. In addition, the transistor 100P, more specifically, the conductive film 11 An insulating film 118 is provided on the layers 2a, 112b and the insulating film 116.

[0095] In the transistor 100P, the insulating films 106 and 107 are The insulating films 114 and 116 function as gate insulating films for the oxide semiconductor film 108. The insulating film 118 functions as a protective insulating film for the transistor 100P. In the transistor 100P, the conductive film 104 functions as a gate The conductive film 112a functions as a source electrode, and the conductive film 1 12b functions as a drain electrode.

[0096] The transistor 100 shown in FIG. 1 has a channel etch structure. The transistor 100P shown in FIGS. 12(A), 12(B), and 12(C) has a channel protection type structure. A channel-protective transistor can also be suitably used in the semiconductor device of one embodiment of the present invention. The other configuration of the transistor 100P can be the same as that of the transistor 100. Therefore, the configuration of the transistor 100 should be taken into consideration.

[0097] 13A is a top view of a transistor 100Q, and FIG. 13B is a top view of a transistor 100Q shown in FIG. 3(A) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 13(C). 13A. This corresponds to a cross-sectional view taken along dashed line Y1-Y2 in FIG.

[0098] The transistor 100Q shown in FIG. 13 is a transistor 100Q shown in FIGS. The shapes of the insulating films 114 and 116 are different from those of the transistor 100P. The insulating films 114 and 116 are provided in an island shape on the channel region of the oxide semiconductor film 108. The other configurations are the same as those of the transistor 100P.

[0099] In addition, the transistor according to the present embodiment can be freely combined with each of the above structures. It is possible.

[0100] <1-5. Components of Semiconductor Device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0101] <Substrate> There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, and sa A fire substrate or the like may be used as the substrate 102. Also, a material such as silicon or silicon carbide may be used. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductors such as silicon germanium, etc. It is also possible to use a substrate, an SOI substrate, or the like, on which a semiconductor element is provided. The resulting material may be used as the substrate 102 .

[0102] When a glass substrate is used as the substrate 102, the sixth generation (1500 mm×185 0mm), 7th generation (1870mm x 2200mm), 8th generation (2200mm x 240 0mm), 9th generation (2400mm x 2800mm), 10th generation (2950mm x 34 By using a large area substrate such as a 300 mm substrate, a large display device can be manufactured.

[0103] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is preferably removed from the substrate 102 after a semiconductor device is partially or entirely completed thereon. The transistor 100 can be separated and transferred to another substrate. It can also be transferred to substrates with poor thermal properties or flexible substrates.

[0104] Conductive film A conductive film 104 functions as a first gate electrode, and a conductive film 11 functions as a source electrode. 2a, a conductive film 112b functioning as a drain electrode, and a conductive film 11 2c, a conductive film 120b functioning as a second gate electrode, and a conductive film 120b functioning as a pixel electrode. The conductive film 120a may be made of chromium (Cr), copper (Cu), aluminum (Al), gold (Au ), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti ), Tungsten (W), Manganese (Mn), Nickel (Ni), Iron (Fe), Cobalt (Co), or an alloy containing the above-mentioned metal element, or Each of the electrodes can be formed using an alloy or the like in which metal elements are combined.

[0105] The conductive films 104, 112a, 112b, 112c, 120a, and 120b are made of Cu. It is preferable to use a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co , Mo, Ta, or Ti) may be applied. By using a Cu-X alloy film, Since the film can be processed by a quick etching process, the manufacturing cost can be reduced.

[0106] In addition, the conductive film 112a_2 included in the conductive film 112a and the conductive film 112b included in the conductive film 112a_1 are The conductive film 112b_2 and the conductive film 112c_2 of the conductive film 112c are made of Cu or the above-mentioned C. The Cu-X alloy film can be preferably used. The Cu-X alloy film can be a Cu-Mn alloy film. However, in one embodiment of the present invention, the present invention is not limited thereto, and the conductive film 112a The conductive film 112b_2, 112b_2, and the conductive film 112c_2 may contain at least copper.

[0107] The regions 112a_2b, 112b_2b, and 112c_2b contain Cu and Si. Preferably, the regions 112a_2b and 112b have copper silicide. _2b, 112c_2b have copper silicide nitride, so copper diffuses outward. Copper silicide is a type of copper that is formed by depositing Cu or an alloy containing Cu. The silane gas is reacted with the silane gas to form the silane gas. For example, copper silicide nitride having Cu, Si, and N can be obtained by reacting it with a plasma containing nitrogen. In addition, the surface of copper or a copper-containing alloy may be covered with an oxide film. If the oxide film is removed, a reduction treatment using hydrogen or ammonia, etc., is carried out before the above reaction. It is preferable to carry out the above process.

[0108] In addition, the conductive films 112a_1, 112a_3, and 112b of the conductive film 112a are The conductive films 112b_1 and 112b_3 and the conductive film 112c Among the above-mentioned metal elements, titanium, tungsten, tantalum, etc. are particularly included in 112c_3. It is preferable that the conductive material contains one or more selected from the group consisting of zinc, zinc carbide, and molybdenum. Electric film 112a_1, 112a_3, 112b_1, 112b_3, 112c_1, 112 c_3 is any one selected from titanium, tungsten, tantalum, and molybdenum; When the conductive films 112a_2, 112b_2, and 112c_2 have one or more copper In other words, the conductive films 112a_1 and 112a_3 can suppress the diffusion of the conductive film 112a_1 and 112a_3 to the outside. , 112b_1, 112b_3, 112c_1, and 112c_3 are so-called barrier metals. It has all the functions.

[0109] In addition, the conductive films 112a_1, 112a_3, 112b_1, 112b_3, 112c_ For the film 112c_3, it is preferable to use a so-called tantalum nitride film containing nitrogen and tantalum. The tantalum nitride film is conductive and has a high barrier property against copper or hydrogen. In addition, the tantalum nitride film releases less hydrogen from itself, so the oxide It can be most suitably used as a conductive film in contact with the semiconductor film 108 .

[0110] In addition, the conductive films 104, 112a_1, 112a_3, 112b_1, 112b_3, 1 12c_1, 112c_3, 120a, and 120b are oxides having indium and tin. tungsten and indium oxide; tungsten, indium and zinc oxide oxides having titanium and indium; oxides having titanium, indium and tin Oxide, oxide having indium and zinc, oxide having silicon, indium and tin Alternatively, an oxide conductor such as an oxide containing indium, gallium, and zinc can be used. Conductive films 112a_1, 112a_3, 112b_1, 112b_3, 112c_1 and 112c_3 has an oxide containing at least one of In and Zn. In order to suppress the diffusion of copper contained in the conductive films 112a_2, 112b_2, and 112c_2 to the outside, It is possible.

[0111] In particular, the conductive film 120a can be preferably made of the oxide conductor described above. The conductive film 120a and the oxide semiconductor film 108 (the oxide semiconductor film 108b and the oxide semiconductor film It is preferable that the metal element of the metal oxide is the same as that of the metal oxide of the metal oxide. This makes it possible to reduce the manufacturing cost.

[0112] Here, the oxide conductor will be described. In this specification, the oxide conductor is referred to as OC The oxide conductor may be, for example, When oxygen vacancies are formed in an oxide semiconductor and hydrogen is added to the oxygen vacancies, a donor is formed near the conduction band. As a result, the oxide semiconductor becomes conductive and becomes a conductor. The oxide semiconductor that has been encapsulated can be called an oxide conductor. Because of its large energy gap, it is transparent to visible light. The oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. The effect of absorption due to donor levels is small, and the transparency to visible light is comparable to that of oxide semiconductors. It has sexuality.

[0113] <Insulating film that functions as the first gate insulating film> The insulating films 106 and 107 functioning as the first gate insulating film of the transistor 100 are Plasma Enhanced Chemical Vapor Deposition (PECVD) Oxidation is performed by the ical vapor deposition (CVD) method, sputtering method, etc. Silicon film, silicon oxynitride film, silicon oxynitride film, silicon nitride film, aluminum oxide hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film , tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and ne oxide film The insulating film 106 and the insulating layer 107 may each include an insulating layer containing one or more oxynitride films. Instead of the laminated structure of 107, a single insulating film selected from the above-mentioned materials or three or more insulating films may be used. An insulating film may also be used.

[0114] The insulating film 106 also functions as a blocking film that suppresses oxygen permeation. For example, the insulating films 107, 114, and 116 and / or the oxide semiconductor film 108 may contain an excess of acid. When oxygen is supplied, the insulating film 106 can suppress oxygen permeation.

[0115] Note that the oxide semiconductor film 108 functioning as a channel region of the transistor 100 The insulating film 107 is preferably an oxide insulating film, and has an oxide content in excess of the stoichiometric composition. It is more preferable that the insulating film 1 has a region containing oxygen (an oxygen excess region). The insulating film 107 is capable of releasing oxygen. In order to provide the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. The insulating film 107 is then heat-treated in an oxygen atmosphere.

[0116] When hafnium oxide is used as the insulating film 107, the following effects are obtained. Hafnium has a higher dielectric constant than silicon oxide and silicon oxynitride. Compared to the case where silicon oxide is used, the thickness of the insulating film 107 can be made larger, so that the tunnel This reduces the leakage current caused by the current. Furthermore, hafnium oxide, which has a crystalline structure, can be used to realize an amorphous structure. It has a higher relative dielectric constant than hafnium oxide, which has a low off-current. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic. The types are not limited to these.

[0117] In this embodiment, a silicon nitride film is formed as the insulating film 106, and the insulating film 107 is The silicon oxide film is formed as a result of the above. The silicon nitride film has a lower dielectric constant than the silicon oxide film. The film thickness required to obtain the same capacitance as a silicon oxide film is large, so it is suitable for transistors. The gate insulating film of the transistor 100 can be made thick by including a silicon nitride film. Therefore, the decrease in the dielectric strength of the transistor 100 can be suppressed, and the dielectric strength can be increased. This can improve the resistance of the transistor 100 and suppress electrostatic damage to the transistor 100.

[0118] <Oxide semiconductor film> For the oxide semiconductor film 108, the above-mentioned materials can be used.

[0119] When the oxide semiconductor film 108b is an In-M-Zn oxide, the In-M-Zn oxide is formed. The atomic ratio of the metal elements in the sputtering target used for this purpose satisfies In>M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is I n:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4 .1 etc.

[0120] In addition, when the oxide semiconductor films 108a and 108c are made of In-M-Zn oxide, The atomic ratio of metal elements in the sputtering target used to form a Zn oxide film is: It is preferable that In≦M is satisfied. The molecular ratios were In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In: M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, etc. Examples include:

[0121] The oxide semiconductor films 108 (108a, 108b, and 108c) are each made of In In the case of In-M-Zn oxide, the sputtering target is polycrystalline In-M-Zn It is preferable to use a target containing an oxide. A target containing a polycrystalline In-M-Zn oxide is used. By using the get, the oxide semiconductor films 108a, 108b, and 108 Note that the oxide semiconductor films 108a, 108b, and 10c are easily formed. The atomic ratio of 8c is the atomic ratio of the metal elements contained in the above sputtering target. For example, the oxide semiconductor film 108b is sputtered. When an atomic ratio of In:Ga:Zn=4:2:4.1 is used as a ring target, The atomic ratio of the oxide semiconductor film 108b to be formed is approximately In:Ga:Zn=4:2:3. This may be the case.

[0122] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using a nitride semiconductor, the off-state current of the transistor 100 can be reduced. In addition, the oxide semiconductor film 108b has an energy gap of 2 eV or more, preferably 2 eV or more. The oxide semiconductor films 108a and 108c are formed using an oxide semiconductor film having a potential of 3.0 eV or more and 3.0 eV or less. It is preferable to use an oxide semiconductor film having an energy gap of 2.5 eV or more and 3.5 eV or less. In addition, the oxide semiconductor films 108a and 108c have a larger densitometric value than the oxide semiconductor film 108b. A larger energy gap is preferred.

[0123] The oxide semiconductor films 108a, 108b, and 108c each have a thickness of 3 nm or more. At most 200 nm, preferably 3 nm to 100 nm, and more preferably 3 nm or more The thickness should be 50 nm or less.

[0124] The oxide semiconductor films 108a and 108c are formed using an oxide semiconductor having a low carrier density. For example, the oxide semiconductor films 108a and 108c each have a carrier density of 1×10 1 7 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 The following applies.

[0125] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the carrier density and impurity of the oxide semiconductor film 108 are The concentration of metals, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. are appropriately adjusted. It is preferable.

[0126] Note that the oxide semiconductor film 108 is formed of an oxide semiconductor having a low impurity concentration and a low density of defect states. By using a semiconductor film, it is possible to manufacture transistors with even better electrical characteristics. Here, the impurity concentration is low and the defect level density is low (there is little oxygen vacancy). This is called high purity authentic or substantially high purity authentic. High purity authentic or substantially high purity authentic Since the oxide semiconductor film has a small number of carrier generation sources, the carrier density can be reduced. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film can be It is rare for the electrical characteristics to become negative at low voltages (also known as normally-on). In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. In addition, the trap density may be low because of the low purity intrinsic or substantially high purity. The intrinsic oxide semiconductor film has a significantly small off-state current and a channel width of 1×10 6 μm Even if the channel length L of the element is 10 μm, the voltage between the source electrode and the drain electrode (drain The off-state current is measured at a voltage between 1V and 10V. below the measurement limit, i.e. 1×10 -13 It is possible to obtain a characteristic of A or less.

[0127] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is provided with a channel. The transistors in which the regions are formed have small variations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor film are dissipated. It takes a long time for the charge to reach a certain level, and it may behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states has a high current density. Impurities include hydrogen, nitrogen, alkali metals, or Alkaline earth metals, etc.

[0128] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. In this case, oxygen vacancies are formed in the lattice from which oxygen has been desorbed (or in the portion from which oxygen has been desorbed). When hydrogen enters the electron carrier, it can generate electrons. It can combine with oxygen, which combines with metal atoms, to generate electrons, which are carriers. A transistor using an oxide semiconductor film containing hydrogen has normally-on characteristics. For this reason, it is preferable that the amount of hydrogen in the oxide semiconductor film 108 be reduced as much as possible. Specifically, in the oxide semiconductor film 108, a hydrogen concentration obtained by SIMS analysis is Degrees, 2 x 10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than or equal to 5×1, more preferably 0 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 below Let us assume that.

[0129] In addition, the oxide semiconductor film 108b has a region with a lower hydrogen concentration than the oxide semiconductor film 108c. It is preferable that the oxide semiconductor film 108b has a region larger than the oxide semiconductor film 108c. By having a region with a low hydrogen concentration, a highly reliable semiconductor device can be obtained.

[0130] In addition, in the oxide semiconductor film 108b, silicon and carbon, which are Group 14 elements, If the oxide semiconductor film 108b contains oxygen, oxygen vacancies are increased in the oxide semiconductor film 108b, causing the oxide semiconductor film 108b to become n-type. Therefore, the concentrations of silicon and carbon in the oxide semiconductor film 108b and the oxide semiconductor film 10 The concentration of silicon and carbon near the interface with 8b (concentration obtained by SIMS analysis) is 2× 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following do.

[0131] In addition, in the oxide semiconductor film 108b, the alkali metal or alkaline earth metal concentration, 1×10 18 atoms / cm 3 Below, preferably 2x 10 16 atoms / cm 3 The following are the oxides of alkali metals and alkaline earth metals. When it bonds with a semiconductor, carriers may be generated, increasing the off-state current of the transistor. For this reason, the alkali metal or alkaline earth metal of the oxide semiconductor film 108b may be It is preferable to reduce the concentration of metalloids.

[0132] When the oxide semiconductor film 108b contains nitrogen, electrons that serve as carriers are generated. The carrier density increases and the oxide semiconductor film containing nitrogen is easily converted to n-type. A transistor using the oxide semiconductor film tends to be normally on. In the present invention, it is preferable that the nitrogen content is reduced as much as possible. For example, it is preferable that the nitrogen content is reduced as much as possible by SIMS analysis. The resulting nitrogen concentration is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0133] The oxide semiconductor film 108b and the oxide semiconductor film 108c each have a non-single crystal structure. The non-single crystal structure may be, for example, CAAC-OS (C Axis Alias) which will be described later. gned Crystalline Oxide Semiconductor), polyconductor The non-single crystalline structure includes a crystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single crystalline structure, the amorphous structure is the most The defect state density of CAAC-OS is the lowest.

[0134] <An insulating film that functions as a second gate insulating film> The insulating films 114 and 116 function as a second gate insulating film of the transistor 100 . The insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108. That is, the insulating films 114 and 116 contain oxygen. The insulating film 114 is an insulating film that can be used to form an insulating film 116 to be formed later. The oxide semiconductor film 108 also functions as a film for reducing damage to the oxide semiconductor film 108 during the formation of the oxide semiconductor film 108.

[0135] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0136] In addition, it is preferable that the insulating film 114 has a small amount of defects. Typically, the insulating film 114 has a small amount of defects as determined by ESR measurement. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 3×10 17 spins / cm 3 This is because the insulating film 114 is preferably If the density of defects is high, oxygen will be bonded to the defects, and the oxygen in the insulating film 114 will The amount of transmission of the light is reduced.

[0137] In the insulating film 114, all of the oxygen that has entered the insulating film 114 from the outside is Some oxygen does not move to the outside of the insulating film 114 and remains in the insulating film 114. At the same time, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, In some cases, oxygen may move through the film 114. When the oxide insulating film capable of forming the insulating film 116 is formed over the insulating film 114, The desorbed oxygen can be transferred to the oxide semiconductor film 108 through the insulating film 114. .

[0138] The insulating film 114 is formed using an oxide insulating film having a low density of states caused by nitrogen oxides. Note that the density of states due to the nitrogen oxides can be determined by the valence Energy of the upper edge of the electronic band (Ev_os) and the lower edge of the conduction band of the oxide semiconductor film The oxide insulating film may be formed between the gate electrodes of the SiO_O_2 layer and the gate electrodes of the SiO_O_2 layer. Silicon oxynitride film with low emission or aluminum oxynitride film with low emission of nitrogen oxide For example, a tungsten film or the like can be used.

[0139] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, is This membrane releases more ammonia than nitrogen oxides, and typically releases ammonia. The amount of emission is 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The following is the case. The amount of monia released is determined when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 50°C or higher and 55°C or lower. This is the amount released by heating at 0℃ or below.

[0140] Nitrogen oxides (NO x , x is more than 0 and not more than 2, preferably 1 or more and not more than 2), typically NO or NO forms a level in the insulating film 114 or the like. The level is Therefore, the nitrogen oxide is located in the energy gap of the insulating film 114 and When the oxide semiconductor film 108 diffuses to the interface, the level traps electrons on the insulating film 114 side. As a result, the trapped electrons may wrap around the insulating film 114 and the oxide semiconductor. Since the ions remain near the interface with the semiconductor film 108, the threshold voltage of the transistor is shifted in the positive direction. It will cause.

[0141] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in the insulating film 116 reacts with ammonia contained in the insulating film 116 during the heat treatment. Therefore, the amount of nitrogen oxide contained in the insulating film 114 is reduced. Electrons are less likely to be trapped at the interface between the oxide semiconductor film 106 and the oxide semiconductor film 108.

[0142] By using the oxide insulating film as the insulating film 114, the threshold voltage of the transistor It is possible to reduce the shift in the electrical characteristics of the transistor. can.

[0143] Heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher and lower than 350° C. By the heat treatment, the insulating film 114 shows the following characteristics in the spectrum obtained by ESR measurement at 100K or less: The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2.001 to 2.002. A second signal with a g value of .003 or less and a third signal with a g value between 1.964 and 1.966, inclusive. A null is observed. Note that the split width of the first signal and the second signal, The split width of the second and third signals is about 5 in the X-band ESR measurement. mT. The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 The sum of the spin densities of the third signal is 1 × 10 18 spins / cm 3 Less than Typically, it is 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Not yet It is full.

[0144] In the ESR spectrum below 100K, the g value is 2.037 or more and 2.039 or less. The first signal below, the second signal with a g-value between 2.001 and 2.003, and the g-value The sum of the spin densities of the third signal, which is greater than or equal to 1.964 and less than or equal to 1.966, is the nitrogen oxide Monster (NO x (x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2) Representative examples of nitrogen oxides include nitrogen monoxide and nitrogen dioxide. The first signal is between 2.037 and 2.039, and the g value is between 2.001 and 2.003. and the third signal having a g value of 1.964 or more and 1.966 or less. The lower the total density of the pins, the lower the nitrogen oxide content in the oxide insulating film. I can say.

[0145] The nitrogen concentration of the oxide insulating film measured by SIMS is 6×10 20 atoms / cm 3 The following is the result.

[0146] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating film by the VD method, a dense and hard film can be obtained. It can be formed.

[0147] The insulating film 116 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film containing more oxygen than the stoichiometric composition is formed using When heated, some of the oxygen is released. The oxygen content is greater than the stoichiometric composition. The oxide insulating film had a loss of oxygen of 1.0×10 in terms of oxygen atoms as determined by TDS analysis. 1 9 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 That's all. The oxide insulating film is used. The surface temperature of the film in the above TDS is 100°C or higher and 70°C or lower. A temperature range of 0° C. or lower, or 100° C. to 500° C. is preferred.

[0148] The insulating film 116 has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., having a thickness of 400 nm or less can be used.

[0149] In addition, it is preferable that the insulating film 116 has a small amount of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5 x 10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 Note that the insulating film 116 is preferably an oxide semiconductor compared to the insulating film 114. Since it is separated from the insulating film 108, it may have a higher defect density than the insulating film 114.

[0150] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating films In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly seen. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a dashed line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. For example, the insulating film 114 may have a single layer structure or a laminated structure of three or more layers. Good too.

[0151] <Insulating film that functions as a protective insulating film> The insulating film 118 functions as a protective insulating film for the transistor 100 .

[0152] The insulating film 118 contains either hydrogen or nitrogen, or both. The insulating film 118 contains nitrogen and silicon. The insulating film 118 contains oxygen, hydrogen, water, and alkali. The insulating film 118 has a function of blocking metals, alkaline earth metals, etc. As a result, oxygen diffuses from the oxide semiconductor film 108 to the outside, and oxygen contained in the insulating films 114 and 116 is prevented from diffusing. The diffusion of oxygen from the outside and the entry of hydrogen, water, and the like into the oxide semiconductor film 108 from the outside are prevented. It can be prevented.

[0153] The insulating film 118 may be, for example, a nitride insulating film. Examples include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. etc.

[0154] Note that the various films described above, such as the conductive film, the insulating film, and the oxide semiconductor film, are formed by sputtering. It can be formed by the CVD method or PECVD method, but other methods such as thermal CVD (Ch Alternatively, the insulating layer may be formed by thermal CVD. As an example of the method, MOCVD (Metal Organic Chemical Vapor Deposition) Deposition method or ALD (Atomic Layer Deposition) method tion method.

[0155] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no additional steps are required.

[0156] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing the reactants on the substrate. You may go.

[0157] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating the gas introduction sequence.

[0158] Thermal CVD methods such as MOCVD and ALD can be used to form the conductive film, insulating film, and oxide film of the above-mentioned embodiment. It is possible to form various films such as semiconductor films and metal oxide films. For example, In-Ga-Zn When forming an O film, trimethylindium, trimethylgallium, and dimethylzinc are used. Lead is used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for dimethylzinc is is Zn(CH3)2. In addition, the combination is not limited to these, and trimethylgalactan Triethylgallium (chemical formula Ga(C2H5)3) can be used instead of diethylgallium. Diethylzinc (chemical formula Zn(C2H5)2) can be used instead of methylzinc.

[0159] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is made by vaporizing hafnium amide (such as TDMAH) and acid. Two types of gases are used: tetrakisdimethylamide (TDA) and ozone (O3). The chemical formula for fluorine is Hf[N(CH3)2]4. Other liquid materials include tetrahydrofuran. Examples include rakis(ethylmethylamido)hafnium.

[0160] For example, when forming an aluminum oxide film using an ALD deposition system, A liquid containing a catalyst and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is added. Two types of gases are used: vaporized source gas and H2O as an oxidizing agent. The chemical formula for aluminum is Al(CH3)3. Other liquid materials include Tris( Dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2 ,2,6,6-tetramethyl-3,5-heptanedionate).

[0161] For example, when forming a silicon oxide film using a deposition system that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, the chlorine contained in the adsorbed matter is removed, and the oxidizing gas (O 2. Nitrous oxide (NO) radicals are supplied to react with the adsorbed material.

[0162] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by repeatedly introducing B2H6 gas and WF A tungsten film is formed using B2H6 gas and H2 gas. iH4 gas may also be used.

[0163] For example, an oxide semiconductor film, such as In-Ga-ZnO, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- An O layer is formed, and then a GaO layer is formed using Ga(CH3)3 gas and O3 gas. After that, a ZnO layer is formed using Zn(CH3)2 gas and O3 gas. The order of these layers is not limited to this example. In addition, it is possible to form an In-Ga-O layer or an In A mixed compound layer such as a -Zn-O layer or a Ga-Zn-O layer may be formed. Instead of H, H2O gas obtained by bubbling with an inert gas such as Ar may be used. It is preferable to use O3 gas that does not contain In. (C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2 H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0164] <1-6. Transistor manufacturing method 1> Next, a manufacturing method of the transistor 100J which is a semiconductor device of one embodiment of the present invention will be described. 14 to 17 are used to explain the manufacturing method of a semiconductor device. 14(A)(C)(E), 15(A)(C)(E), and 1 6(A)(C)(E) and 17(A)(C)(E) are in the channel length direction indicated by X1-X2. 14(B)(D)(F), 15(B)(D)(F), 16(B)(D)( 17(B), (D) and (F) are cross-sectional views in the channel width direction shown in Y1-Y2.

[0165] <Step of forming first gate electrode and first gate insulating film> First, a conductive film is formed on the substrate 102, and the conductive film is then subjected to a lithography process and an etching process. Then, a conductive film 104 that functions as a first gate electrode is formed by carrying out a process. On the conductive film 104, insulating films 106 and 107 that function as a first gate insulating film are formed (see FIG. 14(A)(B)).

[0166] In this embodiment, a glass substrate is used as the substrate 102, which functions as the first gate electrode. The conductive film 104 is made of a titanium film having a thickness of 10 nm, a copper film having a thickness of 100 nm, and a copper film having a thickness of 5 nm. A tantalum nitride film having a thickness of 100 nm is then formed by sputtering.

[0167] In addition, a silicon nitride film having a thickness of 400 nm is formed as the insulating film 106 by the PECVD method. Then, a silicon oxynitride film having a thickness of 15 nm is formed as the insulating film 107 by the PECVD method. The insulating film 106 may have a laminated structure of silicon nitride films. Specifically, the insulating film 106 is made of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminate structure including a silicon oxide film and a silicon dioxide film can be used. It can be formed as follows:

[0168] The first silicon nitride film is formed by, for example, silane at a flow rate of 200 sccm, PECVD was performed using nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as source gas. The pressure in the reaction chamber was controlled at 100 Pa, and a high-frequency wave of 27.12 MHz was generated. A power of 2000 W may be supplied using a microwave power source to form the film to a thickness of 50 nm. stomach.

[0169] For the second silicon nitride film, silane at a flow rate of 200 sccm, The nitrogen gas and the ammonia gas with a flow rate of 2000sccm were used as raw material gases in the PECVD equipment. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high-frequency power supply was used. A power of 2000 W may be supplied using the above method to form a film having a thickness of 300 nm.

[0170] The third silicon nitride film was prepared by using silane at a flow rate of 200 sccm and 5000 sccm. The pressure in the reaction chamber was kept at 100 The thickness was measured by controlling the temperature to 50 Pa and supplying 2000 W of power using a 27.12 MHz high frequency power source. It is sufficient to form it so that the thickness is 50 nm.

[0171] The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during formation can be 350° C. or less.

[0172] By forming the insulating film 106 in a three-layered structure of silicon nitride films, for example, the conductive film 10 When a conductive film containing copper (Cu) is used for 4, the following effects are achieved.

[0173] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive film 104. The second silicon nitride film has the function of releasing hydrogen and functions as a gate insulating film. The third silicon nitride film can improve the breakdown voltage of the insulating film. Hydrogen release from the silicon nitride film is small, and hydrogen released from the second silicon nitride film is diffused. can be suppressed.

[0174] The insulating film 107 is an oxide semiconductor film 108 (more specifically, an oxide In order to improve the interface characteristics with the semiconductor film 108b), the insulating film is formed of an oxygen-containing insulating film. It is preferable that oxygen be added to the insulating film 107 after the insulating film 107 is formed. The oxygen to be added to the film 107 may be an oxygen radical, an oxygen atom, an oxygen atomic ion, or an oxygen molecule. The methods of addition include ion doping, ion implantation, plasma There are methods such as the ma processing method.

[0175] <Process for forming oxide semiconductor film> Next, the oxide semiconductor film 108b and the oxide semiconductor film 108c are formed over the insulating film 107. (See Figures 14(C) and (D)).

[0176] 14C and 14D show an oxide semiconductor film 108 formed on the insulating film 107. 14(C) and (D) are schematic cross-sectional views of the inside of the film forming apparatus when a solid film is formed. A sputtering device was used as the device, and a target was placed inside the sputtering device. 1, a target 191 and a plasma 192 formed below the target 191 are shown. is.

[0177] First, when an oxide semiconductor film is formed, plasma is emitted in an atmosphere containing a first oxygen gas. At that time, oxygen is added to the insulating film 107, which is a surface on which the oxide semiconductor film is to be formed. In addition, when the oxide semiconductor film is formed, an inert gas (e.g., For example, helium gas, argon gas, xenon gas, etc. may be mixed.

[0178] The first oxygen gas may be contained at least when the oxide semiconductor film is formed. The ratio of the first oxygen gas to the entire deposition gas when the oxide semiconductor film is formed is , greater than 0% and less than or equal to 100%, preferably greater than or equal to 10% and less than or equal to 100%, more preferably Between 30% and 100%.

[0179] In addition, in FIG. 14C and FIG. 14D, oxygen or excess oxygen added to the insulating film 107 is This is shown diagrammatically by dashed arrows.

[0180] Note that the oxide semiconductor films 108b and 108c were formed at the same substrate temperature. However, the oxide semiconductor film 108b and the oxide semiconductor film 108 By making the substrate temperature the same as that of the first embodiment, the manufacturing cost can be reduced. do.

[0181] For example, the substrate temperature when the oxide semiconductor film 108 is formed is set to a temperature not lower than room temperature and not higher than 340° C. Preferably, the temperature is from room temperature to 300° C., more preferably from 100° C. to 250° C. The temperature is preferably 100° C. or more and 200° C. or less. By doing so, the crystallinity of the oxide semiconductor film 108 can be improved. In addition, when using a large glass substrate (for example, 6th generation to 10th generation), the oxide semiconductor When the substrate temperature during deposition of the solid film 108 is set to 150° C. or higher and lower than 340° C., Therefore, when using a large glass substrate, In this case, the substrate temperature during the formation of the oxide semiconductor film 108 is set to 100° C. or higher and lower than 150° C. By doing so, deformation of the glass substrate can be suppressed.

[0182] In addition, the sputtering gas must be highly purified. The oxygen gas and argon gas used in the present invention have a dew point of -40°C or less, preferably -80°C or less, and Preferably, the gas is purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using the above, it is possible to prevent moisture and the like from being absorbed into the oxide semiconductor film as much as possible. .

[0183] In addition, when the oxide semiconductor film is formed by a sputtering method, The chamber is a clarified chamber to remove water and other impurities that may be harmful to the oxide semiconductor film as much as possible. A high vacuum (5×10) was achieved by using an adsorption type vacuum pump such as an ion pump. -7 Pa to 1× 10 -4 It is preferable to evacuate the gas to a temperature of about 10 Pa. Alternatively, a turbo molecular pump and a cold A trap is used to extract gases, especially those containing carbon or hydrogen, from the exhaust system into the chamber. It is preferable to prevent backflow.

[0184] After the oxide semiconductor film that will later become the oxide semiconductor film 108b is formed, An oxide semiconductor film that becomes the oxide semiconductor film 108c is formed. When forming the film, plasma may be discharged in an atmosphere containing the second oxygen gas.

[0185] Note that the first oxygen gas used in forming the oxide semiconductor film that will later become the oxide semiconductor film 108b The ratio of the second oxide to the oxide semiconductor film 108c to be formed later is The proportions of the elemental gas may be the same or different.

[0186] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: 2:4.1 [atomic ratio]) by a sputtering method, and the oxide semiconductor film 108 b) is then formed on the oxide semiconductor film, which is then successively grown in vacuum on an In-Ga-Zn metal oxide film. The sputtering was performed using a target of In:Ga:Zn=1:1:1.2 [atomic ratio]. An oxide semiconductor film that will later become the oxide semiconductor film 108c is formed by a etching method. The substrate temperature during the formation of these oxide semiconductor films is set to 170° C. The oxide semiconductor film 08b was formed using oxygen gas at a flow rate of 15 sccm. and argon gas at a flow rate of 35 sccm. The oxide semiconductor film was formed using oxygen gas at a flow rate of 25 sccm and A volume of 25 sccm of argon gas is used.

[0187] Next, the formed oxide semiconductor film is processed into a desired shape to form an island-shaped oxide semiconductor film. The oxide semiconductor film 108b and the island-shaped oxide semiconductor film 108c are formed (see FIGS. 14E and 14F). In this embodiment, the oxide semiconductor film 108b and the oxide semiconductor film 108c The oxide semiconductor film 108 is formed (see FIGS. 14E and 14F).

[0188] After the oxide semiconductor film 108 is formed, heat treatment (hereinafter referred to as first heat treatment) is performed. The first heat treatment is preferably performed to remove hydrogen from the oxide semiconductor film 108. The heat treatment for the purpose of reducing hydrogen, water, etc. The first heat treatment may be performed before processing the semiconductor film 108 into an island shape. This is one of the processes for purifying conductive films.

[0189] The first heat treatment is performed at a temperature of, for example, 150° C. or higher and lower than the distortion point of the substrate, preferably 200° C. The heating temperature can be set to 450°C or higher and more preferably 250°C or higher and 350°C or lower.

[0190] The first heat treatment is performed in an electric furnace or RTA (Rapid Thermal Annealer). l) Equipment such as an RTA device can be used. By using an RTA device, the distortion of the substrate can be measured for a short period of time. Heat treatment can be performed at a temperature above the heating point. This makes it possible to shorten the heating time. The first heat treatment is carried out in the presence of nitrogen, oxygen, or ultra-dry air (water content of 20 ppm or less). , preferably 1 ppm or less, preferably 10 ppb or less, air), or a noble gas (argon The above-mentioned nitrogen, oxygen, ultra-dry air, or helium atmosphere may be used. It is preferable that the rare gas does not contain hydrogen, water, etc. Also, heating in a nitrogen or rare gas atmosphere is performed. After the treatment, heating may be performed in an oxygen or ultra-dry air atmosphere. Hydrogen, water, and the like contained in the oxide semiconductor film can be desorbed and oxygen can be supplied to the oxide semiconductor film. As a result, oxygen vacancies in the oxide semiconductor film can be reduced.

[0191] <Process for forming source electrode and drain electrode> Next, a source electrode and a drain electrode are formed on the insulating film 107 and the oxide semiconductor film 108. A conductive film 112 is formed by a sputtering method (see FIGS. 15A and 15B). .

[0192] In this embodiment, the conductive film 112 includes conductive films 112_1, 112_2, and 112 A tungsten film having a thickness of 50 nm is laminated as the conductive film 112_1, and a conductive film 11 The conductive film 112_2 is a copper film having a thickness of 200 nm, and the conductive film 112_3 is a tungsten film having a thickness of 5 nm. A laminated film in which the silicon film and the silicon film are laminated in this order is formed by sputtering. In this embodiment, the conductive film 112_1 and the conductive film 112_3 are formed using the same material. For example, the conductive film 112_1 may be a tungsten film having a thickness of 50 nm, The conductive film 112_2 is a copper film having a thickness of 200 nm, and the conductive film 112_3 is a copper film having a thickness of 50 nm. Alternatively, a three-layered film of the conductive film 112 may be used. For example, the conductive film 112 may have a two-layer structure. Alternatively, it may have a laminated structure of four or more layers.

[0193] Next, masks 141a and 141b are formed in desired regions on the conductive film 112_3. Then, the conductive films 112_2 and 112_3 are processed using the masks 141a and 141b. The island-shaped conductive films 112a_2, 112b_2, and 112a_3 are separated from each other. , forming 112b_3 (see Figures 15(C) and (D)).

[0194] In this embodiment, a wet etching apparatus is used to etch the conductive film 112_2, However, the method for processing the conductive film 112 is not limited to this. For example, a dry etching device may be used. The conductive film 112 is processed by using a wet etching apparatus rather than by processing the conductive film 112. This can reduce the manufacturing cost.

[0195] Next, the ends of the conductive films 112a_2 and 112b_2 are silicided to form copper-containing and a copper silicide region 112a_2b. , 112b_2b.

[0196] 15(E) and 15(F) show the state where the ends of the conductive films 112a_2 and 112b_2 are silicided. 15(E) and 15(F) are schematic cross-sectional views of the inside of the plasma device. A PECVD apparatus is used as the plasma generating device, and the plasma 195 generated inside the PECVD apparatus is It is represented objectively.

[0197] The copper exposed at the ends of the conductive films 112a_2 and 112b_2 easily forms an oxide film on the surface. Therefore, as a pretreatment for converting copper into silicide, the oxide film covering the copper surface is removed. A gas having reducing properties (e.g., hydrogen gas, ammonia gas, etc.) is used to remove the Plasma is discharged in the atmosphere. At that time, the oxide film covering the copper surface is reduced, and the conductive film 11 Copper is exposed at the ends of 2a_2 and 112b_2. The method is not limited to plasma treatment. For example, a gas having reducing properties (e.g., water) may be used. The copper surface is exposed to an atmosphere containing nitrogen gas, ammonia gas, etc., and then heated to reduce the The substrate temperature during the plasma treatment and the heat treatment is preferably The temperature is preferably 300° C. or higher, and more preferably 350° C. or higher. The substrate temperature is set to 350° C. when removing the oxide film covering the surface.

[0198] Next, the copper is exposed to an atmosphere containing silane gas, and the silane gas reacts with the copper to form a conductive film. forming a copper silicide having copper and silicon at the ends of the films 112a_2 and 112b_2; Regions 112a_2b and 112b_2b are formed. In addition, conductive films 112a_2 and 112b In the first embodiment, regions in which copper silicide is not formed are designated as 112a_2a and 112b_2a. The substrate temperature during the formation of copper silicide is preferably 200° C. or higher and 400° C. or lower. The temperature is preferably 220° C. or higher and 350° C. or lower. The substrate temperature for forming the groove was 220°C, and the flow rate of silane gas was 300 sccm. , and nitrogen gas at a flow rate of 500 sccm.

[0199] In addition, the substrate temperature when removing the oxide film on the copper surface and the substrate temperature when forming the copper silicide were The uniformity of the degree of oxidation means that oxide film removal and copper silicide formation can be performed in the same equipment or in the same chamber. In this case, the substrate temperature during copper silicide formation is set to 350°C. It is preferable to do so.

[0200] The gas used to form copper silicide must contain at least silicon. Preferably, the ratio of silicon-containing gas to the total gas when forming copper silicide is is greater than 0% and less than or equal to 100%, preferably greater than or equal to 10% and less than or equal to 100%, and more preferably is between 30% and 100%.

[0201] In addition, in FIG. 15(E) and (F), the conductive films 112a_2 and 112b_2 are doped with Silicon or silane is represented diagrammatically by a dashed arrow.

[0202] After the copper silicide is formed, plasma is discharged in a nitrogen-containing gas atmosphere. The conductive films 112a_2 and 112b_2 are formed of copper silicide nitride containing copper, silicon and nitrogen. Alternatively, the substrate may be exposed to a nitrogen-containing gas atmosphere and subjected to a heat treatment. As a result, the conductive films 112a_2 and 112b_2 are formed of copper silicide containing copper, silicon, and nitrogen. Alternatively, a doped nitride may be formed.

[0203] Next, a part of the conductive film 112_1 and the conductive films 112a_2, 112b_2, and 112a Masks 142a and 142b are formed in desired areas on the substrate 112b_3 and 112b_3. The conductive film 112_1 is processed using the masks 142a and 142b. Separated island-shaped conductive films 112a_1 and 112b_1 are formed. By carrying out this process, , a conductive film 112a_1, and a conductive film 1 having a region 112a_2a and a region 112a_2b 12a_2, a conductive film 112a having a conductive film 112_3, and a conductive film 112b_1, , a conductive film 112b_2 having a region 112b_2a and a region 112b_2b, and a conductive film 1 A conductive film 112b having the insulating film 12b_3 is formed (see FIGS. 16(A) and 16(B)).

[0204] In this embodiment, the conductive film 112_1 is processed using a dry etching apparatus. However, the method for processing the conductive film 112_1 is not limited to this. For example, A wet etching apparatus may be used. The conductive film 112_1 is processed using a dry etching device rather than processing the conductive film 112_1. In this case, a finer pattern can be formed.

[0205] After the conductive films 112a and 112b are formed, the oxide semiconductor film 108 (more specifically, The surface (back channel side) of the oxide semiconductor film 108b may be cleaned. For example, cleaning using a chemical solution such as phosphoric acid can be used. By performing the cleaning, impurities (e.g., impurities formed on the surface of the conductive film 108b) are removed. The cleaning can be performed without removing the elements contained in the SiO2 particles (e.g., elements contained in 112a and 112b). In some cases, cleaning may not be required.

[0206] In addition, either one of the steps of forming the conductive films 112a and 112b and the above-mentioned cleaning step may be performed. In either case, the region of the oxide semiconductor film 108 that is exposed from the conductive films 112a and 112b is But it may become thinner.

[0207] <<Step of forming second gate insulating film>> Next, the insulating film 114 and the conductive films 112a and 112b are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b. An insulating film 116 is formed (see FIGS. 16(C) and (D)).

[0208] After the insulating film 114 is formed, the insulating film 116 is successively formed without exposing it to the air. After the insulating film 114 is formed, it is preferable to adjust the flow rate, pressure, and temperature of the source gas without exposing the insulating film 114 to the air. By adjusting one or more of the frequency power and the substrate temperature, the insulating film 116 is continuously formed. The concentration of impurities derived from atmospheric components can be reduced at the interface between the insulating film 114 and the insulating film 116. At the same time, oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. As a result, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced. .

[0209] For example, a silicon oxynitride film is formed as the insulating film 114 by using a PECVD method. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include silane, disilane, etc. Examples of oxidizing gases include nitrous oxide, nitrous oxide, and trisilane. In addition, the flow rate of the oxidizing gas is set to 20 times or more the flow rate of the deposition gas. The pressure in the treatment chamber is set to less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the treatment chamber is set to less than 100 Pa. By using the PECVD method at a pressure of 50 Pa or less, preferably 50 Pa or less, the insulating film 114 is The insulating film contains the above and has a small amount of defects.

[0210] In this embodiment, the insulating film 114 is formed by heating the substrate 102 at a temperature of 220° C. The source gases were silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm. The pressure in the treatment chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 M. Hz, 100W (power density is 1.6×10 -2 W / cm 2 ) PECVD method A silicon oxynitride film is formed using this.

[0211] The insulating film 116 is formed by depositing a substrate in a vacuum-evacuated processing chamber of a PECVD apparatus. The temperature is kept at 180°C or higher and 350°C or lower, and the raw material gas is introduced into the treatment chamber to increase the pressure in the treatment chamber. is set to 100 Pa or more and 250 Pa or less, and more preferably set to 100 Pa or more and 200 Pa or less. 0.17 W / cm2 at the electrode installed in the treatment chamber 2 More than 0.5W / cm 2 Below are some more Preferably 0.25W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: In this way, a silicon oxide film or a silicon oxynitride film is formed.

[0212] The conditions for forming the insulating film 116 are as follows: high frequency power density in a reaction chamber with the above pressure; By supplying power, the efficiency of decomposition of the source gas in the plasma increases, and the number of oxygen radicals increases. As the oxidation of the source gas progresses, the oxygen content in the insulating film 116 becomes lower than the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, the bonding strength between silicon and oxygen is Since the oxygen in the film is weak, some of the oxygen in the film is released by the heat treatment in the subsequent process. An oxide that contains more oxygen than satisfies the theoretical composition and loses some of the oxygen when heated. An insulating film can be formed.

[0213] In the step of forming the insulating film 116, the insulating film 114 serves as a protection film for the oxide semiconductor film 108. Therefore, the power density can be reduced while reducing damage to the oxide semiconductor film 108. The insulating film 116 can be formed using high radio frequency power.

[0214] In the deposition conditions for the insulating film 116, a deposition gas containing silicon is mixed with an oxidizing gas. By increasing the flow rate of the gas, it is possible to reduce the amount of defects in the insulating film 116. In the first place, ESR measurements revealed that the g value was 2.001, which is due to the dangling bonds of silicon. The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 spins / cm 3 Less than or equal to 1.5×10 17 spins / cm 3 The following is a missing As a result, the signal quality of the transistor 100 can be improved. It can increase reliability.

[0215] After the insulating films 114 and 116 are formed, heat treatment (hereinafter referred to as second heat treatment) is performed. The nitrogen oxide contained in the insulating films 114 and 116 is preferably removed by the second heat treatment. Alternatively, the second heat treatment can reduce the amount of oxides in the insulating films 114 and 116. Part of the oxygen contained in the oxide semiconductor film 108 is transferred to the oxide semiconductor film 108. This can reduce the amount of oxygen vacancies.

[0216] The temperature of the second heat treatment is typically less than 400° C., preferably less than 375° C., and The second heat treatment is preferably performed at a temperature of 150° C. or higher and 350° C. or lower. Dry air (water content is 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb The reaction may be carried out under an atmosphere of air (see below) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. For the heat treatment, an electric furnace, an RTA device, or the like can be used.

[0217] Next, a mask is formed on the insulating film 116 by a lithography process, and the insulating films 114 and 11 An opening 152c is formed in a desired region of the conductive film 112b. (See Figures 16(E) and (F)).

[0218] <Step of forming second gate electrode> Next, conductive films 120a and 120b are formed on the insulating film 116 so as to cover the opening 152c. (See Figures 17(A)(B)(C)(D)).

[0219] 17(A) and 17(B), conductive films 120a and 120b are formed on the insulating film 116. 17(A) and 17(B) are schematic cross-sectional views of the inside of a film forming apparatus. A sputtering apparatus is used, and a target 193 is installed inside the sputtering apparatus. A plasma 194 formed below the target 193 is also shown diagrammatically.

[0220] First, when forming the conductive films 120a and 120b, the plasma is performed in an atmosphere containing a third oxygen gas. At this time, the insulating film 11, which is the surface on which the conductive films 120a and 120b are to be formed, In addition, oxygen is added to the third oxide when the conductive films 120a and 120b are formed. In addition to the basic gas, inert gases (e.g., helium gas, argon gas, xenon gas, etc.) For example, argon gas and a third oxygen gas may be used to It is preferable to set the flow rate of the third oxygen gas higher than the flow rate of the third oxygen gas. By increasing the amount of oxygen, oxygen can be suitably added to the insulating film 116. The conditions for forming the conductive films 120a and 120b are as follows: The ratio may be set to 50% or more and 100% or less, and preferably 80% or more and 100% or less.

[0221] In addition, in FIG. 17(A) and (B), oxygen or excess oxygen added to the insulating film 116 is This is shown diagrammatically by dashed arrows.

[0222] The substrate temperature during the formation of the conductive films 120a and 120b is set to 340° C. or higher. less than 300°C, preferably from room temperature to 300°C, more preferably from 100°C to 250°C, More preferably, the temperature is 100° C. or higher and 200° C. or lower. By forming the conductive films 120a and 120b, the crystallinity of the conductive films 120a and 120b can be improved. When a large glass substrate (e.g., 6th generation to 10th generation) is used as the plate 102, When the substrate temperature during the formation of the conductive films 120a and 120b is set to 150° C. or higher and lower than 340° C. In this case, the substrate 102 may be deformed (distorted or warped). In this case, the substrate temperature during the formation of the conductive films 120a and 120b is set to 100° C. or less. By setting the temperature to less than 150° C., deformation of the glass substrate can be suppressed.

[0223] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: 2:4.1 [atomic ratio]) to form conductive films 120a and 120b by sputtering. The substrate temperature during the formation of the conductive films 120a and 120b is set to 170° C. The deposition gas used for forming the conductive films 120a and 120b was oxygen at a flow rate of 100 sccm. Gas is used.

[0224] The conductive films 120a and 120b may be, for example, the oxide semiconductor film described above (e.g., For example, In:Ga:Zn=1:1:1 [atomic ratio], In:Ga:Zn=1:3:2 [atomic ratio] Atomic ratio], In:Ga:Zn=1:3:4 [Atomic ratio], In:Ga:Zn=1:3:6 [ [Atomic ratio], In:Ga:Zn=3:1:2 [Atomic ratio], In:Ga:Zn=4:2: 3 [atomic ratio], In:Ga:Zn=5:1:6 [atomic ratio], etc.) may be used.

[0225] In this embodiment, oxygen is added to the insulating film 116 when the conductive films 120a and 120b are formed. The method of adding is exemplified above, but is not limited to this. For example, After the formation of b, oxygen may be further added to the insulating film 116.

[0226] As a method for adding oxygen to the insulating film 116, for example, indium, tin, and silicon An oxide (also called ITSO) target having In2O3:SnO2:SiO2= 85:10:5 [wt %]) to form a 5 nm thick ITSO film as an oxide conductive film. Complete.

[0227] In this case, the thickness of the oxide conductive film is 1 nm or more and 20 nm or less, or 2 nm or more. A thickness of 10 nm or less is preferable because it allows suitable oxygen permeation and inhibits oxygen release. Then, oxygen is added to the insulating film 116 by passing through the oxide conductive film. Examples of the method include ion doping, ion implantation, and plasma treatment. When doping oxygen, a bias voltage is applied to the substrate side to effectively dissipate oxygen into the insulating film 116. The bias voltage can be, for example, applied to an ashing device. The power density of the bias voltage applied to the substrate side of the ashing device is 1 W / cm 2 More than 5W / cm 2 The substrate temperature during oxygen addition should be 300°C or higher than room temperature. C. or less, preferably 100.degree. C. to 250.degree. C., the insulating film 116 can be efficiently heated. Oxygen can be added.

[0228] Next, the formed conductive film is processed into a desired shape to form an island-shaped conductive film 120a and an island-shaped conductive film 120b. Then, a conductive film 120b having a rectangular shape is formed (see FIGS. 17(C) and (D)).

[0229] <Protective insulating film formation process> Next, an insulating film 118 is formed on the insulating film 116 and the conductive films 120a and 120b (FIG. 17(E)(F)).

[0230] The insulating film 118 contains either hydrogen or nitrogen, or both. For example, a silicon nitride film is preferably used as the insulating film 118. For example, it can be formed by using a sputtering method or a PECVD method. When the insulating film 118 is formed by the PECVD method, the substrate temperature is set to less than 400° C., preferably less than 375° C. C., and more preferably, the temperature is 180 to 350.degree. C. In this case, it is preferable to set the substrate temperature in the above-mentioned range since a dense film can be formed. By setting the substrate temperature in the above range when forming the insulating film 118, the insulating films 114 and 1 Therefore, oxygen or excess oxygen in the oxide semiconductor film 106 can be moved to the oxide semiconductor film 108.

[0231] After the insulating film 118 is formed, a heat treatment similar to the first heat treatment or the second heat treatment described above is performed. In this manner, the insulating film 118 may be heated to a temperature of 1000.degree. In the deposition of the insulating film 116, oxygen is added to the insulating film 116, and then the temperature is set to less than 400° C., preferably 375° C. By performing heat treatment at a temperature of less than 180°C and more preferably at a temperature of 180°C or more and 350°C or less, The oxygen or excess oxygen in the insulating film 116 is absorbed in the oxide semiconductor film 108 (particularly, the oxide semiconductor film 108 b) can be moved to fill oxygen vacancies in the oxide semiconductor film 108.

[0232] In addition, the insulating film 106 is provided below the insulating film 107, and the insulating films 114 and 11 An insulating film 118 is provided above the insulating films 106 and 118. By forming the insulating films 107, 114, and 116 from a thin material such as silicon nitride, Since the oxygen contained therein can be trapped on the oxide semiconductor film 108 side, the oxide semiconductor film 108 can be suitably oxidized. This allows oxygen to be transferred to the organic semiconductor film 108.

[0233] The insulating film 118 contains either hydrogen or nitrogen, or both. By forming the insulating film 118, the conductive films 120a and 120b in contact with the insulating film 118 are By adding either or both of hydrogen and nitrogen, the carrier density is increased, It can function as an oxide conductive film.

[0234] In addition, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, silicon It is preferable to use a deposition gas containing nitrile, nitrogen, and ammonia as the source gas. By using a small amount of ammonia compared to hydrogen, ammonia dissociates in the plasma and becomes active. The active species are generated by bonding with silicon and hydrogen contained in the silicon-containing deposition gas. This breaks the triple bond between silicon and nitrogen. As a result, the bond between silicon and nitrogen is promoted, It is possible to form a dense silicon nitride film with few silicon and hydrogen bonds and few defects. On the other hand, if the amount of ammonia relative to nitrogen is large, the deposition gas containing silicon and the nitrogen The decomposition of the silicon does not proceed, silicon and hydrogen bonds remain, and defects increase and the material becomes rough. For these reasons, the source gas is not suitable for ammonia. It is preferable that the flow rate ratio of nitrogen to oxygen is 5 times or more and 50 times or less, and more preferably 10 times or more and 50 times or less.

[0235] In this embodiment, the insulating film 118 is formed by depositing silane, nitrogen, etc., using a PECVD apparatus. A silicon nitride film with a thickness of 100 nm is formed using nitrogen and ammonia as source gases. The flow rates were 50 sccm for silane, 5000 sccm for nitrogen, and 100 for ammonia. The pressure in the processing chamber was 100 Pa, the substrate temperature was 350°C, and the flow rate was 27.12 MWh. A high-frequency power supply of 1000 W is supplied to the parallel plate electrodes. The device has an electrode surface area of ​​6000 cm 2 The parallel plate type PECVD equipment is The force can be converted to power per unit area (power density) of 1.7 x 10 -1 W / cm 2 is .

[0236] Through the above steps, the transistor 100J illustrated in FIGS.

[0237] In addition, in all the manufacturing steps of the transistor 100J, the substrate temperature is set to less than 400° C. The temperature is preferably less than 375°C, and more preferably 180°C to 350°C. This allows the deformation (warping or warping) of the substrate to be kept to a minimum even when using a substrate with a large thickness. In the manufacturing process of the transistor 100J, a process in which the substrate temperature is high Typically, the substrate temperature during the formation of the insulating films 106 and 107 is less than 400° C., preferably or 250° C. or higher and 350° C. or lower), and the substrate temperature during deposition of the oxide semiconductor film 108 (room temperature or higher At most 340°C, preferably at least 100°C but not more than 200°C, and more preferably at least 100°C 150° C.), the substrate temperature during deposition of the insulating films 116 and 118 (less than 400° C., preferably 375°C or less, more preferably 180°C or more and 350°C or less), the first heating step after adding oxygen Heat treatment or second heat treatment (less than 400°C, preferably less than 375°C, more preferably (180°C or higher and 350°C or lower).

[0238] <1-7. Transistor manufacturing method 2> Next, a manufacturing method of the transistor 100M which is a semiconductor device of one embodiment of the present invention will be described. 18 to 20 are used to explain the manufacturing method of a semiconductor device. 18(A)(C)(E), 19(A)(C), and 20(A) are cross-sectional views for explaining the above. ) is the channel length direction indicated by X1-X2, and FIG. 18(B), (D), (F), FIG. 20(D) and FIG. 20(B) are cross-sectional views in the channel width direction shown by Y1-Y2.

[0239] A conductive film 104, insulating films 106 and 107, an oxide semiconductor film 108, a conductive film 112_1, Electrical film 112a_2 (area 112a_2a, 112a_2b), conductive film 112b_2 (area 112b_2a, 112b_2b), the conductive film 112a_3, and the shape of the conductive film 112b_3 The method of forming the transistor 100J is the same as that of the transistor 100 described above. Please refer to 15.

[0240] In this embodiment, the conductive film 112_1 used for the conductive film 112 is 50 nm thick. tungsten film, a copper film having a thickness of 200 nm as the conductive film 112_1, and a conductive film 112_ A laminated film is used in which a 50 nm thick titanium film is laminated in this order as 3.

[0241] Next, the conductive films 112a_2, 112b_2, and 112_3 are used as masks to form the conductive film 112 By processing the conductive film 112a_1, the conductive film 112b is formed in an island shape. By carrying out this process, the conductive film 112a_1 and the conductive film 112a_2 (area A conductive film 112a having a conductive region 112a_2a, a conductive region 112a_2b, and a conductive film 112a_3 , conductive film 112b_1, conductive film 112b_2 (regions 112b_2a, 112b_2b) 18A and 18B, a conductive film 112b having a conductive film 112b_3 is formed (FIG. 18A). )reference).

[0242] The conductive films 112a and 112b are formed in the same manner as in the transistor 100J. It can be used.

[0243] Next, the insulating films 114 and 112 are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b. 18C, 18D, 18E, and 18F, the insulating film 11 is formed. The method for forming the transistors 4, 116, and 118 is the same as that for the transistor 100J. This can be done.

[0244] After the insulating film 118 is formed, a heat treatment similar to the first heat treatment or the second heat treatment described above is performed. In this manner, the insulating film 118 may be heated to a temperature of 1000.degree. In the deposition of the insulating film 116, oxygen is added to the insulating film 116, and then the temperature is set to less than 400° C., preferably 375° C. By performing heat treatment at a temperature of less than 180°C and more preferably at a temperature of 180°C or more and 350°C or less, The oxygen or excess oxygen in the insulating film 116 is absorbed in the oxide semiconductor film 108 (particularly, the oxide semiconductor film 108 b) can be moved to fill oxygen vacancies in the oxide semiconductor film 108.

[0245] Here, oxygen moving into the oxide semiconductor film 108 will be described with reference to FIG. FIG. 20 shows the relationship between the substrate temperature (typically less than 375° C.) during the formation of the insulating film 118 and the temperature of the insulating film The oxide semiconductor film 118 is then heated to a temperature of 375° C. or lower. 20 is a model diagram showing oxygen moving into the oxide semiconductor 108. The oxygen (oxygen radicals, oxygen atoms, or oxygen molecules) shown in the film 108 is represented by dashed arrows. is.

[0246] The oxide semiconductor film 108 shown in FIG. 20 is formed by insulating films (herein, In the case of the insulating film 107 and the insulating film 114, oxygen vacancies are filled by oxygen movement from the insulating film 107 and the insulating film 114. In particular, in the semiconductor device of one embodiment of the present invention, the oxide semiconductor film 108b is When forming the ring, oxygen gas is used to add oxygen to the insulating film 107. In addition, when the oxide conductive film is formed by sputtering, oxygen gas is used. Since oxygen is added to the insulating film 116, the insulating film 116 has an excess oxygen region. In addition, the oxide semiconductor film 108 sandwiched between the insulating films having the excess oxygen region has an oxygen vacancy. will be compensated.

[0247] Next, a mask is formed on the insulating film 118 by a lithography process, and the insulating films 114 and 11 An opening 152c is formed in a desired region of the conductive film 6, 118. It is formed so as to reach 112b (see Figures 19(A) and (B)).

[0248] Next, conductive films 120a and 120b are formed on the insulating film 116 so as to cover the opening 152c. As the conductive films 120a and 120b, a transistor A method similar to that for 100J can be used.

[0249] Through the above steps, the transistor 100M illustrated in FIG. 10C can be manufactured.

[0250] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0251] (Embodiment 2) In this embodiment, a composition of an oxide semiconductor that can be used in one embodiment of the present invention will be described. The structure of the oxide semiconductor and the like will be described with reference to FIGS.

[0252] <2-1. Composition of oxide semiconductor> First, the composition of the oxide semiconductor will be described.

[0253] The oxide semiconductor preferably contains at least indium or zinc. In addition to these, aluminum, gallium, and zinc are preferably included. It is preferable that the alloy contains boron, silicon, or yttrium. , titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Choose from titanium, neodymium, hafnium, tantalum, tungsten, or magnesium. The composition may contain one or more of the above-mentioned compounds.

[0254] Here, a case will be considered in which the oxide semiconductor contains indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Applicable elements for element M include boron, silicon, titanium, iron, nickel, and germanium. Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Tantalum However, the element M may be a combination of multiple of the above elements. There are cases where it is acceptable to combine them.

[0255] First, referring to FIG. 21(A), FIG. 21(B), and FIG. 21(C), one embodiment of the present invention will be described. Regarding the preferable range of the atomic ratio of indium, element M, and zinc contained in the oxide semiconductor, The atomic ratio of oxygen is not shown in FIG. 21. The atomic ratios of indium, element M, and zinc in the conductor are [In], [M ], and [Zn].

[0256] In Figures 21(A), 21(B), and 21(C), the dashed lines indicate the ratio of [In]:[M ]:[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):3, [I n]:[M]:[Zn]=(1+α):(1-α):4, and The line showing the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 is shown. vinegar.

[0257] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β is The line where the atomic ratio is 1:3:β, [In]:[M]:[Zn ]=1:4:β atomic ratio line, [In]:[M]:[Zn]=2:1:β atomic ratio line The line with the atomic ratio of [In]:[M]:[Zn]=5:1:β Represents in.

[0258] The dotted line indicates the atomic arrangement of [In]:[M]:[Zn]=(1+γ):2:(1-γ). The line where the ratio of [In]:[M]:[ Oxide semiconductors with an atomic ratio of Zn=0:2:1 or close to that have a spinel-type crystal structure. It is easy to make.

[0259] 21A and 21B show the indium-ion doped oxide semiconductor of one embodiment of the present invention. 1 shows an example of a preferable range of the atomic ratio of element M, element C, and zinc.

[0260] As an example, FIG. 22 shows InMZn where [In]:[M]:[Zn]=1:1:1. Figure 22 shows the crystal structure of InMZ when observed from a direction parallel to the b-axis. The crystal structure of nO4 is shown in FIG. 22. The metal element in the layer (Zn) represents element M or zinc. In this case, element M and zinc The proportion of lead is equal. The elements M and zinc are interchangeable and the arrangement is random. do.

[0261] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 22. The layer containing elements M, zinc, and oxygen (hereinafter referred to as the In layer) is 1. The (M,Zn) layer containing oxygen is layer 2.

[0262] Indium and element M can be substituted for each other. Therefore, the elements of the (M, Zn) layer The element M can be replaced with indium and expressed as an (In,M,Zn) layer. In that case, In It has a layered structure with one layer and two (In,M,Zn) layers.

[0263] In an oxide semiconductor with an atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer It has a layered structure with 1 (M,Zn) layer and 3 (M,Zn) layers. On the other hand, when [Zn] becomes large, when the oxide semiconductor crystallizes, the (M,Z n) layer proportion increases.

[0264] However, in the oxide semiconductor, the number of In layers is 1 and the number of (M, Zn) layers is a non-integer. In this case, there may be multiple types of layered structures in which the number of In layers is 1 and the number of (M, Zn) layers is an integer. For example, when [In]:[M]:[Zn]=1:1:1.5, the In layer is 1: The layered structure with two (M,Zn) layers and the layered structure with three (M,Zn) layers are mixed. In some cases, a layered structure may result.

[0265] For example, when an oxide semiconductor is formed by a sputtering device, the atomic ratio of the target In particular, depending on the substrate temperature during film formation, the target In some cases, the [Zn] of the film may be smaller than the [Zn] of the substrate.

[0266] In addition, a plurality of phases may coexist in an oxide semiconductor (eg, two-phase coexistence, three-phase coexistence, etc.). For example, in the atomic ratio [In]:[M]:[Zn]=0:2:1, which is close to the atomic ratio In [In], two phases, a spinel type crystal structure and a layered crystal structure, tend to coexist. At the atomic ratio near the atomic ratio of [M]:[Zn]=1:0:0, Two phases, a crystalline structure with a silicide layer and a layered crystalline structure, tend to coexist. When these coexist, grain boundaries form between different crystal structures. may be formed.

[0267] In addition, by increasing the indium content, the carrier mobility (electron transfer) of the oxide semiconductor is improved. This is because the oxide semiconductor having indium, element M and zinc can be In conductors, the s-orbitals of heavy metals mainly contribute to carrier conduction, and the indium content By increasing the indium content, the area where the s orbitals overlap becomes larger. Oxide semiconductors with a high indium content have a higher carrier mobility than oxide semiconductors with a low indium content. This is because

[0268] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0, and In the atomic ratios near this value (for example, region C shown in FIG. 21(C)), the insulating properties become high. .

[0269] Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility and few grain boundaries. It is preferable that the atomic ratio is shown in region A in FIG. 21(A), which is likely to form a layer structure having a good atomic ratio. It is nice.

[0270] In addition, in the region B shown in FIG. 21B, [In]:[M]:[Zn]=4:2:3 to 4 .1 and its neighboring values. For example, the atomic ratio [In]:[M ]:[Zn]=5:3:4. Oxide semiconductors having the atomic ratio shown in region B In particular, it is an excellent oxide semiconductor having high crystallinity and high carrier mobility.

[0271] The condition for an oxide semiconductor to form a layered structure is not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. However, depending on the formation conditions, a layered structure may or may not be formed. The illustrated region is a region showing the atomic ratio in which the oxide semiconductor has a layered structure. The boundaries between areas A and C are not strict.

[0272] <2-2. Structure using oxide semiconductor in transistor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0273] Note that by using the oxide semiconductor in a transistor, carrier scattering at grain boundaries and other problems can be prevented. This allows the realization of transistors with high field effect mobility. In addition, a highly reliable transistor can be realized.

[0274] In addition, an oxide semiconductor with low carrier density is preferably used for the transistor. For example, oxide semiconductors have a carrier density of 8×10 11 / cm 3 Less than 1x1 0 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That should be enough.

[0275] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a carrier generation source. Since the carrier density is low, the carrier density can be reduced. Intrinsic oxide semiconductors have a low density of defect states and therefore a low density of trap states. There are cases.

[0276] In addition, the time required for the charge trapped in the trap level of the oxide semiconductor to disappear is Therefore, the trap level density is high. In a transistor in which a channel region is formed in a thin oxide semiconductor, the electrical characteristics may become unstable. There is a match.

[0277] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In order to reduce the impurity concentration in the oxide semiconductor, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0278] Here, the influence of each impurity in an oxide semiconductor will be described.

[0279] When oxide semiconductors contain silicon or carbon, which is one of the group 14 elements, they become oxidized. Defect levels are formed in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (secondary ion mass spectrometry) (SIMS: Secondary Ion Mass Spectrometry) The concentration that can be obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0280] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, the defect level is reduced. Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such an element tends to be normally-on. Therefore, it is possible to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, it is preferable to use an alkali metal or The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0281] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and The nitrogen density increases and it becomes easier to make the oxide semiconductor n-type. Therefore, the transistor used in the oxide semiconductor In this case, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen content in the oxide semiconductor is The concentration is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Below, More preferably 5×10 17 atoms / cm 3 The following applies.

[0282] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the carrier, In some cases, hydrogen atoms are formed by bonding with oxygen atoms that bond with metal atoms. Therefore, it is necessary to use an oxide semiconductor that contains hydrogen. Therefore, the hydrogen in the oxide semiconductor tends to cause a transistor to be normally on. It is preferable that the Si content in the oxide semiconductor is as low as possible. The hydrogen concentration obtained by MS is 1×10 20 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 Less than.

[0283] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, This makes it possible to impart stable electrical characteristics.

[0284] <2-3. Stacked structure of oxide semiconductors> Next, the case where the oxide semiconductor has a two-layer structure or a three-layer structure will be described. The insulating layer in contact with the stacked structure of the compound semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S3 is The band diagram and the band of the insulator in contact with the stacked structure of the oxide semiconductor S2 and the oxide semiconductor S3 are shown. The diagram will be explained with reference to FIG.

[0285] FIG. 23A shows an insulator I1, an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S FIG. 23 is an example of a band diagram in the thickness direction of a laminated structure having an insulator I2 and an insulator I3. (B) has an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. 1 is an example of a band diagram in the film thickness direction of a laminated structure. Note that the band diagram is shown in FIG. Insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3, and insulator I2 The energy level (Ec) at the bottom of the conduction band of

[0286] The oxide semiconductors S1 and S3 have a lower energy at the conduction band edge than the oxide semiconductor S2. The energy level is close to the vacuum level, typically the energy level at the bottom of the conduction band of the oxide semiconductor S2. The difference between the energy level of the oxide semiconductor S1 and the energy level of the oxide semiconductor S3 at the bottom of the conduction band is 0 .15eV or more, or 0.5eV or more and 2eV or less, or 1eV or less In other words, the oxide semiconductor S1 and the oxide semiconductor S3 have a higher electron affinity than the oxide semiconductor S2. The electron affinity of the oxide semiconductor S2 is large, and the electron affinity of the oxide semiconductor S1 and the oxide semiconductor S3 is and the electron affinity of the oxide semiconductor S2 is 0.15 eV or more, or 0.5 eV or more. , and is preferably 2 eV or less, or 1 eV or less.

[0287] As shown in FIG. 23(A) and FIG. 23(B), an oxide semiconductor S1, an oxide semiconductor S 2. In the oxide semiconductor S3, the energy level at the bottom of the conduction band changes gradually. In other words, it can be said that the band changes continuously or that the junction is continuous. In order to have the above, the interface between the oxide semiconductor S1 and the oxide semiconductor S2 or the oxide semiconductor When the defect level density of the mixed layer formed at the interface between S2 and the oxide semiconductor S3 is reduced, good.

[0288] Specifically, the oxide semiconductor S1 and the oxide semiconductor S2, the oxide semiconductor S2 and the oxide semiconductor S3 S3 has a common element other than oxygen (as the main component), so that the defect level density is low. For example, when the oxide semiconductor S2 is an In-Ga-Zn oxide semiconductor, In the case of the body, the oxide semiconductor S1 and the oxide semiconductor S3 are In-Ga-Zn oxide semiconductors. , Ga-Zn oxide semiconductor, gallium oxide, or the like may be used.

[0289] At this time, the main carrier path is the oxide semiconductor S2. Defects at the interface with the oxide semiconductor S2 and the interface between the oxide semiconductor S2 and the oxide semiconductor S3 Since the density of recessed levels can be reduced, the effect of interface scattering on carrier conduction is small. , a high on-current can be obtained.

[0290] When an electron is captured in a trap level, the captured electron behaves like a fixed charge. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing the oxide semiconductor S3, the trap level is moved away from the oxide semiconductor S2. By adopting this configuration, the threshold voltage of the transistor can be shifted in the positive direction. This can prevent the device from being damaged.

[0291] The oxide semiconductors S1 and S3 have sufficient electrical conductivity compared to the oxide semiconductor S2. In this case, the oxide semiconductor S2 and the oxide semiconductor S The interface between the oxide semiconductor S1 and the oxide semiconductor S2 and the oxide semiconductor S3 are mainly the channel region. For example, the oxide semiconductor S1 and the oxide semiconductor S3 have the following structure as shown in FIG. In this case, an oxide semiconductor having an atomic ratio shown in region C where the insulating property is high may be used. Region C shown in FIG. 21(C) is [In]:[M]:[Zn]=0:1:0 or its vicinity. The atomic ratios shown are the atomic ratios.

[0292] In particular, when an oxide semiconductor having an atomic ratio shown in region A is used for the oxide semiconductor S2, In the compound semiconductor S1 and the oxide semiconductor S3, [M] / [In] is 1 or more, preferably 2 It is preferable to use an oxide semiconductor having a conductivity of at least 100 nm. Oxides with [M] / ([Zn]+[In]) of 1 or more that can provide high insulating properties It is preferable to use a semiconductor.

[0293] <2-4. Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0294] Oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Nanocrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconducting ductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor) and amorphous oxide semiconductor. be.

[0295] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductors, and nc-OS.

[0296] Amorphous structures are generally isotropic and have no inhomogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The positions are not fixed, the bond angles are flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0297] That is, a stable oxide semiconductor is transformed into a completely amorphous s) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, it has a periodic structure in a small area). An oxide semiconductor having an Al structure cannot be called a completely amorphous oxide semiconductor. ike OS is not isotropic, but has an unstable structure with voids. In terms of instability, the a-like OS is physically similar to an amorphous oxide semiconductor. stomach.

[0298] <CAAC-OS> First, let me explain about CAAC-OS.

[0299] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0300] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals was analyzed by the out-of-plane method. As shown in FIG. 24(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so In this case, the crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be confirmed that the direction is perpendicular to the surface of the crystal, or perpendicular to the surface of the crystal. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The nearby peak is due to a crystal structure classified into the space group Fd-3m. It is preferred that the C-OS does not exhibit such a peak.

[0301] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS in a direction parallel to the surface on which the X-ray is to be formed. When structural analysis was performed using the ane method, a peak appeared at 2θ of approximately 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. Then, the sample is rotated around the normal vector of the sample surface as an axis (φ axis) while analyzing (φ scan). Even if this is done, no clear peak appears as shown in FIG. 24(B). On the other hand, single crystal InGa When 2θ is fixed at around 56° and φ is scanned for ZnO4, the results shown in Figure 24(C) As shown in the figure, six peaks attributable to crystal planes equivalent to the (110) plane are observed. XRD structural analysis revealed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0302] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was parallel to the CAAC-OS surface. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern ( This is also called a selected area electron diffraction pattern.) may appear. This diffraction pattern includes I The spots are due to the (009) plane of the nGaZnO4 crystal. Diffraction also confirmed that the pellets contained in the CAAC-OS have a c-axis orientation and that the c-axis is the unformed On the other hand, for the same sample, the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly to the ) is shown. From FIG. 24(E), a ring-shaped diffraction pattern is confirmed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the PEG-1000 nanometers in the CAAC-OS It can be seen that the a-axis and b-axis of the slits have no orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. The second ring in Fig. 24(E) is thought to be due to the (110) plane. It is thought that.

[0303] In addition, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope. When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. (also called underly.) may not be clearly identified. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0304] Figure 25(A) shows a high-resolution cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. A spherical aberration correction (SCA) was used for high-resolution TEM imaging. The spherical aberration corrector function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. Therefore, it can be observed.

[0305] From FIG. 25(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. The size of each pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used as a C-Axis Aligned Navigator (CANC). The pellets can also be called oxide semiconductors with no crystals. The C-OS film reflects the unevenness of the surface on which it is formed or the top surface, and the CAAC-OS film Or parallel to the top surface.

[0306] In addition, Fig. 25(B) and Fig. 25(C) show CAA images observed from a direction approximately perpendicular to the sample surface. Cs-corrected high-resolution TEM images of the C-OS surface. 25(B) and 25(C), respectively. First, the processing method of FIG. 25(B) is Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the acquired FFT image, the origin is used as the reference point, and the -1 From 5.0 nm -1 The range between Next, the masked FFT image is transformed by inverse fast Fourier transform (IFFT : Inverse Fast Fourier Transform) processing is used to The image obtained in this way is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. This indicates a child array.

[0307] In FIG. 25(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area indicated by the dashed line is the connection between the pellets. The broken line shows the hexagonal shape, so we can see that the pellet is hexagonal. The shape of the let is not limited to a regular hexagon, and is often a non-regular hexagon.

[0308] In FIG. 25(E), a dot is drawn between an area with a uniform lattice arrangement and an area with a different uniform lattice arrangement. The grain boundaries are shown by dotted lines. Even in the vicinity of the dotted lines, no clear crystal grain boundaries can be confirmed. When connecting the surrounding lattice points with a nearby lattice point at the center, a distorted hexagon, pentagon, or / and heptagon is formed. In other words, the formation of grain boundaries can be suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is dense in the ab-plane direction. The substitution of metal elements changes the bond distance between atoms. , it is believed that this is because distortion can be tolerated.

[0309] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called lane-anchored crystal.

[0310] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is determined by the presence of impurities. CAAC-OS is designed to prevent impurities and defects from causing degradation. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0311] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0312] ≪nc-OS≫ Next, we will explain nc-OS.

[0313] The following describes the case where nc-OS is analyzed by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0314] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region of m, the result shown in Fig. 2 A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in FIG. 6(A) was observed. In addition, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample ( The nanobeam electron diffraction pattern is shown in Figure 26(B). Therefore, the nc-OS has a probe diameter of 50 nm. No order was observed when an electron beam with a probe diameter of 1 nm was incident. When light is incident on it, order is confirmed.

[0315] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 26(C), an electron diffraction pattern was observed in which the spots were arranged in a substantially regular hexagonal shape. Therefore, it is considered that the nc-OS is ordered in the range of thickness less than 10 nm. It can be seen that the crystals are highly ordered. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0316] FIG. 26(D) shows the Cs-corrected height of the cross section of the nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image as the area indicated by the auxiliary lines. How to identify the crystals and the areas where no clear crystals can be identified The crystal parts in the nc-OS have a size of 1 nm to 10 nm. In particular, the size of the crystals is often between 1 nm and 3 nm. An oxide semiconductor having a size of 10 nm or more and 100 nm or less is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). o crystalline oxide semiconductor) For example, in the case of nc-OS, the grain boundaries are often not clearly visible in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be referred to as a pellet.

[0317] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, particularly The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the Cr-Al-Al-Fe-Al-Fe-O-Pb-Al-Zn ... Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0318] In addition, since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is , oxidation with RANC (Random Aligned nanocrystals) Semiconductors or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor has a conductivity of 1000.

[0319] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0320] ≪a-like OS≫ The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0321] FIG. 27 shows a high-resolution cross-sectional TEM image of the a-like OS. is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. B) is 4.3 x 10 8 e - / nm 2 Electrons (e - ) A-like OS after irradiation High-resolution cross-sectional TEM images. Figures 27(A) and 27(B) show that a-like O It can be seen that striped bright regions extending in the vertical direction are observed in S from the start of electron irradiation. It can also be seen that the shape of the bright regions changes after electron irradiation. It is suspected to be a density region.

[0322] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0323] As samples, a-like OS, nc-OS and CAAC-OS are prepared. Both samples are In-Ga-Zn oxides.

[0324] First, high-resolution cross-sectional TEM images of each sample are obtained. All of the materials have crystalline parts.

[0325] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers in the c-axis direction. The distance between these adjacent layers is the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is called InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0326] Figure 28 shows an example of the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes is the size of the crystal part. e. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. From Figure 28, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that grew up (also called the initial nucleus) absorbs electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the n For c-OS and CAAC-OS, the cumulative electron irradiation dose was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of 100 to 150 mm. Therefore, the size of the crystalline parts of nc-OS and CAAC-OS is constant regardless of the cumulative dose of electron irradiation. , and 1.3 nm and 1.8 nm, respectively. The Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The conditions were an acceleration voltage of 300 kV and a current density of 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter of the region was set to 230 nm.

[0327] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. That is, a-like OS is not seen in comparison with nc-OS and CAAC-OS. , it is clear that this is an unstable structure.

[0328] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0329] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 Less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0330] If single crystals of the same composition are not available, single crystals of different compositions may be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions. However, the density can be estimated by using as few types of single crystals as possible. A combined estimate is preferred.

[0331] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0332] <2-5. Carrier density of oxide semiconductors> Next, the carrier density of an oxide semiconductor will be described below.

[0333] Factors that affect the carrier density of oxide semiconductors include oxygen vacancies in the oxide semiconductor. (Vo), or impurities in the oxide semiconductor.

[0334] When the number of oxygen vacancies in an oxide semiconductor increases, hydrogen bonds to the oxygen vacancies (this state is called VoH When the oxide semiconductor is filled with impurities, the density of defect states increases. In this case, the density of defect states due to the impurities increases. By controlling the density of states, the carrier density of the oxide semiconductor can be controlled.

[0335] Here, a transistor in which an oxide semiconductor is used for a channel region will be considered.

[0336] Suppression of negative shift of the threshold voltage of a transistor or suppression of off-current of a transistor In order to reduce the carrier density of the oxide semiconductor, it is preferable to reduce the carrier density of the oxide semiconductor. In order to reduce the carrier density of an oxide semiconductor, the impurity concentration in the oxide semiconductor must be increased. In the present specification and the like, the impurity concentration is low, and the defect level density is low. A low density of defect states is called high purity intrinsic or substantially high purity intrinsic. The carrier density of a quartz semiconductor is 8×10 15 cm -3 Less than 1 x 10 1 1 cm -3 less than 1×10 10cm -3 Less than 1 x 10 -9 cm -3 That should be enough.

[0337] On the other hand, the improvement of the on-state current of a transistor or the field effect mobility of a transistor In that case, it is preferable to increase the carrier density of the oxide semiconductor. In order to increase the carrier density of a nitride semiconductor, the impurity concentration of the oxide semiconductor must be increased slightly. Alternatively, the density of defect states in the oxide semiconductor may be increased slightly. It is advantageous to make the band gap of the compound semiconductor smaller. For example, the Id-V In the range where the on / off ratio of the g characteristic can be obtained, the impurity concentration is slightly high or the defect level is low. Oxide semiconductors with slightly higher potential density can be considered essentially intrinsic. As a result, the band gap becomes smaller, and the number of thermally excited electrons ( An oxide semiconductor with an increased density of carriers can be considered to be essentially intrinsic. When an oxide semiconductor having a large charge is used, the threshold voltage of a transistor is lowered. do.

[0338] The oxide semiconductor with the increased carrier density is slightly n-type. Therefore, oxide semiconductors with increased carrier density can be called "slightly-n". good.

[0339] The carrier density of a substantially intrinsic oxide semiconductor is 1×10 5 cm -3 More than 1×10 18 cm -3 Less than 1×10 is preferable. 7 cm -3 More than 1×10 17 cm-3 The following is preferred: 1×10 9 cm -3 5×10 or more 16 cm -3 More preferably, 1×10 1 0 cm -3 More than 1×10 16 cm -3 More preferably, 1×10 11 cm -3 End 1×10 15 cm -3 The following is even more preferred:

[0340] The configuration shown in this embodiment may be appropriately combined with configurations shown in other embodiment modes or examples. , can be used in combination.

[0341] (Embodiment 3) In this embodiment, a display device including the transistor described in the above embodiment will be An example will be described below with reference to FIGS.

[0342] Fig. 29 is a top view showing an example of a display device. The display device 700 shown in Fig. 29 is a first A pixel portion 702 is provided on the first substrate 701, and a source driver is provided on the first substrate 701. A pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, A sealant 712 is disposed so as to surround the path portion 704 and the gate driver circuit portion 706. and a second substrate 705 disposed so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 29, a display element is provided between the first substrate 701 and the second substrate 705. can be done.

[0343] The display device 700 is surrounded by a sealant 712 on the first substrate 701. In a region different from the region, a pixel section 702, a source driver circuit section 704, a gate driver circuit section FPC terminals electrically connected to the path portion 706 and the gate driver circuit portion 706, A sub-unit 708 (FPC: Flexible printed circuit) is provided. In addition, an FPC 716 is connected to the FPC terminal portion 708. Various signals are supplied to the element section 702, the source driver circuit section 704, and the gate driver circuit section 706. In addition, a pixel section 702, a source driver circuit section 704, a gate driver circuit section A signal line 710 is connected to the path portion 706 and the FPC terminal portion 708. Various signals supplied from 716 are transmitted through signal lines 710 to the pixel section 702, the source driver 716, and the like. 704, a gate driver circuit section 706, and an FPC terminal section 708. do.

[0344] The display device 700 may include a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is formed on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead, we use COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0345] The display device 700 also includes a pixel portion 702, a source driver circuit portion 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0346] The display device 700 can also include various elements, such as: For example, electroluminescence (EL) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (light-emitting elements that emit light according to electric current) transistors, electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, Wetting element, plasma display (PDP), MEMS (microelectromechanical systems) Toro Mechanical Systems) displays (e.g., grating light valves (G LV), Digital Micromirror Device (DMD), Digital Micro Shutter (DMS) elements, interferometric modulation (IMOD) elements, etc.) , piezoelectric ceramic displays, etc.

[0347] An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductio n Electron-emitter Display) and others. An example of such a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Display, reflective LCD display, direct-view LCD display, projection LCD display Examples of display devices using electronic ink elements or electrophoretic elements include: Electronic paper. Semi-transmissive LCDs and reflective LCDs are also used. In this case, a part or the whole of the pixel electrode should function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This can further reduce power consumption.

[0348] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying in color are R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a pixel, and a pixel of white (W). As in the column, two colors of RGB compose one color element, and two different colors are created by the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. may be selected for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, and may be used with monochrome displays. The present invention can also be applied to display devices such as those shown in FIG.

[0349] Also, white light is emitted from the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) In order to display full color using (W), a colored layer (also called a color filter) is The colored layer may be, for example, red (R), green (G), blue (B), or red (C). ), yellow (Y), etc. can be used in appropriate combination. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a color layer and a region not having a color layer, The white light in the region may be directly used for display. By placing the colored layer over the entire display, the decrease in brightness caused by the colored layer can be reduced during bright display, and power consumption can be reduced by 2. However, in some cases, the emission of light from organic EL elements and inorganic EL elements can be reduced by about 10 to 30%. When using optical elements to display full color, R, G, B, Y, and W are each emitted in different colors. By using a self-luminous element, it is possible to obtain a light emission from a colored layer. In some cases, power consumption can be reduced even further.

[0350] In addition, as a colorization method, a part of the light emitted from the above-mentioned white light is passed through a color filter. In addition to the color filter method, which converts the light into red, green, and blue by filtering the light, A method that uses two colors of light (three-color method), or a method that uses part of the light emitted from the blue light to emit red or A method for converting to green (color conversion method, quantum dot method) may be applied.

[0351] In this embodiment, a liquid crystal element and an EL element are used as display elements. 30 and 32. Note that FIG. 30 shows the state of the circuit shown in FIG. FIG. 32 is a cross-sectional view of the liquid crystal display device shown in FIG. 29 is a cross-sectional view taken along the dashed line QR shown in FIG. 29, and shows a configuration in which an EL element is used as a display element. It is.

[0352] First, the common parts shown in FIG. 30 and FIG. 32 will be explained, and then the different parts will be explained. This will be explained below.

[0353] <3-1. Explanation of common parts of display devices> The display device 700 shown in FIG. 30 and FIG. 32 includes a wiring portion 711 and a pixel portion 702. The display panel 700 includes a source driver circuit section 704 and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Yes.

[0354] Transistor 750 and transistor 752 are similar to transistor 100 shown above. The structures of the transistors 750 and 752 are the same as those described above. Any other transistors than those shown in the embodiment modes may be used.

[0355] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. It is possible to extend the retention time of electrical signals such as signals, and the write interval can be extended when the power is on. This allows the frequency of refresh operations to be reduced, resulting in reduced power consumption. It has the effect of suppressing power.

[0356] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section In other words, the driver transistor can be formed on the same substrate as the driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, a high quality image can be provided.

[0357] The capacitor 790 includes a conductive film that functions as a first gate electrode of the transistor 750. The lower electrode formed through a process of processing the same conductive film and the Through a process of processing the same conductive film as the conductive film that functions as the source electrode and the drain electrode, and an upper electrode formed on the lower electrode. A step of forming an insulating film identical to the insulating film functioning as the first gate insulating film of 750. That is, the capacitor 790 is formed by forming an insulating film between a pair of electrodes. It has a laminated structure in which an insulating film that functions as a conductor film is sandwiched.

[0358] 30 and 32, a transistor 750, a transistor 752, and a capacitor A planarization insulating film 770 is provided on the capacitor 790 .

[0359] The planarization insulating film 770 may be made of a polyimide resin, an acrylic resin, or a polyimide amide resin. Heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin In addition, by stacking multiple insulating films made of these materials, A planarization insulating film 770 may be formed. Alternatively, the planarization insulating film 770 may not be provided. This is also fine.

[0360] 30 and 32, the transistor 750 and the A transistor having the same structure as the transistor 752 included in the source driver circuit portion 704 is used. The configuration used is illustrated above, but is not limited to this. For example, A transistor different from that in the driver circuit section 704 may be used. 02 is a staggered transistor, and the source driver circuit portion 704 is In the pixel portion 702, an inverted staggered transistor is used. A reverse staggered transistor is used, and a staggered transistor is provided in the source driver circuit section 704. The source driver circuit section 704 may be configured as a gate driver. It may also be read as a driver circuit section.

[0361] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed through the same process as the conductive film that functions as the signal line 710. When materials containing this material are used, signal delays caused by wiring resistance are minimal, making it possible to display images on a large screen. It becomes Noh.

[0362] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed through the same process as the conductive film that functions as the drain electrode. , and is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780 .

[0363] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0364] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. A device for controlling the distance (cell gap) between the first substrate 701 and the second substrate 705 is provided. In addition, a spherical spacer may be used as the structure 778.

[0365] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and A colored film 736 that functions as a color filter, a light-shielding film 738 that is in contact with the colored film 736, and An insulating film 734 is provided.

[0366] <3-2. Configuration examples of display devices using liquid crystal elements> The display device 700 shown in FIG. 30 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is a second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. By controlling the light transmission or non-transmission, an image can be displayed.

[0367] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770. The conductive film 772 functions as a pixel electrode, that is, one electrode of a display element. The display device 700 shown in FIG. 72 reflects light and displays it through a colored film 736, so-called a reflective color liquid crystal display device. be.

[0368] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a reflectivity can be used. For example, a material containing one of the elements indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed of A conductive film that is reflective in visible light is used.

[0369] In FIG. 30, the conductive film 772 functions as a drain electrode of the transistor 750. However, the present invention is not limited to this. For example, the structure shown in FIG. As shown in FIG. 1, a conductive film 772 is sandwiched between a conductive film 777 serving as a connection electrode and a transistor. The drain electrode of the transistor 750 may be electrically connected to the conductive film. Note that the conductive film 777 functions as a second gate electrode of the transistor 750. Since it is formed through the same process of processing the conductive film as the conductive film used, there is no need to add any additional manufacturing steps. It can be formed.

[0370] The display device 700 shown in FIG. 30 is a reflective color liquid crystal display device. However, the present invention is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. Alternatively, a reflective color liquid crystal display device may be used. A so-called semi-transmissive color liquid crystal display is a combination of a transmissive color liquid crystal display. The display device may be a liquid crystal display device.

[0371] An example of a transmission type color liquid crystal display device is shown in FIG. 33. FIG. 33 shows the same as that shown in FIG. This is a cross-sectional view taken along the dashed line QR, and shows a configuration in which liquid crystal elements are used as display elements. In addition, the display device 700 shown in FIG. 33 uses a horizontal electric field method (for example, F In the configuration shown in FIG. 33, the pixel electrode functions as An insulating film 773 is provided over a conductive film 772, and a conductive film 774 is provided over the insulating film 773. In this case, the conductive film 774 functions as a common electrode. An electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773 causes the liquid The orientation of the crystal layer 776 can be controlled.

[0372] Although not shown in FIGS. 30 and 33, the conductive film 772 or the conductive film 774 An alignment film is provided on either one or both of the surfaces of the liquid crystal layer 776. Although not shown in FIG. 30 and FIG. 33, a polarizing member, a phase difference member, a reflecting member, etc. Optical members (optical substrates) such as a polarizing substrate and a positioning member may be provided as appropriate. Circularly polarized light produced by a retardation substrate may be used. Either may be used.

[0373] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0374] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is used in the liquid crystal layer. The response speed is short, and since it is optically isotropic, no alignment treatment is required. Since rubbing is unnecessary, the electrostatic discharge caused by rubbing is eliminated. It is possible to prevent damage and reduce defects and damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials that exhibit a blue phase have little viewing angle dependency.

[0375] In addition, when liquid crystal elements are used as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr Electrochemical Liquid Crystal (ECC) mode can be used. .

[0376] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode mode, ASV mode, etc. can be used.

[0377] <3-3. Display devices using light-emitting elements> The display device 700 shown in FIG. 32 includes a light-emitting element 782. The light-emitting element 782 is a conductive film The display device 700 shown in FIG. The EL layer 786 of the light element 782 emits light, thereby displaying an image. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0378] Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, In addition, the elements of the 12th and 16th families, the 13th and 15th families, or the 14th and 16th families Materials containing the element group may also be used. Cadmium (Cd), selenium (Se), Zinc (Zn), Sulfur (S), Phosphorus (P), Indium (In), Tellurium (Te), Lead (P b) Quantum with elements such as gallium (Ga), arsenic (As), aluminum (Al), etc. Dot material may also be used.

[0379] In addition, in the display device 700 shown in FIG. An insulating film 730 is provided. The insulating film 730 covers a part of the conductive film 772. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits the light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to this. For example, a bottom emission structure in which light is emitted to both the conductive film 772 and the conductive film 788; It can also be applied to al-emission structures.

[0380] A colored film 736 is provided at a position overlapping the light emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided at the position where the light-shielding film 738 is to be formed, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is illustrated. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0381] <3-4. Example of a configuration in which an input / output device is provided on a display device> Also, an input / output device may be provided in the display device 700 shown in FIG. An example of the force device is a touch panel.

[0382] 34 and 35, a structure in which a touch panel 791 is provided on the display device 700 shown in FIG. 32 and FIG. 33 is shown. This is shown in Figure 35.

[0383] FIG. 34 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. FIG. 35 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. be.

[0384] First, the touch panel 791 shown in FIG. 34 and FIG. 35 will be described below.

[0385] The touch panel 791 shown in FIG. 34 and FIG. 35 is provided between a substrate 705 and a colored film 736. The touch panel 791 is a so-called in-cell type touch panel. 736 may be formed on the substrate 705 side before the colored film 736 is formed.

[0386] The touch panel 791 includes a light-shielding film 738, an insulating film 792, an electrode 793, and an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. When a detection object such as a stylus approaches, the mutual capacitance between electrode 793 and electrode 794 changes. It is possible to detect the change.

[0387] 34 and 35, an electrode 793 and The electrode 796 is formed by passing through an opening in the insulating film 795. The electrode 794 is electrically connected to the two electrodes 793 that sandwich the electrode 794 via the electrodes 793. 35, a configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702 is illustrated. However, the present invention is not limited to this. For example, the light emitting diode 704 may be formed in the source driver circuit section 704.

[0388] The electrodes 793 and 794 are provided in a region overlapping with the light-shielding film 738. As shown in FIG. 1, the electrode 793 is preferably provided so as not to overlap with the light-emitting element 782. In addition, as shown in FIG. 35, the electrode 793 is provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 overlaps with the light-emitting element 782 and the liquid crystal element 775. In other words, the electrode 793 has a mesh shape. By this configuration, the electrode 793 does not block the light emitted by the light emitting element 782. Alternatively, the electrode 793 may be configured so as not to block light passing through the liquid crystal element 775. Therefore, the reduction in brightness due to the placement of the touch panel 791 is extremely small. Since the number of pixels is small, a display device with high visibility and reduced power consumption can be realized. The pole 794 may be of a similar configuration.

[0389] In addition, since the electrodes 793 and 794 do not overlap with the light-emitting element 782, The electrode 794 may be made of a metal material having a low transmittance of visible light. Since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, In addition, a metal material having a low transmittance of visible light can be used.

[0390] Therefore, compared with electrodes using oxide materials with high visible light transmittance, the electrodes 793 and The resistance of the electrode 794 can be reduced, improving the sensor sensitivity of the touch panel. It is possible.

[0391] For example, the electrodes 793, 794, and 796 may be made of conductive nanowires. The nanowires have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm. The size of the nanoparticles may be 5 nm or less, and more preferably 5 nm or more and 25 nm or less. The wires are metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires. For example, electrodes 793 and 794 may be used. When Ag nanowires are used for either 94 or 796, or for all of them, the The light transmittance is to be 89% or more, and the sheet resistance is to be 40Ω / □ or more and 100Ω / □ or less. can.

[0392] 34 and 35 show an example of the configuration of an in-cell type touch panel. However, the present invention is not limited to this. For example, a so-called on-cell type transistor formed on the display device 700 may be used. A so-called out-cell type touch panel that is attached to the display device 700. It is also possible to use the following.

[0393] In this manner, the display device according to one embodiment of the present invention can be used in combination with various types of touch panels. It can be used.

[0394] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0395] (Embodiment 4) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0396] <4. Circuit configuration of display device> The display device shown in FIG. 36(A) has a region having pixels of a display element (hereinafter, referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504) and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. This is also fine.

[0397] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Band). It can be implemented by using the onding.

[0398] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter, referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter, a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a) to supply a signal (data signal) for driving the display element of the pixel. The pixel circuit 504 includes a driver circuit such as a circuit (hereinafter, referred to as a source driver 504b).

[0399] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via a terminal unit 507, and a signal is output. For example, a start pulse signal, a clock signal, etc. are input to the gate driver 504a. The gate driver 504a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it. However, the gate driver 50 has a function of supplying 4a may also provide another signal.

[0400] The source driver 504b includes a shift register and the like. Through the terminal section 507, a signal for driving the shift register as well as a source of a data signal are input. The source driver 504b outputs a pixel circuit based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data line 101 through the data line 102. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0401] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a number of analog switches, The image signal can be time-division-multiplexed and output as a data signal. Also, a shift register, etc. This may be used to configure the source driver 504b.

[0402] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is inputted through the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or smaller than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via a source driver 504c (n is a natural number equal to or smaller than Y).

[0403] The protection circuit 506 shown in FIG. 36(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit 506 may be a wiring between the source driver 504b and the terminal unit 507. The terminal unit 507 can be connected to a power supply and a power supply line from an external circuit to the display device. This refers to the part provided with terminals for inputting control signals and image signals.

[0404] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0405] As shown in FIG. 36A, a protection circuit 50 is provided in each of a pixel section 502 and a driver circuit section 504. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrent caused by electrostatic discharge (ESD) and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal portion 507. It can also be done like this.

[0406] In FIG. 36(A), the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit is formed separately. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is It may also be configured to be equipped with

[0407] In addition, the pixel circuits 501 shown in FIG. 36(A) may have a configuration shown in FIG. 36(B), for example. It can be said that:

[0408] The pixel circuit 501 shown in FIG. 36B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiment. can be applied.

[0409] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0410] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of different types of sensors can be used.

[0411] In the pixel circuit 501 in the mth row and the nth column, One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scan lines G The transistor 550 is electrically connected to the data signal writing terminal L_m. It has the function of controlling.

[0412] One of a pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0413] For example, in a display device having the pixel circuit 501 shown in FIG. The pixel circuits 501 in each row are sequentially selected by a gate driver 504a shown in FIG. 550 is turned on to write data of the data signal.

[0414] In the pixel circuit 501 in which data has been written, the transistor 550 is turned off. By repeating this process row by row, an image can be displayed.

[0415] In addition, the pixel circuits 501 shown in FIG. 36(A) may have a configuration shown in FIG. 36(C), for example. It can be said that:

[0416] The pixel circuit 501 shown in FIG. 36C includes transistors 552 and 554 and a capacitance element. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either or both of the above. .

[0417] A data signal is applied to one of the source and drain electrodes of the transistor 552. The transistor 55 is electrically connected to a wiring (hereinafter, referred to as a signal line DL_n). The gate electrode of 2 is electrically connected to the wiring (hereinafter referred to as the scanning line GL_m) to which the gate signal is applied. are connected to the network.

[0418] The transistor 552 has a function of controlling writing of data signals.

[0419] One of a pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0420] The capacitor 562 functions as a storage capacitor for storing written data.

[0421] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. In addition, the gate electrode of the transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0422] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b. The other one is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0423] The light-emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0424] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0425] In a display device having the pixel circuit 501 shown in FIG. 36(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0426] In the pixel circuit 501 to which the data has been written, the transistor 552 is turned off. Furthermore, the transistor 554 is in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0427] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0428] (Embodiment 5) In this embodiment, the circuit configuration to which the transistors described in the above embodiment can be applied is An example will be described with reference to FIGS.

[0429] Note that in this embodiment, the transistor having the oxide semiconductor described in the above embodiment In the following description, the above-mentioned transistor will be referred to as an OS transistor.

[0430] <5. Example of inverter circuit configuration> FIG. 37(A) shows a circuit that can be applied to a shift register, a buffer, etc. in a driver circuit. 8 shows a circuit diagram of an inverter that can be used for this purpose. The inverter 800 outputs a signal that is the inverted version of the logic of the input terminal IN. The inverter 800 outputs a signal to an output terminal OUT. . signal S BG is a signal that can switch the electrical characteristics of an OS transistor.

[0431] FIG. 37B is an example of an inverter 800. The inverter 800 is an OS transistor. The inverter 800 includes an n-channel Since it can be fabricated using only complementary metal-oxide semiconductor (CMOS) transistors, Y Metal Oxide Semiconductor inverter (CMOS inverter) It is possible to manufacture the device at a lower cost than manufacturing a conventional inverter.

[0432] The inverter 800 having OS transistors is made of Si transistors. The inverter 800 can be placed on the CMOS circuit. Therefore, an increase in the circuit area due to the addition of the inverter 800 can be suppressed.

[0433] The OS transistors 810 and 820 each have a first gate functioning as a front gate and a back gate. The second gate acts as a gate electrode and the first gate acts as either a source or a drain. It has one terminal and a second terminal that functions as the other of the source or drain.

[0434] A first gate of the OS transistor 810 is connected to a second terminal of the OS transistor 810. The second gate of the OS transistor 810 is connected to a signal S BG Connected to the wiring that supplies A first terminal of the OS transistor 810 is connected to a wiring that supplies a voltage VDD. The second terminal of the transistor 810 is connected to the output terminal OUT.

[0435] A first gate of the OS transistor 820 is connected to the input terminal IN. A second gate of the OS transistor 820 is connected to the input terminal IN. The second terminal of the OS transistor 820 is connected to the output terminal OUT. The GND is connected to a wire that supplies

[0436] FIG. 37C is a timing chart for explaining the operation of the inverter 800. In the timing chart of FIG. 37(C), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are Signal waveform, signal S BG 8 and the change in the threshold voltage of the OS transistor 810. This shows the following:

[0437] signal S BG to the second gate of the OS transistor 810. The threshold voltage of 810 can be controlled.

[0438] signal S BG is the voltage V for shifting the threshold voltage negatively. BG_A ,threshold Voltage V for positively shifting the voltage BG_B The second gate has a voltage V BG_A By providing TH_A negative shift to Also, the second gate can be connected to the voltage V BG_B By providing The threshold voltage V TH_B can be shifted positively to

[0439] To visualize the above explanation, Figure 38(A) shows one of the electrical characteristics of a transistor. 1 shows an Id-Vg curve.

[0440] The electrical characteristics of the OS transistor 810 described above are as follows: BG_A of By increasing the value so as to shift the curve to the curve represented by the dashed line 840 in FIG. The electrical characteristics of the OS transistor 810 can be expressed as follows: Voltage V BG_B By making it smaller, the curve represented by the solid line 841 in FIG. As shown in FIG. 38A, the OS transistor 810 can be signal S BG to the voltage V BG_A Or voltage V BG_B By switching like this, The threshold voltage can be shifted positively or negatively.

[0441] Threshold voltage V TH_B By shifting the OS transistor The capacitor 810 can be made to have a state in which it is difficult for a current to flow. Visualize and show.

[0442] As shown in FIG. 38B, a current I B Extremely small Therefore, when the signal applied to the input terminal IN is high level, the OS trans When the resistor 820 is in the ON state, it causes the voltage at the output terminal OUT to drop sharply. can be done.

[0443] As shown in FIG. 38B, the current flowing through the OS transistor 810 is difficult. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 831 can be changed sharply. Since the through current flowing between the wiring that supplies S can be reduced, it is possible to achieve low power consumption. The action can be performed.

[0444] Also, the threshold voltage is V TH_A By shifting it negatively, the OS The transistor 810 can be made to be in a state in which a current can easily flow. The state is visualized. As shown in FIG. 38(C), the current I A Less At least current I B Therefore, the signal applied to the input terminal IN can be When the OS transistor 820 is in an off state (OFF) at a low level, the voltage of the output terminal OUT As shown in FIG. 38(C), the OS transistor Since the current flowing through 810 can be made to flow easily, the type shown in FIG. This allows the signal waveform 832 at the output terminal in the timing chart to be changed sharply.

[0445] In addition, signal S BG The control of the threshold voltage of the OS transistor 810 by It is preferable to perform this before the state of register 820 changes, i.e., before time T1 or T2. For example, as shown in FIG. 37(C), when the signal given to the input terminal IN is high level, Before the time T1 when the transistor switches to the TH_A From the threshold voltage V TH _B It is preferable to change the threshold voltage of the OS transistor 810 in FIG. As shown in FIG. 7(C), the signal applied to the input terminal IN is switched to a low level at time T Before 2, the threshold voltage V TH_B to threshold voltage V TH_A OS transistor It is preferable to switch the threshold voltage of 810.

[0446] In the timing chart of FIG. 37(C), the signal changes according to the signal applied to the input terminal IN. No. S BG However, other configurations may be used. For example, the threshold voltage is The control voltage is applied to the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. As shown in (A).

[0447] In FIG. 39A, in addition to the circuit configuration shown in FIG. 37B, an OS transistor 850 The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a voltage V BG_B (or Pressure V BG_A The first gate of the OS transistor 850 is connected to a wiring that provides a signal No. S F The second gate of the OS transistor 850 is connected to a wiring that supplies a voltage V BG _B (or voltage V BG_A ) is connected to the wire that provides the

[0448] The operation of FIG. 39(A) will be described with reference to the timing chart of FIG. 39(B).

[0449] A voltage for controlling the threshold voltage of the OS transistor 810 is applied to the input terminal IN. The second gate of OS transistor 810 is turned on before time T3 when the signal The signal SF is set to a high level to turn on the OS transistor 850. In this state, node N BG Voltage V for controlling the threshold voltage BG_B Gives.

[0450] Node N BG is the voltage V BG_B After this, the OS transistor 850 is turned off. The OS transistor 850 has an extremely small off-state current and can be kept in an off state. So, once node N BG The threshold voltage V BG_B It is possible to hold Therefore, the second gate of the OS transistor 850 is supplied with a voltage V BG_B The number of actions to give is reduced. Therefore, the voltage V BG_B Therefore, the power consumption required for rewriting the data can be reduced.

[0451] In the circuit configurations in FIGS. 37B and 39A, the second We have shown a configuration in which the voltage applied to the gate is controlled from outside, but we will also consider other configurations. For example, a signal for controlling the threshold voltage may be applied to the input terminal IN. and provided to the second gate of the OS transistor 810. FIG. 40A shows an example of a circuit configuration that can realize the above configuration.

[0452] In FIG. 40(A), the input terminal IN and the OS transistor are connected in the circuit configuration shown in FIG. A CMOS inverter 860 is provided between the second gate of the transistor 810 and the CMOS inverter 860. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal is connected to the second gate of OS transistor 810.

[0453] The operation of FIG. 40(A) will be described with reference to the timing chart of FIG. 40(B). In the timing chart of Figure 40(B), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are 8, the output waveform IN_B of the CMOS inverter 860, and the output waveform IN_C of the OS transistor 810. The change in threshold voltage is shown.

[0454] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is This signal can be used to control the threshold voltage of the transistor 810. As described with reference to FIGS. 38A to 38C, the threshold voltage of the OS transistor 810 is controlled. For example, at time T4 in FIG. 40(B), the signal applied to the input terminal IN is When the signal is at a high level, the OS transistor 820 is turned on. B is at a low level. Therefore, the OS transistor 810 is in a state where it is difficult for a current to flow. Therefore, the rising voltage of the output terminal OUT can be made to drop sharply.

[0455] At time T5 in FIG. 40(B), the signal applied to the input terminal IN becomes low. At this time, the OS transistor 820 is turned off. Therefore, the OS transistor 810 can be in a state where a current easily flows. This allows the voltage at the output terminal OUT to rise sharply.

[0456] As described above, in the configuration of this embodiment, the inverter having the OS transistor The back gate voltage is switched according to the logic of the signal at the input terminal IN. By using this configuration, the threshold voltage of the OS transistor can be controlled. The threshold voltage of the OS transistor is controlled by the signal applied to IN. The OUT voltage can be changed sharply. This allows the current to be reduced, thereby enabling low power consumption.

[0457] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0458] (Embodiment 6) In this embodiment, the transistor including the oxide semiconductor described in the above embodiment ( An example of a semiconductor device using an OS transistor in a plurality of circuits is shown in FIG. 4 will be used to explain.

[0459] <6. Circuit configuration example of semiconductor device> FIG. 41A is a block diagram of a semiconductor device 900. The semiconductor device 900 is A circuit 901, a circuit 902, a voltage generating circuit 903, a circuit 904, a voltage generating circuit 905, and a circuit It has a path 906.

[0460] The power supply circuit 901 supplies a reference voltage V ORG This is a circuit that generates a voltage V ORG teeth, It is acceptable to use multiple voltages instead of a single voltage. Voltage V ORG From the outside of the semiconductor device 900 The semiconductor device 900 can generate the voltage V1 based on the voltage V2 given from the outside. Based on a single power supply voltage, the voltage V ORG Therefore, the semiconductor device 900 can generate It can operate without applying multiple power supply voltages from the outside.

[0461] Circuits 902, 904, and 906 are circuits that operate on different power supply voltages. The power supply voltage of the circuit 902 is the voltage V ORG and voltage V SS (V ORG >V SS ) and applied by The power supply voltage for the circuit 904 is the voltage V POG and voltage V SS ( V POG >V ORG ) is a voltage applied by the power supply of the circuit 906. Voltage is voltage V ORG and voltage V NEG (V ORG >V SS >V NEG ) and applied by The voltage V SS If the potential is the same as the ground (GND), the power supply circuit The number of types of voltages generated by 901 can be reduced.

[0462] The voltage generating circuit 903 generates a voltage V POG The voltage generating circuit 903 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V POG Therefore, The semiconductor device 900 having the circuit 904 operates based on a single power supply voltage provided from the outside. It can be made.

[0463] The voltage generating circuit 905 generates a voltage V NEG The voltage generating circuit 905 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V NEG Therefore, The semiconductor device 900 having the circuit 906 operates based on a single power supply voltage provided from the outside. It can be made.

[0464] Figure 41(B) shows the voltage V POGFIG. 41C shows an example of a circuit 904 that operates in accordance with the 4 is an example of a waveform of a signal for operating the

[0465] FIG. 41B shows a transistor 911. The applied signal is, for example, a voltage V POG and voltage V SS The signal is generated based on the When the transistor 911 is in the conductive state, the voltage V POG , the voltage when in non-conducting state V SS Let the voltage V POG As shown in FIG. 41(C), the voltage V ORG Bigger Therefore, the transistor 911 is in a conductive state between the source (S) and the drain (D). As a result, the circuit 904 is less likely to malfunction. The circuit can be constructed as follows.

[0466] Figure 41(D) shows the voltage V NEG FIG. 41(E) shows an example of a circuit 906 that operates in accordance with the 4 is an example of a waveform of a signal for operating the

[0467] FIG. 41D shows a transistor 912 having a back gate. The signal applied to the gate of the transistor 912 is, for example, a voltage V ORG and voltage V SS Generated based on The signal is a voltage V ORG , Non-guided When the voltage V SS In addition, the back gate of the transistor 912 is The voltage that can be applied is V NEG It is generated based on the voltage V NEG is illustrated in FIG. So, the voltage V SS(GND). Therefore, the threshold voltage of the transistor 912 is Therefore, the transistor 912 can be controlled to shift in the positive direction. It is possible to ensure that the transistor is in a non-conducting state, and the current flowing between the source (S) and the drain (D) As a result, the circuit 906 can reduce malfunctions and achieve low power consumption. The circuit can be constructed as follows.

[0468] In addition, the voltage V NEG can also be applied directly to the back gate of the transistor 912. Alternatively, the voltage V ORG and voltage V NEG Based on this, a voltage is applied to the gate of the transistor 912. Alternatively, a signal that corresponds to the back gate of the transistor 912 may be generated and provided to the back gate of the transistor 912. good.

[0469] Moreover, Figs. 42(A) and (B) show modified examples of Figs. 41(D) and (E).

[0470] In the circuit diagram shown in FIG. 42(A), a control circuit is provided between a voltage generating circuit 905 and a circuit 906. A transistor 922 whose conduction state can be controlled by a path 921 is shown. The control signal S output from the control circuit 921 is an n-channel OS transistor. BG is a signal for controlling the conduction state of the transistor 922. Transistors 912A and 912B are OS transistors similar to transistor 922.

[0471] In the timing chart of FIG. 42(B), the control signal S BG and transistor 912A, The state of the potential of the back gate of 912B is BG The control signal S B G When the voltage at the node N BG is the voltage V N EG Then, the control signal S BG When is low, node N BG Electrically flow Since the transistor 922 is an OS transistor, its off-state current is small. Therefore, node N BG Even if the voltage V is electrically floating, NEG can be held.

[0472] FIG. 43A shows an example of a circuit configuration that can be applied to the voltage generating circuit 903 described above. The voltage generating circuit 903 shown in FIG. The charge pump has five stages including C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 through C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS and is applied by If the voltage V ORG is boosted to a positive voltage five times higher than the Voltage V POG The forward voltage of the diodes D1 to D5 is 0V. In addition, by changing the number of charge pump stages, the desired voltage V POG Get It is possible.

[0473] FIG. 43B shows an example of a circuit configuration that can be applied to the voltage generating circuit 905 described above. The voltage generating circuit 905 shown in FIG. The charge pump has four stages including C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 through C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS and is applied by If the voltage at the clock signal CLK is SS From Pressure V ORG The voltage V is stepped down to a negative voltage four times higher than the NEG It is possible to obtain the above. The forward voltage of the nodes D1 to D5 is set to 0 V. In addition, the number of stages of the charge pump is changed. This allows the desired voltage V NEG can be obtained.

[0474] The circuit configuration of the voltage generating circuit 903 described above corresponds to the circuit configuration shown in FIG. For example, modified examples of the voltage generating circuit 903 are shown in FIG. The modified example of the voltage generating circuit 903 is the voltage generating circuit shown in FIG. In the circuits 903A to 903C, the voltage applied to each wiring may be changed, or the elements This can be achieved by changing the arrangement of the

[0475] The voltage generating circuit 903A shown in FIG. The clock signal CLK is supplied to the transistors C11 to C14 and the inverter INV1. The gates of the transistors M1 to M10 are supplied directly or through an inverter INV1. The clock signal CLK drives the voltage V ORG The voltage V is boosted to four times the positive voltage PO G By changing the number of stages, the desired voltage V POGto get The voltage generating circuit 903A shown in FIG. By using S transistors, the off-state current can be reduced, and the capacitors C11 to C14 are This effectively suppresses the leakage of the charge. ORG to voltage V POG Ascension to It is possible to measure pressure.

[0476] The voltage generating circuit 903B shown in FIG. The clock signal CLK is , directly to the gates of transistors M11 to M14 or via inverter INV2 The clock signal CLK generates a voltage V ORG The voltage boosted to twice the positive voltage Pressure V POG The voltage generating circuit 903B shown in FIG. By using OS transistors as the transistors M11 to M14, the off-state current can be reduced. This can suppress leakage of the charge stored in the capacitors C15 and C16. Therefore, the voltage V ORG to voltage V POG It is possible to boost the voltage to

[0477] The voltage generating circuit 903C shown in FIG. The transistor M15 has a diode D6 and a capacitor C17. The conduction state is controlled by the control signal EN. The control signal EN controls the voltage V ORG but The boosted voltage V POG The voltage generating circuit 903C shown in FIG. Since the inductor Ind1 is used to boost the voltage, the voltage is boosted with high conversion efficiency. It is possible to do so.

[0478] As described above, in the configuration of this embodiment, the voltage required for the circuit of the semiconductor device is This allows the semiconductor device to reduce the number of power supply voltages that are applied from the outside. It can be reduced.

[0479] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. There can be.

[0480] (Embodiment 7) In this embodiment, a display module and an electronic device each including a semiconductor device according to one embodiment of the present invention will be described. This will be described with reference to FIGS.

[0481] <7-1. Display module> The display module 7000 shown in FIG. 45 includes an upper cover 7001 and a lower cover 7002. Between them, touch panel 7004 connected to FPC 7003 and A display panel 7006, a backlight 7007, a frame 7009, and a printed circuit board 701 0, has battery 7011.

[0482] The semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.

[0483] The upper cover 7001 and the lower cover 7002 are connected to the touch panel 7004 and the display panel The shape and dimensions can be changed as appropriate to match the size of 7006.

[0484] The touch panel 7004 is a resistive or capacitive touch panel. The display panel 7006 may be overlapped with the opposing substrate (sealing substrate). It is also possible to provide the display panel 7 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 006 to make it into an optical touch panel.

[0485] The backlight 7007 has a light source 7008. In FIG. In the above embodiment, the light source 7008 is disposed on the light source 7007. However, the present invention is not limited to this. For example, a light source 7008 is arranged at the end of a backlight 7007, and a light diffusion plate is further used. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective In the case of a liquid crystal panel, the backlight 7007 may not be provided.

[0486] The frame 7009 protects the display panel 7006 and also supports the movement of the printed circuit board 7010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 7009 may also function as a heat sink.

[0487] The printed circuit board 7010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 7011 provided separately. , this can be omitted when using a commercial power source.

[0488] In addition, the display module 7000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0489] <7-2.Electronic equipment 1> Next, examples of electronic devices are shown in FIGS.

[0490] FIG. 46(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0491] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0492] In this example, a camera 8000 is used, and a lens 8006 is detached from a housing 8001 and replaced. However, the lens 8006 and the housing may be integrated together.

[0493] The camera 8000 can capture an image by pressing the shutter button 8004. The display unit 8002 also functions as a touch panel. It is also possible to capture an image by doing so.

[0494] The housing 8001 of the camera 8000 has a mount having electrodes, and a finder 810 In addition to 0, strobe devices etc. can also be connected.

[0495] The finder 8100 includes a housing 8101, a display unit 8102, a button 8103, and the like. .

[0496] The housing 8101 has a mount that engages with the mount of the camera 8000, The mount can be attached to the camera 8000. The mount also includes an electrode The image received from the camera 8000 through the electrode is displayed on the display unit 8102. It is possible to do so.

[0497] The button 8103 functions as a power button. The 8102 display can be switched on and off.

[0498] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied.

[0499] In FIG. 46(A), the camera 8000 and the finder 8100 are treated as separate electronic devices. These are configured to be removable, but the camera 8000 has a housing 8001 equipped with a display device. The camera may have a built-in viewfinder that can be used to capture images.

[0500] FIG. 46B is a diagram showing the external appearance of the head mounted display 8200.

[0501] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0502] A cable 8205 supplies power from a battery 8206 to the main body 8203. 03 is equipped with a wireless receiver and the like, and image information such as image data received is displayed on a display unit 8204. In addition, the camera installed in the main body 8203 can record the movement of the user's eyeballs and eyelids. The system captures the user's gaze and calculates the coordinates of the user's gaze based on that information. It can be used as an input means.

[0503] Furthermore, the mounting unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 detects the current flowing through the electrodes in response to the movement of the user's eyeball, The device may have a function of recognizing the user's viewpoint. Also, the device may have a function of detecting the current flowing through the electrode. By doing so, the mounting unit 820 may have a function of monitoring the pulse of the user. The sensor 1 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The device may have a function of displaying the user's biological information on the display unit 8204. The image displayed on the display unit 8204 is changed according to the movement of the part. Good too.

[0504] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0505] 46(C), (D), and (E) are diagrams showing the appearance of the head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, and a backlight. The optical element has a band-shaped fixture 8304 and a pair of lenses 8305.

[0506] A user can view the display on the display unit 8302 through the lens 8305 . It is preferable to arrange the display portion 8302 in a curved state. This allows the user to feel a high sense of realism.

[0507] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition. Even if the image is magnified using the lens 8305, the pixels are not visible to the user, and the image is more This makes it possible to display images with a higher sense of reality.

[0508] <7-3.Electronic equipment 2> Next, an example of the electronic device shown in FIG. 46(A) to FIG. 46(E) and a different electronic device will be described with reference to FIG. 7(A) to 47(G).

[0509] The electronic device shown in FIG. 47A to FIG. 47G includes a housing 9000, a display portion 9001, a switch A speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared rays), 9008, etc.

[0510] The electronic devices shown in FIG. 47(A) to FIG. 47(G) have various functions. Function to display various information (still images, videos, text images, etc.) on the display unit, touch panel function , calendar, date or time display functions, various software (programs) A function for controlling processing by wireless communication, a function for controlling various computers by using wireless communication, Functions for connecting to a network and transmitting or receiving various data using wireless communication functions A function to read out a program or data recorded on a recording medium and display it on the display unit. The electronic devices shown in FIGS. The functions that can be possessed by the can be not limited to these, and can have various functions. Although not shown in FIG. 47(A) to FIG. 47(G), the electronic device may have a plurality of display units. The electronic device may be provided with a camera or the like to capture still images. , the function to shoot videos, and save the captured images to a recording medium (external or built-in to the camera) The camera may have a function of capturing an image on a display unit, a function of displaying a captured image on a display unit, etc.

[0511] The electronic devices shown in FIGS. 47(A) to 47(G) will be described in detail below.

[0512] FIG. 47A is a perspective view showing a television device 9100. 100 is a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more It is possible to incorporate a display unit 9001 such as the above.

[0513] FIG. 47B is a perspective view showing a portable information terminal 9101. For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The information terminal 9101 can display text and image information on multiple sides. The four operation buttons 9050 (also called operation icons or simply icons) are provided on the display unit 9001. In addition, information 9051 indicated by a dashed rectangle can be displayed on one surface of the display unit 900. 1. An example of the information 9051 is an e-mail or Displays to notify you of incoming calls and SNS (social networking services), Subject of email or SNS, sender name of email or SNS, date and time, time, The remaining battery level, antenna reception strength, etc. Or, the information 9051 is displayed. In place of the information 9051, operation buttons 9050 or the like may be displayed.

[0514] FIG. 47C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 holds the portable information terminal 9102 in the breast pocket of the clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed on the mobile information terminal 9102 so that it can be observed from above. The user can read the display without taking the mobile information terminal 9102 out of his pocket. You can check the number and decide whether to answer the call or not.

[0515] Fig. 47(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is used for mobile phone calls, e-mail, document browsing and writing, music playback, and Internet communications. It is possible to execute various applications such as computer games. The display unit 9001 has a curved display surface, and displays information along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. Power may also be supplied wirelessly without going through 6.

[0516] 47(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 47(E) is a perspective view of the portable information terminal 9201 in an unfolded state. (F) shows the mobile information terminal 9201 being changed from one of the unfolded and folded states to the other. FIG. 47(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded and is unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. The portable information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0517] 48(A) and (B) are perspective views of a display device having multiple display panels. FIG. 48(A) is a perspective view of a state in which a plurality of display panels are rolled up, and FIG. ) is a perspective view of a state in which a plurality of display panels are unfolded.

[0518] The display device 9500 shown in FIG. 48(A) and (B) includes a plurality of display panels 9501 and a shaft portion 9 511 and a bearing portion 9512. The display panels 9501 have a display area 9502 and a light-transmitting region 9503.

[0519] In addition, the display panels 9501 are flexible. The filters 9501 are arranged so that they partially overlap each other. For example, A light-transmitting region 9503 of the display panel 9501 can be overlapped. By using the display panel 9501, a large-screen display device can be provided. The display panel 9501 can be rolled up depending on the situation, making it a versatile display. The display device may be a display device.

[0520] In addition, in FIG. 48(A) and (B), the display area 9502 is adjacent to the display panel 950 1 shows a state in which the display panels are spaced apart from each other, but this is not limited thereto. For example, the display panels 9 By overlapping the display areas 9502 of 501 without any gaps, a continuous display area 9502 is created. You may do so.

[0521] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. This can also be applied to vessels.

[0522] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0523] (Embodiment 8) In this embodiment, the memory contents can be retained even when power is not supplied, and writing is possible. A semiconductor device (memory device) with no limit on the number of times it can be written to, and a CPU that includes the device. 9 to 51. The CPU described in this embodiment is, for example, the same as the previous embodiment. The present invention can be used in electronic devices described in the following embodiments.

[0524] <8-1. Storage device> It is possible to retain memory contents even when power is not supplied, and there is no limit to the number of times it can be written to. An example of a semiconductor device (memory device) without the above-mentioned structure is shown in FIG. 49. Note that FIG. 49(B) is the same as FIG. FIG. 1 is a circuit diagram showing the above.

[0525] The semiconductor device shown in FIG. 49(A) and (B) includes a transistor using a first semiconductor material. 3200, a transistor 3300 using a second semiconductor material, and a capacitor element 3400 It has.

[0526] The first and second semiconductor materials have different energy gaps. For example, the first semiconductor material is preferably a semiconductor material other than an oxide semiconductor (silicon ( (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide , aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.) The second semiconductor material can be an oxide semiconductor. Transistors using crystalline silicon, etc., can easily operate at high speed. A transistor using such a material has a low off-state current.

[0527] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The off-state current of the transistor 3300 is small, so that the transistor 3300 can be used. It is possible to retain memory contents for a longer period of time, i.e., no refresh operation is required. To provide a semiconductor memory device that does not require a refresh operation or requires an extremely low frequency of refresh operations. This makes it possible to sufficiently reduce power consumption.

[0528] In FIG. 49B, a first wiring 3101 is connected to a source electrode of a transistor 3200. The second wiring 3102 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3103 is connected to the source electrode of the transistor 3300 or The fourth wiring 3104 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the The other of the source electrode and the drain electrode of the transistor 3300 is a capacitor 3400. The fifth wiring 3105 is electrically connected to one of the electrodes of the capacitor 3400. and is electrically connected to

[0529] In the semiconductor device shown in FIG. 49A, the potential of the gate electrode of the transistor 3200 is held. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0530] The writing and holding of data will be described. First, the potential of the fourth wiring 3104 is set to The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3103 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate of the transistor 3200 is A constant charge is applied (write). Here, the charges ( Hereinafter, either a low level charge or a high level charge is given. After that, the potential of the fourth wiring 3104 is set to a potential at which the transistor 3300 is turned off. By turning off the transistor 3300, The applied charge is retained (retention).

[0531] Since the off-state current of the transistor 3300 is extremely small, the gate The charge is retained for a long time.

[0532] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3101. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3105, the transistor Depending on the amount of charge held in the gate of the transistor 3200, the second wiring 3102 has a different potential. In general, if the transistor 3200 is an n-channel type, When a high-level charge is applied to the gate electrode, the apparent threshold voltage Vth_H is When a low-level charge is applied to the gate electrode of transistor 3200, This is because the apparent threshold voltage is lower than the threshold voltage Vth_L of the transistor. This refers to the potential of the fifth wiring 3105 required to turn the transistor 3200 on. Therefore, the potential of the fifth wiring 3105 is set to a potential V0 between Vth_H and Vth_L. By this, the charge applied to the gate of the transistor 3200 can be determined. For example, In the case where a high level charge is applied in the write operation, the fifth wiring 3105 When the potential of becomes V0 (>Vth_H), the transistor 3200 is in the "on state." When a low-level charge is applied, the potential of the fifth wiring 3105 becomes V0 ( <Vt h_L), the transistor 3200 remains in the "off state." By determining the potential of the wiring 3102 in FIG. 2, the stored data can be read out. .

[0533] The semiconductor device shown in FIG. 49(C) is different from the semiconductor device shown in FIG. 49( In this case, the same operation as above is performed to write and hold information. is possible.

[0534] Next, reading of information from the semiconductor device shown in FIG. When the capacitor 3300 is turned on, the third wiring 3103 and the capacitor element 3400, which are in a floating state, and the third wiring 3103 are electrically connected, and charge is redistributed between the third wiring 3103 and the capacitor 3400. As a result, the potential of the third wiring 3103 changes. The amount of change in the potential of the third wiring 3103 is expressed as a capacitance The potential of one of the electrodes of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0535] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3103 is denoted by CB, and the capacitance of the third wiring 3103 before the charge is redistributed is denoted by If the potential of the third wiring 3103 after the charge is redistributed is VB0, the potential of the third wiring 3103 after the charge is redistributed is (CB ×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes 3400 can take two states, V1 and V0 (V1>V0), then the potential The potential of the bit line BL when V1 is held (=(CB×VB0+C×V1) / (CB +C)) is the potential of the bit line BL when the potential V0 is held (=(CB×VB0+C × V0) / (CB+C)).

[0536] Then, the potential of the third wiring 3103 is compared with a predetermined potential, thereby reading out information. This can be done.

[0537] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cells. A transistor in which a second semiconductor material is applied is used as the transistor 3300. The transistor may be laminated on the driver circuit.

[0538] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, it is possible to operate the device without power supply (although it is preferable that the potential is fixed). Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0539] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem with element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. In other words, the problem of deterioration of the gate insulating film does not occur at all. In a physical device, there is no limit to the number of times data can be rewritten, which is a problem with conventional non-volatile memory. This will dramatically improve reliability. Furthermore, the on and off states of transistors will determine the information Since the data is written in a single bit, high speed operation can be easily achieved.

[0540] The above storage device may be implemented, for example, by a CPU (Central Processing In addition to the Digital Signal Processor (DSP), LSI, PLD (Programmable Logic Device) etc. SI, RF-ID (Radio Frequency Identification) It can also be applied to.

[0541] <8-2.CPU> The following describes a CPU including the above storage device.

[0542] FIG. 50 is a block diagram showing a configuration of an example of a CPU including the above storage device.

[0543] The CPU shown in FIG. 50 includes an ALU 2191 (ALU: Arithmetic Unit) on a board 2190. tic logic unit, ALU controller 2192, instruction Action Decoder 2193, Interrupt Controller 2194, Timing Controller 2195, register 2196, register controller 2197, bus interface 2198 (Bus I / F), rewritable ROM2199, and ROM interface The substrate 2190 is a semiconductor substrate, a SOI substrate, A plate, a glass substrate, etc. are used. The ROM 2199 and the ROM interface 2189 are It may be provided on a separate chip. Of course, the CPU shown in FIG. 50 is a simplified version of the configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, A configuration including the CPU or arithmetic circuit shown in FIG. 50 is considered as one core, and a configuration including multiple such cores is considered as Alternatively, each core may be configured to operate in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It can be, for example, a .

[0544] The instructions input to the CPU via the bus interface 2198 are The signal is input to the ALU controller 2192, the input decoder 2193, and then decoded. Trigger controller 2194, register controller 2197, timing controller It is entered into Ra2195.

[0545] ALU controller 2192, interrupt controller 2194, register controller The controller 2197 and the timing controller 2195 control various Specifically, the ALU controller 2192 controls the operation of the ALU 2191. The interrupt controller 2194 also generates signals to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 2197 determines the address of the register 2196 and processes it. It generates an address and reads or writes register 2196 depending on the CPU state. .

[0546] The timing controller 2195 also includes an ALU 2191 and an ALU controller 21 92, an instruction decoder 2193, an interrupt controller 2194, and It generates a signal to control the operation timing of the register controller 2197. The timing controller 2195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0547] In the CPU shown in FIG. 50, a register 2196 is provided with a storage device.

[0548] In the CPU shown in FIG. 50, the register controller 2197 In accordance with the instruction of register 2196, the holding operation is selected. In the storage device of 196, data is held by a flip-flop or a capacity Select whether to hold data by the element. If selected, a power supply voltage is applied to the memory device in register 2196 . When data retention in the capacitive element is selected, data rewrite to the capacitive element is This allows the supply of power voltage to the memory device in register 2196 to be stopped.

[0549] FIG. 51 is an example of a circuit diagram of a storage element that can be used as the register 2196. The memory element 2200 includes a circuit 2201 in which stored data is volatilized when the power is cut off, and a circuit 2202 in which stored data is volatilized when the power is cut off. A circuit 2202 in which memory data is not volatile, a switch 2203, a switch 2204, and a logic The circuit includes an element 2206, a capacitor 2207, and a circuit 2220 having a selection function. The circuit 2202 includes a capacitive element 2208, a transistor 2209, and a transistor 2210. The memory element 2200 may include a diode, a resistor, an inductor, etc., as necessary. It may further include other elements such as a converter.

[0550] Here, the above-mentioned memory device can be used for the circuit 2202. When the supply of power supply voltage to GND is stopped, the gate of transistor 2209 in circuit 2202 is A ground potential (0V) or a potential at which the transistor 2209 is turned off is continuously input. For example, the gate of the transistor 2209 is grounded via a load such as a resistor. do.

[0551] The switch 2203 is a transistor 2213 of one conductivity type (for example, an n-channel type). The switch 2204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 2214 of the switch 2203 is used. The terminal corresponds to one of the source and drain of the transistor 2213, and the first terminal of the switch 2203. The terminal 2 corresponds to the other of the source and drain of the transistor 2213, and the terminal 2 corresponds to the other of the source and drain of the switch 2203. The first terminal and the second terminal are connected to each other by a control signal RD input to the gate of the transistor 2213. Conduction or non-conduction between the terminals of the transistor 2213 (i.e., the on or off state of the transistor 2213) The first terminal of the switch 2204 is connected to the source and drain of the transistor 2214. The second terminal of the switch 2204 corresponds to one of the drains of the and the other drain of the switch 2204 is input to the gate of the transistor 2214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The on or off state of transistor 2214 is selected.

[0552] One of the source and drain of the transistor 2209 is connected to a pair of electrodes of the capacitor 2208. The other of the two is electrically connected to the gate of the transistor 2210. The node M2 ​​is connected to the source or drain of the transistor 2210. The other is electrically connected to a wiring (for example, a GND line) that can supply 2203 (one of the source and drain of the transistor 2213). The second terminal of the switch 2203 (the source and drain of the transistor 2213) is connected to the The other terminal of the switch 2204 (one of the source and drain terminals of the transistor 2214) The second terminal of the switch 2204 (the source terminal of the transistor 2214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 2203 (the other of the source and drain of the transistor 2213) ) and a first terminal of a switch 2204 (one of the source and drain of a transistor 2214 ), an input terminal of a logic element 2206, and one of a pair of electrodes of a capacitor 2207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 2207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 2208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (GND, etc.) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor 220. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0553] The capacitors 2207 and 2208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0554] A control signal WE is input to the first gate (first gate electrode) of the transistor 2209. The switch 2203 and the switch 2204 are connected to a control signal RD that is different from the control signal WE. Thus, a conductive state or a non-conductive state between the first terminal and the second terminal is selected, and one of the switches When the first and second terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a conductive state. There is no continuity between the terminals.

[0555] The other of the source and drain of the transistor 2209 is connected to a data terminal of the circuit 2201. In FIG. 51, the signal output from the circuit 2201 corresponds to the In the example shown, the other of the source and drain of the switch 2203 is connected to the source of the transistor 2209. The signal output from the second terminal (the other of the source and drain of the transistor 2213) is The logic value of the inverted signal is inverted by the logic element 2206 and is output via the circuit 2220. The signal is then input to the circuit 2201.

[0556] In FIG. 51, the second terminal of the switch 2203 (the source of the transistor 2213) The signal output from the other drain is routed through the logic element 2206 and the circuit 2220. The second terminal of the switch 2203 is connected to the first terminal of the switch 2203. The signal output from the other of the source and drain of the transistor 2213 is inverted. For example, the following may be included in the circuit 2201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 2203 (the other of the source and drain of the transistor 2213) A signal output from the input terminal can be input to the node.

[0557] In addition, in FIG. 51, among the transistors used in the memory element 2200, The transistors other than the transistor 2209 are formed of a layer or a substrate 21 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 2200 are transistors whose channels are formed of oxide semiconductor films. Alternatively, the memory element 2200 may include a transistor 2209 or a In addition, a transistor in which a channel is formed of an oxide semiconductor film may be included. The transistor has a channel formed in a layer or substrate 2190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be formed by

[0558] For example, a flip-flop can be used for the circuit 2201 in FIG. In addition, the logic element 2206 may be, for example, an inverter or a clocked inverter. This can be done.

[0559] In the semiconductor device described in this embodiment, while a power supply voltage is not supplied to the memory element 2200, The data stored in the circuit 2201 is transferred to the capacitor 2208 in the circuit 2202. It can be held by

[0560] In addition, a transistor in which a channel is formed in an oxide semiconductor film has an extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor film is The off-state current is significantly lower than that of a transistor having a channel formed in silicon. For this reason, a transistor in which a channel is formed in an oxide semiconductor film is referred to as a transistor 2209. By using the storage element 2200 as a storage element, the capacitance element 22 The signal held in memory element 2200 is maintained for a long period of time. It is possible to retain memory contents (data) even when pressure supply is stopped.

[0561] In addition, by providing the switches 2203 and 2204, the precharge operation Since the circuit 2201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0562] In the circuit 2202, the signal held by the capacitor 2208 is Therefore, the supply of the power supply voltage to the memory element 2200 is restarted. After the signal is released, the signal held by the capacitive element 2208 is transferred to the transistor 2210 in the state (on or off state) and can be read out from the circuit 2202. Therefore, even if the potential corresponding to the signal held in the capacitance element 2208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0563] Such a memory element 2200 may be a register or a cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, or multiple logic circuits, the power can be stopped for a short period of time, reducing power consumption. can be suppressed.

[0564] In the present embodiment, the memory element 2200 is used as a CPU. The memory element 2200 is a DSP (Digital Signal Processor), LSI, PLD (Programmable Logic Device) etc. SI, RF-ID (Radio Frequency Identification) It can also be applied to.

[0565] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0566] (Embodiment 9) In this embodiment, an imaging device in which the semiconductor device of one embodiment of the present invention can be used will be described. This will be explained with reference to Figures 52 and 53.

[0567] 52A to 52C show examples of circuit configurations of an imaging device.

[0568] <9. Imaging device> The imaging device 610 having the circuit shown in FIG. 52(A) includes a photoelectric conversion element 601, a transistor, The transistor 602 has a capacitance element 606. One of the source and the drain is electrically connected to the photoelectric conversion element 601. The other of the source or drain of 602 is connected to a transistor via a node 607 (charge storage section). The gate of the transistor 604 is electrically connected to the transistor 604 .

[0569] The transistor 602 is preferably an OS transistor. Since the off-current of the transistor can be made extremely small, the capacitance element 606 can be made small. Alternatively, as shown in FIG. 52(B), the capacitor element 606 can be omitted. In addition, when an OS transistor is used as the transistor 602, the potential of the node 607 Therefore, it is possible to realize an imaging device that is less susceptible to the effects of noise. As the transistor 602, for example, a transistor as exemplified in the above embodiment is used. Note that the transistor 604 may be an OS transistor.

[0570] The photoelectric conversion element 601 has a pn-type or pin-type junction formed on a silicon substrate. A diode element can be used. Alternatively, an amorphous silicon film or a microcrystalline silicon film can be used. Alternatively, a pin-type diode element using a diode may be used. A variable resistor utilizing the photoelectric effect may also be used. It may be formed using selenium, selenium, etc.

[0571] In addition, materials capable of absorbing radiation and generating electric charges are used as photoelectric conversion elements. The material capable of absorbing radiation and generating a charge may be iodine. These include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

[0572] The imaging device 610 having the circuit shown in FIG. 52C includes a photodiode 601 as a photoelectric conversion element. The imaging device 610 shown in FIG. Element 601, transistor 602, transistor 603, transistor 604, transistor The source or drain of the transistor 602 is connected to the transistor 605 and the capacitor 606. One of the terminals is electrically connected to the cathode of the photoelectric conversion element 601, and the other terminal is electrically connected to the node 607. The anode of the photoelectric conversion element 601 is electrically connected to the wiring 611. The source or drain of the transistor 603 is electrically connected to a node 607. The other end is electrically connected to a wiring 608. The transistor is electrically connected to a node 607, and one of the source and drain is electrically connected to a wiring 609. The other end is electrically connected to one of the source and drain of the transistor 605. The other of the source and the drain of the transistor 605 is electrically connected to a wiring 608. One electrode of the capacitor 606 is electrically connected to a node 607, and the other electrode The pole is electrically connected to a wire 611 .

[0573] The transistor 602 can function as a transfer transistor. A transfer signal TX is supplied to the transistor 603. The transistor 603 serves as a reset transistor. A reset signal RST is supplied to the gate of the transistor 603. Transistor 604 can function as an amplifying transistor. Transistor 605 can function as a selection transistor. The gate of the transistor 605 is supplied with a selection signal SEL. In addition, VDD is supplied to the wiring 608, and VSS is supplied to the wiring 611.

[0574] Next, the operation of the imaging device 610 having the circuit shown in FIG. Then, the transistor 603 is turned on to supply VDD to the node 607 (reset operation). After that, when the transistor 603 is turned off, VDD is held at the node 607. Next, when the transistor 602 is turned on, a current flows in response to the amount of light received by the photoelectric conversion element 601. Then, the potential of the node 607 changes (storage operation). When the transistor 605 is turned on, the potential of the node 607 is maintained. Then, a potential corresponding to the potential of the node 607 is output from the wiring 609 (selection operation). By detecting the potential of the wiring 609, the amount of light received by the photoelectric conversion element 601 can be known.

[0575] The transistors 602 and 603 may be OS transistors. As described above, the off-state current of the OS transistor can be made extremely small. Therefore, the capacitance element 606 can be made smaller. Alternatively, the capacitance element 606 can be omitted. In addition, the transistors 602 and 603 may be OS transistors. When a capacitor is used, the potential of the node 607 is less likely to fluctuate. Therefore, the node 607 is less susceptible to noise. An imaging device can be realized.

[0576] The imaging device 610 having any of the circuits shown in FIG. 52(A) to FIG. 52(C) is used as a matrix. By arranging the pixels in a rectangular shape, a high-resolution imaging device can be realized.

[0577] For example, if the image pickup devices 610 are arranged in a 1920×1080 matrix, Full HD (also called "2K resolution", "2K1K", "2K") resolution In addition, for example, the imaging device 610 can be used as a 4 When arranged in a matrix of 10096 x 2160 pixels, it becomes what is known as ultra-high definition (4K An imaging device capable of capturing images at a resolution of 1080p (1024p), also called "4K2K" or "4K". In addition, for example, the imaging device 610 can be used as a matrix of 8192×4320. When these are arranged in a grid, they form what is known as super high vision (8K resolution, 8K4K, It is possible to realize an imaging device capable of capturing images at a resolution of 1080p (also known as "8K"). By increasing the number of display elements, it is possible to realize an imaging device capable of capturing images at resolutions of 16K or 32K. is also possible.

[0578] A structural example of an imaging device 610 using the above-described transistor is shown in FIGS. 53(A) and (B) are cross-sectional views of the imaging device 610.

[0579] The imaging device 610 shown in FIG. 53(A) uses an n-type semiconductor as the substrate 641. In addition, a p-type semiconductor 1221 of the photoelectric conversion element 601 is provided in the substrate 641. A part of the substrate 641 functions as the n-type semiconductor 1223 of the photoelectric conversion element 601 .

[0580] The transistor 604 is provided on a substrate 641. In addition, a p-type semiconductor layer is formed on a portion of the substrate 641. The well 1220 is formed in the same manner as the formation of the p-type semiconductor 1221. The well 1220 and the p-type semiconductor 1221 can be formed at the same time. It is possible.

[0581] The imaging device 610 shown in FIG. 53B includes a transistor 604 and a transistor The transistor 604 is an n-channel transistor. The transistor 605 can function as a p-channel transistor.

[0582] In addition, the imaging device 610 shown in FIG. 53(B) has a photoelectric conversion element 601 provided on a substrate 641. It is being done.

[0583] The photoelectric conversion element 601 shown in FIG. 53(B) has an electrode 686 made of a metal material or the like and a transparent A photoelectric conversion layer 681 is provided between the photoconductive layer 682. In FIG. The photoelectric conversion element 60 using a selenium-based material is shown in FIG. The photoelectric conversion element 1 has a high external quantum efficiency for visible light. The sensor is highly sensitive because it has a large amplification of electrons relative to the amount of light incident due to the Vanish phenomenon. In addition, since the selenium-based material has a high light absorption coefficient, it is easy to make the photoelectric conversion layer 681 thin. This has many advantages.

[0584] As the selenium-based material, amorphous selenium or crystalline selenium can be used. For example, amorphous selenium can be obtained by forming a film of amorphous selenium and then performing a heat treatment. By making the grain size of the crystalline selenium smaller than the pixel pitch, the characteristic variation between pixels is reduced. Crystalline selenium also has a higher spectral sensitivity to visible light than amorphous selenium. It has the characteristics of high sensitivity and light absorption coefficient.

[0585] Although the photoelectric conversion layer 681 is illustrated as a single layer, the selenium-based material has holes on the light receiving surface side. Gallium oxide or cerium oxide is provided as an injection blocking layer, and electrons are injected to the electrode 686 side. The blocking layer may be made of nickel oxide or antimony sulfide.

[0586] The photoelectric conversion layer 681 is a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. In CIS and CIGS, the avalanche phenomenon is similar to that in the case of a single layer of selenium. A usable photoelectric conversion element can be formed.

[0587] In addition, CIS and CIGS are p-type semiconductors, and n-type semiconductors are used to form junctions. Cadmium sulfide, zinc sulfide, or the like may be provided in contact with the metal.

[0588] In order to generate the avalanche phenomenon, a relatively high voltage (for example, 1 It is preferable to apply a voltage of 0 V or more to the OS transistor. Since it has high rain withstand voltage characteristics, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, we have developed an OS transistor with a high drain withstand voltage and a selenium-based photoconductive By combining it with a photoelectric conversion element with a photodiode, a highly sensitive and reliable imaging device can be obtained. It is possible.

[0589] The transparent conductive layer 682 may be made of, for example, indium tin oxide or indium tin containing silicon. Oxides, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, aluminum Zinc oxide containing fluorine, tin oxide, tin oxide containing antimony, or graphite In addition, the light-transmitting conductive layer 682 is not limited to a single layer, but may be a stack of different films. It may be a layer.

[0590] The photoelectric conversion element 601 is made of p-type semiconductor using an amorphous silicon film or a microcrystalline silicon film. An in-type diode element or the like may be used. The photodiode has an n-type semiconductor layer The i-type semiconductor layer has a structure in which an i-type semiconductor layer and a p-type semiconductor layer are laminated in this order. The conductor layer is preferably made of amorphous silicon. The semiconductor layers are made of amorphous silicon or microcrystalline silicon containing dopants that impart the respective conductivity types. A photodiode using amorphous silicon as a photoelectric conversion layer can be used. The card has high sensitivity in the visible light wavelength range and can easily detect weak visible light.

[0591] In addition, pn-type and pin-type diode elements are designed so that the p-type semiconductor layer is the light-receiving surface. By using a p-type semiconductor layer as a light receiving surface, the output of the photoelectric conversion element 601 The current can be increased.

[0592] The photoelectric conversion element 601 formed using the above-mentioned selenium-based material, amorphous silicon, etc. It is made using general semiconductor manufacturing processes such as film formation, lithography, and etching. It is possible to manufacture.

[0593] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible. EXAMPLES

[0594] In this embodiment, a semiconductor device having a conductive film which can be used in a semiconductor device of one embodiment of the present invention will be described. A sample was prepared and the cross-sectional shape of the sample was observed using a scanning transmission electron microscope (STEM). Observed using a scanning electron microscope (STEM). In addition, the sample was subjected to XPS (X-ray photoelectron spectroscopy) analysis.

[0595] <Sample preparation> The sample A1 was a 35 nm thick film on a 720 mm x 600 mm glass substrate. Tantalum nitride with a thickness of 100 nm and copper with a thickness of 200 nm were deposited in this order using a sputtering device. Ta.

[0596] Sample A2 was prepared by disposing a 35 nm thick film on a 720 mm x 600 mm glass substrate. Tantalum nitride and copper with a thickness of 200 nm were sequentially deposited using a sputtering apparatus. Next, silicidation of the copper surface was performed. As the conditions for the silicidation treatment, first, in order to remove the oxide film formed on the copper surface, plasma was discharged in an atmosphere containing ammonia gas using a PECVD apparatus. Subsequently, silane gas was introduced into the PECVD apparatus, and copper silicide was formed by exposing the silane gas to the copper surface. Note that the substrate temperature when removing the oxide film on the copper surface was 350 °C. Also, the substrate temperature when forming copper silicide was 220 °C, and silane gas with a flow rate of 300 sccm and nitrogen gas with a flow rate of 500 sccm were used.

[0597] <Cross-sectional Observation> The above-prepared samples A1 and A2 were observed for their cross-sectional shapes by STEM. Figure 54(A) is a cross-sectional STEM photograph of sample A1, and Figure 54(B) is a cross-sectional STEM photograph of sample A2.

[0598] From the cross-sectional STEM photographs in Figures 54(A) and (B), it was confirmed that in sample A2, a film (copper silicide layer) different from copper was formed on the outermost surface of the film.

[0599] <XPS Analysis> Next, XPS analysis of the surface of sample A2 was performed. Table 1 shows the composition determined by XPS. Note that the detection depth in the surface XPS is about 5 nm.

[0600]

Table 1

[0601] On the surface of sample A2, copper and silicon were detected, and the ratio of silicon to copper (Si / C) u) was 0.47.

[0602] Next, the results of the XPS analysis of the sample A2 in the depth direction are shown in FIG. Copper (Cu), silicon (Si), and tantalum in the depth direction from the A2 film surface to the glass substrate The profiles of Ta, oxygen (O), and nitrogen (N) are shown.

[0603] As shown in FIG. 55, copper (Cu) and silicon (Si) were detected near the surface of the film. It was done.

[0604] Next, Cu2p obtained by XPS analysis in the depth direction of sample A2 3 / 2 Spectrum of, and The spectra of Si2p and Si2p are shown in Figure 56(A)(B), respectively. It stands for Binding Energy.

[0605] In FIG. 56(A), the peak in the range of 931 eV to 934 eV is Cu-Si In FIG. 56(B), peaks in the range of 98 eV to 100 eV are The peak is attributed to the metal-Si group.

[0606] From the above, in sample A2, copper silicide ( It was confirmed that copper silicide was formed.

[0607] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. EXAMPLES

[0608] In this example, a transistor according to one embodiment of the present invention was manufactured and its electrical characteristics were evaluated. Ta.

[0609] The transistor 10 shown in FIGS. 10A and 10B was used as a transistor for evaluating electrical characteristics. Samples B1 and B2 corresponding to the LT were prepared. Note that sample B1 is a trans- Sample B1 is a transistor for comparison.

[0610] The transistor 100L includes a conductive film 104 over a substrate 102, the conductive film 104 serving as a gate electrode, and The insulating films 106 and 107 functioning as a first gate insulating film are formed on the substrate 102 and the conductive film 104. 7, an oxide semiconductor film 108 on the insulating film 107, and a The conductive film 112a serving as a source electrode and the oxide semiconductor film 108 are electrically connected to the conductive film 112a. The conductive film 112b serving as a drain electrode connected to the oxide semiconductor film 108 and the conductive film 112b Insulating films 114 and 116 functioning as second gate insulating films on the films 112a and 112b; An insulating film 118 that functions as a protective insulating film on the insulating film 116 and a second gate insulating film on the insulating film 118 are provided. The oxide semiconductor film 108 has a gate electrode 120b. The semiconductor film includes semiconductor films 108b and 108c.

[0611] The conductive film 112a includes a conductive film 112a_1, a conductive film 112a_2, and a conductive film 112a_3. 3, and the conductive film 112b includes conductive films 112b_1, 1...

Claims

1. a first conductive film having a region functioning as a gate electrode; a first insulating film having a region located above the first conductive film and functioning as a gate insulating film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region; a second conductive film having a region located above the oxide semiconductor film and functioning as a source electrode or a drain electrode; a second insulating film having a region located above the second conductive film; a third conductive film having a region located above the second insulating film and functioning as a pixel electrode; a fourth conductive film having a region overlapping the third conductive film via a third insulating film and functioning as a common electrode; the oxide semiconductor film includes a first semiconductor film and a second semiconductor film having a region on and in contact with the first semiconductor film, the oxide semiconductor film has a first region overlapping with the second conductive film, In the first region, a thickness of the second semiconductor film is greater than a thickness of the first semiconductor film; The third conductive film has a region in contact with the second conductive film.

2. a first conductive film having a region functioning as a gate electrode; a first insulating film having a region located above the first conductive film and functioning as a gate insulating film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region; a second conductive film having a region located above the oxide semiconductor film and functioning as a source electrode or a drain electrode; a second insulating film having a region located above the second conductive film; a third conductive film having a region located above the second insulating film and functioning as a pixel electrode; a fourth conductive film having a region overlapping the third conductive film via a third insulating film and functioning as a common electrode; a spacer having a region located above the fourth conductive film; the oxide semiconductor film includes a first semiconductor film and a second semiconductor film having a region on and in contact with the first semiconductor film, the oxide semiconductor film has a first region overlapping with the second conductive film, In the first region, a thickness of the second semiconductor film is greater than a thickness of the first semiconductor film; the third conductive film has a region in contact with the second conductive film, The spacer has a region overlapping with the oxide semiconductor film.

3. In claim 1 or 2, The first semiconductor film and the second semiconductor film each contain In, Zn, and M (M represents Al, Ga, Y, or Sn).

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