Semiconductor device

Abstract

To suppress fluctuation in electric characteristics in a transistor including an oxide semiconductor film.SOLUTION: A transistor comprises a first gate electrode, a first insulation film on the first gate electrode, an oxide semiconductor film on the first insulation film, a source electrode on the oxide semiconductor film, a drain electrode on the oxide semiconductor film, second insulation films on the oxide semiconductor film, the source electrode, and the drain electrode, and second gate electrodes on the second insulation films. The first insulation film includes a first opening, and a connection electrode electrically connected to the first gate electrode via the first opening is formed on the first insulation film. The second insulation film includes a second opening reaching the connection electrode. The second gate electrode includes an oxide conductive film and a metal film on the oxide conductive film. The connection electrode and the second gate electrode are electrically connected using the metal film.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device including an oxide semiconductor film. Regarding the law.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, The present invention relates to a storage device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials such as silicon are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] For example, a transistor with a dual gate structure in which an oxide semiconductor film is provided between two gate electrodes is By using a transistor, the formation of a parasitic channel due to gate BT stress is suppressed. A semiconductor device is disclosed (see Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-241404 A Summary of the Invention [Problem to be solved by the invention]

[0007] As a transistor using an oxide semiconductor film for the channel region, For example, the mobility, or μFE, of the ferroelectric thin film shown in Patent Document 1 is preferably high. As shown in Fig. 1, a transistor with a dual gate structure in which an oxide semiconductor film is provided between two gate electrodes is used. By using a transistor, it is possible to increase the on-state current and field effect mobility of the transistor. can.

[0008] In addition, when a transistor having a dual gate structure is used, one gate electrode and the other gate It is preferable that the connection resistance with the gate electrode is low. The electrical characteristics are unstable.

[0009] In addition, as a transistor using an oxide semiconductor film for a channel region, The oxygen vacancies formed in the semiconductor layer are problematic because they affect the transistor characteristics. For example, When oxygen vacancies are formed in the oxide semiconductor film, hydrogen is bonded to the oxygen vacancies to supply carriers. When a carrier supply source is generated in the oxide semiconductor film, The electrical characteristics of the transistor change, typically the threshold voltage shift. Therefore, the electrical characteristics of each transistor vary. In the channel region, it is preferable that the oxygen deficiency is as small as possible.

[0010] In view of the above problems, one embodiment of the present invention is a transistor including an oxide semiconductor film, One of the objectives is to suppress fluctuations in electrical characteristics and improve reliability. One aspect of the present invention is a transistor having a dual gate structure having two gate electrodes. In this case, the connection resistance between one gate electrode and the other gate electrode is reduced, resulting in stable electrical characteristics. Another object of the present invention is to provide a semiconductor device having a It is an object of the present invention to provide a semiconductor device with reduced power consumption. An object of the present invention is to provide a novel semiconductor device. One of the objects of the present invention is to provide a novel display device.

[0011] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above may be solved by the specification. The above problems are obvious from the description of the specification, etc., and problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: a gate electrode, a first insulating film on the first gate electrode, and an oxide semiconductor on the first insulating film. a source electrode on the oxide semiconductor film; a drain electrode on the oxide semiconductor film; A second insulating film on the conductor film, the source electrode, and the drain electrode; and a second gate insulating film on the second insulating film. a first insulating film having a first opening, and a first insulating film having a first insulating layer and a first A connection electrode is formed which is electrically connected to the first gate electrode through the opening, and a second insulating The insulating film has a second opening that reaches the connection electrode, and the second gate electrode includes an oxide conductive film and a metal film on the oxide conductive film, and the connection electrode and the second gate electrode are formed using the metal film. The semiconductor device is electrically connected.

[0013] Another embodiment of the present invention is a semiconductor device including a transistor. The photodiode includes a first gate electrode, a first insulating film on the first gate electrode, and an oxide film on the first insulating film. a source electrode on the oxide semiconductor film; and a drain electrode on the oxide semiconductor film. a second insulating film on the oxide semiconductor film, the source electrode, and the drain electrode; a second gate electrode, the first insulating film having a first opening, a connection electrode electrically connected to the first gate electrode through the first opening is formed on the first gate electrode. The second insulating film has a second opening that reaches the connection electrode and a source electrode and a drain electrode. and a third opening reaching either one of the first gate electrode and the second gate electrode. a metal film on the nitride conductive film, and a conductive film having the same composition as the metal film is formed in the third opening. The connection electrode and the second gate electrode are electrically connected to each other using a metal film. It is.

[0014] In the above embodiment, the source electrode and the drain electrode are each formed of a first metal film and a first a second metal film in contact with the first metal film and a third metal film in contact with the second metal film, The second metal film contains copper, and the first metal film and the third metal film each suppress the diffusion of copper. The first metal film includes a material that controls the thickness of the first metal film, and an end of the first metal film is located outside an end of the second metal film. The third metal film covers the top and side surfaces of the second metal film and is in contact with the first metal film. It is preferable that the region has a

[0015] In the above embodiment, the metal film, the conductive film, the first metal film, and the third metal film are Each of the metals is independently selected from titanium, tungsten, tantalum, and molybdenum. It is preferred to have one or more.

[0016] In the above embodiment, the oxide conductive film contains a small amount of a metal element contained in the oxide semiconductor film. It is preferable to have one of both.

[0017] In the above embodiment, the oxide semiconductor film contains In and M (M is Al, Ga, Y, or In the above embodiment, the oxide semiconductor film preferably contains Sn and Zn. It is preferable that the crystal portion has a c-axis orientation.

[0018] Another aspect of the present invention is a semiconductor device comprising: Another embodiment of the present invention is a display device including the display device and a touch sensor. In addition, another aspect of the present invention is a display module having any of the above aspects. The semiconductor device according to any one of claims 1 to 5, the display device, or the display module, and an operation key or is an electronic device having a battery. Effect of the Invention

[0019] According to one embodiment of the present invention, in a transistor including an oxide semiconductor film, In addition, the present invention can suppress the movement of the semiconductor device and improve the reliability. In a transistor having a dual gate structure having two gate electrodes, one of the gates Semiconductor device having stable electrical characteristics by reducing the connection resistance between an electrode and another gate electrode According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a novel display device can be provided. Cut.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0021] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 4] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 5] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 6] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 13] 1A and 1B are diagrams illustrating the range of atomic ratios of oxide semiconductors. [Figure 14] A diagram explaining the InMZnO4 crystal. [Figure 15] FIG. 1 is a band diagram of a stacked structure of oxide semiconductors. [Figure 16] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Figure 17] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and corresponding image analysis images. [Figure 18] Electron diffraction pattern and cross-sectional TEM image of nc-OS. [Figure 19] Cross-sectional TEM image of a-like OS. [Figure 20] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 21] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 22] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 23] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 24] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 25]FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 26] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 27] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 28] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 29] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 30] 1A and 1B are graphs and circuit diagrams illustrating one embodiment of the present invention. [Diagram 31] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 32] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 33] 1A to 1C are a block diagram, a circuit diagram, and waveform diagrams illustrating one embodiment of the present invention. [Diagram 34] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 35] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 36] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 37] FIG. 2 is a diagram illustrating a display module. [Figure 38] 1A to 1C are diagrams illustrating electronic devices. [Figure 39] 1A to 1C are diagrams illustrating electronic devices. [Diagram 40] FIG. 1 is a perspective view illustrating a display device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments will be described with reference to the drawings. The present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily understood by those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0024] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0025] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0026] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. In this specification and the like, the channel region refers to a region through which a current mainly flows. The flow area.

[0027] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0028] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0029] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0030] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to:

[0031] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source When gs is lower than the threshold voltage Vth, the gate and This refers to a state in which the voltage Vgs between the n-channel transistors is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage between the gate and source, Vgs, that is, the threshold voltage, Vt This may refer to the drain current when it is lower than h.

[0032] The off-state current of a transistor may depend on Vgs. The off-state current is I or less if there exists a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows through it in the off-state at a given Vgs. , an off-state at Vgs within a given range or a sufficiently reduced off-current is obtained. In some cases, it may refer to the off-state current at Vgs.

[0033] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -1 3 A, and the drain current at Vgs -0.5 V is 1×10 -19 A and Vg The drain current at s = -0.8 V is 1 × 10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: , or 1×10 when Vgs is in the range of -0.5V to -0.8V -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 There are cases where it is said to be A or lower. The drain current of the transistor is 1×10 -22 A or less Vgs exists. Therefore, the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0034] In this specification, the off-state current of a transistor having a channel width W is expressed as It is sometimes expressed as the current value that flows per watt. Also, for a given channel width (for example, 1 μm), In the latter case, the unit of the off-state current is current / length. It may be expressed in units with an element (e.g., A / μm).

[0035] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the operating temperature is room temperature, 60°C, 85°C, 95°C, or 125°C. Or, the reliability of a semiconductor device including the transistor may be guaranteed. The temperature at which the transistor is certified, or the temperature at which a semiconductor device or the like that contains the transistor is used (e.g. For example, the off-state current at any one of temperatures from 5° C. to 35° C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or The temperature at which the semiconductor device containing the transistor is used (for example, any one of 5°C to 35°C) (temperature), there exists a value of Vgs at which the off-state current of the transistor is equal to or less than I. There are cases where it is pointed out.

[0036] The off-state current of a transistor may depend on the voltage Vds between the drain and source In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or In some cases, it indicates the off-state current at 20 V. In other cases, it indicates the off-state current at 20 V. Vds that guarantees the reliability of semiconductor devices, or semiconductor devices including the transistor The term may also refer to the off-state current at Vds used in the transistor off-state. The current is equal to or less than I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device in which the transistor is used, or Vds used in semiconductor devices, etc., where the off-state current of the transistor is I or less This may refer to the existence of a gs value.

[0037] In the above description of the off-state current, the drain may be read as the source. The current may also refer to the current through the source when the transistor is in the off state.

[0038] In this specification and the like, the term "leak current" may be used to mean the same thing as the "off current." In this specification, the off-state current refers to, for example, the current flowing when a transistor is in an off state. , may refer to the current flowing between the source and drain.

[0039] In addition, even when the term "semiconductor" is used in this specification, for example, If the electrical conductivity is low enough, the material may have the properties of an insulator. The boundary between "insulators" and "insulators" is unclear, and it may not be possible to strictly distinguish them. In some cases, the term "semiconductor" in the above can be replaced with "insulator." In some cases, the term "insulator" in the specification can be replaced with "semiconductor." In some cases, the term "insulator" in this specification can be rephrased as "semi-insulator." .

[0040] In addition, even when the term "semiconductor" is used in this specification, for example, If the electrical conductivity is high enough, it may have the properties of a "conductor". The boundary between the term "conductor" and the term "electrical conductor" is unclear, and it may not be possible to strictly distinguish between them. In some cases, the term "semiconductor" in the above can be replaced with "conductor." The term "conductor" in the specification etc. may be replaced with "semiconductor" in some cases.

[0041] In this specification, the term "impurities in a semiconductor" refers to anything other than the main component that constitutes the semiconductor film. For example, an element with a concentration of less than 0.1 atomic percent is an impurity. This causes the formation of DOS (Density of States) in the semiconductor and the In some cases, the rear mobility and crystallinity of the semiconductor may decrease. In the case of an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 There are elements, group 2 elements, group 14 elements, group 15 elements, transition metals other than the main components, etc. Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, In the case of oxide semiconductors, oxygen vacancies can occur due to the inclusion of impurities such as hydrogen. In addition, when the semiconductor contains silicon, the properties of the semiconductor may be changed. Examples of impurities include oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0042] (Embodiment 1) In this embodiment, a semiconductor device and a manufacturing method of the semiconductor device according to one embodiment of the present invention will be described. The following description will be given with reference to FIGS.

[0043] <1-1. Configuration example 1 of semiconductor device> FIG. 1A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. 1B corresponds to a cross-sectional view taken along dashed line X1-X2 in FIG. 1A. FIG. 1C is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 1A. In FIG. 1A, in order to avoid complication, the transistor 100 Some of the components (such as the insulating film that functions as the gate insulating film) are omitted in the figure. The dashed line X1-X2 direction is the channel length direction, and the dashed line Y1-Y2 direction is the channel width direction. In the top view of the transistor, As in FIG. 1(A), some of the components may be omitted.

[0044] The transistor 100 includes a conductive film 104 on a substrate 102 and a conductive film 104. an insulating film 106 on the insulating film 106; an insulating film 107 on the insulating film 106; and an oxide semiconductor on the insulating film 107. the oxide semiconductor film 108, the conductive film 112a on the oxide semiconductor film 108, and the conductive film 112b on the oxide semiconductor film 108. and insulating films over the oxide semiconductor film 108, the conductive film 112a, and the conductive film 112b. A film 114, an insulating film 116 on the insulating film 114, a conductive film 120a on the insulating film 116, and a conductive film 120b on the insulating film 116.

[0045] The insulating film 106 and the insulating film 107 have an opening 151. A conductive film 112 is formed on the film 107 and is electrically connected to the conductive film 104 through the opening 151. Furthermore, the insulating film 114 and the insulating film 116 have an opening reaching the conductive film 112b. The conductive film 112c has a portion 152a and an opening 152b reaching the conductive film 112c.

[0046] The oxide semiconductor film 108 is formed by stacking an oxide semiconductor film 108b on the conductive film 104 side and an oxide and an oxide semiconductor film 108c over the oxide semiconductor film 108b. The oxide semiconductor film 8b and the oxide semiconductor film 108c are made of In and M (M is Al, Ga, Y, or has Sn) and Zn.

[0047] For example, in the oxide semiconductor film 108b, a region in which the atomic ratio of In is larger than the atomic ratio of M is In addition, the oxide semiconductor film 108c preferably has a region It is preferable to have a region in which the number of In atoms is smaller than that of b.

[0048] the oxide semiconductor film 108b has a region in which the atomic ratio of In is higher than the atomic ratio of M; In this way, the field effect mobility of the transistor 100 can be increased. The field effect mobility of the 100 ZnS is 10 cm 2 / Vs, more preferably The field effect mobility of Star 100 is 30 cm 2 / Vs can be exceeded.

[0049] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. A driver (especially a demux connected to the output terminal of a shift register of a gate driver) By using it in a semiconductor device or display device with a narrow frame (also called a narrow frame), Locations can be provided.

[0050] On the other hand, the oxide semiconductor film 108b has a region in which the atomic ratio of In is larger than the atomic ratio of M. In this case, the electrical characteristics of the transistor 100 are likely to vary when exposed to light. In the semiconductor device of one embodiment of the present invention, an oxide semiconductor film 108b is The oxide semiconductor film 108c is formed. Since the oxide semiconductor film 108 has a region with a low atomic ratio of In, Eg is larger than that of the oxide semiconductor film 108b. Therefore, the stacked structure of the oxide semiconductor film 108b and the oxide semiconductor film 108c The oxide semiconductor film 108 can have high resistance to a negative bias stress test using light irradiation. It becomes.

[0051] In addition, the oxide semiconductor film 108, particularly the channel region of the oxide semiconductor film 108b, Impurities such as hydrogen and moisture are problematic because they affect transistor characteristics. Therefore, in the channel region of the oxide semiconductor film 108b, hydrogen, moisture, and the like are The fewer the impurities, the more preferable. The oxygen vacancies that occur in the oxide semiconductor layer affect the transistor characteristics, which is a problem. When oxygen vacancies are formed in the channel region of the membrane 108b, hydrogen bonds to the oxygen vacancies, A carrier supply source is generated in the channel region of the oxide semiconductor film 108b. When the oxide semiconductor film 108b is formed, the electric characteristics of the transistor 100 including the oxide semiconductor film 108b are changed, Generally speaking, a shift in the threshold voltage occurs. In the hole region, the fewer the oxygen deficiencies, the more preferable.

[0052] In view of this, in one embodiment of the present invention, an insulating film in contact with the oxide semiconductor film 108, specifically, In the present embodiment, the insulating films 114 and 116 formed above the oxide semiconductor film 108 contain excess oxygen. Oxygen or excess oxygen is introduced from the insulating films 114 and 116 to the oxide semiconductor film 108. By the movement, oxygen vacancies in the oxide semiconductor film can be reduced.

[0053] In one embodiment of the present invention, the insulating films 114 and 116 are made to contain excess oxygen. Specifically, the conductive film 120a is a layered structure of an oxide film. The semiconductor device has an oxide conductive film 120a_1 and a metal film 120a_2 on the oxide conductive film 120a_1. The conductive film 120b is formed by an oxide conductive film 120b_1 and a metal layer on the oxide conductive film 120b_1. The film 120b_2.

[0054] With the above-described configuration, for example, the oxide conductive film 120a_1 and the oxide conductive film 120 In the process of forming b_1, a sputtering method is used in an atmosphere containing oxygen gas. By forming the oxide conductive film, oxygen or In addition, the metal film 120a_2 and the metal film 120b can add excess oxygen. By providing the insulating layer 104, the oxide semiconductor film 108 can be irradiated with light from above. can be suppressed.

[0055] The conductive film 112c and the conductive film 120a are electrically connected to each other using a metal film 120a_2. The conductive film 112b and the conductive film 120b are electrically connected to each other using a metal film 120b_2. To be continued.

[0056] For example, when the conductive film 120a is formed of only the oxide conductive film 120a_1, In this configuration, the conductive film 120b_1 and the conductive film 112c are connected to each other. In some cases, the connection resistance between the conductive film 120a and the conductive film 12c increases. In this embodiment, the metal film 120a_2 is used to connect to the conductive film 112c. This makes it possible to reduce the connection resistance between the film 112c and the conductive film 120a.

[0057] Similarly, when the conductive film 120b is formed of only the oxide conductive film 120b_1, In this configuration, the conductive film 120b_1 and the conductive film 112b are connected to each other. In some cases, the connection resistance between the conductive film 12b and the conductive film 120b increases. In this case, the metal film 120b_2 is used to connect to the conductive film 120b. This makes it possible to reduce the connection resistance between the film 112b and the conductive film 120b.

[0058] In addition, the metal film 120a_2 of the conductive film 120a and the metal film 120a_3 of the conductive film 120b are The opening 152 is formed by processing the same metal film. A metal film 120b_2 having the same composition as the metal film 120a_2 is formed on a.

[0059] In addition, an insulating film 118 is provided on the transistor 100. It is formed to cover the insulating film 116, the conductive film 120a, and the conductive film 120b.

[0060] Note that in the transistor 100, the insulating films 106 and 107 The insulating films 114 and 116 function as a first gate insulating film. The insulating film 118 serves as a second gate insulating film for protecting the transistor 100. In the transistor 100, the conductive film 104 functions as an insulating film. The conductive film 120a functions as a first gate electrode, and the conductive film 120b functions as a second gate electrode. The conductive film 120b functions as a pixel electrode for use in a display device. In the transistor 100, the conductive film 112a functions as a source electrode. The drain electrode 112b functions as a drain electrode. The conductive film 112c functions as a connection electrode. The insulating films 114 and 116 are referred to as a second insulating film, and the insulating film 118 is referred to as a first insulating film. are sometimes referred to as the third insulating film.

[0061] The conductive film 112a is made up of a metal film 112a_1 and a metal film in contact with the metal film 112a_1. The metal film 112a_3 is in contact with the metal film 112a_2. In addition, the conductive film 120b is a metal film 112b_1 and a metal film 112b_2 that is in contact with the metal film 112b_1. The metal film 112b_2 and the metal film 112b_3 are disposed on and in contact with the metal film 112b_2.

[0062] The metal film 112a_2 and the metal film 112b_2 each contain copper. 1, the metal film 112b_1, the metal film 112a_3, and the metal film 112b_3 are each made of copper. The metal film 112a_1 includes a material that suppresses the diffusion of the metal film 112a_2. The metal film 112a_3 has a region located outside the end of the metal film 112a_2. The upper surface and the side surface are covered, and the metal film 112a_1 is in contact with the metal film 112a_1. The end of the metal film 2b_1 has an area located outside the end of the metal film 112b_2, The metal film 112b_3 covers the upper surface and side surfaces of the metal film 112b_2 and is connected to the metal film 112b_1. The end of the metal film 112c_1 is closer to the end of the metal film 112c_2 than the end of the metal film 112c_2. The metal film 112c_3 has an area located on the outer side of the upper surface of the metal film 112c_2 and It covers the side surface and has a region in contact with the metal film 112c_1.

[0063] By forming the conductive films 112a and 112b in the above-described manner, the wiring resistance can be reduced. In addition, it is possible to prevent the copper elements contained in the conductive films 112a and 112b from diffusing to the outside. Therefore, it is possible to provide a semiconductor device having stable electrical characteristics. can.

[0064] As shown in FIG. 1C, the conductive film 120a functioning as the second gate electrode is A conductive film 112c serving as a connection electrode is sandwiched between the first gate electrode and the second gate electrode. The conductive film 104 is electrically connected to the conductive film 120a. The same potential is applied.

[0065] As shown in FIG. 1C, the oxide semiconductor film 108 functions as a first gate electrode. The conductive film 104 functions as a second gate electrode, and the conductive film 120a functions as a second gate electrode. The conductive film 120 is sandwiched between two films that function as gate electrodes. The length of the conductive film 120a in the channel length direction and the length of the conductive film 120a in the channel width direction are The length of the oxide semiconductor film 108 in the channel length direction and the length of the oxide semiconductor film 108 in the channel width direction The entire oxide semiconductor film 108 is conductive through the insulating films 114 and 116. It is covered with a conductive film 120a.

[0066] In other words, in the channel width direction of the transistor 100, The conductive film 104 functioning as the second gate electrode and the conductive film 120a functioning as the first gate electrode are The insulating films 106 and 107 functioning as a first gate insulating film and the insulating film 108 functioning as a second gate insulating film The oxide semiconductor film 108 is surrounded by insulating films 114 and 116 therebetween.

[0067] With such a structure, the oxide semiconductor film 108 included in the transistor 100 The conductive film 104 functions as a first gate electrode and the conductive film 105 functions as a second gate electrode. The conductive film 120a can electrically surround the transistor 100. The electric field of the first gate electrode and the second gate electrode causes an oxide film in which a channel region is formed. The device structure of the transistor that electrically surrounds the nitride semiconductor film is called the Surrounded C This can be called a hannel (S-channel) structure.

[0068] Since the transistor 100 has an S-channel structure, the first gate electrode The conductive film 104 functions as a gate insulating film, and the electric field for inducing the channel is effectively applied to the oxide semiconductor. Since the voltage can be applied to the body film 108, the current driving capability of the transistor 100 is improved. It is possible to obtain high on-current characteristics. It is also possible to increase the on-current. Therefore, it is possible to miniaturize the transistor 100. The conductive film 104 functions as a first gate electrode and the conductive film 105 functions as a second gate electrode. Since the transistor 100 has a structure surrounded by the conductive film 120a, the mechanical strength of the transistor 100 is increased. It can be done.

[0069] As described above, in the semiconductor device according to one embodiment of the present invention, The conductive film to be used as the second gate electrode is formed as a laminated structure of an oxide conductive film and a metal film. The conductive film is formed on a surface thereof, and the metal film is connected to a connection electrode. By using this, the connection resistance can be reduced. It is possible to realize a semiconductor device in which the fluctuations are suppressed.

[0070] <1-2. Components of Semiconductor Device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0071] [substrate] There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, and sa A fire substrate or the like may be used as the substrate 102. Also, a material such as silicon or silicon carbide may be used. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductors such as silicon germanium, etc. It is also possible to use a substrate, an SOI substrate, or the like, on which a semiconductor element is provided. The substrate 102 may be a glass substrate. If you have 6th generation (1500mm x 1850mm), 7th generation (1870mm x 220 0mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 280 By using large-area substrates such as 10th generation (2950mm x 3400mm), Larger display devices can be manufactured.

[0072] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is preferably removed from the substrate 102 after a semiconductor device is partially or entirely completed thereon. The transistor 100 can be separated and used for transfer to another substrate. It can also be transferred to substrates with poor thermal properties or flexible substrates.

[0073] [Conductive film] A conductive film 104 functions as a first gate electrode, and a conductive film 11 functions as a source electrode. 2a, a conductive film 112b functioning as a drain electrode, and a conductive film 11 2c, a conductive film 120a functioning as a second gate electrode, and a conductive film 120b functioning as a pixel electrode. The conductive film 120b may be made of chromium (Cr), copper (Cu), aluminum (Al), gold (Au ), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti ), Tungsten (W), Manganese (Mn), Nickel (Ni), Iron (Fe), Cobalt (Co), or an alloy containing the above-mentioned metal element, or Each of the electrodes can be formed using an alloy or the like in which metal elements are combined.

[0074] In addition, the conductive films 104, 112a, 112b, 112c, 120a, and 120b are oxides containing tungsten and tin, oxides containing tungsten and indium, oxides containing tungsten oxides containing titanium, indium and zinc; oxides containing titanium and indium; and oxides having indium and tin, oxides having indium and zinc, oxides having silicon and indium Oxides such as oxides containing indium and tin, oxides containing indium, gallium and zinc, etc. A material conductor may also be applied.

[0075] In particular, the oxide conductive film 120a_1 included in the conductive film 120a and the oxide conductive film 120a_2 included in the conductive film 120b are The oxide conductive film 120b_1 may be formed of any of the above-mentioned oxide conductors. In addition, the oxide conductive films 120a_1 and 120b_1 and the oxide semiconductor film 108 (oxide semiconductor It is preferable that the oxide semiconductor film 108b and the oxide semiconductor film 108c contain the same metal element. By adopting this configuration, it is possible to reduce the manufacturing cost.

[0076] Here, the oxide conductor will be described. In this specification, the oxide conductor is referred to as OC The oxide conductor may be, for example, When oxygen vacancies are formed in an oxide semiconductor and hydrogen is added to the oxygen vacancies, a donor is formed near the conduction band. As a result, the oxide semiconductor becomes conductive and becomes a conductor. The oxide semiconductor that has been encapsulated can be called an oxide conductor. Because of its large energy gap, it is transparent to visible light. The oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. The effect of absorption due to donor levels is small, and the transparency to visible light is comparable to that of oxide semiconductors. It has sexuality.

[0077] The conductive films 104, 112a, 112b, 112c, 120a, and 120b are made of Cu. -X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) is applied. By using a Cu-X alloy film, it can be processed by a wet etching process. Therefore, it is possible to reduce the manufacturing cost.

[0078] In particular, the metal film 112a_2 of the conductive film 112a and the metal film 112a_1 of the conductive film 112b The conductive film 112c includes a metal film 112c_2 and a Cu-X alloy. As the Cu-X alloy film, a Cu-Mn alloy film is particularly preferable. However, in one embodiment of the present invention, the present invention is not limited to this. The metal film 112c_2 needs to contain at least copper.

[0079] In addition, the metal films 112a_1 and 112a_3 of the conductive film 112a and the conductive film 112b_ The metal films 112b_1 and 112b_3 included in the conductive film 112c and the metal film 112 C_1 and 112C_3 contain the above-mentioned metal elements, especially titanium, tungsten, and tungsten. It is preferable that the alloy contains one or more selected from the group consisting of zinc, tantalum, and molybdenum. Metal film 112a_1, 112a_3, 112b_1, 112b_3, 112c_1, 11 2c_3 is any one selected from titanium, tungsten, tantalum, and molybdenum; When one or more of the metal films 112a_2 and 112b_2 are provided, the copper of the metal films 112a_2 and 112b_2 can be diffused outward. That is, the metal films 112a_1, 112a_3, 112b_ 1, 112b_3, 112c_1, and 112c_3 function as a barrier metal. do.

[0080] Metal films 112a_1, 112a_3, metal films 112b_1, 112b_3, and 112 For c_1 and 112c_3, it is preferable to use a so-called tantalum nitride film containing nitrogen and tantalum. The tantalum nitride film has electrical conductivity and high barrier properties against copper or hydrogen. In addition, the tantalum nitride film releases less hydrogen from itself, so it is more resistant to oxidation. As a metal film in contact with the oxide semiconductor film 108 or in the vicinity of the oxide semiconductor film 108 , can be most preferably used.

[0081] The metal films 112a_3 and 112b_3 are made of titanium, tungsten, tantalum, or molybdenum. By using a composition having one or more selected from among ribide, the metal film 1 The connection resistance between the metal film 120a_2 and the metal film 120b_2 can be reduced. If the metal films 112a_3 and 112b_3 have the same material, the connection This is preferable because the resistance can be further reduced.

[0082] [Insulating film functioning as the first gate insulating film] The insulating films 106 and 107 functioning as the first gate insulating film of the transistor 100 are Plasma Enhanced Chemical Vapor Deposition (PECVD) Oxidation is performed by the ical vapor deposition (CVD) method, sputtering method, etc. Silicon film, silicon oxynitride film, silicon oxynitride film, silicon nitride film, aluminum oxide hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film , tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and ne oxide film The insulating film 106 and the insulating layer 107 may each include an insulating layer containing one or more oxynitride films. Instead of the laminated structure of 107, a single insulating film selected from the above-mentioned materials or three or more insulating films may be used. An insulating film may also be used.

[0083] The insulating film 106 also functions as a blocking film that suppresses oxygen permeation. For example, the insulating films 107, 114, and 116 and / or the oxide semiconductor film 108 may contain an excess of acid. When oxygen is supplied, the insulating film 106 can suppress oxygen permeation.

[0084] Note that the oxide semiconductor film 108 functioning as a channel region of the transistor 100 The insulating film 107 is preferably an oxide insulating film, and has an oxide content in excess of the stoichiometric composition. It is more preferable that the insulating film 1 has a region containing oxygen (an oxygen excess region). The insulating film 107 is capable of releasing oxygen. In order to provide the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. The insulating film 107 is then heat-treated in an oxygen atmosphere.

[0085] When hafnium oxide is used as the insulating film 107, the following effects are obtained. Hafnium has a higher dielectric constant than silicon oxide and silicon oxynitride. Compared to the case where silicon oxide is used, the thickness of the insulating film 107 can be made larger, so that the tunnel This reduces the leakage current caused by the current. Furthermore, hafnium oxide, which has a crystalline structure, can be used to realize an amorphous structure. It has a higher relative dielectric constant than hafnium oxide, which has a low off-current. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic. The types are not limited to these.

[0086] In this embodiment, a silicon nitride film is formed as the insulating film 106, and the insulating film 107 is The silicon oxide film is formed as a result of the above. The silicon nitride film has a lower dielectric constant than the silicon oxide film. The film thickness required to obtain the same capacitance as a silicon oxide film is large, so it is suitable for transistors. The gate insulating film of the transistor 100 can be made thick by including a silicon nitride film. Therefore, the decrease in the dielectric strength of the transistor 100 can be suppressed, and the dielectric strength can be increased. This improves the resistance of the transistor 100 and suppresses electrostatic damage to the transistor 100.

[0087] [Oxide semiconductor film] For the oxide semiconductor film 108, the above-mentioned materials can be used.

[0088] When the oxide semiconductor film 108b is an In-M-Zn oxide, the In-M-Zn oxide is formed. The atomic ratio of the metal elements in the sputtering target used for this purpose satisfies In>M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is I n:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4 .1 etc.

[0089] In addition, when the oxide semiconductor film 108c is an In-M-Zn oxide, The atomic ratio of metal elements in the sputtering target used to deposit the film is In≦M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn= 1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, etc. do.

[0090] The oxide semiconductor film 108b and the oxide semiconductor film 108c are each an In-MZ In the case of n-oxide, polycrystalline In-M-Zn oxide is used as the sputtering target. It is preferable to use a target containing polycrystalline In-M-Zn oxide. By using the above, the oxide semiconductor films 108b and 108c having crystallinity can be formed. Note that the oxide semiconductor film 108b and the oxide semiconductor film 108c are formed. The atomic ratios of the metal elements contained in the sputtering target are For example, the sputtering of the oxide semiconductor film 108b When the atomic ratio of In:Ga:Zn=4:2:4.1 is used as the target, the film is formed. The atomic ratio of the oxide semiconductor film 108b to be formed is approximately In:Ga:Zn=4:2:3. There are cases.

[0091] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using a nitride semiconductor, the off-state current of the transistor 100 can be reduced. In addition, the oxide semiconductor film 108b has an energy gap of 2 eV or more, preferably 2 eV or more. The oxide semiconductor film 108c has an energy It is preferable to use an oxide semiconductor film having a gap of 2.5 eV or more and 3.5 eV or less. In addition, the energy gap of the oxide semiconductor film 108c is larger than that of the oxide semiconductor film 108b. It is preferable to do so.

[0092] The oxide semiconductor film 108b and the oxide semiconductor film 108c each have a thickness of 3n m or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 200 nm or less. The thickness should be 50 nm or more.

[0093] As the oxide semiconductor film 108c, an oxide semiconductor film with low carrier density is used. For example, the second oxide semiconductor film 108c has a carrier density of 1×10 17 cm -3 below , preferably 1 x 10 15 cm -3 Less than 1×10, more preferably 13 cm -3 below, More preferably, 1×10 11 cm -3 The following applies.

[0094] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of the transistor, the oxide semiconductor film 108b and the oxide semiconductor The carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, and interatomic It is preferable to set the distance, density, etc. appropriately.

[0095] Note that the oxide semiconductor films 108b and 108c each contain impurities. By using an oxide semiconductor film with a low concentration of dopants and a low density of defect states, it is possible to obtain even better electrical properties. In this embodiment, the impurity concentration is low, and A low density of defect levels (low oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film is characterized in that a carrier generation source is Therefore, the carrier density can be reduced. The transistor in which the gate region is formed has electrical characteristics in which the threshold voltage is negative (normal Also, it is rare for the product to become intrinsic or substantially intrinsic. In some oxide semiconductor films, the density of defect states is low, and therefore the density of trap states may also be low. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a significantly low off-state current. It is very small and has a channel width of 1×10 6 Even if the element has a channel length L of 10 μm, When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, The off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 After A The following characteristics can be obtained.

[0096] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is provided with a channel. The transistors in which the regions are formed have small variations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor film are dissipated. It takes a long time for the charge to reach a certain level, and it may behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states has a high current density. Impurities include hydrogen, nitrogen, alkali metals, or Alkaline earth metals, etc.

[0097] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. In this case, oxygen vacancies are formed in the lattice from which oxygen has been desorbed (or in the portion from which oxygen has been desorbed). When hydrogen enters the electron carrier, it can generate electrons. It can combine with oxygen, which combines with metal atoms, to generate electrons, which are carriers. A transistor using an oxide semiconductor film containing hydrogen has normally-on characteristics. For this reason, it is preferable that the amount of hydrogen in the oxide semiconductor film 108 be reduced as much as possible. Specifically, in the oxide semiconductor film 108, a hydrogen concentration obtained by SIMS analysis is Degrees, 2 x 10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than or equal to 5×1, more preferably 0 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 below Let us assume that.

[0098] In addition, the oxide semiconductor film 108b has a region with a lower hydrogen concentration than the oxide semiconductor film 108c. It is preferable that the oxide semiconductor film 108b has a region larger than the oxide semiconductor film 108c. By having a region with a low hydrogen concentration, a highly reliable semiconductor device can be obtained.

[0099] In addition, in the oxide semiconductor film 108b, silicon and carbon, which are Group 14 elements, If the oxide semiconductor film 108b contains oxygen, oxygen vacancies are increased in the oxide semiconductor film 108b, causing the oxide semiconductor film 108b to become n-type. Therefore, the concentrations of silicon and carbon in the oxide semiconductor film 108b and the oxide semiconductor film 10 The concentration of silicon and carbon near the interface with 8b (concentration obtained by SIMS analysis) is 2× 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3The following do.

[0100] In addition, in the oxide semiconductor film 108b, the alkali metal or alkaline earth metal concentration, 1×10 18 atoms / cm 3 Below, preferably 2x 10 16 atoms / cm 3 The following are the oxides of alkali metals and alkaline earth metals. When it bonds with a semiconductor, carriers may be generated, increasing the off-state current of the transistor. For this reason, the alkali metal or alkaline earth metal of the oxide semiconductor film 108b may be It is preferable to reduce the concentration of metalloids.

[0101] When the oxide semiconductor film 108b contains nitrogen, electrons that serve as carriers are generated. The carrier density increases and the oxide semiconductor film containing nitrogen is easily converted to n-type. A transistor using the oxide semiconductor film tends to be normally on. In the present invention, it is preferable that the nitrogen content is reduced as much as possible. For example, it is preferable that the nitrogen content is reduced as much as possible by SIMS analysis. The resulting nitrogen concentration is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0102] The oxide semiconductor film 108b and the oxide semiconductor film 108c each have a non-single crystal structure. The non-single crystal structure may be, for example, CAAC-OS (C Axis Alias) which will be described later. gned Crystalline Oxide Semiconductor), polyconductor The non-single crystalline structure includes a crystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single crystalline structure, the amorphous structure is the most The defect state density of CAAC-OS is the lowest.

[0103] [Insulating film that functions as the second gate insulating film] The insulating films 114 and 116 function as a second gate insulating film of the transistor 100 . The insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108. That is, the insulating films 114 and 116 contain oxygen. The insulating film 114 is an insulating film that can be used to form an insulating film 116 to be formed later. The oxide semiconductor film 108 also functions as a film for reducing damage to the oxide semiconductor film 108 during the formation of the oxide semiconductor film 108.

[0104] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0105] In addition, it is preferable that the insulating film 114 has a small amount of defects. Typically, the insulating film 114 has a small amount of defects as determined by ESR measurement. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 3×10 17 spins / cm 3 This is because the insulating film 114 is preferably If the density of defects is high, oxygen will be bonded to the defects, and the oxygen in the insulating film 114 will The amount of transmission of the light is reduced.

[0106] In the insulating film 114, all of the oxygen that has entered the insulating film 114 from the outside is Some oxygen does not move to the outside of the insulating film 114 and remains in the insulating film 114. At the same time, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, In some cases, oxygen may move through the film 114. When the oxide insulating film capable of forming the insulating film 116 is formed over the insulating film 114, The desorbed oxygen can be transferred to the oxide semiconductor film 108 through the insulating film 114. .

[0107] The insulating film 114 is formed using an oxide insulating film having a low density of states caused by nitrogen oxides. Note that the density of states due to the nitrogen oxides can be determined by the valence Energy of the upper edge of the electronic band (Ev_os) and the lower edge of the conduction band of the oxide semiconductor film The oxide insulating film may be formed between the gate electrodes of the SiO_O_2 layer and the gate electrodes of the SiO_O_2 layer. Silicon oxynitride film with low emission or aluminum oxynitride film with low emission of nitrogen oxide For example, a tungsten film or the like can be used.

[0108] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, is This membrane releases more ammonia than nitrogen oxides, and typically releases ammonia. The amount of emission is 1×10 18 molecule / cm 3 5×10 or more 19 molecule / cm 3 The following is the case. The amount of ammonia released is controlled when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 50°C or higher. The amount released is determined by heat treatment at 550°C or less.

[0109] Nitrogen oxides (NO x , x is more than 0 and not more than 2, preferably 1 or more and not more than 2), typically NO or NO forms a level in the insulating film 114 or the like. The level is Therefore, the nitrogen oxide is located in the energy gap of the insulating film 114 and When the oxide semiconductor film 108 diffuses to the interface, the level traps electrons on the insulating film 114 side. As a result, the trapped electrons may wrap around the insulating film 114 and the oxide semiconductor. Since the ions remain near the interface with the semiconductor film 108, the threshold voltage of the transistor is shifted in the positive direction. It will cause.

[0110] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in the insulating film 116 reacts with ammonia contained in the insulating film 116 during the heat treatment. Therefore, the amount of nitrogen oxide contained in the insulating film 114 is reduced. Electrons are less likely to be trapped at the interface between the oxide semiconductor film 106 and the oxide semiconductor film 108.

[0111] By using the oxide insulating film as the insulating film 114, the threshold voltage of the transistor It is possible to reduce the shift in the electrical characteristics of the transistor. can.

[0112] Heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher and lower than 350° C. By the heat treatment, the insulating film 114 shows the following characteristics in the spectrum obtained by ESR measurement at 100K or less: The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2.001 to 2.002. A second signal with a g value of .003 or less and a third signal with a g value between 1.964 and 1.966, inclusive. A null is observed. Note that the split width of the first signal and the second signal, The split width of the second and third signals is about 5 in the X-band ESR measurement. mT. The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 The sum of the spin densities of the third signal is 1 × 10 18spins / cm 3 Less than Typically, it is 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Not yet It is full.

[0113] In the ESR spectrum below 100K, the g value is 2.037 or more and 2.039 or less. The first signal below, the second signal with a g-value between 2.001 and 2.003, and the g-value The sum of the spin densities of the third signal, which is greater than or equal to 1.964 and less than or equal to 1.966, is the nitrogen oxide Monster (NO x (x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2) Representative examples of nitrogen oxides include nitrogen monoxide and nitrogen dioxide. The first signal is between 2.037 and 2.039, and the g value is between 2.001 and 2.003. and the third signal having a g value of 1.964 or more and 1.966 or less. The lower the total density of the pins, the lower the nitrogen oxide content in the oxide insulating film. I can say.

[0114] The nitrogen concentration of the oxide insulating film measured by SIMS is 6×10 20 atoms / cm 3 The following is the result.

[0115] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating film by the VD method, a dense and hard film can be obtained. It can be formed.

[0116] The insulating film 116 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film containing more oxygen than the stoichiometric composition is formed using When heated, some of the oxygen is released. The oxygen content is greater than the stoichiometric composition. The oxide insulating film had a loss of oxygen of 1.0×10 in terms of oxygen atoms as determined by TDS analysis. 1 9 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 That's all. The oxide insulating film is used. The surface temperature of the film in the above TDS is 100°C or higher and 70°C or lower. A temperature range of 0° C. or lower, or 100° C. to 500° C. is preferred.

[0117] The insulating film 116 has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., having a thickness of 400 nm or less can be used.

[0118] In addition, it is preferable that the insulating film 116 has a small amount of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5 x 10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 Note that the insulating film 116 is preferably an oxide semiconductor compared to the insulating film 114. Since it is separated from the insulating film 108, it may have a higher defect density than the insulating film 114.

[0119] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating films In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly seen. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a dashed line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. For example, the insulating film 114 may have a single layer structure or a laminated structure of three or more layers. Good too.

[0120] [Insulating film functioning as a protective insulating film] The insulating film 118 functions as a protective insulating film for the transistor 100 .

[0121] The insulating film 118 contains either hydrogen or nitrogen, or both. The insulating film 118 contains nitrogen and silicon. The insulating film 118 contains oxygen, hydrogen, water, and alkali. The insulating film 118 has a function of blocking metals, alkaline earth metals, etc. As a result, oxygen diffuses from the oxide semiconductor film 108 to the outside, and oxygen contained in the insulating films 114 and 116 is prevented from diffusing. The diffusion of oxygen from the outside and the entry of hydrogen, water, and the like into the oxide semiconductor film 108 from the outside are prevented. It can be prevented.

[0122] The insulating film 118 may be, for example, a nitride insulating film. Examples include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. etc.

[0123] The above-mentioned various films, such as the conductive film, the insulating film, the oxide semiconductor film, and the metal film, can be formed by sputtering. It can be formed by a deposition method or a PECVD method, but other methods such as thermal CV It may be formed by a Chemical Vapor Deposition (D) method. As an example of thermal CVD, MOCVD (Metal Organic Chemical Vapor Deposition) is apor deposition method or ALD (Atomic Layer Deposition) method Examples include the (position) method.

[0124] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no additional steps are required.

[0125] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing the reactants on the substrate. You may go.

[0126] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating the gas introduction sequence.

[0127] Thermal CVD methods such as MOCVD and ALD can be used to form the conductive film, insulating film, and oxide film of the above-mentioned embodiment. It is possible to form various films such as semiconductor films and metal oxide films. For example, In-Ga-Zn When forming an O film, trimethylindium, trimethylgallium, and dimethylzinc are used. Lead is used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for dimethylzinc is is Zn(CH3)2. In addition, the combination is not limited to these, and trimethylgalactan Triethylgallium (chemical formula Ga(C2H5)3) can be used instead of diethylgallium. Diethylzinc (chemical formula Zn(C2H5)2) can be used instead of methylzinc.

[0128] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is made by vaporizing hafnium amide (such as TDMAH) and acid. Two types of gases are used: tetrakisdimethylamide (TDA) and ozone (O3). The chemical formula for fluorine is Hf[N(CH3)2]4. Other liquid materials include tetrahydrofuran. Examples include rakis(ethylmethylamido)hafnium.

[0129] For example, when forming an aluminum oxide film using an ALD deposition system, A liquid containing a catalyst and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is added. Two types of gases are used: vaporized source gas and H2O as an oxidizing agent. The chemical formula for aluminum is Al(CH3)3. Other liquid materials include Tris( Dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2 ,2,6,6-tetramethyl-3,5-heptanedionate).

[0130] For example, when forming a silicon oxide film using a deposition system that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, the chlorine contained in the adsorbed matter is removed, and the oxidizing gas (O 2. Nitrous oxide (NO) radicals are supplied to react with the adsorbed material.

[0131] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by repeatedly introducing B2H6 gas and WF A tungsten film is formed using B2H6 gas and H2 gas. iH4 gas may also be used.

[0132] For example, an oxide semiconductor film, such as In-Ga-ZnO, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- An O layer is formed, and then a GaO layer is formed using Ga(CH3)3 gas and O3 gas. After that, a ZnO layer is formed using Zn(CH3)2 gas and O3 gas. The order of these layers is not limited to this example. In addition, by mixing these gases, In-Ga-O layers and In A mixed compound layer such as a -Zn-O layer or a Ga-Zn-O layer may be formed. Instead of H, H2O gas obtained by bubbling with an inert gas such as Ar may be used. It is preferable to use O3 gas that does not contain In. (C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2 H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0133] <1-3. Configuration example 2 of semiconductor device> Next, modified examples of the transistor 100 shown in FIGS. This will be explained using Figure 6.

[0134] 2A and 2B show a transistor which is a modification of the transistor 100 shown in FIGS. 1B and 1C. 3A and 3B are cross-sectional views of the transistor 100A shown in FIG. 4B is a cross-sectional view of a transistor 100B, which is a modification of the transistor 100. A) and (B) are transistors which are modifications of the transistor 100 shown in FIGS. 1(B) and (C). 5(A) and (B) are cross-sectional views of the transistor 100C shown in FIG. 6(A) and 6(B) are cross-sectional views of a transistor 100D, which is a modified example of the transistor 100. 1B and 1C, a transistor 100E FIG.

[0135] The transistor 100A shown in FIGS. 2A and 2B is a transistor 100A shown in FIGS. The oxide semiconductor film 108 included in the capacitor 100 has a three-layer structure. The oxide semiconductor film 108 included in the transistor 100A includes an oxide semiconductor film 108a and an oxide The oxide semiconductor film 108b on the oxide semiconductor film 108a and the oxide semiconductor film 108b on the oxide semiconductor film 108b and a semiconductor film 108c.

[0136] The transistor 100B shown in FIGS. 3A and 3B is a transistor having a structure similar to that shown in FIGS. The oxide semiconductor film 108 of the transistor 100 has a single-layer structure. The transistor 100B includes an oxide semiconductor film 108b.

[0137] The transistor 100C shown in FIGS. 4A and 4B is a transistor having a structure similar to that shown in FIGS. The shape of the oxide semiconductor film 108 in the transistor 100 is different. In the drawing, the oxide semiconductor film 108c in the semiconductor device 100 is separated from the conductive films 112a and 112b. In other words, the thickness of the region exposed from the oxide semiconductor film is thin. On the other hand, the oxide semiconductor film 108c included in the transistor 100C is In the drawing, the thickness of the area exposed from the conductive films 112a and 112b is not thin. In this case, part of the oxide semiconductor film does not have a recess.

[0138] The transistor 100D shown in FIGS. 5A and 5B is a transistor having a structure similar to that shown in FIGS. The structures of the conductive films 112a, 112b, and 112c of the photovoltaic cell 100 are different. The conductive films 112a, 112b, and 112c of the transistor 100D have a single-layer structure. be.

[0139] The transistor 100E shown in FIGS. 6A and 6B is a so-called channel protection type transistor. An insulating film 115 functioning as a channel protective film is provided over the oxide semiconductor film 108. The insulating film 115 can be formed using a material similar to that of the insulating film 114. In the case where the insulating film 115 is provided, the insulating film 114 is not provided, and the conductive films 112a and 11 2b, an insulating film 116 may be provided on the insulating film 115.

[0140] As described above, the semiconductor device of the present invention includes a stacked structure of oxide semiconductor films, an oxide semiconductor The present invention can be applied even if the shape of the film or the laminated structure of the conductive film is different. The transistor according to the present embodiment can be freely combined with each of the above structures. is possible.

[0141] <1-4. Manufacturing method of semiconductor device> Next, a method for manufacturing the transistor 100 which is a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 7 to 12.

[0142] 7(A) to 7(C), 8(A) to 8(C), 9(A) to 9(C), C), Figs. 10(A) to 10(C), Figs. 11(A) to 11(C), and Fig. 12 are 7A to 7C and 8 are cross-sectional views illustrating a method for manufacturing a semiconductor device. (A) to (C), Figs. 9(A) to (C), Figs. 10(A) to 10(C), In FIG. 11(A) to FIG. 11(C) and FIG. 12, the left side is a cross-sectional view in the channel length direction. The right side is a cross-sectional view in the channel width direction.

[0143] First, a conductive film is formed on the substrate 102, and the conductive film is then subjected to a lithography process and an etching process. Then, a conductive film 104 that functions as a first gate electrode is formed by carrying out a process. On the conductive film 104, insulating films 106 and 107 that function as a first gate insulating film are formed (see FIG. 7(A)).

[0144] In this embodiment, a glass substrate is used as the substrate 102, which functions as the first gate electrode. The conductive film 104 is a titanium film having a thickness of 50 nm and a copper film having a thickness of 200 nm. The insulating film 106 is formed by a nitride film having a thickness of 400 nm. A silicon film is formed by the PECVD method, and a silicon oxide nitride film having a thickness of 50 nm is formed as the insulating film 107. The silicon film is formed by the PECVD method.

[0145] The insulating film 106 may have a stacked structure of a silicon nitride film. The insulating film 106 is made of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminate structure with a silicon film can be formed. An example of the three-layer laminate structure is as follows: It can be formed as follows:

[0146] The first silicon nitride film is formed by, for example, silane at a flow rate of 200 sccm, PE-CV was performed using nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as source gas. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high-frequency If a power of 2000 W is supplied using a frequency power supply and the thickness is formed to be 50 nm, good.

[0147] For the second silicon nitride film, silane at a flow rate of 200 sccm, The nitrogen gas and the ammonia gas with a flow rate of 2000sccm were used as raw material gases in the PECVD equipment. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high-frequency power supply was used. A power of 2000 W may be supplied using the above method to form a film having a thickness of 300 nm.

[0148] The third silicon nitride film was prepared by using silane at a flow rate of 200 sccm and 5000 sccm. The pressure in the reaction chamber was kept at 100 The thickness was measured by controlling the temperature to 50 Pa and supplying 2000 W of power using a 27.12 MHz high frequency power source. It is sufficient to form it so that the thickness is 50 nm.

[0149] The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during formation can be 350° C. or less.

[0150] By forming the insulating film 106 in a three-layered structure of silicon nitride films, for example, the conductive film 10 When a conductive film containing copper is used for 4, the following effects are obtained.

[0151] The first silicon nitride film can suppress the diffusion of copper elements from the conductive film 104. The second silicon nitride film has a function of releasing hydrogen and acts as an insulating film that functions as a gate insulating film. The third silicon nitride film can improve the breakdown voltage of the film. The hydrogen released from the second silicon nitride film is small, and the diffusion of hydrogen released from the second silicon nitride film is suppressed. It is possible.

[0152] The insulating film 107 is an oxide semiconductor film 108 (more specifically, an oxide In order to improve the interface characteristics with the semiconductor film 108b), the insulating film is formed of an oxygen-containing insulating film. It is preferable that oxygen be added to the insulating film 107 after the insulating film 107 is formed. The oxygen to be added to the film 107 may be an oxygen radical, an oxygen atom, an oxygen atomic ion, or an oxygen molecule. The methods of addition include ion doping, ion implantation, plasma There are methods such as the ma processing method.

[0153] Next, the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_0 are formed over the insulating film 107. (See Figures 7(B) and (C)).

[0154] Note that FIG. 7B shows a process for forming the oxide semiconductor film 108b_0 over the insulating film 107. FIG. 7(B) is a schematic cross-sectional view of the inside of a film forming apparatus. A target 191 is installed inside the sputtering apparatus. 1 and a plasma 192 formed below.

[0155] First, when the oxide semiconductor film 108b_0 is formed, a plasma is At this time, the insulating film 107, which is to be the surface on which the oxide semiconductor film 108b_0 is to be formed, is When the oxide semiconductor film 108b_0 is formed, oxygen is added to the oxide semiconductor film 108b_0. In addition, inert gases (e.g., helium gas, argon gas, xenon gas, etc.) are mixed. It may be allowed.

[0156] The oxygen gas is contained at least when the oxide semiconductor film 108b_0 is formed. The ratio of oxygen gas in the entire deposition gas when the oxide semiconductor film 108b_0 is formed may be The ratio is more than 0% and not more than 100%, preferably 10% or more and not more than 100%, and more preferably 10% or more and not more than 100%. The range is preferably 30% or more and 100% or less.

[0157] In addition, in FIG. 7B, oxygen or excess oxygen added to the insulating film 107 is shown as It is represented by a dashed arrow.

[0158] Note that the substrate temperature during the formation of the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_0 was However, the thickness of the oxide semiconductor film 108b_0 and the thickness of the oxide semiconductor film 108b_1 may be the same or different. By making the substrate temperature the same as that of the conductive film 108c_0, the manufacturing cost can be reduced. This is preferable because

[0159] For example, the substrate temperature when the oxide semiconductor film 108 is formed is set to room temperature or higher and less than 340° C. Preferably, the temperature is from room temperature to 300° C., more preferably from 100° C. to 250° C. The temperature is preferably 100° C. or more and 200° C. or less. By doing so, the crystallinity of the oxide semiconductor film 108 can be improved. In addition, when using a large glass substrate (for example, 6th generation to 10th generation), the oxide semiconductor When the substrate temperature during deposition of the solid film 108 is set to 150° C. or higher and lower than 340° C., Therefore, when using a large glass substrate, In this case, the substrate temperature during the formation of the oxide semiconductor film 108 is set to 100° C. or higher and lower than 150° C. By doing so, deformation of the glass substrate can be suppressed.

[0160] In addition, the sputtering gas must be highly purified. The oxygen gas and argon gas used in the present invention have a dew point of -40°C or less, preferably -80°C or less, and Preferably, the gas is purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using the above, it is possible to prevent moisture and the like from being absorbed into the oxide semiconductor film as much as possible. .

[0161] In addition, when the oxide semiconductor film is formed by a sputtering method, The chamber is a clarified chamber to remove water and other impurities that may be harmful to the oxide semiconductor film as much as possible. A high vacuum (e.g., 5×10) is created using an adsorption-type vacuum pump such as an ion pump. -7 Pa From 1×10 -4 It is preferable to evacuate the gas to a level of about 10 Pa. Alternatively, a turbo molecular pump may be used. A cold trap is used to trap gas, especially carbon or hydrogen, from the exhaust system into the chamber. It is preferable to prevent the gas contained therein from flowing backward.

[0162] After the oxide semiconductor film 108b_0 is formed, the oxide semiconductor film 108c The oxide semiconductor film 108c_0 is formed on the oxide semiconductor film 108b. The conditions for forming the oxide semiconductor film 108b_0 can be similar to those for forming the oxide semiconductor film 108b_0. However, the formation conditions of the oxide semiconductor film 108b_0 and the shape of the oxide semiconductor film 108c_0 are different. The synthesis conditions may be the same or different.

[0163] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: 2:4.1 [atomic ratio]) by sputtering, 0 was formed, and then, in vacuum, an In-Ga-Zn metal oxide target (In: The oxide semiconductor was deposited by sputtering using Ga:Zn=1:1:1.2 (atomic ratio). The conductive film 108c_0 is formed. In addition, the substrate temperature during the formation of the oxide semiconductor film 108b_0 is The substrate temperature during the formation of the oxide semiconductor film 108c_0 is set to 170° C. In addition, the oxide semiconductor film 108b_0 was formed using an oxygen gas having a flow rate of 60 sccm. The oxide semiconductor film 108 is formed by oxidizing the oxide semiconductor film 108 with a flow rate of 100 sccm. The deposition gas for forming c_0 was oxygen gas with a flow rate of 100 sccm and cm of argon gas is used.

[0164] Next, the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_ are processed into desired shapes. In this way, island-shaped oxide semiconductor films 108b and 108c are formed. Note that in this embodiment, the oxide semiconductor film 108b and the oxide semiconductor film 10 The oxide semiconductor film 108 is formed from 8c (see FIG. 8A).

[0165] After the oxide semiconductor film 108 is formed, heat treatment (hereinafter referred to as first heat treatment) is performed. The first heat treatment is preferably performed to remove hydrogen from the oxide semiconductor film 108. The heat treatment for the purpose of reducing hydrogen, water, etc. The first heat treatment may be performed before processing the semiconductor film 108 into an island shape. This is one of the processes for purifying conductive films.

[0166] The first heat treatment is performed at a temperature of, for example, 150° C. or higher and lower than the distortion point of the substrate, preferably 200° C. The heating temperature can be set to 450°C or higher and more preferably 250°C or higher and 350°C or lower.

[0167] The first heat treatment can be performed using an electric furnace, an RTA device, or the like. By using this, it is possible to perform heat treatment at a temperature above the distortion point of the substrate for a short period of time. Therefore, the heating time can be shortened. Dry air (water content is 20 ppm or less, preferably 1 ppm or less, preferably 10 ppm The reaction may be carried out under an atmosphere of air (air (B) or less) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. In addition, after heat treatment in a nitrogen or rare gas atmosphere, it is heated in an oxygen or ultra-dry air atmosphere. As a result, hydrogen, water, and the like contained in the oxide semiconductor film are released, and the oxide semiconductor film is deoxidized. As a result, oxygen can be supplied to the oxide semiconductor film. The oxygen deficiency can be reduced.

[0168] Next, openings 151 are formed in desired regions of the insulating film 106 and the insulating film 107. The opening 151 reaches the conductive film 104 (see FIG. 8B).

[0169] The opening 151 is formed by either a dry etching method or a wet etching method. In this embodiment, the dry etching method is used. The opening 151 is formed by a bonding method.

[0170] Next, a conductive film 112_1 is formed over the insulating film 107, the oxide semiconductor film 108, and the conductive film 104. , 112_2 are formed (see FIG. 8(C)).

[0171] In this embodiment, a titanium film having a thickness of 30 nm is formed by sputtering as the conductive film 112_1. A copper film having a thickness of 200 nm is formed as the conductive film 112_2 by sputtering. The film is formed by the ring method.

[0172] Next, masks 141a, 141b, and 141c are formed in desired regions on the conductive film 112_2. Subsequently, the conductive film 112_2 is processed using the masks 141a, 141b, and 141c. By this, the island-shaped metal film 112a_2, the island-shaped metal film 112b_2, and the island-shaped metal film 112c_2 (see FIG. 9(A)).

[0173] In this embodiment, the conductive film 112_2 is formed by using a wet etching apparatus. However, the method for processing the conductive film 112_2 is not limited to this, and may be, for example, A dry etching device may also be used.

[0174] Next, the masks 141a, 141b, and 141c are removed. A conductive film 112_3 is formed on the metal films 112a_2, 112b_2, and 112c_2. (See Figure 9(B)).

[0175] In this embodiment, a titanium film having a thickness of 10 nm is formed by sputtering as the conductive film 112_3. By forming the conductive film 112_3, the metal film 112a_2, 112b_2 and 112c_2 are structures surrounded by the conductive film 112_1 and the conductive film 112_3. The conductive film 112_1 and the conductive film 112_3 form metal films 112a_2, 112b_2, By configuring the metal films 112a_2, 112b_2, and 112c_2 to surround each other, The copper element contained in the insulating film 2 is prevented from diffusing to the outside, particularly to the oxide semiconductor film 108. This can be done.

[0176] Next, masks 142a, 142b, and 142c are formed in desired regions on the conductive film 112_3. Subsequently, the conductive film 112_1 and the conductive By processing the conductive film 112_3, an island-shaped metal film 112a_1 and an island-shaped metal film 112b _1, an island-shaped metal film 112c_1, an island-shaped metal film 112a_3, and an island-shaped metal film 11 By carrying out this process, the metal film 2b_3 and the island-shaped metal film 112c_3 are formed. A conductive film 112a having a metal film 112a_1, a metal film 112a_2, and a metal film 112a_3; , a conductive film 1 having a metal film 112b_1, a metal film 112b_2, and a metal film 112b_3. 12b, and a metal film 112c_1, a metal film 112c_2, and a metal film 112c_3. A conductive film 112c is formed (see FIG. 9C).

[0177] In this embodiment, a dry etching apparatus is used to etch the conductive films 112_1 and The conductive film 112_3 is processed. However, the processing method of the conductive film 112_1 and the conductive film 112_3 is The method is not limited to this, and for example, a wet etching device may be used.

[0178] After the conductive films 112a and 112b are formed, the oxide semiconductor film 108 (more specifically, The surface (back channel side) of the oxide semiconductor film 108c may be cleaned. For example, cleaning using a chemical solution such as phosphoric acid can be used. By performing the cleaning, impurities (e.g., impurities formed on the surface of the conductive film 108c) are removed. The cleaning can be performed without removing the elements contained in the SiO2 particles (e.g., elements contained in 112a and 112b). In some cases, cleaning may not be required.

[0179] In addition, either one of the steps of forming the conductive films 112a and 112b and the above-mentioned cleaning step may be performed. In either case, the region of the oxide semiconductor film 108 that is exposed from the conductive films 112a and 112b is But it may become thinner.

[0180] Next, the insulating film 114 and the insulating layer 115 are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b. The border membrane 116 is formed (see FIG. 10(A)).

[0181] After the insulating film 114 is formed, the insulating film 116 is successively formed without exposing it to the air. After the insulating film 114 is formed, it is preferable to adjust the flow rate, pressure, and temperature of the source gas without exposing the insulating film 114 to the air. By adjusting one or more of the frequency power and the substrate temperature, the insulating film 116 is continuously formed. The concentration of impurities derived from atmospheric components can be reduced at the interface between the insulating film 114 and the insulating film 116. can.

[0182] For example, a silicon oxynitride film is formed as the insulating film 114 by using a PECVD method. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include silane, disilane, etc. Examples of oxidizing gases include nitrous oxide, nitrous oxide, and trisilane. In addition, the flow rate of the oxidizing gas is set to 20 times or more than 50 times the flow rate of the deposition gas. 00 times or less, preferably 40 times or more and 100 times or less.

[0183] In this embodiment, the insulating film 114 is formed by heating the substrate 102 at a temperature of 220° C. The source gases were silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm. The pressure in the treatment chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 M. Hz, 100W (power density is 1.6×10 -2 W / cm2 ) PECVD method A silicon oxynitride film is formed using this.

[0184] The insulating film 116 is formed by depositing a substrate in a vacuum-evacuated processing chamber of a PECVD apparatus. The temperature is kept at 180°C or higher and 350°C or lower, and the raw material gas is introduced into the treatment chamber to increase the pressure in the treatment chamber. is set to 100 Pa or more and 250 Pa or less, and more preferably set to 100 Pa or more and 200 Pa or less. 0.17 W / cm2 at the electrode installed in the treatment chamber 2 More than 0.5W / cm 2 Below are some more Preferably 0.25W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: In this way, a silicon oxide film or a silicon oxynitride film is formed.

[0185] The conditions for forming the insulating film 116 are as follows: high frequency power density in a reaction chamber with the above pressure; By supplying power, the efficiency of decomposition of the source gas in the plasma increases, and the number of oxygen radicals increases. As the oxidation of the source gas progresses, the oxygen content in the insulating film 116 becomes lower than the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, the bonding strength between silicon and oxygen is Since the oxygen in the film is weak, some of the oxygen in the film is released by the heat treatment in the subsequent process. An oxide that contains more oxygen than satisfies the theoretical composition and loses some of the oxygen when heated. An insulating film can be formed.

[0186] In the step of forming the insulating film 116, the insulating film 114 serves as a protection film for the oxide semiconductor film 108. Therefore, the power density can be reduced while reducing damage to the oxide semiconductor film 108. The insulating film 116 can be formed using high radio frequency power.

[0187] In the deposition conditions for the insulating film 116, a deposition gas containing silicon is mixed with an oxidizing gas. By increasing the flow rate of the gas, it is possible to reduce the amount of defects in the insulating film 116. In the first place, ESR measurements revealed that the g value was 2.001, which is due to the dangling bonds of silicon. The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 spins / cm 3 Less than or equal to 1.5×10 17 spins / cm 3 The following is a missing As a result, the signal quality of the transistor 100 can be improved. It can increase reliability.

[0188] After the insulating films 114 and 116 are formed, heat treatment (hereinafter referred to as second heat treatment) is performed. The nitrogen oxide contained in the insulating films 114 and 116 is preferably removed by the second heat treatment. Alternatively, the second heat treatment can reduce the amount of oxides in the insulating films 114 and 116. Part of the oxygen contained in the oxide semiconductor film 108 is transferred to the oxide semiconductor film 108. This can reduce the oxygen vacancies that occur.

[0189] The temperature of the second heat treatment is typically less than 400° C., preferably less than 375° C., and The second heat treatment is preferably performed at a temperature of 150° C. or higher and 350° C. or lower. Dry air (water content is 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb The reaction may be carried out under an atmosphere of air (see below) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. The heat treatment can be performed using an electric furnace, RTA, or the like.

[0190] Next, an oxide conductive film 120_1 is formed over the insulating film 116 (see FIGS. 10B and 10C). ).

[0191] FIG. 10B shows a film formation process for forming the oxide conductive film 120_1 over the insulating film 116. FIG. 10(B) is a schematic cross-sectional view of the inside of the device. A target 193 is installed inside the sputtering apparatus. 1 and a plasma 194 formed below the plasma 194 are shown diagrammatically.

[0192] First, when forming the oxide conductive film 120_1, plasma is generated in an atmosphere containing oxygen gas. At this time, an oxide conductive film 120_1 is formed on the insulating film 116, and an oxide conductive film 120_2 is formed on the insulating film 116. When forming the oxide conductive film 120_1, in addition to oxygen gas, inactive A reactive gas (e.g., helium gas, argon gas, xenon gas, etc.) may be mixed. .

[0193] The oxygen gas may be any gas that is contained at least when the oxide conductive film 120_1 is formed. The ratio of oxygen gas to the total deposition gas when forming the oxide conductive film 120_1 is often The ratio is more than 0% and not more than 100%, preferably 10% or more and not more than 100%, and more preferably is between 30% and 100%.

[0194] In FIG. 10B, oxygen or excess oxygen added to the insulating film 116 is The dashed arrow indicates the

[0195] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: 2:4.1 [atomic ratio]) by sputtering to form an oxide conductive film 120_1. Form.

[0196] In this embodiment, when the oxide conductive film 120_1 is formed, the insulating film 116 is not subjected to oxidation. However, the present invention is not limited to the above-mentioned method. For example, After the formation of the insulating film 116, oxygen may be further added to the insulating film 116.

[0197] The method of adding oxygen to the insulating film 116 is, for example, a method of adding indium, tin, and silicon. An oxide (also called ITSO) target having In2O3:SnO2:SiO2= 85:10:5 [wt %]) to form a 5 nm thick ITSO film on an oxide conductive film 120_ Form as 1.

[0198] In this case, the thickness of the oxide conductive film 120_1 is 1 nm or more and 20 nm or less, When the thickness is set to 2 nm or more and 10 nm or less, oxygen can be suitably transmitted and oxygen release can be suppressed. Then, oxygen is added to the insulating film 116 by passing through the oxide conductive film 120_1. Methods for adding oxygen include ion doping, ion implantation, plasma treatment, etc. In addition, applying a bias voltage to the substrate side when adding oxygen is effective. In addition, oxygen can be added to the insulating film 116. The power density of the bias voltage applied to the substrate side of the ashing device was set to 1 W / cm 2 More than 5W / cm 2 The substrate temperature when oxygen is added is set to 0.5° C. or less. In this case, the temperature is set to be from room temperature to 300°C, preferably from 100°C to 250°C. Oxygen can be efficiently added to the insulating film 116.

[0199] Next, a mask is formed on the oxide conductive film 120_1 by a lithography process. Openings 152a and 152b are formed in desired regions of the conductive film 120_1 and the insulating films 114 and 116. The opening 152a is formed so as to reach the conductive film 112b. The portion 52b is formed so as to reach the conductive film 112c (see FIG. 11A).

[0200] The openings 152a and 152b are formed by dry etching and wet etching. In this embodiment, the driver circuit can be formed by using either one or both of the above. The openings 152a and 152b are formed by dry etching.

[0201] Next, a metal film 12 is formed on the oxide conductive film 120_1, the conductive film 112b, and the conductive film 112c. 0_2 (see FIG. 11(B)).

[0202] In this embodiment, the metal film 120_2 is formed by sputtering to a thickness of 100 nm. A titanium film having a thickness of 1 m is formed.

[0203] Next, a mask is formed on the metal film 120_2 by lithography, and then the metal film 12 0_2 and the oxide conductive film 120_1 are processed into a desired shape to form an island-shaped conductive film 12 The conductive film 120a is an island-shaped oxide film. The conductive film 120a_1 and the island-shaped metal film 120a_2 are included. The conductive film 120b is an island-shaped The insulating film 120b includes an oxide conductive film 120b_1 and an island-shaped metal film 120b_2 (see FIG. 11(C)). see).

[0204] Next, an insulating film 118 is formed on the insulating film 116 and the conductive films 120a and 120b (FIG. 12).

[0205] The insulating film 118 contains either hydrogen or nitrogen, or both. For example, a silicon nitride film is preferably used as the insulating film 118. For example, it can be formed by using a sputtering method or a PECVD method. When the insulating film 118 is formed by the PECVD method, the substrate temperature is set to less than 400° C., preferably less than 375° C. The temperature is preferably less than 180° C. and more preferably 350° C. or higher. In this case, it is preferable to set the substrate temperature in the above-mentioned range since a dense film can be formed. By setting the substrate temperature in the above range when forming the insulating film 118, the insulating films 114 and 1 Therefore, oxygen or excess oxygen in the oxide semiconductor film 106 can be moved to the oxide semiconductor film 108.

[0206] In addition, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, silicon It is preferable to use a deposition gas containing nitrile, nitrogen, and ammonia as the source gas. By using a small amount of ammonia compared to hydrogen, ammonia dissociates in the plasma and becomes active. The active species are generated by bonding with silicon and hydrogen contained in the silicon-containing deposition gas. This breaks the triple bond between silicon and nitrogen. As a result, the bond between silicon and nitrogen is promoted, It is possible to form a dense silicon nitride film with few silicon and hydrogen bonds and few defects. On the other hand, if the amount of ammonia relative to nitrogen is large, the deposition gas containing silicon and the nitrogen The decomposition of the silicon does not proceed, silicon and hydrogen bonds remain, and defects increase and the material becomes rough. For these reasons, the source gas is not suitable for ammonia. It is preferable that the flow rate ratio of nitrogen to oxygen is 5 times or more and 50 times or less, and more preferably 10 times or more and 50 times or less.

[0207] In this embodiment, the insulating film 118 is formed by depositing silane, nitrogen, etc., using a PECVD apparatus. A silicon nitride film with a thickness of 50 nm is formed using nitrogen and ammonia as source gases. The flow rates were 50 sccm for silane, 5000 sccm for nitrogen, and 100 for ammonia. The pressure in the processing chamber was 100 Pa, the substrate temperature was 350°C, and the flow rate was 27.12 MWh. A high-frequency power supply of 1000 W is supplied to the parallel plate electrodes. The device has an electrode surface area of ​​6000 cm 2 The parallel plate type PECVD equipment is The force can be converted to power per unit area (power density) of 1.7 x 10 -1 W / cm 2 is .

[0208] After the insulating film 118 is formed, the insulating film 118 is heated by the same heat treatment as the first heat treatment and the second heat treatment described above. A heat treatment (hereinafter referred to as a third heat treatment) may be performed.

[0209] By performing the third heat treatment, a conductive oxide film 120_1 is added to the insulating film 116 during the formation of the conductive oxide film 120_1. The added oxygen moves into the oxide semiconductor film 108 (particularly the oxide semiconductor film 108b) and is oxidized. The oxygen vacancies in the semiconductor film 108 are compensated for.

[0210] Through the above steps, the transistor 100 illustrated in FIGS.

[0211] In addition, in all the manufacturing steps of the transistor 100, the substrate temperature is preferably less than 400° C. or less than 375°C, and more preferably 180°C to 350°C. This is preferable because it is possible to minimize deformation (distortion or warping) of the substrate even when using the substrate. In the manufacturing process of the transistor 100, the substrate temperature is increased. Typically, the substrate temperature during the formation of the insulating films 106 and 107 is less than 400° C., preferably The substrate temperature during deposition of the oxide semiconductor film 108 (room temperature or higher, 3 Less than 40°C, preferably 100°C to 200°C, more preferably 100°C to 15 0° C.), the substrate temperature during deposition of the insulating films 116 and 118 (less than 400° C., preferably 37 5°C or less, more preferably 180°C or more and 350°C or less), the first heating treatment, the second heating or a third heat treatment (less than 400° C., preferably less than 375° C., more preferably (180°C or higher and 350°C or lower).

[0212] Note that the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0213] (Embodiment 2) In this embodiment, a composition of an oxide semiconductor that can be used in one embodiment of the present invention will be described. The structure of the oxide semiconductor and the like will be described with reference to FIGS.

[0214] <2-1. Composition of oxide semiconductor> First, the composition of the oxide semiconductor will be described.

[0215] The oxide semiconductor preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0216] Here, a case will be considered in which the oxide semiconductor contains indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Applicable elements for element M include boron, silicon, titanium, iron, nickel, and germanium. Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Tantalum However, the element M may be a combination of multiple of the above elements. It's okay to combine them.

[0217] First, the oxidation method according to the present invention will be described with reference to FIGS. 13(A), 13(B), and 13(C). The preferable range of the atomic ratio of indium, element M, and zinc contained in the compound semiconductor will be described. In addition, the atomic ratio of oxygen is not shown in FIG. 13. The atomic ratios of indium, element M, and zinc are [In], [M], and and [Zn].

[0218] In Figures 13(A), 13(B), and 13(C), the dashed lines indicate the ratio of [In]:[M ]:[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):3, [I n]:[M]:[Zn]=(1+α):(1-α):4, and The line showing the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 is shown. vinegar.

[0219] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β is The line where the atomic ratio is 1:3:β, [In]:[M]:[Zn ]=1:4:β atomic ratio line, [In]:[M]:[Zn]=2:1:β atomic ratio line The line with the atomic ratio of [In]:[M]:[Zn]=5:1:β Represents in.

[0220] The dotted line indicates the atomic number of [In]:[M]:[Zn]=(1+γ):2:(1-γ). The line where the ratio (-1 ≦ γ ≦ 1) is shown in FIG. n] = 0:2:1 or a value close to that. It is easy to take.

[0221] 13A and 13B show an indium-ion semiconductor layer in an oxide semiconductor of one embodiment of the present invention. 1 shows an example of a preferable range of the atomic ratio of tungsten, the element M, and zinc.

[0222] As an example, FIG. 14 shows InMZn where [In]:[M]:[Zn]=1:1:1. Figure 14 shows the crystal structure of InMZ when observed from a direction parallel to the b-axis. The crystal structure of nO4 is shown in FIG. 14. The layer having M, Zn, and oxygen (hereinafter, (M, The metal element in the layer (Zn) represents element M or zinc. In this case, element M and zinc The proportion of lead is equal. The elements M and zinc are interchangeable and the arrangement is random. do.

[0223] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 14. The layer containing elements M, zinc, and oxygen (hereinafter referred to as the In layer) is 1. The (M,Zn) layer containing oxygen is layer 2.

[0224] Indium and element M can be substituted for each other. Therefore, the elements of the (M, Zn) layer The element M can be replaced with indium and expressed as an (In,M,Zn) layer. In that case, In It has a layered structure with one layer and two (In,M,Zn) layers.

[0225] In an oxide semiconductor with an atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer It has a layered structure with 1 (M,Zn) layer and 3 (M,Zn) layers. On the other hand, when [Zn] becomes large, when the oxide semiconductor crystallizes, the (M,Z n) layer proportion increases.

[0226] However, in the oxide semiconductor, the number of In layers is 1 and the number of (M, Zn) layers is a non-integer. In this case, there may be multiple types of layered structures in which the number of In layers is 1 and the number of (M, Zn) layers is an integer. For example, when [In]:[M]:[Zn]=1:1:1.5, the In layer is 1: The layered structure with two (M, Zn) layers and the layered structure with three (M, Zn) layers are mixed. In some cases, a layered structure may result.

[0227] For example, when an oxide semiconductor is formed by a sputtering device, the atomic ratio of the target In particular, depending on the substrate temperature during film formation, the target In some cases, the [Zn] of the film may be smaller than the [Zn] of the substrate.

[0228] In addition, a plurality of phases may coexist in an oxide semiconductor (eg, two-phase coexistence, three-phase coexistence, etc.). For example, in the atomic ratio [In]:[M]:[Zn]=0:2:1, which is close to the atomic ratio In [In], two phases, a spinel type crystal structure and a layered crystal structure, tend to coexist. At the atomic ratio near the atomic ratio of [M]:[Zn]=1:0:0, Two phases, a crystalline structure with a silicide layer and a layered crystalline structure, tend to coexist. When these coexist, grain boundaries form between different crystal structures. may be formed.

[0229] In addition, by increasing the indium content, the carrier mobility (electron transfer) of the oxide semiconductor is improved. This is because the oxide semiconductor having indium, element M and zinc can be In conductors, the s-orbitals of heavy metals mainly contribute to carrier conduction, and the indium content By increasing the indium content, the area where the s orbitals overlap becomes larger. Oxide semiconductors with a high indium content have a higher carrier mobility than oxide semiconductors with a low indium content. This is because

[0230] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0, and In the atomic ratios near this value (for example, region C shown in FIG. 13C), the insulating properties become high. .

[0231] Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility and few grain boundaries. It is preferable that the atomic ratio be that shown in region A in FIG. 13(A), which is likely to form a layer structure having a good atomic ratio. It is.

[0232] In addition, in the region B shown in FIG. 13B, [In]:[M]:[Zn]=4:2:3 to 4 .1 and its neighboring values. For example, the atomic ratio [In]:[M ]:[Zn]=5:3:4. Oxide semiconductors having the atomic ratio shown in region B In particular, it is an excellent oxide semiconductor having high crystallinity and high carrier mobility.

[0233] The condition for an oxide semiconductor to form a layered structure is not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. However, depending on the formation conditions, a layered structure may or may not be formed. The illustrated region is a region showing the atomic ratio in which the oxide semiconductor has a layered structure. The boundaries between areas A and C are not strict.

[0234] <2-2. Structure using oxide semiconductor in transistor> Next, a structure in which an oxide semiconductor is used for a transistor will be described.

[0235] By using an oxide semiconductor for a transistor, carrier scattering at grain boundaries can be reduced. This allows the realization of a transistor with high field effect mobility. Moreover, a highly reliable transistor can be realized.

[0236] In addition, an oxide semiconductor with low carrier density is used for a channel region of a transistor. For example, the oxide semiconductor has a carrier density of 8×10 11 / cm 3Less than, good Preferably 1×10 11 / cm 3 less than 1×10 10 / cm 3 Less than , 1×10 -9 / cm 3 That should be enough.

[0237] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a carrier generation source. Since the carrier density is low, the carrier density can be reduced. Intrinsic oxide semiconductors have a low density of defect states and therefore a low density of trap states. There are cases.

[0238] In addition, the time required for the charge trapped in the trap level of the oxide semiconductor to disappear is Therefore, the trap level density is high. In a transistor in which a channel region is formed in a thin oxide semiconductor, the electrical characteristics may become unstable. There is a match.

[0239] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In order to reduce the impurity concentration in the oxide semiconductor, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0240] Here, the influence of each impurity in an oxide semiconductor will be described.

[0241] When oxide semiconductors contain silicon or carbon, which is one of the group 14 elements, they become oxidized. Defect levels are formed in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (secondary ion mass spectrometry) (SIMS: Secondary Ion Mass Spectrometry) The concentration that can be obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0242] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, the defect level is reduced. Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such an element tends to be normally-on. Therefore, it is possible to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, it is preferable to use an alkali metal or The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0243] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and The nitrogen density increases and it becomes easier to make the oxide semiconductor n-type. Therefore, the transistor used in the oxide semiconductor In this case, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen content in the oxide semiconductor is The concentration is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm3 Less than or equal to 1×10 18 atoms / cm 3 Below, More preferably 5×10 17 atoms / cm 3 The following applies.

[0244] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the carrier, In some cases, hydrogen atoms are formed by bonding with oxygen atoms that bond with metal atoms. Therefore, it is necessary to use an oxide semiconductor that contains hydrogen. Therefore, the hydrogen in the oxide semiconductor tends to cause a transistor to be normally on. It is preferable that the Si content in the oxide semiconductor is as low as possible. The hydrogen concentration obtained by MS is 1×10 20 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 Less than.

[0245] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, This makes it possible to impart stable electrical characteristics.

[0246] In addition, the oxide semiconductor film has an energy gap of 2 eV or more, or 2.5 eV or more. Alternatively, it is preferably 3 eV or more.

[0247] The thickness of the oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 100 nm. 00 nm or less, and more preferably 3 nm or more and 60 nm or less.

[0248] In addition, when the oxide semiconductor film is an In-M-Zn oxide film, the In-M-Zn oxide film is formed. The atomic ratio of the metal elements in the sputtering target used for the sputtering was In:M:Zn. =1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, I n:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2 :1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M: Zn=5:1:7, etc. is preferred.

[0249] The atomic ratio of metal elements in the oxide semiconductor film to be formed is set to the above-mentioned sputtering ratio. The atomic ratio of metal elements contained in the target varies by about ±40%. For example, a sputtering target with an atomic ratio of In:Ga:Zn=4: When 2:4.1 is used, the atomic ratio of the oxide semiconductor film to be formed is In:Ga:Zn= In some cases, the atomic ratio is around 4:2:3. In the case where In:Ga:Zn=5:1:7 is used, the atomic ratio of the oxide semiconductor film to be formed is In some cases, the ratio is approximately In:Ga:Zn=5:1:6.

[0250] <2-3. Stacked structure of oxide semiconductors> Next, a stacked structure of oxide semiconductors will be described.

[0251] Here, the oxide semiconductor has a two-layer structure or a three-layer structure. The case where the oxide semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S The band diagram of the insulator in contact with the stacked structure of S3 and the product of the oxide semiconductor S2 and the oxide semiconductor S3 are shown in FIG. The band diagram of the insulator in contact with the layer structure will be explained with reference to FIG.

[0252] FIG. 15A shows an insulator I1, an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S FIG. 15 is an example of a band diagram in the thickness direction of a laminated structure having an insulator I2 and an insulator I3. (B) has an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. 1 is an example of a band diagram in the film thickness direction of a laminated structure. Note that the band diagram is shown in FIG. Insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3, and insulator I2 The energy level (Ec) at the bottom of the conduction band of

[0253] The oxide semiconductors S1 and S3 have a lower energy at the conduction band edge than the oxide semiconductor S2. The energy level is close to the vacuum level, typically the energy level at the bottom of the conduction band of the oxide semiconductor S2. The difference between the energy level of the oxide semiconductor S1 and the energy level of the oxide semiconductor S3 at the bottom of the conduction band is 0 .15eV or more, or 0.5eV or more and 2eV or less, or 1eV or less In other words, the electron affinity of the oxide semiconductor S1 and the oxide semiconductor S3 and the The difference between the electron affinity of the conductor S2 is 0.15 eV or more, or 0.5 eV or more and 2 eV It is preferably 1 eV or less, or 1 eV or less.

[0254] As shown in FIG. 15(A) and FIG. 15(B), an oxide semiconductor S1, an oxide semiconductor S2 In the oxide semiconductor S3, the energy level at the bottom of the conduction band changes gradually. Then, it can be said that the band changes continuously or that the junction is continuous. In order to have such a property, the interface between the oxide semiconductor S1 and the oxide semiconductor S2 or the oxide semiconductor S The defect level density of the mixed layer formed at the interface between the oxide semiconductor S2 and the oxide semiconductor S3 is reduced. stomach.

[0255] Specifically, the oxide semiconductor S1 and the oxide semiconductor S2, the oxide semiconductor S2 and the oxide semiconductor S3 S3 has a common element other than oxygen (as the main component), so that the defect level density is low. For example, when the oxide semiconductor S2 is an In-Ga-Zn oxide semiconductor, In the case of the body, the oxide semiconductor S1 and the oxide semiconductor S3 are In-Ga-Zn oxide semiconductors. , Ga-Zn oxide semiconductor, gallium oxide, or the like may be used.

[0256] At this time, the main carrier path is the oxide semiconductor S2. Defects at the interface with the oxide semiconductor S2 and at the interface between the oxide semiconductor S2 and the oxide semiconductor S3 Since the level density can be reduced, the effect of interface scattering on carrier conduction is small. A high on-current can be obtained.

[0257] When an electron is captured in a trap level, the captured electron behaves like a fixed charge. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing the oxide semiconductor S3, the trap level is moved away from the oxide semiconductor S2. By adopting this configuration, the threshold voltage of the transistor can be shifted in the positive direction. This can prevent the device from being damaged.

[0258] The oxide semiconductors S1 and S3 have sufficient electrical conductivity compared to the oxide semiconductor S2. In this case, the oxide semiconductor S2 and the oxide semiconductor S The interface between the oxide semiconductor S1 and the oxide semiconductor S2 and the oxide semiconductor S3 are mainly the channel region. For example, the oxide semiconductor S1 and the oxide semiconductor S3 have the following structure: Therefore, it is sufficient to use an oxide semiconductor having an atomic ratio shown in region C where the insulating property is high. Region C shown in 3(C) is [In]:[M]:[Zn]=0:1:0 or its neighboring values. The atomic ratio is shown as:

[0259] In particular, when an oxide semiconductor having an atomic ratio shown in region A is used for the oxide semiconductor S2, In the compound semiconductor S1 and the oxide semiconductor S3, [M] / [In] is 1 or more, preferably 2 or more. It is preferable to use an oxide semiconductor having a sufficient conductivity as the oxide semiconductor S3. An oxide semiconductor with a high insulating property, [M] / ([Zn]+[In]) of 1 or more, is used. It is preferable to use a conductor.

[0260] <2-4. Structure of oxide semiconductor> Next, the structure of the oxide semiconductor will be described.

[0261] Oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Nanocrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconducting ductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- amorphous oxide semiconductors and amorphous oxide semiconductors. do.

[0262] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductors, and nc-OS.

[0263] Amorphous structures are generally isotropic and have no inhomogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The positions are not fixed, the bond angles are flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0264] That is, a stable oxide semiconductor is transformed into a completely amorphous In addition, the semiconductor is not isotropic (for example, A periodic oxide semiconductor cannot be called a completely amorphous oxide semiconductor. -like OS is not isotropic, but has an unstable structure with voids. In terms of instability, the a-like OS is physically an amorphous oxide semiconductor. Close to.

[0265] [CAAC-OS] First, let me explain about CAAC-OS.

[0266] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0267] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals was analyzed by the out-of-plane method. As shown in FIG. 16(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so In this case, the crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be confirmed that the direction is perpendicular to the surface of the crystal, or perpendicular to the surface of the crystal. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The nearby peak is due to a crystal structure classified into the space group Fd-3m. It is preferred that the C-OS does not exhibit such a peak.

[0268] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS in a direction parallel to the surface on which the X-ray is to be formed. When structural analysis was performed using the ane method, a peak appeared at 2θ of approximately 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. Then, the sample is rotated around the normal vector of the sample surface as an axis (φ axis) while analyzing (φ scan). Even if this is done, no clear peak appears, as shown in FIG. When 2θ is fixed at around 56° and φ is scanned for ZnO4, the results shown in Figure 16(C) As shown in the figure, six peaks attributable to crystal planes equivalent to the (110) plane are observed. From the structural analysis using XRD, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0269] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was parallel to the CAAC-OS surface. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern ( This is also called a selected area electron diffraction pattern.) may appear. This diffraction pattern includes I The spots are due to the (009) plane of the nGaZnO4 crystal. Diffraction also confirmed that the pellets contained in the CAAC-OS have a c-axis orientation and that the c-axis is the unformed On the other hand, for the same sample, the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm was incident perpendicularly to the ) As shown in FIG. 16(E), a ring-shaped diffraction pattern is observed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the PEG-1000 nanometers in the CAAC-OS It can be seen that the a-axis and b-axis of the slits have no orientation. The ring is thought to be due to the (010) and (100) planes of the InGaZnO4 crystal. In addition, the second ring in Fig. 16(E) is thought to be due to the (110) plane, etc. can be obtained.

[0270] In addition, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope. When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. (also called underly.) may not be clearly identified. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0271] Figure 17(A) shows a high-resolution cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. A spherical aberration correction (SCA) was used for high-resolution TEM imaging. The spherical aberration corrector function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. Therefore, it can be observed.

[0272] From FIG. 17(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. The size of each pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used as a C-Axis Aligned Navigator (CANC). The pellets can also be called oxide semiconductors with no crystals. It reflects the unevenness of the surface on which the C-OS is formed or the top surface, and the unevenness of the surface on which the CAAC-OS is formed or It is parallel to the top surface.

[0273] In addition, Fig. 17(B) and Fig. 17(C) show CAAC images observed from a direction approximately perpendicular to the sample surface. 17(D) and 17(E) show the Cs-corrected high-resolution TEM images of the -OS plane. These are images obtained by processing the images in Fig. 17(B) and Fig. 17(C), respectively. First, the fast Fourier transform (FFT) of FIG. Then, the FFT image is obtained by performing FFT (Fourier Transform) processing on the acquired 2.8 nm based on the origin in the FFT image -1 From 5.0 nm -1Leave the range between Next, the masked FFT image is subjected to inverse fast Fourier transform (IFFT). Image processing using 3D Fast Fourier Transform (3D Fast Fourier Transform) The image obtained in this way is called an FFT filtered image. The tarring image is an image in which the periodic components are extracted from a Cs-corrected high-resolution TEM image, and the lattice arrangement This shows that.

[0274] In FIG. 17(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area indicated by the dashed line is the connection between the pellets. The broken line shows the hexagonal shape, so we can see that the pellet is hexagonal. The shape of the let is not limited to a regular hexagon, and is often a non-regular hexagon.

[0275] In FIG. 17(E), a grid is formed between an area with a uniform lattice arrangement and an area with a different uniform lattice arrangement. The dotted lines indicate the changes in the orientation of the child array, and the dashed lines indicate the changes in the orientation of the lattice array. Even in the vicinity of the dotted line, no clear crystal grain boundaries can be confirmed. When you connect the surrounding lattice points around the center, a distorted hexagon, pentagon, and / or heptagon is formed. In other words, it is clear that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not dense in the ab-plane direction and The substitution of metal elements changes the bond distance between atoms, allowing for distortion. This is thought to be because

[0276] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called an oxide semiconductor having lane-anchored crystals. Cut.

[0277] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is determined by the presence of impurities. CAAC-OS is designed to prevent impurities and defects from causing degradation. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0278] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0279] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the ZnO traps hydrogen and becomes a carrier generation source.

[0280] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11cm -3 Less than 1 x 10 11 cm -3 Less than, More preferably, 1×10 10 cm -3 Less than 1 x 10 -9 cm -3 More than a career Such an oxide semiconductor can be a high-purity intrinsic or It is essentially a high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and In other words, it can be said that the oxide semiconductor has stable characteristics.

[0281] [nc-OS] Next, we will explain nc-OS.

[0282] The following describes the case where nc-OS is analyzed by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0283] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region of m, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in FIG. 8(A) was observed. In addition, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample ( The nanobeam electron diffraction pattern is shown in Figure 18(B). Therefore, the nc-OS has a probe diameter of 50 nm. No order was observed when an electron beam with a probe diameter of 1 nm was incident. When light is incident on it, order is confirmed.

[0284] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 18(C), an electron diffraction pattern was observed in which the spots were arranged in a substantially regular hexagonal shape. Therefore, it is considered that the nc-OS is ordered in the range of thickness less than 10 nm. It can be seen that the crystals are highly ordered. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0285] FIG. 18(D) shows the Cs-corrected height of the cross section of the nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image as the area indicated by the auxiliary lines. How to identify the crystals and the areas where no clear crystals can be identified The crystal parts in the nc-OS have a size of 1 nm to 10 nm. In particular, the size of the crystals is often between 1 nm and 3 nm. An oxide semiconductor having a size of 10 nm or more and 100 nm or less is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). o crystalline oxide semiconductor) For example, in the case of nc-OS, the grain boundaries are often not clearly visible in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be referred to as a pellet.

[0286] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, particularly The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the Cr-Al-Al-Fe-Al-Fe-O-Pb-Al-Zn ... Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0287] In addition, since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is , oxidation with RANC (Random Aligned nanocrystals) Semiconductors or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor has a conductivity of 1000.

[0288] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0289] [a-like OS] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0290] FIG. 19 shows a high-resolution cross-sectional TEM image of the a-like OS. is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. B) is 4.3 x 10 8 e - / nm 2 Electrons (e - ) A-like OS after irradiation High-resolution cross-sectional TEM images. Figures 19(A) and 19(B) show that a-like OS It can be seen that from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. It can be seen that the shape of the bright regions changes after electron irradiation. It is estimated to be in the degree range.

[0291] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0292] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample in is also an In-Ga-Zn oxide.

[0293] First, high-resolution cross-sectional TEM images of each sample are obtained. All of the materials have crystalline parts.

[0294] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers in the c-axis direction. The distance between these adjacent layers is the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is called InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0295] Figure 20 shows an example of the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes is the size of the crystal part. e. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. As can be seen from Fig. 20, in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that grew up (also called the initial nucleus) absorbs electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the n For c-OS and CAAC-OS, the cumulative electron irradiation dose was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals in the range from The size of the crystalline parts of the nc-OS and CAAC-OS was approximately the same regardless of the cumulative dose of electron irradiation. The thicknesses of the electron beam irradiation and T The EM observation was performed using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were The speed voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 s), diameter of the irradiated area was set to 230 nm.

[0296] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in nc-OS and CAAC-OS is hardly observed by electron irradiation. That is, the a-like OS is inferior to the nc-OS and CAAC-OS. It is clear that this is a stable structure.

[0297] In addition, because of the porosity, a-like OS is more resistant to nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS and CAAC- The density of the OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78%.

[0298] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 Less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0299] If single crystals of the same composition are not available, single crystals of different compositions may be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions. However, the density can be estimated by using as few types of single crystals as possible. A combined estimate is preferred.

[0300] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0301] The configuration shown in this embodiment may be appropriately combined with configurations shown in other embodiment modes or examples. , can be used in combination.

[0302] (Embodiment 3) In this embodiment, a display device including the transistor described in the above embodiment will be An example will be described below with reference to FIGS.

[0303] 21 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver is provided on the first substrate 701. A pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, A sealant 712 is disposed so as to surround the path portion 704 and the gate driver circuit portion 706. and a second substrate 705 disposed so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 21, a display element is provided between the first substrate 701 and the second substrate 705. can be done.

[0304] The display device 700 is surrounded by a sealant 712 on the first substrate 701. In a region different from the region, a pixel section 702, a source driver circuit section 704, a gate driver circuit section FPC terminals electrically connected to the path portion 706 and the gate driver circuit portion 706, A sub-unit 708 (FPC: Flexible printed circuit) is provided. In addition, an FPC 716 is connected to the FPC terminal portion 708. Various signals are supplied to the element section 702, the source driver circuit section 704, and the gate driver circuit section 706. In addition, a pixel section 702, a source driver circuit section 704, a gate driver circuit section A signal line 710 is connected to the path portion 706 and the FPC terminal portion 708. Various signals supplied from 716 are transmitted through signal lines 710 to the pixel section 702, the source driver 716, and the like. 704, a gate driver circuit section 706, and an FPC terminal section 708. do.

[0305] The display device 700 may include a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is formed on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead, we use COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0306] The display device 700 also includes a pixel portion 702, a source driver circuit portion 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0307] The display device 700 can also include various elements, such as: For example, electroluminescence (EL) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (light-emitting elements that emit light according to electric current) transistors, electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, Rowetting element, plasma display panel (PDP), MEMS (microelectromechanical systems) Electro-mechanical systems) displays (e.g., grating light bars) GLV, Digital Micromirror Device (DMD), Digital Microsha Dispersive Modulation (DMS) element, Interferometric Modulation (IMOD) element ), piezoelectric ceramic displays, etc.

[0308] An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductio n Electron-emitter Display) and others. An example of such a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Display, reflective LCD display, direct-view LCD display, projection LCD display Examples of display devices using electronic ink elements or electrophoretic elements include: Electronic paper. Semi-transmissive LCDs and reflective LCDs are also used. In this case, a part or the whole of the pixel electrode should function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This can further reduce power consumption.

[0309] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying in color are R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a pixel, and a pixel, or a pen tile. As in the column, two colors of RGB compose one color element, and two different colors are created by the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. may be selected for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, and may be used with monochrome displays. The present invention can also be applied to display devices such as those shown in FIG.

[0310] Also, white light is emitted from the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) In order to display full color using (W), a colored layer (also called a color filter) is The colored layer may be, for example, red (R), green (G), blue (B), or red (C). ), yellow (Y), etc. can be used in appropriate combination. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a color layer and a region not having a color layer, The white light in the region may be directly used for display. By placing the colored layer over the entire display, the decrease in brightness caused by the colored layer can be reduced during bright display, and power consumption can be reduced by 2. However, in some cases, the emission of light from organic EL elements and inorganic EL elements can be reduced by about 10 to 30%. When using optical elements to display full color, R, G, B, Y, and W are each emitted in different colors. By using a self-luminous element, it is possible to obtain a light emission from a colored layer. In some cases, power consumption can be reduced even further.

[0311] In addition, as a colorization method, a part of the light emitted from the above-mentioned white light is passed through a color filter. In addition to the color filter method, which converts the light into red, green, and blue by filtering the light, A method that uses two colors of light (three-color method), or a method that uses part of the light emitted from the blue light to emit red or A method for converting to green (color conversion method, quantum dot method) may be applied.

[0312] In this embodiment, a liquid crystal element and an EL element are used as display elements. 22 and 24. Note that FIG. 22 shows the area indicated by the dashed line QR in FIG. FIG. 24 is a cross-sectional view of the liquid crystal display device, which uses a liquid crystal element as a display element. 21, which is a cross-sectional view taken along the dashed line QR, and shows a configuration in which an EL element is used as a display element. It is.

[0313] First, the common parts shown in FIG. 22 and FIG. 24 will be explained, and then the different parts will be explained. This will be explained below.

[0314] <3-1. Explanation of common parts of display devices> The display device 700 shown in FIG. 22 and FIG. 24 includes a wiring portion 711 and a pixel portion 702. The display panel 700 includes a source driver circuit section 704 and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Yes.

[0315] Transistor 750 and transistor 752 are similar to transistor 100 shown above. The structures of the transistors 750 and 752 are the same as those described above. Any other transistors than those shown in the embodiment modes may be used.

[0316] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. It is possible to extend the retention time of electrical signals such as signals, and the write interval can be extended when the power is on. This allows the frequency of refresh operations to be reduced, resulting in reduced power consumption. It has the effect of suppressing power.

[0317] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section In other words, the driver transistor can be formed on the same substrate as the driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, a high quality image can be provided.

[0318] The capacitor 790 includes a conductive film that functions as a first gate electrode of the transistor 750. The lower electrode formed through a process of processing the same conductive film and the Through a process of processing the same conductive film as the conductive film that functions as the source electrode and the drain electrode, and an upper electrode formed on the lower electrode. A step of forming an insulating film identical to the insulating film functioning as the first gate insulating film of 750. That is, the capacitor 790 is formed by forming an insulating film between a pair of electrodes. It has a laminated structure in which an insulating film that functions as a conductor film is sandwiched.

[0319] 22 and 24, a transistor 750, a transistor 752, and a capacitor A planarization insulating film 770 is provided on the capacitor 790 .

[0320] The planarization insulating film 770 may be made of a polyimide resin, an acrylic resin, or a polyimide amide resin. Heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin In addition, by stacking multiple insulating films made of these materials, A planarization insulating film 770 may be formed. Alternatively, the planarization insulating film 770 may not be provided. This is also fine.

[0321] 22 and 24, the transistor 750 and the A transistor having the same structure as the transistor 752 included in the source driver circuit portion 704 is used. The configuration used is illustrated above, but is not limited to this. For example, A transistor different from that in the driver circuit section 704 may be used. 02 is a staggered transistor, and the source driver circuit portion 704 is In the pixel portion 702, an inverted staggered transistor is used. A reverse staggered transistor is used, and a staggered transistor is provided in the source driver circuit section 704. The source driver circuit section 704 may be configured as a gate driver. It may also be read as a driver circuit section.

[0322] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed through the same process as the conductive film that functions as the signal line 710. When materials containing this material are used, signal delays caused by wiring resistance are minimal, making it possible to display images on a large screen. It becomes Noh.

[0323] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed through the same process as the conductive film that functions as the drain electrode. , and is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780 .

[0324] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0325] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. A device for controlling the distance (cell gap) between the first substrate 701 and the second substrate 705 is provided. In addition, a spherical spacer may be used as the structure 778.

[0326] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and A colored film 736 that functions as a color filter, a light-shielding film 738 that is in contact with the colored film 736, and An insulating film 734 is provided.

[0327] <3-2. Configuration examples of display devices using liquid crystal elements> The display device 700 shown in FIG. 22 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is a second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. By controlling the light transmission or non-transmission, an image can be displayed.

[0328] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770. The conductive film 772 functions as a pixel electrode, that is, one electrode of a display element. The display device 700 shown in FIG. 72 reflects light and displays it through a colored film 736, so-called a reflective color liquid crystal display device. be.

[0329] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a reflectivity can be used. For example, a material containing one of the elements indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed of A conductive film that is reflective in visible light is used.

[0330] In FIG. 22, the conductive film 772 functions as a drain electrode of the transistor 750. However, the present invention is not limited to this. For example, the structure shown in FIG. As shown in FIG. 1, a conductive film 772 is sandwiched between a conductive film 777 serving as a connection electrode and a transistor. The drain electrode of the transistor 750 may be electrically connected to the conductive film. Note that the conductive film 777 functions as a second gate electrode of the transistor 750. Since it is formed through the same process of processing the conductive film as the conductive film used, there is no need to add any additional manufacturing steps. It can be formed.

[0331] The display device 700 shown in FIG. 22 is a reflective color liquid crystal display device. However, the present invention is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. Alternatively, a reflective color liquid crystal display device may be used. A so-called semi-transmissive color liquid crystal display is a combination of a transmissive color liquid crystal display. The display device may be a liquid crystal display device.

[0332] An example of a transmissive color liquid crystal display device is shown in FIG. 25. FIG. 25 shows the same as that shown in FIG. This is a cross-sectional view taken along the dashed line QR, and shows a configuration in which liquid crystal elements are used as display elements. In addition, the display device 700 shown in FIG. 25 uses a horizontal electric field method (for example, F In the configuration shown in FIG. 25, the pixel electrode functions as An insulating film 773 is provided over a conductive film 772, and a conductive film 774 is provided over the insulating film 773. In this case, the conductive film 774 functions as a common electrode. An electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773 causes the liquid The orientation of the crystal layer 776 can be controlled.

[0333] Although not shown in FIGS. 22 and 25, the conductive film 772 or the conductive film 774 An alignment film is provided on either one or both of the surfaces of the liquid crystal layer 776. Although not shown in FIG. 22 and FIG. 25, a polarizing member, a phase difference member, a reflecting member, etc. Optical members (optical substrates) such as a polarizing substrate and a positioning member may be provided as appropriate. Circularly polarized light produced by a retardation substrate may be used. Either may be used.

[0334] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0335] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. Since the liquid crystal display has a short rotational angle and is optically isotropic, no alignment treatment is required. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is prevented. This can prevent the occurrence of defects or damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials exhibiting a blue phase have little viewing angle dependency.

[0336] In addition, when liquid crystal elements are used as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr Electrochemical Liquid Crystal (ECC) mode can be used. .

[0337] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode mode, ASV mode, etc. can be used.

[0338] <3-3. Display devices using light-emitting elements> The display device 700 shown in FIG. 24 includes a light-emitting element 782. The light-emitting element 782 is a conductive film The display device 700 shown in FIG. The EL layer 786 of the light element 782 emits light, thereby displaying an image. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0339] Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, In addition, the elements of the 12th and 16th families, the 13th and 15th families, or the 14th and 16th families Materials containing the element group may also be used. Cadmium (Cd), selenium (Se), Zinc (Zn), Sulfur (S), Phosphorus (P), Indium (In), Tellurium (Te), Lead (P b) Quantum with elements such as gallium (Ga), arsenic (As), aluminum (Al), etc. Dot material may also be used.

[0340] In addition, in the display device 700 shown in FIG. An insulating film 730 is provided. The insulating film 730 covers a part of the conductive film 772. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits the light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to this. For example, a bottom emission structure in which light is emitted to both the conductive film 772 and the conductive film 788; It can also be applied to al-emission structures.

[0341] A colored film 736 is provided at a position overlapping the light emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided at the position where the light-shielding film 738 is to be formed, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is illustrated. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0342] <3-4. Example of a configuration in which an input / output device is provided on a display device> Also, an input / output device may be provided in the display device 700 shown in FIG. An example of the force device is a touch panel.

[0343] 26 and 27, a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. 24 and FIG. 25 is shown. This is shown in Figure 27.

[0344] FIG. 26 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. FIG. 27 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. be.

[0345] First, the touch panel 791 shown in FIG. 26 and FIG. 27 will be described below.

[0346] The touch panel 791 shown in FIG. 26 and FIG. 27 is provided between a substrate 705 and a colored film 736. The touch panel 791 is a so-called in-cell type touch panel. 736 may be formed on the substrate 705 side before the colored film 736 is formed.

[0347] The touch panel 791 includes a light-shielding film 738, an insulating film 792, an electrode 793, and an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. When a detection object such as a stylus approaches, the mutual capacitance between electrode 793 and electrode 794 changes. It is possible to detect the change.

[0348] 26 and 27, an electrode 793 and The electrode 796 is formed by passing through an opening in the insulating film 795. The electrode 794 is electrically connected to the two electrodes 793 that sandwich the electrode 794 via the electrodes 793. 27, a configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702 is illustrated. However, the present invention is not limited to this. For example, the light emitting diode 704 may be formed in the source driver circuit section 704.

[0349] The electrodes 793 and 794 are provided in a region overlapping with the light-shielding film 738. As shown in FIG. 1, the electrode 793 is preferably provided so as not to overlap with the light-emitting element 782. As shown in FIG. 27, the electrode 793 is provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 overlaps with the light-emitting element 782 and the liquid crystal element 775. In other words, the electrode 793 has a mesh shape. By this configuration, the electrode 793 does not block the light emitted by the light emitting element 782. Alternatively, the electrode 793 may be configured so as not to block light passing through the liquid crystal element 775. Therefore, the reduction in brightness due to the placement of the touch panel 791 is extremely small. Since the number of pixels is small, a display device with high visibility and reduced power consumption can be realized. The pole 794 may be of a similar configuration.

[0350] In addition, since the electrodes 793 and 794 do not overlap with the light-emitting element 782, The electrode 794 may be made of a metal material having a low transmittance of visible light. Since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, In addition, a metal material having a low transmittance of visible light can be used.

[0351] Therefore, compared with electrodes using oxide materials with high visible light transmittance, the electrodes 793 and The resistance of the electrode 794 can be reduced, improving the sensor sensitivity of the touch panel. It is possible.

[0352] For example, the electrodes 793, 794, and 796 may be made of conductive nanowires. The nanowires have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm. The size of the nanoparticles may be 5 nm or less, and more preferably 5 nm or more and 25 nm or less. The wires are metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires. For example, electrodes 664, 665, 6666, etc. may be used. When Ag nanowires are used for either 65 or 667, or for all of them, the The light transmittance is to be 89% or more, and the sheet resistance is to be 40Ω / □ or more and 100Ω / □ or less. can.

[0353] 26 and 27 show examples of the configuration of an in-cell type touch panel. However, the present invention is not limited to this. For example, a so-called on-cell type transistor formed on the display device 700 may be used. A so-called out-cell type touch panel that is attached to the display device 700. It is also possible to use the following.

[0354] In this manner, the display device according to one embodiment of the present invention can be used in combination with various types of touch panels. It can be used.

[0355] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0356] (Embodiment 4) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0357] <4. Circuit configuration of display device> The display device shown in FIG. 28A has a region having pixels of a display element (hereinafter, referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504) and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. This is also fine.

[0358] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Band). It can be implemented by using the onding.

[0359] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter, referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter, a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a) to provide a signal (data signal) for driving the display element of the pixel. The pixel circuit 504 includes a driver circuit such as a circuit (hereinafter, referred to as a source driver 504b).

[0360] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via a terminal unit 507, and a signal is output. For example, a start pulse signal, a clock signal, etc. are input to the gate driver 504a. The gate driver 504a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it. However, the gate driver 50 has a function of supplying 4a may also provide another signal.

[0361] The source driver 504b includes a shift register and the like. Through the terminal section 507, a signal for driving the shift register as well as a source of a data signal are input. The source driver 504b outputs a pixel circuit based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data line 101 through the data line 102. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0362] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a number of analog switches, The image signal can be time-division-multiplexed and output as a data signal. Also, a shift register, etc. This may be used to configure the source driver 504b.

[0363] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is inputted through the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or smaller than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via a source driver 504c (n is a natural number equal to or smaller than Y).

[0364] The protection circuit 506 shown in FIG. 28(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit 506 may be a wiring between the source driver 504b and the terminal unit 507. The terminal unit 507 can be connected to a power supply and a power supply line from an external circuit to the display device. This refers to the part provided with terminals for inputting control signals and image signals.

[0365] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0366] As shown in FIG. 28A, a protection circuit 50 is provided in each of a pixel section 502 and a driver circuit section 504. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrent caused by electrostatic discharge (ESD) and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal portion 507. It can also be written as:

[0367] In FIG. 28A, the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit is formed separately. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is It may also be configured to be equipped with

[0368] In addition, the pixel circuits 501 shown in FIG. 28(A) may be, for example, a configuration shown in FIG. 28(B). It can be said that:

[0369] The pixel circuit 501 shown in FIG. 28B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiment. can be applied.

[0370] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0371] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of different types of sensors can be used.

[0372] In the pixel circuit 501 in the mth row and the nth column, One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scan lines G L_m. The transistor 550 can be turned on or off. Thus, the write control circuit 100 has a function of controlling the writing of data of the data signal.

[0373] One of a pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0374] For example, in a display device having the pixel circuit 501 shown in FIG. The pixel circuits 501 in each row are sequentially selected by a gate driver 504a shown in FIG. 550 is turned on to write data of the data signal.

[0375] In the pixel circuit 501 in which data has been written, the transistor 550 is turned off. By repeating this process row by row, an image can be displayed.

[0376] In addition, the pixel circuits 501 shown in FIG. 28(A) may have a configuration shown in FIG. 28(C), for example. It can be said that:

[0377] The pixel circuit 501 shown in FIG. 28C includes transistors 552 and 554 and a capacitance element. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either or both of the above. .

[0378] A data signal is applied to one of the source and drain electrodes of the transistor 552. The transistor 55 is electrically connected to a wiring (hereinafter, referred to as a signal line DL_n). The gate electrode of 2 is electrically connected to the wiring (hereinafter referred to as the scanning line GL_m) to which the gate signal is applied. are connected to the network.

[0379] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0380] One of a pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0381] The capacitor 562 functions as a storage capacitor for storing written data.

[0382] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. In addition, the gate electrode of the transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0383] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b. The other one is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0384] The light-emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0385] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0386] In a display device having the pixel circuit 501 shown in FIG. 28C, for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0387] In the pixel circuit 501 to which the data has been written, the transistor 552 is turned off. Furthermore, the transistor 554 is in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0388] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0389] (Embodiment 5) In this embodiment, the circuit configuration to which the transistors described in the above embodiment can be applied is An example will be described with reference to FIGS.

[0390] Note that in this embodiment, the transistor having the oxide semiconductor described in the above embodiment In the following description, the above-mentioned transistor will be referred to as an OS transistor.

[0391] <5. Example of inverter circuit configuration> FIG. 29(A) shows a circuit that can be applied to a shift register, a buffer, etc. in a driver circuit. 8 shows a circuit diagram of an inverter 800 that can convert the logic of a signal provided to an input terminal IN into a The inverter 800 outputs an inverted signal of the OS transistors to the output terminal OUT. Signal S BG is a signal that can switch the electrical properties of an OS transistor. The number is.

[0392] FIG. 29B is an example of an inverter 800. The inverter 800 is an OS transistor. The inverter 800 includes an n-channel Since it can be fabricated using only complementary metal-oxide semiconductor (CMOS) transistors, Y Metal Oxide Semiconductor inverter (CMOS inverter) It is possible to manufacture the device at a lower cost than manufacturing a conventional inverter.

[0393] The inverter 800 having OS transistors is made of Si transistors. The inverter 800 can be placed on the CMOS circuit. Therefore, an increase in the circuit area due to the addition of the inverter 800 can be suppressed.

[0394] The OS transistors 810 and 820 each have a first gate functioning as a front gate and a back gate. The second gate acts as a gate electrode and the first gate acts as either a source or a drain. It has one terminal and a second terminal that functions as the other of the source or drain.

[0395] The first gate of the OS transistor 810 is connected to the second terminal. The second gate of 10 is the signal S BG The OS transistor 810 is connected to a wiring that supplies The first terminal of the OS transistor 810 is connected to a wiring that supplies a voltage VDD. The input terminal is connected to the output terminal OUT.

[0396] A first gate of the OS transistor 820 is connected to the input terminal IN. A second gate of the OS transistor 820 is connected to the input terminal IN. The second terminal of the OS transistor 820 is connected to the output terminal OUT. The GND is connected to a wire that supplies

[0397] FIG. 29C is a timing chart for explaining the operation of the inverter 800. In the timing chart of FIG. 29(C), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are Signal waveform, signal S BG 8 and the change in the threshold voltage of the OS transistor 810. This shows the following:

[0398] signal S BG to the second gate of the OS transistor 810. The threshold voltage of 810 can be controlled.

[0399] signal S BG is the voltage V for shifting the threshold voltage negatively. BG_A ,threshold Voltage V for positively shifting the voltage BG_B The second gate has a voltage V BG_A By providing TH_A negative shift to Also, the second gate can be connected to the voltage V BG_B By providing The threshold voltage V TH_B can be shifted positively to

[0400] To visualize the above explanation, Figure 30(A) shows one of the electrical characteristics of a transistor. 1 shows an Id-Vg curve.

[0401] The electrical characteristics of the OS transistor 810 described above are as follows: BG_A of By increasing the value so as to shift the curve to the dashed line 840 in FIG. The electrical characteristics of the OS transistor 810 can be expressed as follows: Voltage V BG_BBy making it smaller, the curve represented by the solid line 841 in FIG. As shown in FIG. 30A, the OS transistor 810 can be signal S BG to the voltage V BG_A Or voltage V BG_B By switching like this, The threshold voltage can be shifted positively or negatively.

[0402] Threshold voltage V TH_B By shifting the OS transistor The capacitor 810 can be made to have a state in which it is difficult for a current to flow. Visualize and show.

[0403] As shown in FIG. 30B, a current I B Extremely small Therefore, when the signal applied to the input terminal IN is high level, the OS trans When the resistor 820 is in the ON state, it causes the voltage at the output terminal OUT to drop sharply. can be done.

[0404] As shown in FIG. 30B, a current is unlikely to flow through the OS transistor 810. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 831 can be changed sharply. Since the through current flowing between the wiring that supplies S can be reduced, it is possible to achieve low power consumption. The action can be performed.

[0405] Also, the threshold voltage is V TH_A By shifting it negatively, the OS The transistor 810 can be made to be in a state in which a current can easily flow. The state is visualized. As shown in FIG. 30(C), the current I A Less At least current I B Therefore, the signal applied to the input terminal IN can be When the OS transistor 820 is in an off state (OFF) at a low level, the voltage of the output terminal OUT As shown in FIG. 30(C), the OS transistor Since the current flowing through 810 can be made to flow easily, the type shown in FIG. This allows the signal waveform 832 at the output terminal in the timing chart to be changed sharply.

[0406] In addition, signal S BG The control of the threshold voltage of the OS transistor 810 by It is preferable to perform this before the state of register 820 changes, i.e., before time T1 or T2. For example, as shown in FIG. 29(C), when the signal applied to the input terminal IN is high level, Before the time T1 when the transistor switches to the TH_A From the threshold voltage V TH _B It is preferable to change the threshold voltage of the OS transistor 810 in FIG. As shown in FIG. 9(C), the signal applied to the input terminal IN is switched to a low level at time T Before 2, the threshold voltage V TH_B to threshold voltage V TH_A OS transistor It is preferable to switch the threshold voltage of 810.

[0407] In the timing chart of FIG. 29(C), the signal changes according to the signal applied to the input terminal IN. No.S BG However, other configurations may be used. For example, the threshold voltage is The control voltage is applied to the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. As shown in (A).

[0408] In FIG. 31A, in addition to the circuit configuration shown in FIG. 29B, an OS transistor 850 The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a voltage V BG_B (or Pressure V BG_A The first gate of the OS transistor 850 is connected to a wiring that provides a signal No.S F The second gate of the OS transistor 850 is connected to a wiring that supplies a voltage V BG _B (or voltage V BG_A ) is connected to the wire that provides the

[0409] The operation of FIG. 31(A) will be described with reference to the timing chart of FIG. 31(B).

[0410] A voltage for controlling the threshold voltage of the OS transistor 810 is applied to the input terminal IN. The second gate of OS transistor 810 is turned on before time T3 when the signal The signal S F is set to a high level to turn on the OS transistor 850. In this state, node N BG Voltage V for controlling the threshold voltage BG_B Gives.

[0411] Node N BG is the voltage V BG_B After this, the OS transistor 850 is turned off. The OS transistor 850 has an extremely small off-state current and can be kept in an off state. So, once node N BG The threshold voltage V BG_B It is possible to hold Therefore, the second gate of the OS transistor 850 is supplied with a voltage V BG_B The number of actions to give is reduced. Therefore, the voltage V BG_B Therefore, the power consumption required for rewriting the data can be reduced.

[0412] In the circuit configurations in FIGS. 29B and 31A, the second We have shown a configuration in which the voltage applied to the gate is controlled from outside, but we will also consider other configurations. For example, a signal for controlling the threshold voltage may be applied to the input terminal IN. and provided to the second gate of the OS transistor 810. FIG. 32A shows an example of a circuit configuration that can realize the above configuration.

[0413] In FIG. 32(A), the input terminal IN and the OS transistor are connected in the circuit configuration shown in FIG. 29(B). A CMOS inverter 860 is provided between the second gate of the transistor 810 and the CMOS inverter 860. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal is connected to the second gate of OS transistor 810.

[0414] The operation of FIG. 32(A) will be described with reference to the timing chart of FIG. 32(B). In the timing chart of FIG. 32(B), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are 8, the output waveform IN_B of the CMOS inverter 860, and the output waveform IN_C of the OS transistor 810. The change in threshold voltage is shown.

[0415] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is The threshold voltage of the transistor 810 can be controlled by the signal shown in FIG. As described with reference to FIGS. 30A to 30C, the threshold voltage of the OS transistor 810 is controlled. For example, at time T4 in FIG. 32(B), the signal applied to the input terminal IN is When the signal is at a high level, the OS transistor 820 is turned on. B is at a low level. Therefore, the OS transistor 810 is in a state where it is difficult for a current to flow. Therefore, the rising voltage of the output terminal OUT can be made to drop sharply.

[0416] At time T5 in FIG. 32(B), the signal applied to the input terminal IN becomes low. At this time, the OS transistor 820 is turned off. Therefore, the OS transistor 810 can be in a state where a current easily flows. This allows the voltage at the output terminal OUT to rise sharply.

[0417] As described above, in the configuration of this embodiment, the inverter having the OS transistor The back gate voltage is switched according to the logic of the signal at the input terminal IN. By using this configuration, the threshold voltage of the OS transistor can be controlled. The threshold voltage of the OS transistor is controlled by the signal applied to IN. The OUT voltage can be changed sharply. This allows the current to be reduced, thereby enabling low power consumption.

[0418] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0419] (Embodiment 6) In this embodiment, the transistor including the oxide semiconductor described in the above embodiment ( FIG. 33 and FIG. 34 show an example of a semiconductor device using an OS transistor in a plurality of circuits. This will be explained using 6.

[0420] <6. Circuit configuration example of semiconductor device> FIG. 33A is a block diagram of a semiconductor device 900. The semiconductor device 900 is A circuit 901, a circuit 902, a voltage generating circuit 903, a circuit 904, a voltage generating circuit 905, and a circuit It has a path 906.

[0421] The power supply circuit 901 supplies a reference voltage V ORG This is a circuit that generates a voltage V ORG teeth, It is acceptable to use multiple voltages instead of a single voltage. Voltage V ORG From the outside of the semiconductor device 900 The semiconductor device 900 can generate the voltage V1 based on the voltage V2 given from the outside. Based on a single power supply voltage, the voltage V ORG Therefore, the semiconductor device 900 can generate It can operate without applying multiple power supply voltages from the outside.

[0422] Circuits 902, 904, and 906 are circuits that operate on different power supply voltages. The power supply voltage of the circuit 902 is the voltage V ORG and voltage V SS (V ORG >V SS ) and applied by The power supply voltage for the circuit 904 is the voltage V POG and voltage V SS ( V POG >V ORG ) is a voltage applied by the power supply of the circuit 906. Voltage is voltage V ORGand voltage V NEG (V ORG >V SS >V NEG ) and applied by The voltage V SS If the potential is the same as the ground (GND), the power supply circuit The number of types of voltages generated by 901 can be reduced.

[0423] The voltage generating circuit 903 generates a voltage V POG The voltage generating circuit 903 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V POG Therefore, The semiconductor device 900 having the circuit 904 operates based on a single power supply voltage provided from the outside. It can be made.

[0424] The voltage generating circuit 905 generates a voltage V NEG The voltage generating circuit 905 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V NEG Therefore, The semiconductor device 900 having the circuit 906 operates based on a single power supply voltage provided from the outside. It can be made.

[0425] Figure 33(B) shows the voltage V POG FIG. 33C shows an example of a circuit 904 that operates in accordance with the 4 is an example of a waveform of a signal for operating the

[0426] FIG. 33B shows a transistor 911. The applied signal is, for example, a voltage V POG and voltage V SS The signal is generated based on the When the transistor 911 is in the conductive state, the voltage V POG , the voltage when in non-conducting state VSS Voltage V POG As shown in FIG. 33(C), the voltage V ORG Bigger Therefore, the transistor 911 is in a conductive state between the source (S) and the drain (D). As a result, the circuit 904 is less likely to malfunction. The circuit can be constructed as follows.

[0427] Figure 33(D) shows the voltage V NEG FIG. 33(E) shows an example of a circuit 906 that operates in accordance with the 4 is an example of a waveform of a signal for operating the

[0428] FIG. 33D shows a transistor 912 having a back gate. The signal applied to the gate of the transistor 912 is, for example, a voltage V ORG and voltage V SS Generated based on The signal is a voltage V ORG , Non-guided When the voltage V SS In addition, the back gate of the transistor 912 is The voltage that can be applied is V NEG It is generated based on the voltage V NEG is illustrated in FIG. So, the voltage V SS (GND). Therefore, the threshold voltage of the transistor 912 is Therefore, the transistor 912 can be controlled to shift in the positive direction. It is possible to ensure that the transistor is in a non-conducting state, and the current flowing between the source (S) and the drain (D) As a result, the circuit 906 can reduce malfunctions and achieve low power consumption. The circuit can be constructed as follows.

[0429] In addition, the voltage V NEGcan also be applied directly to the back gate of the transistor 912. Alternatively, the voltage V ORG and voltage V NEG Based on this, a gate voltage of the transistor 912 is applied to the gate of the transistor 912. Alternatively, a signal that corresponds to the back gate of the transistor 912 may be generated and provided to the back gate of the transistor 912. good.

[0430] Also, Figures 34(A) and (B) show modifications of Figures 33(D) and (E).

[0431] In the circuit diagram shown in FIG. 34(A), a control circuit is provided between a voltage generating circuit 905 and a circuit 906. A transistor 922 whose conduction state can be controlled by a path 921 is shown. The control signal S output from the control circuit 921 is an n-channel OS transistor. BG is a signal for controlling the conduction state of the transistor 922. Transistors 912A and 912B are OS transistors similar to transistor 922.

[0432] In the timing chart of FIG. 34(B), the control signal S BG and transistor 912A, The state of the potential of the back gate of 912B is BG The control signal S B G When the voltage at the node N BG is the voltage V N EG Then, the control signal S BG When is low, node N BG Electrically flow Since the transistor 922 is an OS transistor, its off-state current is small. Therefore, node N BG Even if the voltage V is electrically floating, NEG can be held.

[0433] FIG. 35A shows an example of a circuit configuration that can be applied to the voltage generating circuit 903 described above. The voltage generating circuit 903 shown in FIG. The charge pump has five stages including C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 through C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS and is applied by If the voltage V ORG is boosted to a positive voltage five times higher than the Voltage V POG The forward voltage of the diodes D1 to D5 is 0V. In addition, by changing the number of charge pump stages, the desired voltage V POG Get It is possible.

[0434] FIG. 35B shows an example of a circuit configuration that can be applied to the voltage generating circuit 905 described above. The voltage generating circuit 905 shown in FIG. The charge pump has four stages including C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 through C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS and is applied by If the voltage at the clock signal CLK is SS From Pressure V ORG The voltage V is stepped down to a negative voltage four times higher than the NEGIt is possible to obtain the above. The forward voltage of the nodes D1 to D5 is set to 0 V. In addition, the number of stages of the charge pump is changed. This allows the desired voltage V NEG can be obtained.

[0435] The circuit configuration of the voltage generating circuit 903 described above corresponds to the circuit configuration shown in FIG. For example, modified examples of the voltage generating circuit 903 are shown in FIGS. In addition, the modified example of the voltage generating circuit 903 is the voltage generating circuit shown in FIG. In the circuits 903A to 903C, the voltage applied to each wiring may be changed, or the elements This can be achieved by changing the arrangement of the

[0436] The voltage generating circuit 903A shown in FIG. The clock signal CLK is supplied to the transistors C11 to C14 and the inverter INV1. The gates of the transistors M1 to M10 are supplied directly or through an inverter INV1. The clock signal CLK drives the voltage V ORG The voltage V is boosted to four times the positive voltage PO G By changing the number of stages, the desired voltage V POG to get The voltage generating circuit 903A shown in FIG. By using S transistors, the off-state current can be reduced, and the capacitors C11 to C14 are This effectively suppresses the leakage of the charge. ORG to voltage V POG Ascension to It is possible to measure pressure.

[0437] The voltage generating circuit 903B shown in FIG. The clock signal CLK is , directly to the gates of transistors M11 to M14 or via inverter INV2 The clock signal CLK generates a voltage V ORG The voltage boosted to twice the positive voltage Pressure V POG The voltage generating circuit 903B shown in FIG. By using OS transistors as the transistors M11 to M14, the off-state current can be reduced. This can suppress leakage of the charge stored in the capacitors C15 and C16. Therefore, the voltage V ORG to voltage V POG It is possible to boost the voltage to

[0438] The voltage generating circuit 903C shown in FIG. The transistor M15 has a diode D6 and a capacitor C17. The conduction state is controlled by the control signal EN. The control signal EN controls the voltage V ORG but The boosted voltage V POG The voltage generating circuit 903C shown in FIG. Since the inductor Ind1 is used to boost the voltage, the voltage is boosted with high conversion efficiency. It is possible to do so.

[0439] As described above, in the configuration of this embodiment, the voltage required for the circuit of the semiconductor device is This allows the semiconductor device to reduce the number of power supply voltages that are applied from the outside. It can be reduced.

[0440] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. There can be.

[0441] (Embodiment 7) In this embodiment, a display module and an electronic device each including a semiconductor device according to one embodiment of the present invention will be described. This will be described with reference to FIGS.

[0442] <7-1. Display module> The display module 7000 shown in FIG. 37 includes an upper cover 7001 and a lower cover 7002. Between them, touch panel 7004 connected to FPC 7003 and A display panel 7006, a backlight 7007, a frame 7009, and a printed circuit board 701 0, has battery 7011.

[0443] The semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.

[0444] The upper cover 7001 and the lower cover 7002 are connected to the touch panel 7004 and the display panel The shape and dimensions can be changed as appropriate to match the size of 7006.

[0445] The touch panel 7004 is a resistive or capacitive touch panel. The display panel 7006 may be overlapped with the opposing substrate (sealing substrate). It is also possible to provide the display panel 7 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 006 to make it into an optical touch panel.

[0446] The backlight 7007 has a light source 7008. In the above embodiment, the light source 7008 is disposed on the light source 7007. However, the present invention is not limited to this. For example, a light source 7008 is arranged at the end of a backlight 7007, and a light diffusion plate is further used. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective In the case of a liquid crystal panel, the backlight 7007 may not be provided.

[0447] The frame 7009 protects the display panel 7006 and also supports the movement of the printed circuit board 7010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 7009 may also function as a heat sink.

[0448] The printed circuit board 7010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 7011 provided separately. , this can be omitted when using a commercial power source.

[0449] In addition, the display module 7000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0450] <7-2.Electronic equipment 1> Next, examples of electronic devices are shown in FIGS.

[0451] FIG. 38(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0452] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0453] In this example, a camera 8000 is used, and a lens 8006 is detached from a housing 8001 and replaced. However, the lens 8006 and the housing may be integrated together.

[0454] The camera 8000 can capture an image by pressing the shutter button 8004. The display unit 8002 also functions as a touch panel. It is also possible to capture an image by doing so.

[0455] The housing 8001 of the camera 8000 has a mount having electrodes, and a finder 810 In addition to 0, strobe devices etc. can also be connected.

[0456] The finder 8100 includes a housing 8101, a display unit 8102, a button 8103, and the like. .

[0457] The housing 8101 has a mount that engages with the mount of the camera 8000, The mount can be attached to the camera 8000. The mount also includes an electrode The image received from the camera 8000 through the electrode is displayed on the display unit 8102. It is possible to do so.

[0458] The button 8103 functions as a power button. The 8102 display can be switched on and off.

[0459] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied.

[0460] In FIG. 38(A), the camera 8000 and the finder 8100 are treated as separate electronic devices. These are configured to be removable, but the camera 8000 has a housing 8001 equipped with a display device. The camera may have a built-in viewfinder that can be used to capture images.

[0461] FIG. 38B is a diagram showing the external appearance of the head mounted display 8200.

[0462] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0463] A cable 8205 supplies power from a battery 8206 to the main body 8203. 03 is equipped with a wireless receiver and the like, and image information such as image data received is displayed on a display unit 8204. In addition, the camera installed in the main body 8203 can record the movement of the user's eyeballs and eyelids. The system captures the user's gaze and calculates the coordinates of the user's gaze based on that information. It can be used as an input means.

[0464] Furthermore, the mounting unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 detects the current flowing through the electrodes in response to the movement of the user's eyeball, The device may have a function of recognizing the user's viewpoint. Also, the device may have a function of detecting the current flowing through the electrode. By doing so, the mounting unit 820 may have a function of monitoring the pulse of the user. The sensor 1 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The device may have a function of displaying the user's biological information on the display unit 8204. The image displayed on the display unit 8204 is changed according to the movement of the part. Good too.

[0465] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0466] 38(C), (D), and (E) are diagrams showing the appearance of the head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, and a backlight. The optical element has a band-shaped fixture 8304 and a pair of lenses 8305.

[0467] A user can view the display on the display unit 8302 through the lens 8305 . It is preferable to arrange the display portion 8302 in a curved state. By doing so, the user can feel a high sense of realism. Although the above embodiment illustrates a configuration in which one display unit 8302 is provided, the present invention is not limited to this. For example, In this case, one display unit is provided for each eye of the user. If the display is configured so that the display section is arranged in the same way, it will be possible to perform 3D display using parallax. .

[0468] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition. Even if the image is magnified using the lens 8305, the pixels are not visible to the user, and the image is more This makes it possible to display images with a higher sense of reality.

[0469] <7-3.Electronic equipment 2> Next, an example of an electronic device different from the electronic devices shown in FIG. 38(A) to FIG. 38(E) will be described with reference to FIG. 9(A) to 39(G).

[0470] The electronic device shown in FIG. 39A to FIG. 39G includes a housing 9000, a display portion 9001, a switch A speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared rays), 9008, etc.

[0471] The electronic devices shown in FIGS. 39A to 39G have various functions. Function to display various information (still images, videos, text images, etc.) on the display unit, touch panel function , calendar, date or time display functions, various software (programs) A function for controlling processing by wireless communication, a function for controlling various computers by using wireless communication, Functions for connecting to a network and transmitting or receiving various data using wireless communication functions A function to read out a program or data recorded on a recording medium and display it on the display unit. The electronic devices shown in FIGS. The functions that can be possessed by the can be not limited to these, and can have various functions. Although not shown in FIG. 39(A) to FIG. 39(G), the electronic device may have a plurality of display units. The electronic device may be provided with a camera or the like to capture still images. , the function to shoot videos, and save the captured images to a recording medium (external or built-in to the camera) The camera may have a function of capturing an image on a display unit, a function of displaying a captured image on a display unit, etc.

[0472] The electronic devices shown in FIGS. 39A to 39G will be described in detail below.

[0473] FIG. 39(A) is a perspective view showing a television device 9100. 100 is a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more It is possible to incorporate a display unit 9001 such as the above.

[0474] FIG. 39B is a perspective view showing a portable information terminal 9101. For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The information terminal 9101 can display text and image information on multiple sides. The four operation buttons 9050 (also called operation icons or simply icons) are provided on the display unit 9001. In addition, information 9051 indicated by a dashed rectangle can be displayed on one surface of the display unit 900. 1. An example of the information 9051 is an e-mail or Displays to notify you of incoming calls and SNS (social networking services), Subject of email or SNS, sender name of email or SNS, date and time, time, The remaining battery level, antenna reception strength, etc. Or, the information 9051 is displayed. In place of the information 9051, operation buttons 9050 or the like may be displayed.

[0475] FIG. 39C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 holds the portable information terminal 9102 in the breast pocket of the clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed on the mobile information terminal 9102 so that it can be observed from above. The user can read the display without taking the mobile information terminal 9102 out of his pocket. You can check the number and decide whether to answer the call or not.

[0476] 39(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is used for mobile phone calls, e-mail, document browsing and writing, music playback, and Internet communications. It is possible to execute various applications such as computer games. The display unit 9001 has a curved display surface, and displays information along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. Power may also be supplied wirelessly without going through 6.

[0477] 39(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 39(E) is a perspective view of the portable information terminal 9201 in an unfolded state. (F) shows the mobile information terminal 9201 being changed from one of the unfolded and folded states to the other. FIG. 39(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded and is unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. The portable information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0478] Next, the electronic devices shown in FIGS. 38(A) to 38(E) and the electronic devices shown in FIGS. An example of an electronic device different from the electronic device shown in FIG. 40(A) and (B) is shown in FIG. 40(A). FIG. 40(B) is a perspective view of a display device having a plurality of display panels. FIG. 40(B) is a perspective view of a state in which a plurality of display panels are rolled up. FIG. 2 is a perspective view of the device in an unfolded state.

[0479] The display device 9500 shown in FIG. 40(A) and (B) includes a plurality of display panels 9501 and a shaft portion 9 511 and a bearing portion 9512. The display panels 9501 have a display area 9502 and a light-transmitting region 9503.

[0480] In addition, the display panels 9501 are flexible. The filters 9501 are arranged so that they partially overlap each other. For example, A light-transmitting region 9503 of the display panel 9501 can be overlapped. By using the display panel 9501, a large-screen display device can be provided. The display panel 9501 can be rolled up depending on the situation, making it a versatile display. The display device may be a display device.

[0481] In addition, in FIG. 40(A) and (B), the display area 9502 is adjacent to the display panel 950 1 shows a state in which the display panels are spaced apart from each other, but this is not limited thereto. For example, the display panels 9 By overlapping the display areas 9502 of 501 without any gaps, a continuous display area 9502 is created. You may do so.

[0482] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. This can also be applied to vessels.

[0483] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible. [Explanation of symbols]

[0484] 100 transistors 100A Transistor 100B Transistor 100C transistor 100D Transistor 100E Transistor 102 Substrate 104 Conductive film 106 Insulating film 107 Insulating film 108 Oxide semiconductor film 108a Oxide semiconductor film 108b Oxide semiconductor film 108b_0 Oxide semiconductor film 108c Oxide semiconductor film 108c_ Oxide semiconductor film 108c_0 Oxide semiconductor film 112_1 Conductive film 112_2 Conductive film 112_3 Conductive film 112a Conductive film 112a_1 Metal film 112a_2 Metal film 112a_3 Metal film 112b Conductive film 112b_ Conductive film 112b_1 Metal film 112b_2 Metal film 112b_3 Metal film 112c conductive film 112c_1 Metal film 112c_2 Metal film 112c_3 Metal film 114 Insulating film 115 Insulating film 116 Insulating film 118 Insulating film 120_1 Oxide conductive film 120_2 Metal film 120a Conductive film 120a_1 Oxide conductive film 120a_2 Metal film 120b Conductive film 120b_1 Oxide conductive film 120b_2 Metal film 141a Mask 141b Mask 141c Mask 142a Mask 142b Mask 142c Mask 151 Opening 152a opening 152b opening 191 Target 192 Plasma 193 Target 194 Plasma 501 Pixel circuit 502 Pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 Transistor 552 Transistor 554 Transistor 560 Capacitive element 562 Capacitive element 570 Liquid crystal element 572 Light emitting element 664 Electrode 665 Electrode 667 Electrode 700 Display device 701 Substrate 702 Pixel section 704 Source driver circuit section 705 Substrate 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light-shielding film 750 Transistors 752 Transistor 760 Connection electrode 770 Planarizing Insulating Film 772 Conductive Film 773 Insulating Film 774 Conductive Film 775 Liquid crystal elements 776 Liquid crystal layer 777 Conductive Film 778 Structure 780 Anisotropic Conductive Film 782 Light emitting element 786 EL layer 788 Conductive Film 790 Capacitive element 791 Touch Panel 792 Insulating film 793 Electrode 794 Electrode 795 Insulating Film 796 Electrode 797 Insulating Film 800 Inverter 810 OS Transistor 820 OS Transistor 831 Signal Waveform 832 Signal Waveform 840 dashed line 841 Solid Line 850 OS Transistor 860 CMOS Inverter 900 Semiconductor device 901 Power supply circuit 902 Circuit 903 Voltage Generation Circuit 903A Voltage Generation Circuit 903B Voltage Generation Circuit 903C Voltage Generation Circuit 904 Circuit 905 Voltage Generation Circuit 906 Circuit 911 Transistor 912 Transistor 912A Transistor 912B Transistor 921 Control circuit 922 Transistor 7000 Display Module 7001 Top cover 7002 Lower cover 7003 FPC 7004 Touch Panel 7005 FPC 7006 Display Panel 7007 Backlight 7008 Light source 7009 Frame 7010 Printed Circuit Board 7011 Battery 8000 Camera 8001 Case 8002 Display section 8003 Operation button 8004 Shutter button 8006 Lens 8100 Finder 8101 Case 8102 Display section 8103 Button 8200 Head Mounted Display 8201 Mounting part 8202 Lens 8203 Main unit 8204 Display section 8205 Cable 8206 Battery 8300 Head Mounted Display 8301 Case 8302 Display section 8304 Fixtures 8305 Lens 9000 Chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television equipment 9101 Portable information terminal 9102 Portable information terminal 9200 Mobile Information Terminal 9201 Portable information terminals 9500 display device 9501 Display Panel 9502 Display area 9503 area 9511 Shaft 9512 Bearing section

Claims

1. a first conductive film having a region functioning as a gate electrode; an oxide semiconductor film having a channel formation region; a second conductive film having a region functioning as a source electrode or a drain electrode; a first insulating film having a region in contact with an upper surface of the oxide semiconductor film and a region in contact with an upper surface of the second conductive film; a second insulating film having a region in contact with an upper surface of the first insulating film; a third conductive film having a region in contact with an upper surface of the second insulating film; a fourth conductive film having a region in contact with an upper surface of the third conductive film; the fourth conductive film is always electrically connected to the first conductive film via a fifth conductive film having a region in contact with a lower surface of the first insulating film; a region where the fourth conductive film and the fifth conductive film are in contact with each other and which overlaps with a region where the fifth conductive film and the first conductive film are in contact with each other;

2. a first conductive film having a region functioning as a gate electrode; an oxide semiconductor film having a channel formation region; a second conductive film having a region functioning as a source electrode or a drain electrode; a first insulating film having a region in contact with an upper surface of the oxide semiconductor film and a region in contact with an upper surface of the second conductive film; a second insulating film having a region in contact with an upper surface of the first insulating film; a third conductive film having a region in contact with an upper surface of the second insulating film; a fourth conductive film having a region in contact with an upper surface of the third conductive film; the fourth conductive film has a region overlapping with the oxide semiconductor film, the fourth conductive film is always electrically connected to the first conductive film via a fifth conductive film having a region in contact with a lower surface of the first insulating film; a region where the fourth conductive film and the fifth conductive film are in contact with each other and which overlaps with a region where the fifth conductive film and the first conductive film are in contact with each other;

Images