Semiconductor device

Abstract

To provide a semiconductor device having high reliability; and provide a manufacturing method of a semiconductor device having high reliability; and provide a semiconductor device with low power consumption; and provide a manufacturing method of a semiconductor device with low power consumption; and provide a semiconductor device with high mass productivity; and provide a manufacturing method of a semiconductor device with high mass productivity.SOLUTION: It is preferable to use an oxide semiconductor layer by removing an impurity remaining in an oxide semiconductor layer and defecating the oxide semiconductor layer to extremely high purity. In particular, it is preferable to use the oxide semiconductor layer by adding halogen to the oxide semiconductor layer and subsequently performing a heat treatment to remove the impurity. It is preferable to use fluorine as the halogen.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a method for manufacturing the semiconductor device. A semiconductor device generally refers to elements and devices that function by utilizing semiconductor properties. do. [Background technology]

[0002] A technique for forming a transistor using a semiconductor layer formed on a substrate having an insulating surface is known. For example, transistors are being fabricated on glass substrates using thin films containing silicon-based semiconductor materials. There is known a technique for forming a semiconductor device and applying it to a liquid crystal display device or the like.

[0003] The transistors used in liquid crystal displays are mainly made of amorphous silicon or polycrystalline silicon. Amorphous silicon transistors are made of semiconductor materials such as silicon. Although the field effect mobility is low, it can be used for large-area glass substrates. Although crystalline silicon transistors have high field effect mobility, they are difficult to fabricate using laser annealing, etc. The crystallization process is required, and it is not necessarily suitable for making large-area glass substrates. It has.

[0004] Another material that is attracting attention is oxide semiconductors. Zinc or zinc oxide is known as a component. 1 8 / cm 3 A thin-film transistor made of amorphous oxide (oxide semiconductor) with a thickness of less than Patent documents 1 to 3 disclose a method for manufacturing a semiconductor laser. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165527 A [Patent Document 2] JP 2006-165528 A [Patent Document 3] JP 2006-165529 A Summary of the Invention [Problem to be solved by the invention]

[0006] Transistors that utilize semiconductor characteristics have small variations in threshold voltage due to degradation over time. In addition, it is desirable that the off-state current is small. For example, the variation of the threshold voltage due to aging is small. A transistor with a large capacitance reduces the reliability of a semiconductor device that uses the transistor. A transistor with a large off-state current increases the power consumption of a semiconductor device using the transistor.

[0007] An object of the present invention is to provide a semiconductor device having high reliability. An object of the present invention is to provide a method for manufacturing a semiconductor device.

[0008] Another object of the present invention is to provide a semiconductor device with low power consumption. An object of the present invention is to provide a method for manufacturing a semiconductor device.

[0009] Another object is to provide a semiconductor device with high mass productivity. An object of the present invention is to provide a method for manufacturing a semiconductor device. [Means for solving the problem]

[0010] In order to solve the above problems, the present inventors have developed a semiconductor device using an oxide semiconductor for a semiconductor layer. In the present invention, the concentration of impurities contained in the oxide semiconductor layer changes the threshold voltage and the off-state current. The impurities include, for example, hydrogen and water. The impurity containing hydrogen is, for example, a material containing hydrogen. The hydrogen is donated to the metal, creating an impurity level.

[0011] Impurities contained in the oxide semiconductor layer are removed by subjecting the oxide semiconductor layer to high temperature (e.g. However, the oxide semiconductor can be removed by heat treatment at a temperature of 600°C. Impurities that bond strongly with the metal (such as hydrogen and hydroxyl groups) are oxidized due to their strong bond. If an oxide semiconductor with residual impurities is used for the semiconductor layer, This can cause problems such as an increase in the load current.

[0012] In order to solve the above problems, impurities remaining in an oxide semiconductor layer are removed, and the oxide semiconductor Specifically, the oxide semiconductor layer may be formed by purifying the oxide semiconductor layer to a high purity. After adding a substance that strongly bonds with the pure material, heat treatment is performed to turn the stable substance containing hydrogen into an oxide. The substance that strongly bonds with the impurity may be, for example, a halogen atom. A substance containing a halogen element having high kinetic energy is preferably used. By adding, for example, the bond between the metal and hydrogen that constitutes the oxide semiconductor, the bond between the metal and the hydroxyl group, or the oxygen-hydrogen bond in a hydroxyl group that is bonded to a metal.

[0013] On the other hand, by adding a substance that strongly binds to impurities to the oxide semiconductor layer, When the bond with the substance is broken, a dangling bond may be generated on the metal atom. If there are dangling bonds, carriers are generated and the carrier density increases. In a semiconductor device having a high-density oxide semiconductor layer, the threshold voltage is decreased and the device has a normally-on property. This is undesirable because it shows a tendency.

[0014] The above problem can also be solved by adding a halogen element to the oxide semiconductor layer. The halogen element bonds to the dangling bonds of the metal atom and terminates the dangling bonds, so that the generation of carriers is This can suppress the formation of

[0015] That is, one embodiment of the present invention is to form a gate electrode on a substrate having an insulating surface, A gate insulating layer is formed on the electrode, and an oxide semiconductor is formed in contact with the gate insulating layer and overlapping the gate electrode. A conductor layer is formed, a halogen element is added to the oxide semiconductor layer, and an oxide semiconductor layer having a halogen element added thereto is formed. The oxide semiconductor layer is subjected to a first heat treatment, and an end portion is formed in contact with the heat-treated oxide semiconductor layer. A source electrode and a drain electrode are formed so as to overlap the gate electrode, and a channel of the oxide semiconductor layer is formed. A semiconductor device is fabricated by forming an insulating layer in contact with a surface of an oxide semiconductor layer and overlapping a hole formation region. This is the manufacturing method.

[0016] Another embodiment of the present invention is a semiconductor device including a source electrode and a drain electrode formed over a substrate having an insulating surface. An oxide semiconductor layer is formed to cover the ends of the source electrode and the drain electrode. A halogen element is added to the oxide semiconductor layer, and a first heat treatment is performed on the oxide semiconductor layer to which the halogen element is added. The heat treatment is performed on the oxide semiconductor layer, and the ends of the source electrode and the drain electrode are formed in contact with the oxide semiconductor layer. A gate insulating layer is formed so as to overlap the gate insulating layer, and a source electrode and a drain electrode are formed in contact with the gate insulating layer. The present invention relates to a method for manufacturing a semiconductor device, in which a gate electrode is formed so as to overlap an end of a electrode.

[0017] In the above-described method for manufacturing a semiconductor device, after the first heat treatment, When oxygen is added to the oxide semiconductor layer, the main component constituting the oxide semiconductor is In addition, the oxide semiconductor layer can be provided with oxygen, which is a decomposition material. After the halogen element is added, a second heat treatment may be performed. Impurities that could not be removed by the treatment are removed by adding oxygen and by the second heat treatment. As a result, the oxide semiconductor layer is further purified and electrically made to be i-type (intrinsic) or substantially It can be made into an I-type.

[0018] In the above-mentioned method for manufacturing a semiconductor device, the first heat treatment is performed at a temperature of 250° C. or higher and 600° C. or lower. It is preferable to carry out the process in the following manner.

[0019] In the method for manufacturing a semiconductor device, after the oxide semiconductor layer is formed, heat treatment is performed. After the oxide semiconductor layer is formed, heat treatment is performed to remove hydrogen from the oxide semiconductor layer. Alternatively, impurities such as moisture may be removed and exhausted. By adding an oxygen-containing gas, the concentration of impurities contained in the oxide semiconductor layer can be further reduced.

[0020] In another embodiment of the present invention, the semiconductor device is provided on an insulating film formed on a first transistor. The present invention relates to a method for manufacturing a semiconductor device, in which a second transistor is manufactured by using the method for manufacturing a semiconductor device.

[0021] Another embodiment of the present invention is a method for manufacturing a semiconductor device comprising: A gate insulating layer is formed on the gate insulating layer, and a halogen element is doped on the gate insulating layer. 15 atoms / cm 3 Below Top 1018 atoms / cm 3 An oxide semiconductor layer containing the following at a concentration: A source electrode, a drain electrode, a gate insulating layer, an oxide semiconductor layer, A semiconductor having an insulating layer over a source electrode and a drain electrode, the insulating layer being in contact with a part of the oxide semiconductor layer. It is a device.

[0022] Another aspect of the present invention is a semiconductor device comprising: a source electrode and a drain electrode on an insulating surface; On the source electrode and the drain electrode, halogen elements are added at 10 15 atoms / cm 3 1 more 0 18 atoms / cm 3 An oxide semiconductor layer containing the following at the following concentration, an insulating surface, a source electrode, A gate insulating layer is formed on the drain electrode and the oxide semiconductor layer, and a gate electrode is formed on the gate insulating layer. The semiconductor device has a pole.

[0023] In the above semiconductor device, the halogen element is preferably fluorine. The bond energy between fluorine and hydrogen is higher than that between other halogen elements and hydrogen. is more stable than the bonds between other halogen elements and hydrogen. Effect of the Invention

[0024] According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. It is possible to provide a method for producing the above.

[0025] One embodiment of the present invention can provide a semiconductor device with low power consumption. A method for making the device can be provided.

[0026] According to one embodiment of the present invention, a semiconductor device with high mass productivity can be provided. It is possible to provide a method for producing the above. [Brief description of the drawings]

[0027] [Figure 1] 1A to 1C illustrate a structure of a semiconductor device according to an embodiment. [Diagram 2] 1A to 1C illustrate a method for manufacturing a semiconductor device according to an embodiment. [Diagram 3] 1A to 1C illustrate a structure of a semiconductor device according to an embodiment. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device according to an embodiment. [Diagram 5] 1A to 1C illustrate a structure of a semiconductor device according to an embodiment. [Figure 6] 1A to 1C illustrate a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1A to 1C illustrate a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 1A to 1C illustrate a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 1A to 1C illustrate a structure of a semiconductor device according to an embodiment. [Figure 11] 1A to 1C illustrate a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 1A to 1C illustrate a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] 1 is a circuit diagram of a semiconductor device according to an embodiment. [Figure 14] 1 is a circuit diagram of a semiconductor device according to an embodiment. [Figure 15] 1 is a circuit diagram of a semiconductor device according to an embodiment. [Figure 16] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to an embodiment. [Figure 17] FIG. 1 is a schematic diagram illustrating an example of a calculation model. [Figure 18] FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to an embodiment. [Figure 19]1A to 1C illustrate a structure of a liquid crystal display device according to an embodiment. [Figure 20] 4 is a timing chart illustrating the operation of the liquid crystal display device according to the embodiment. [Figure 21] 5 is a timing chart illustrating the operation of a display control circuit of the liquid crystal display device according to the embodiment. [Figure 22] 5A and 5B are diagrams illustrating the frequency of writing image signals for each frame period in a period in which a moving image is displayed and a period in which a still image is displayed in the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention should not be construed as being limited to the contents described below. The same reference numerals are used in different drawings to indicate the same parts or parts having similar functions. A repeated explanation thereof will be omitted.

[0029] (Embodiment 1) In this embodiment, fluorine is added to the oxide semiconductor layer and then heat treatment is performed to remove impurities. A bottom-gate transistor is fabricated by using a method for purifying an oxide semiconductor layer by removing the oxide semiconductor layer. The manufacturing method will be described with reference to FIG. 1 and FIG.

[0030] The structure of a bottom-gate transistor 550 manufactured in this embodiment is shown in FIG. FIG. 1A shows a top view of a transistor 550, and FIG. 1B shows a cross-sectional view of the transistor 550. FIG. 1(B) corresponds to a cross-sectional view taken along line P1-P2 in FIG. 1(A).

[0031] The transistor 550 includes a gate electrode 511 and a gate insulating film 520 formed on a substrate 500 having an insulating surface. The gate insulating layer 502 covers the gate electrode 511. The highly purified oxide semiconductor layer 513c overlapping with the electrode 511 and the oxide semiconductor layer 51 3c, and functions as a source electrode or drain electrode whose end overlaps with the gate electrode 511. The first electrode 515a and the second electrode 515b are connected to the oxide semiconductor layer. The insulating layer 507 overlapping the channel formation region and the protective insulating layer 508 covering the transistor 550 are It has an edge layer 508 .

[0032] In the oxide semiconductor used in this embodiment, hydrogen acting as an n-type impurity is removed, and the oxide semiconductor By purifying the conductor to the maximum extent possible so that it contains no impurities other than the main component, it is a type I (true) The oxide semiconductor is an oxide semiconductor or an oxide semiconductor that is extremely close to an i-type (intrinsic) semiconductor.

[0033] In addition, the number of carriers in a highly purified oxide semiconductor is extremely small, and the carrier concentration is 1× 10 14 / cm 3 Less than 1 x 10 12 / cm 3 Less than 1×1 0 11 / cm 3 In addition, the small number of carriers reduces the The current (off-state current) becomes sufficiently small.

[0034] Specifically, in the above-described transistor including an oxide semiconductor layer, The leakage current density (off-state current density) per 1 μm of channel width between the source and drain is When the voltage between the lines is 3.5V and the temperature conditions are as specified for use (e.g., 25°C), the A / μm(1×10 -19 A / μm) or less, or 10zA / μm (1×10 -20 A / μm), and even 1zA / μm (1×10 -21 A / μm) or less. do.

[0035] In addition, a transistor including a highly purified oxide semiconductor layer has a low temperature dependence of off-state current. Almost no change is observed, and the off-state current remains very small even at high temperatures.

[0036] Next, a method for manufacturing a transistor 550 on a substrate 500 will be described with reference to FIGS. ) will be used to explain.

[0037] First, a conductive film is formed on a substrate 500 having an insulating surface, and then a first photolithography process is performed. A wiring layer including a gate electrode 511 is formed by the process. In any photolithography process of the transistor manufacturing process, a resist mask is used. If the resist mask is formed by the inkjet method, the photoresist can be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0038] In this embodiment mode, a glass substrate is used as the substrate 500 having an insulating surface.

[0039] An insulating film serving as a base film may be provided between the substrate 500 and the gate electrode 511. Impurity elements from the substrate 500 (e.g., alkali metals such as lithium and sodium, It has the function of preventing the diffusion of alkaline earth metals such as calcium, and silicon nitride film , a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film in a single layer or a laminated layer. It can be formed.

[0040] The gate electrode 511 is made of molybdenum, titanium, tantalum, tungsten, or aluminum. The material is made of metals such as aluminum, copper, neodymium, scandium, etc., or alloys made of these materials as the main components. The insulating film may be formed as a single layer or a multilayer.

[0041] Aluminum and copper are high melting point metals to avoid problems of heat resistance and corrosion. It is recommended to use them in combination with high melting point metal materials such as molybdenum, titanium, and chromium. , tantalum, tungsten, neodymium, scandium, etc. can be used.

[0042] When copper is used, the underlayer is copper-magnesium-aluminum (Cu-Mg It is preferable to form a Cu-Mg-Al alloy on the substrate and then form copper thereon. This has the effect of improving the adhesion between the copper and the base material such as an oxide film.

[0043] Next, a gate insulating layer 502 is formed on the gate electrode 511. The gate insulating layer 502 is A silicon oxide layer, a silicon nitride layer, or a silicon nitride layer is formed by using a plasma CVD method or a sputtering method. A silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, A single layer of aluminum oxynitride, aluminum oxide nitride, or hafnium oxide is formed. It can be formed by laminating.

[0044] The oxide semiconductor of this embodiment is an i-type or substantially i-type oxide semiconductor from which impurities have been removed. Such a highly purified oxide semiconductor has a low interface state density and a low interface The interface between the oxide semiconductor layer and the gate insulating layer is important because it is extremely sensitive to surface charges. Therefore, the gate insulating layer in contact with the highly purified oxide semiconductor must be of high quality. can be.

[0045] For example, high-density plasma CVD using microwaves (e.g., 2.45 GHz frequency) produces dense This is preferable because it allows the formation of a high-quality insulating layer with high dielectric strength. The close contact between the gate insulating layer and the high-quality gate insulating layer reduces the interface state density and improves the interface characteristics. This is because it can be made into something that is

[0046] Of course, if a good insulating layer can be formed as a gate insulating layer, sputtering is also possible. Other deposition methods such as the plasma CVD method and the like can be applied. Even if the insulating layer is one in which the film quality of the gate insulating layer and the interface characteristics with the oxide semiconductor are modified by In any case, the film quality as a gate insulating layer is good, and the oxidation Any material may be used as long as it can reduce the interface state density with the solid semiconductor and form a good interface.

[0047] Note that the gate insulating layer 502 is in contact with an oxide semiconductor layer 513c that will be formed later. If hydrogen diffuses into the conductor layer 513c, the semiconductor characteristics are impaired. It is preferable that the gate insulating layer 502 does not contain hydrogen, hydroxyl groups, or moisture. In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor film as much as possible, As a pretreatment for forming the conductive film, the gate electrode 511 is formed in the preheating chamber of the sputtering device. The substrate 500 on which the gate insulating layer 502 is formed or the substrate 500 on which the gate insulating layer 502 is formed is preheated. It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 500. The exhaust means provided in the preheating chamber is preferably a cryopump. This pre-heating may be omitted. Also, the pre-heating may be performed before the insulating layer 507 is formed on the first electrode 502. The same process may be carried out on the substrate 500 on which the first electrode 15a and the second electrode 515b have been formed.

[0048] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm or more, is formed on the gate insulating layer 502. An oxide semiconductor film having a thickness of 30 nm or less is formed.

[0049] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced. A reverse sputtering process is carried out to generate plasma, and the powdery material adhering to the surface of the gate insulating layer 502 is removed. It is preferable to remove the substances (also called particles or dust). No voltage was applied to the target side, and a voltage was applied to the substrate using an RF power supply in an argon atmosphere. This is a method to modify the surface by forming plasma near the substrate. In addition, nitrogen, helium, oxygen, etc. may be used.

[0050] The oxide semiconductor film is formed by a sputtering method using a metal oxide as a target. In addition, the oxide semiconductor film is heated under a rare gas (for example, argon) atmosphere, an oxygen atmosphere, or a rare gas It can be formed by sputtering in a mixed atmosphere of argon (e.g., argon) and oxygen. do.

[0051] The oxide semiconductor used for the oxide semiconductor film is a quaternary metal oxide, In-Sn-G a-Zn-O oxide semiconductors and In-Ga-Zn-O oxides, which are ternary metal oxides Semiconductors, In-Sn-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors, Sn-Ga-Zn-O oxide semiconductor, Al-Ga-Zn-O oxide semiconductor, Sn-A l-Zn-O oxide semiconductors and In-Zn-O oxide semiconductors, which are binary metal oxides , Sn-Zn-O oxide semiconductor, Al-Zn-O oxide semiconductor, Zn-Mg-O oxide oxide semiconductors, Sn-Mg-O oxide semiconductors, In-Mg-O oxide semiconductors, In-G aO-based oxide semiconductors, In-O-based oxide semiconductors, which are single-element metal oxides, and Sn-O-based Oxide semiconductors, Zn-O-based oxide semiconductors, etc. can be used. The conductor may contain SiO2. The oxide semiconductor film is provided with silicon oxide (Si O x (X>0)), after the formation of the oxide semiconductor film during the manufacturing process, When the material is heated, crystallization can be suppressed. n-Ga-Zn-O oxide semiconductors are semiconductors that are made of indium (In), gallium (Ga), and zinc (Zn). (Zn) means an oxide film having the above-mentioned composition ratio. Elements other than n, Ga, and Zn may be included.

[0052] In addition, the oxide semiconductor film is made of InMO3(ZnO) m (m>0 and m is a natural number. In this case, M is Ga, Al, Mn, and It represents one or more metal elements selected from Ga, Ga, and Al. , Ga and Mn, or Ga and Co.

[0053] In addition, when using an In-Zn-O-based material as an oxide semiconductor, the composition of the target used The composition ratio is In:Zn=50:1-1:2 in atomic ratio (In2O3 In:ZnO=25:1 to 1:4, preferably In:Zn=20:1 to 1:1 (molar ratio) In terms of In2O3:ZnO=10:1 to 1:2), more preferably In:Zn=1 5:1 to 1.5:1 (converted to a molar ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used for forming an In-Zn-O oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0054] The oxide semiconductor used in this embodiment is preferably an oxide semiconductor containing In. An oxide semiconductor containing In and Ga is more preferable. In this embodiment, the oxide semiconductor film is The film is formed by sputtering using an In-Ga-Zn-O oxide target. .

[0055] As a target for forming an oxide semiconductor film by a sputtering method, for example, The ratio of the oxide target was In2O3:Ga2O3:ZnO=1:1:1 [molar ratio]. In-Ga-Zn-O film is formed using a target. For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio], Or oxide having a composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [molar ratio] A physical target may also be used.

[0056] The filling rate of the oxide target is 90% or more and 100% or less, preferably 95% or more and 99% or less. By using a metal oxide target with a high filling rate, the oxide film formed is The compound semiconductor film can be made dense. The purity of the target is 99.99% or more. The above is preferred, and in particular, alkali metals such as Na and Li and alkaline earth metals such as Ca. It is preferable that the impurities are reduced.

[0057] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. It is preferable to use a high-purity gas from which all impurities have been removed. The following high purity gases are preferred:

[0058] The substrate is held in a film-forming chamber maintained in a reduced pressure state, and the substrate temperature is preferably set to 100° C. or more and 600° C. or less. The temperature is preferably 200° C. or higher and 400° C. or lower. In addition, the concentration of impurities in the oxide semiconductor film can be reduced. Damage caused by etching is reduced. The removed sputtering gas is introduced, and an oxide semiconductor is deposited on the substrate 500 using the target. To remove residual moisture in the deposition chamber, a vacuum pump of the adsorption type, e.g. It is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump is filled with hydrogen and chemicals containing hydrogen such as water. Since compounds (and more preferably compounds containing carbon) are exhausted, the film formed in the film formation chamber is The concentration of impurities contained in the oxide semiconductor film can be reduced.

[0059] The atmosphere in which the sputtering method is performed is a rare gas (typically argon) atmosphere, an oxygen atmosphere, Alternatively, a mixture atmosphere of rare gas and oxygen may be used.

[0060] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed DC power supply is used, the powdery substances (particles, etc.) generated during film formation are reduced. This is preferable because it can reduce the amount of adhesion (also referred to as the "friction") and make the film thickness distribution uniform.

[0061] In addition, the leak rate of the sputtering equipment processing chamber was set to 1×10 -10 Pa·m 3 / second or less By doing so, it is possible to prevent alkali from being added to the oxide semiconductor film during the film formation by the sputtering method. The inclusion of impurities such as metals and hydrides can be reduced.

[0062] In addition, by using an adsorption type vacuum pump as the exhaust system, alkali metals, hydrogen, etc. are removed from the exhaust system. , the backflow of impurities such as water, hydroxyl radicals, or hydrides can be reduced.

[0063] In addition, alkali metals such as Li and Na and arsenic such as Ca contained in the oxide semiconductor layer It is preferable that impurities such as alkaline earth metals are reduced. The impurity concentrations in the layer were measured using SIMS to determine that Li was 5×10 15 cm -3 Less than or equal to 1×10 15 cm -3 Below, Na is 5 × 10 15 cm -3 The following is preferred: 1×10 15 cm -3 In the following, K is 5×10 15 cm -3 Less than or equal to 1×10 1 5 cm -3 It is preferable that:

[0064] Alkali metals and alkaline earth metals are harmful impurities for oxide semiconductors. In particular, among alkali metals, Na is a metal that is highly likely to cause the insulating film in contact with the oxide semiconductor to become oxide. If so, Na will diffuse into it. + In addition, in the oxide semiconductor, It breaks the oxygen bonds or breaks into the bonds. As a result, the transistor characteristics are deteriorated ( For example, this leads to a normally-on state (a shift of the threshold voltage to the negative side), a decrease in mobility, etc. In addition, this can cause variations in characteristics. Such a problem occurs particularly when hydrogen is present in an oxide semiconductor. This is remarkable when the hydrogen concentration in the oxide semiconductor is sufficiently low. 5×10 19 cm -3 Below, especially 5×10 18 cm -3 If it is below, then it is alkaline. The above metal concentrations are highly desirable.

[0065] Next, the oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 5. Process into 13a.

[0066] In addition, when a contact hole is formed in the gate insulating layer 502, the process is performed using an oxide semiconductor. This can be done simultaneously with the processing of the membrane.

[0067] Note that the etching of the oxide semiconductor film here may be performed by dry etching or wet etching. For example, a wet etching method for an oxide semiconductor film may be used. The etching solution that can be used is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used. ) as shown in

[0068] In addition, the etching gas used in the dry etching is a gas containing chlorine (e.g., chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl 4) and the like) are preferred. In addition, gases containing fluorine (e.g., carbon tetrafluoride (CF4), hexafluoride Sulfur (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), bromide Hydrogen (HBr), oxygen (O2), and these gases with helium (He) and argon (Ar) Any gas containing any rare gas can be used.

[0069] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0070] Next, fluorine is added to the oxide semiconductor layer 513a. Fluorine is added by ionizing a gas containing fluorine into a plasma. The ion species contained in this plasma are extracted and accelerated. The fluorine ions may be added to the oxide semiconductor layer as an ion beam. For example, the amount of fluorine ions to be injected is 10 -13 ion / cm 2 Over 10 -15 ion / cm 2 The following would suffice.

[0071] Examples of fluorine-containing gases include carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), and trifluoride. Nitrogen fluoride (NF3), trifluoromethane (CHF3), and the combination of these gases with helium and ammonia A gas containing a rare gas such as argon added thereto, etc. can be used.

[0072] Although an example in which fluorine is added is described in this embodiment, one embodiment of the present invention is not limited thereto. For example, a gas containing chlorine (e.g., chlorine (C l2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4) Chlorine may be added using a method such as the above.

[0073] The pressure at which fluorine is added is 10 -4 Pa or more 10 2 It is preferable that the pressure is 0.1 Pa or less.

[0074] By using a plasma doping device, the pressure during fluorine doping can be increased to 10 -2 Pa or more 10 2 Pa The plasma generating means can be ICP (Inductively Coupled Plasma) Using excitation techniques such as inductively coupled plasma (Inductively Coupled Plasma) For example, when using a plasma doping device and ICP as the excitation method, A high-frequency voltage is applied to both the antenna and the electrode on the substrate side. The ion species contained in this plasma are then excited by a high-frequency voltage applied to the electrode on the substrate side. The ions are accelerated by the bias voltage generated by the ion beam and are deposited on the oxide semiconductor layer on the substrate. Also, fluorine can be added in the same way using a dry etching device. It is possible to do so.

[0075] For example, nitrogen trifluoride (NF3) is used as the gas, and the power applied to the antenna is 600 W. The power applied to the electrode on the substrate side was 100 W, the pressure was 1.35 Pa, and the gas flow rate was 70 s ccm, plasma treatment may be performed for 60 seconds to add fluorine.

[0076] In addition, by using an ion doping device, the pressure during fluorine doping can be increased to 10 -3 Pa or more 10 - 2 The acceleration voltage can be set to 10 keV or more and 100 keV or less. When fluorine is added using an ion doping device, a gas containing fluorine is The plasma is generated, and ion species are extracted from the plasma by the action of a specific electric field. The ion species are accelerated without being mass-separated and are injected into the oxide semiconductor layer as an ion beam. The ion doping apparatus has a larger area to be irradiated with the ion beam than the ion implantation apparatus described later. By adding fluorine using an ion doping device, The tact time can be reduced.

[0077] In addition, by using an ion implantation device, the pressure during fluorine addition can be increased to 10 -4 Pa or more 10 -3 Pa The acceleration voltage can be set to 100 keV or more and 300 keV or less. When fluorine is added using an ion implantation device, a gas containing fluorine is converted into plasma. The ion species contained in this plasma are extracted and separated by mass to obtain ions having a predetermined mass. The ion species are accelerated and injected into the oxide semiconductor layer as an ion beam. By adding fluorine using an on-implantation device, impurities such as metal elements are dissolved in oxygen along with the fluorine. This can prevent the doping of the oxide semiconductor layer.

[0078] By adding fluorine to the oxide semiconductor layer 513a, for example, a metal constituting the oxide semiconductor and hydrogen, between a metal and a hydroxyl group, or oxygen in a hydroxyl group bonded to a metal Note that the oxide semiconductor layer 513a can break the bond between the metal and hydrogen. This results in an oxide semiconductor layer 513b containing a pure substance (FIG. 2B).

[0079] Before fluorine is added to the oxide semiconductor layer 513a, preliminary heat treatment is performed. Impurities such as hydrogen and moisture in 513a may be desorbed and exhausted. The preferred exhaust means is a cryopump. The temperature of the preliminary heating process is 250°C to 500°C. When fluorine is added after the preliminary heat treatment, the fluorine contained in the oxide semiconductor layer The concentration of impurities can be further reduced.

[0080] Next, a first heat treatment is performed on the oxide semiconductor layer 513b containing the impurities released from the metal. By the first heat treatment, impurities released from the metal can be removed from the oxide semiconductor layer. For example, hydrogen or hydroxyl groups released from metal react with added fluorine to produce fluoride. It can remove hydrogen and other elements that are strongly bonded to metals without adding halogen elements. Compared with methods that directly remove hydroxyl groups (such as high-temperature heat treatment), the generated hydrogen fluoride, etc. It is easy to remove it by heating.

[0081] The temperature of the first heat treatment is 250° C. or more and 750° C. or less. By adding fluorine to the semiconductor layer, impurities are easily released from the oxide semiconductor layer. Therefore, the first heat treatment can be performed at a low temperature. This allows processing in a short time.

[0082] Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated to a nitrogen atmosphere. After heat treatment at 450℃ for 1 hour in a nitrogen atmosphere, the material was oxidized without exposure to air. The re-mixing of water or hydrogen into the oxide semiconductor layer is prevented, and an oxide semiconductor layer 513c is obtained (FIG. 2C). .

[0083] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. A device that heats the workpiece by radiation may be used. For example, a GRTA (Gas Reactor Atomic (GRTA) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. al) equipment can be used. The LRTA equipment can be a halogen lamp, a metal halide lamp, lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp or other light source. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment Active gas is used. RTA (Rapid Thermal Anneal) is used for heat treatment. By using this method, dehydration or dehydrogenation can be performed in a short time, so the strain point of the glass substrate can be exceeded. It can be processed at temperatures as high as

[0084] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., 1 ppm or less, It is preferable that the concentration of the ion exchange resin is 0.1 ppm or less.

[0085] After the oxide semiconductor layer is heated by the first heat treatment, high-purity oxygen gas, high-purity 200°C N2O gas or ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm or less (-55°C in dew point equivalent). Air (preferably 1 ppm or less, preferably 10 ppb or less) may be introduced. It is preferable that the N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or NO gas introduced into the apparatus is set to 6N or more, preferably 7N or more (i.e., The impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably 0.1 ppm or less. It is preferable to dehydrate or dehydrogenate the material by the action of oxygen gas or N2O gas. The main components of the oxide semiconductor that were reduced at the same time as the impurity removal process By supplying oxygen, which is a component material, the oxide semiconductor layer is highly purified and electrically To become a type (authentic).

[0086] Further, fluorine may be added before the oxide semiconductor film is processed into an island shape. The first heat treatment may be performed before or after the second photolithography step. stomach.

[0087] Note that the first heat treatment is performed after fluorine is added and before another layer is formed over the oxide semiconductor layer. However, other than the above, it is also possible to carry out the treatment after adding fluorine to the oxide semiconductor layer. After laminating a gate insulating layer on the gate insulating layer, or after forming a gate electrode on the gate insulating layer, Either method may be used.

[0088] In addition, when a contact hole is formed in the gate insulating layer 502, the process is performed using an oxide semiconductor. This may be performed before or after the first heat treatment of the film. stomach.

[0089] Through the above steps, the hydrogen concentration in the oxide semiconductor layer can be reduced and the oxide semiconductor layer can be highly purified. This makes it possible to stabilize the oxide semiconductor layer. It is possible to form an oxide semiconductor film having an extremely low density and a wide band gap. Therefore, transistors can be manufactured using large-area substrates, which improves mass productivity. In addition, by using the oxide semiconductor film in which the hydrogen concentration is reduced and which is highly purified, A transistor having high withstand voltage and extremely low off-state current can be manufactured. The treatment can be performed at any time after the formation of the oxide semiconductor layer.

[0090] In the case where the oxide semiconductor film is heated, depending on the material of the oxide semiconductor film and heating conditions, Plate-like crystals may be formed on the surface of the oxide semiconductor film. It is preferable that the crystal be a plate crystal having a c-axis oriented approximately vertically.

[0091] In addition, the oxide semiconductor layer is formed in two separate steps and heat treatment is performed in two separate steps. The material of the base member that comes into contact with the oxide semiconductor layer formed for this purpose is a material such as oxide, nitride, or metal. Regardless of the thickness, the crystal region (single crystal region) with a thick film thickness, i.e., the crystal with the c-axis oriented perpendicular to the film surface, For example, a first oxide semiconductor layer having a thickness of 3 nm to 15 nm may be formed. The oxide semiconductor film is formed, a first fluorine addition is performed, and nitrogen, oxygen, a rare gas, or a dry A first heat treatment is performed at 450°C to 850°C in an air atmosphere, and the surface region is A first oxide semiconductor film having a crystal region (including a plate-like crystal) is formed. A second oxide semiconductor film is formed to be thicker than the oxide semiconductor film, and a second fluorine addition is performed. A second heat treatment is performed at a temperature higher than or equal to 50° C. and lower than or equal to 850° C. to grow the first oxide semiconductor film as a seed for crystal growth. As a result, the second oxide semiconductor film is entirely crystallized. An oxide semiconductor layer having a thick crystal region may be formed. When fluorine is added to the first oxide semiconductor film, the crystal region of the first oxide semiconductor film is Therefore, in the second fluorination, the first oxidation It is necessary to select appropriate conditions (accelerating voltage, etc.) so that fluorine is not added to the semiconductor film. .

[0092] In addition, when forming the oxide semiconductor layer, the substrate is heated to a temperature at which the oxide semiconductor is oriented along the c-axis. By performing the deposition while aligning the film, an oxide semiconductor having a crystal region with a c-axis oriented perpendicular to the film surface was obtained. A conductive layer may be formed. By using such a film forming method, the process can be shortened. The temperature to which the substrate is heated varies depending on the deposition equipment, as other deposition conditions differ. For example, the substrate temperature during film formation using a sputtering device may be set appropriately. The film may be formed at a temperature of 250° C. or higher.

[0093] Next, a source electrode and a drain electrode were formed on the gate insulating layer 502 and the oxide semiconductor layer 513c. A conductive film is formed to become the source electrode (including wiring formed in the same layer). The conductive film used for the drain electrode is, for example, Al, Cr, Cu, Ta, Ti, M A metal film containing an element selected from the group consisting of o and W, or a metal nitride containing the above-mentioned elements as components. Films such as titanium nitride film, molybdenum nitride film, and tungsten nitride film can be used. In addition, metal films such as Al and Cu are often used on the underside or upper side to avoid problems with heat resistance and corrosion. A high melting point metal film such as Ti, Mo, W, Cr, Ta, Nd, Sc, Y, etc. is applied to one or both of the electrodes. or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) In particular, a conductive film containing titanium may be provided on the side in contact with the oxide semiconductor layer. It is preferable to provide such a function.

[0094] The conductive film may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of an aluminum film containing titanium, a two-layer structure of a titanium film laminated on an aluminum film, A titanium film is then formed on top of the aluminum film, and then a titanium film is formed on top of that. Examples include a three-layer structure that forms a membrane.

[0095] The conductive film may be made of a conductive metal oxide. Indium oxide, tin oxide, zinc oxide, indium oxide tin oxide alloy, indium oxide Zinc alloy or the above metal oxide material containing silicon or silicon oxide is used. There can be.

[0096] In addition, when a heat treatment is performed after the conductive film is formed, the conductive film must have heat resistance sufficient to withstand the heat treatment. It is preferable to have it.

[0097] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. a first electrode 515a that functions as a source electrode or a drain electrode through switching; After the second electrode 515b is formed, the resist mask is removed (FIG. 2(D)).

[0098] In the third photolithography process, ultraviolet light or KrF laser is used for exposure when forming the resist mask. The first electrodes adjacent to each other over the oxide semiconductor layer 513c may be irradiated with a laser beam or an ArF laser beam. The width of the gap between the bottom end of the first electrode and the bottom end of the second electrode determines the channel width of the transistor to be formed later. In addition, when performing exposure with a channel length L of less than 25 nm, the number n Extreme ultraviolet rays have extremely short wavelengths of 10 nm to several tens of nm. ) is used to perform exposure when forming a resist mask in the third photolithography process. Extreme ultraviolet light exposure provides high resolution and a large depth of focus. It is also possible to set the channel length L of the transistor to 10 nm or more and 1000 nm or less. The operating speed can be increased.

[0099] In order to reduce the number of photomasks and steps used in the photolithography process, The resist pattern is formed by a multi-tone mask, which is an exposure mask that allows the light to be projected at multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. This allows for multiple etching processes to be performed to create different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0100] Note that when the conductive film is etched, the oxide semiconductor layer 513c is etched and divided. It is desirable to optimize the etching conditions so that the conductive film does not become and the oxide semiconductor layer 513c is not etched at all. Therefore, the oxide semiconductor layer 513c is only partly etched during etching of the conductive film. In some cases, the oxide semiconductor layer 513c has a groove (a depression).

[0101] In this embodiment, a Ti film is used as the conductive film, and an In-Ga -Since a Zn-O-based oxide semiconductor film was used, in this combination, the etcher By using ammonia hydrogen peroxide (a mixture of ammonia, water, and hydrogen peroxide) as a solvent, This allows the conductive film to be etched more selectively.

[0102] Then, a plasma treatment is performed using a gas such as N2O, N2, or Ar to remove the exposed Water adsorbed on the surface of the oxide semiconductor layer may be removed by using oxygen and argon. In the case of plasma treatment, the mixed gas may be used. The insulating layer 507 is formed as a protective insulating film in contact with a part of the oxide semiconductor layer without being damaged. .

[0103] It is preferable that the insulating layer 507 contains as little impurities as possible, such as moisture, hydrogen, and oxygen. The insulating film may be a single insulating film, or may be made up of a plurality of laminated insulating films.

[0104] The insulating layer 507 has a thickness of at least 1 nm. The insulating layer 507 can be formed by using a method that does not mix impurities such as hydrogen. When hydrogen is contained in the oxide semiconductor layer, the hydrogen penetrates into the oxide semiconductor layer, or the hydrogen penetrates into the oxide semiconductor layer. Oxygen in the layer is extracted, and the back channel of the oxide semiconductor layer becomes low-resistance (N-type). Therefore, the insulating layer 507 should be as thin as possible. It is important that the deposition process does not use hydrogen, resulting in a hydrogen-free film.

[0105] In addition, it is preferable to use a material with high barrier properties for the insulating layer 507. As insulating films with high thermal conductivity, silicon nitride film, silicon oxynitride film, aluminum nitride film, and nitride An aluminum oxide film, an aluminum oxide film, a gallium oxide film, or the like can be used. By using an insulating film with a high barrier property, the island-shaped oxide semiconductor layer 513b and the gate In the insulating layer 502, or at the interface between the island-shaped oxide semiconductor layer 513b and another insulating layer, This can prevent impurities such as moisture or hydrogen from entering the vicinity.

[0106] The insulating layer 507 is made of a silicon oxide film, a silicon oxynitride film, or an aluminum oxynitride film. It is also possible to use an aluminum film.

[0107] For example, a gallium oxide film having a thickness of 200 nm is formed by sputtering. The insulating film has a structure in which aluminum oxide films with a thickness of 100 nm are laminated. The substrate temperature during the film formation may be set to be equal to or higher than room temperature and equal to or lower than 300° C. It is preferable that the oxygen content is high, exceeding the stoichiometric ratio, preferably It is preferable that the oxygen content is more than 1 to 2 times the stoichiometric ratio. When the insulating film contains excess oxygen, the oxide semiconductor layer 513b It is possible to supply oxygen to the interface and reduce oxygen deficiencies.

[0108] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed as the insulating layer 507 by sputtering. The substrate temperature during film formation should be between room temperature and 300°C. In the embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas ( Typically, under an argon atmosphere, oxygen atmosphere, or a mixture of rare gas and oxygen atmosphere. The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an atmosphere containing oxygen. A silicon oxide film can be formed by sputtering in air.

[0109] In the same manner as in the formation of the oxide semiconductor film, in order to remove residual moisture in the deposition chamber of the insulating layer 507, It is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating layer 507 formed in the deposition chamber evacuated by using a vacuum can be reduced. In addition, a turbo exhaust was used as an exhaust means for removing residual moisture in the deposition chamber for the insulating layer 507. A cold trap may be added to the pump.

[0110] The sputtering gas used in forming the insulating layer 507 is hydrogen, water, a hydroxyl group, a hydride, or the like. It is preferable to use a high-purity gas from which impurities have been removed.

[0111] Next, a second heat treatment (oxide semiconductor When the layer is formed in two separate steps and the heat treatment is performed in two separate steps, a third heat treatment is performed. The heat treatment may be performed in nitrogen, ultra-dry air, or rare gas (argon, helium, etc.). The reaction is carried out in an atmosphere of 200° C. or more and 400° C. or less. The content is 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less. It is preferable to perform RTA treatment at a high temperature for a short time in the same manner as the first heat treatment. After the insulating layer 507 containing the insulating material is provided, heat treatment is performed. Therefore, even if oxygen vacancies occur in the oxide semiconductor layer 513c, the oxygen is not transferred from the insulating layer 507 to the oxide semiconductor layer 513c. Then, oxygen is supplied to the oxide semiconductor layer 513c. By providing oxygen to the oxide semiconductor layer 513c, oxygen vacancies serving as donors are reduced and the oxide semiconductor layer 513c is oxidized. As a result, the oxide semiconductor layer 513c can be made closer to i-type. This reduces the variation in the electrical characteristics of the transistors due to oxygen vacancies, and improves the electrical characteristics. The timing of the second heat treatment is set to the time when the insulating layer 507 is heated. There are no particular limitations as long as it is after formation, and other processes, such as heat treatment during resin film formation and light transmission, may be performed. By combining this with a heat treatment for reducing the resistance of the conductive film, the number of steps can be reduced. In this way, the oxide semiconductor layer 513c can become closer to i-type.

[0112] In addition, the oxide semiconductor layer 513c is subjected to heat treatment in an oxygen atmosphere. Even if oxygen is added to reduce oxygen vacancies serving as donors in the oxide semiconductor layer 513c, The temperature of the heat treatment is, for example, 100° C. or higher and lower than 350° C., preferably 150° C. or higher and lower than 2 The temperature is less than 50°C. The oxygen gas used in the heat treatment in the oxygen atmosphere does not contain water, hydrogen, etc. It is preferable that the purity of the oxygen gas introduced into the heat treatment device is 6 or less. N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. oxygen It is preferable to keep the impurity concentration in the catalyst to 1 ppm or less, and preferably 0.1 ppm or less.

[0113] In this embodiment, the second heat treatment is preferably performed in an inert gas atmosphere or an oxygen gas atmosphere. Preferably, the temperature is 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0114] The second heat treatment has the following effect. Impurities such as hydrogen, water, hydroxyl groups, and hydrides (also called hydrogen compounds) are intentionally removed from the However, there are cases where oxygen, one of the main components of oxide semiconductors, is reduced. The second heat treatment is performed in order to supply oxygen to the oxide semiconductor layer that has been subjected to the first heat treatment. Therefore, the oxide semiconductor layer is highly purified and becomes electrically i-type (intrinsic).

[0115] As described above, fluorine is added to the oxide semiconductor film, and the first heat treatment is performed after the addition of fluorine. By going through the process of carrying out the above, hydrogen, moisture, hydroxyl groups, or hydrides (also called hydrogen compounds) are eliminated. ) can be intentionally removed from the oxide semiconductor layer. The conductor layer is highly purified and electrically I-type (intrinsic) or substantially I-type. A transistor 550 is formed.

[0116] In the transistor of this embodiment, a halogen element may be contained in an oxide semiconductor layer. The halogen elements in the compound semiconductor layer easily bond with the dangling bonds of the metal atoms and terminate the dangling bonds. For example, the oxide semiconductor layer Fluorine is 10 15 atoms / cm 3 Over 10 18 atoms / cm 3 At the following concentration: It may contain.

[0117] In addition, when a silicon oxide layer containing many defects is used for the insulating layer 507, The second heat treatment is performed to convert impurities such as hydrogen and water contained in the oxide semiconductor layer into silicon oxide. The impurities contained in the oxide semiconductor layer are diffused into the silicon layer, and the impurities are effectively reduced. .

[0118] In addition, when a silicon oxide layer containing excess oxygen is used for the insulating layer 507, By this heat treatment, oxygen in the insulating layer 507 moves to the oxide semiconductor layer 513b, and the oxide semiconductor This has the effect of improving the oxygen concentration in the conductor layer 513b and achieving high purity.

[0119] A protective insulating layer 508 may be further formed on the insulating layer 507. For example, The RF sputtering method is suitable for mass production and is therefore preferred as a method for forming a protective insulating layer. The protective insulating layer does not contain impurities such as moisture and prevents them from entering from the outside. An inorganic insulating film is used to lock the film, and a silicon nitride film, an aluminum nitride film, etc. are used. In this embodiment, the protective insulating layer 508 is formed using a silicon nitride film (FIG. 2(E)).

[0120] In this embodiment, the substrate 500 on which the insulating layer 507 is formed is used as the protective insulating layer 508. It contains high-purity nitrogen that has been heated to a temperature between 100℃ and 400℃ and has had hydrogen and moisture removed. A sputtering gas is introduced and a silicon nitride film is formed using a silicon semiconductor target. In this case, similarly to the insulating layer 507, the protective insulating layer 507 is formed while removing the residual moisture in the processing chamber. Preferably, layer 508 is deposited.

[0121] After the protective insulation layer is formed, it is further heated in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed at a constant heating temperature. In addition, the temperature is increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then decreased from the heating temperature to room temperature. The temperature drop at 0.5° C. may be repeated several times.

[0122] In this manner, the transistor including the highly purified oxide semiconductor layer manufactured according to this embodiment The transistor has a small variation in threshold voltage. By applying the manufacturing method, a highly reliable semiconductor device can be provided. It is possible to provide a semiconductor device having a high

[0123] In addition, since the off-current can be reduced, a semiconductor device with low power consumption can be provided.

[0124] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0125] (Embodiment 2) In this embodiment, fluorine is added to the oxide semiconductor layer and then heat treatment is performed to remove impurities. A top-gate transistor is fabricated by using a method for purifying an oxide semiconductor layer by removing the oxide semiconductor layer. The manufacturing method will be described with reference to FIGS.

[0126] The structure of a top-gate transistor 650 manufactured in this embodiment is shown in FIG. FIG. 3A shows a top view of a transistor 650, and FIG. 3B shows a cross-sectional view of the transistor 650. FIG. 3(B) corresponds to a cross-sectional view taken along line Q1-Q2 in FIG. 3(A).

[0127] The transistor 650 is formed on a substrate 600 having an insulating surface. The first electrode 615a and the second electrode 615b function as electrodes. A highly purified oxide semiconductor layer 613c covers the ends of the first electrode 615a and the second electrode 615b. and a gate insulating layer 602 covering the oxide semiconductor layer 613c. A gate electrode that contacts 602 and overlaps the ends of the first electrode 615a and the second electrode 615b. 611 and a protective insulating layer 608 that is in contact with the gate electrode and covers the transistor 650 .

[0128] Next, a method for manufacturing a transistor 650 on a substrate 600 will be described with reference to FIGS. ) will be used to explain.

[0129] First, a source electrode and a drain electrode (which are formed in the same layer) are formed on a substrate 600 having an insulating surface. A conductive film is formed to be used for the source electrode and the drain electrode. The conductive film is, for example, a film selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Metal films containing the elements, or metal nitride films containing the above elements (titanium nitride film, nitride Molybdenum film, tungsten nitride film, etc. can be used. The metal film is coated with high-molecular-weight metals such as Ti, Mo, W, Cr, Ta, Nd, Sc, and Y on either or both of the top and bottom of the film. Melting point metal film or metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) In particular, a titanium film may be stacked on the side in contact with the oxide semiconductor layer. It is preferable to provide a conductive film containing

[0130] A resist mask is formed on the conductive film by a first photolithography process, and selective etching is performed. a first electrode 615a that functions as a source electrode or a drain electrode through switching; A second electrode 615b is formed, and the resist mask is removed.

[0131] In this embodiment mode, a glass substrate is used as the substrate 600 having an insulating surface.

[0132] An insulating film serving as a base film is provided between the first electrode 615a and the substrate 600, and between the second electrode 615b and the substrate 600. The base film has a function of preventing diffusion of impurity elements from the substrate 600. A single layer of silicon oxide, silicon oxide, silicon nitride oxide, or silicon oxynitride is used. Alternatively, it may be formed by laminating.

[0133] Then, a first electrode 615a serving as a source electrode or a drain electrode, and a second On the electrode 615b, a film thickness of 2 nm to 200 nm, preferably 5 nm to 30 nm, is formed. An oxide semiconductor film is formed.

[0134] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced. Reverse sputtering is performed to generate plasma, and the surfaces of the first electrode 615a and the second electrode 615b are Powdery substances (particles, dust, etc.) adhering to the insulating surface of the substrate 600 and the exposed insulating surface of the substrate 600 It is preferable to remove the

[0135] The oxide semiconductor film described in this embodiment is similar to the oxide semiconductor film described in Embodiment 1. Specifically, the oxide semiconductor film can be formed by using the above-mentioned materials, method, and conditions. The oxide semiconductor used, the deposition method, the target composition, the target filling rate, and the purity of the sputtering gas temperature, substrate temperature during film formation, exhaust means of the sputtering device, and composition of the sputtering gas. Therefore, for details, the description of the first embodiment can be referred to. do.

[0136] Next, the oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 6 Process into 13a.

[0137] Note that the etching of the oxide semiconductor film here may be performed by dry etching or wet etching. For example, a wet etching method for an oxide semiconductor film may be used. The etching solution that can be used is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used. ) as shown in

[0138] Next, fluorine is added to the oxide semiconductor layer 613a in the same manner as in Embodiment 1. The materials, methods, and conditions described in the first embodiment can be used. By adding fluorine to the oxide semiconductor layer 613a, For example, the bond between the metal and hydrogen that constitutes an oxide semiconductor, or the oxygen of a hydroxyl group that bonds with a metal The bond between the metal and hydrogen or the bond between the metal and a hydroxyl group can be broken. The oxide semiconductor layer 613a becomes the oxide semiconductor layer 613b containing impurities released from the metal (FIG. 4B). ).

[0139] As in Embodiment 1, preheat treatment is performed before fluorine is added to the oxide semiconductor layer 613a. You can go.

[0140] Next, a first heat treatment is performed on the oxide semiconductor layer 613b containing the impurities released from the metal. (FIG. 4C) The first heat treatment is performed by the same method and under the same conditions as those in the first embodiment. Therefore, for details, the description of the first embodiment can be referred to. By the first heat treatment, impurities released from the metal can be removed from the oxide semiconductor layer 613b. For example, the fluorine that is added reacts with the hydrogen and hydroxyl groups that are released from the metal to produce fluorine. Hydrogen ions, etc. can be removed. Hydrogen that is tightly bound to metals can be removed without adding halogen elements. In contrast to the method of directly removing hydroxyl groups, the generated hydrogen fluoride and other substances can be removed by heating. The method is easy.

[0141] Further, fluorine may be added before the oxide semiconductor film is processed into an island shape. The first heat treatment may be performed before or after the second photolithography step. stomach.

[0142] Note that the first heat treatment is performed after fluorine is added and before another layer is formed over the oxide semiconductor layer. However, other than the above, it is also possible to carry out the treatment after adding fluorine to the oxide semiconductor layer. After laminating a gate insulating layer on the gate insulating layer, or after forming a gate electrode on the gate insulating layer, Either method may be used.

[0143] In addition, the oxide semiconductor layer is formed in two separate steps and heat treatment is performed in two separate steps. The material of the base member that comes into contact with the oxide semiconductor layer formed for this purpose is a material such as oxide, nitride, or metal. Regardless of the thickness, the crystallographic region (non-single crystal region) with a thick film thickness, i.e., the crystallographic region with the c-axis oriented perpendicular to the film surface, An oxide semiconductor layer having a crystalline region may be formed. The deposition conditions shown in the embodiment mode 1 can be used for the layers. The description of embodiment 1 may be taken into consideration.

[0144] Then, a plasma treatment is performed using a gas such as N2O, N2, or Ar to remove the exposed In addition, adsorbed water or the like attached to the surface of the oxide semiconductor layer may be removed by the plasma treatment. Thereafter, a gate insulating layer 602 is formed in contact with the oxide semiconductor layer without exposure to air.

[0145] The oxide semiconductor of this embodiment is an i-type or substantially i-type oxide semiconductor from which impurities have been removed. Such a highly purified oxide semiconductor has a low interface state density and a low interface The interface between the oxide semiconductor layer and the gate insulating layer is important because it is extremely sensitive to surface charges. Therefore, the gate insulating layer in contact with the highly purified oxide semiconductor layer must be of high quality. will be done.

[0146] The gate insulating layer 602 has a thickness of at least 1 nm and is formed by a gate insulating method such as sputtering. The layer 602 can be formed by appropriately using a method that does not allow impurities such as water and hydrogen to be mixed into the layer 602 . When hydrogen is contained in the gate insulating layer 602, the hydrogen may enter the oxide semiconductor layer or the gate insulating layer 602 may be damaged. This causes oxygen to be extracted from the oxide semiconductor layer, resulting in a decrease in the resistance of the channel of the oxide semiconductor layer. Therefore, the gate insulating layer may become N-type and a parasitic channel may be formed. In order to obtain a film that contains as little hydrogen as possible, it is important not to use hydrogen in the film formation method. It is essential.

[0147] In this embodiment, a silicon oxide film is formed as the gate insulating layer 602 by a sputtering method. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. The temperature is set to 100°C. The silicon oxide film is formed by sputtering using a rare gas (typically argon). The test should be performed under an atmosphere of rare gas, oxygen, or a mixture of rare gas and oxygen. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used to perform spat deposition in an atmosphere containing oxygen. A silicon oxide film can be formed in contact with the oxide semiconductor layer by a deposition method. The gate insulating layer 602 does not contain impurities such as moisture and hydrogen, and is therefore protected from intrusion by these impurities from the outside. An inorganic insulating film that blocks the intrusion of silicon is used, typically a silicon oxide film or a silicon oxynitride film. A film made of aluminum, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0148] In the same manner as in the formation of the oxide semiconductor film, moisture remaining in the deposition chamber for the gate insulating layer 602 is removed. For this purpose, it is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the gate insulating layer 602 formed in a film formation chamber evacuated using an opamp In addition, the amount of water remaining in the deposition chamber of the gate insulating layer 602 can be reduced. The stage may be a turbo pump plus a cold trap.

[0149] The sputtering gas used in forming the gate insulating layer 602 is hydrogen, water, a hydroxyl group, or a hydrogenated It is preferable to use a high-purity gas from which impurities such as ions have been removed. The diagram is shown in FIG.

[0150] Next, when a contact hole is formed in the gate insulating layer 602, a third photolithography is performed. A contact hole is formed in the gate insulating layer 602 by a contact hole forming process. The cut holes are not shown.

[0151] Next, a conductive film is formed over the gate insulating layer 602, and then a fourth photolithography process is performed. A wiring layer including a gate electrode 611 is formed.

[0152] The gate electrode 611 is made of molybdenum, titanium, tantalum, tungsten, or aluminum. The material is made of metals such as aluminum, copper, neodymium, scandium, etc., or alloys made of these materials as the main components. Through the above steps, the transistor 650 is formed. will be done.

[0153] In the transistor of this embodiment, a halogen element may be contained in an oxide semiconductor layer. The halogen elements in the compound semiconductor layer easily bond with the dangling bonds of the metal atoms and terminate the dangling bonds. Therefore, the formation of carriers can be suppressed.

[0154] A protective insulating layer 608 may be formed on the gate electrode 611. For example, the protective insulating layer 608 may be formed by using an RF sputtering method. The RF sputtering method is suitable for mass production and is therefore preferred as a method for forming the protective insulating layer. The protective insulation layer does not contain impurities such as moisture and prevents them from entering from the outside. In this embodiment, an inorganic insulating film such as a silicon nitride film or an aluminum nitride film is used. In this embodiment, the protective insulating layer 608 is formed using a silicon nitride film. A cross-sectional view is shown in FIG.

[0155] In this embodiment, the protective insulating layer 608 is a substrate 600 on which a gate electrode 611 is formed. The mixture is heated to a temperature of 100°C to 400°C, and hydrogen and moisture are removed. A sputtering gas containing silicon is introduced, and a silicon nitride film is formed using a silicon semiconductor target. In this case, the remaining moisture in the treatment chamber is removed in the same manner as for the gate insulating layer 602. It is preferable to deposit a protective insulating layer 608 .

[0156] After the protective insulation layer is formed, it is further heated in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed at a constant heating temperature. In addition, the temperature is increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then decreased from the heating temperature to room temperature. The temperature drop at 0.5° C. may be repeated several times.

[0157] In this manner, the transistor including the highly purified oxide semiconductor layer manufactured according to this embodiment The transistor has a small variation in threshold voltage. By applying the manufacturing method, a highly reliable semiconductor device can be provided. It is possible to provide a semiconductor device having a high

[0158] In addition, since the off-current can be reduced, a semiconductor device with low power consumption can be provided.

[0159] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0160] (Embodiment 3) In this embodiment, fluorine is added to the oxide semiconductor layer and then heat treatment is performed to remove impurities. In the present embodiment, a method different from that in the first embodiment is used to purify the oxide semiconductor layer by removing the oxide semiconductor layer. A method for manufacturing a gate-type transistor will be described with reference to FIGS.

[0161] A structure of a bottom-gate transistor 1050 manufactured in this embodiment mode is shown in FIG. FIG. 10A is a top view of the transistor 1050, and FIG. 10B is a top view of the transistor 1050. 10(B) is a cross-sectional view taken along the line R1-R2 shown in FIG. This corresponds to a surface view.

[0162] The transistor 1050 includes a gate electrode 1011 and a gate insulating film 1021 formed on a substrate 1000 having an insulating surface. The gate insulating layer 1002 covers the gate electrode 1011. A highly purified oxide semiconductor layer 1013d overlapping with the gate electrode 1011 and an oxide semiconductor layer 1013e ​​are formed on the gate electrode 1012. A source electrode or a gate electrode It has a first electrode 1015a which functions as a drain electrode and a second electrode 1015b. In addition, an insulating layer 1007 which is in contact with the oxide semiconductor layer and overlaps with a channel formation region of the oxide semiconductor layer and a transistor It has a protective insulating layer 1008 covering the transistor 1050 .

[0163] Next, a method for manufacturing a transistor 1050 over a substrate 1000 will be described with reference to FIG. This will be explained with reference to FIGS. 11A to 11C and 12A to 12C.

[0164] First, a conductive film is formed on a substrate 1000 having an insulating surface, and then a first photolithography process is performed. A wiring layer including a gate electrode 1011 is formed by a bonding process, and a gate electrode 1011 is formed on the gate electrode 1011. The gate electrode 1011 and the gate insulating layer 1002 are respectively The gate electrode 511 and the gate insulating layer 502 are formed in the same manner and under the same conditions as those in the first embodiment. Therefore, for details, the description of the first embodiment can be referred to. can.

[0165] Next, a film having a thickness of 2 nm to 200 nm, preferably 3 nm, is formed on the gate insulating layer 1002. An oxide semiconductor film having a thickness of 50 nm or more and a thickness of 50 nm or less is formed, and the oxide semiconductor film is subjected to a second photolithography. The oxide semiconductor layer 1013a is then processed into an island shape by a film forming process (FIG. 11A). The oxide semiconductor layer 1013a shown in this embodiment is the same as the oxide semiconductor layer 51 described in Embodiment 1. It can be formed using the same materials, methods, and conditions as those in 3a. For this information, the description in embodiment 1 can be referred to.

[0166] Next, fluorine is added to the oxide semiconductor layer 1013a. Similar materials, methods, and conditions can be used. Therefore, details are given in the embodiments. The description of the first embodiment can be referred to. For example, the bond between the metal and hydrogen that constitutes the oxide semiconductor, or the hydroxyl group that bonds with the metal It can break the bond between oxygen and hydrogen in the oxide or between metal and hydroxyl groups. The semiconductor layer 1013a becomes an oxide semiconductor layer 1013b containing impurities released from the metal. (Figure 11(B)).

[0167] As in Embodiment 1, a preliminary heat treatment is performed before fluorine is added to the oxide semiconductor layer 1013a. may also be carried out.

[0168] Next, a first heat treatment is performed on the oxide semiconductor layer 1013b including the impurities released from the metal. The first heat treatment is performed as described in the embodiment. The same method and conditions as those in Example 1 can be used. Therefore, for details, see the embodiment The description of 1 can be taken into consideration. The impurities that are removed from the metal by this first heat treatment The material can be removed from the oxide semiconductor layer 1013b.

[0169] Next, oxygen is added to the oxide semiconductor layer 1013c to obtain an oxide semiconductor layer 1013d (FIG. 12(A)). The method of adding oxygen is to use high-energy oxygen ion implantation or ion implantation. The doping method may be used to add the element.

[0170] When oxygen gas is used to add oxygen by ion implantation, the acceleration voltage should be set to 5 keV or higher and 10 0 keV or less, oxygen ion implantation dose of 1×10 14 [atoms / cm 2 ] or more 5×10 17 [atoms / cm 2 ] or less.

[0171] High-energy oxygen is injected into an oxide semiconductor using ion implantation or ion doping. By adding oxygen to the oxide semiconductor, oxygen, which is the main component of the oxide semiconductor, can be supplied. do.

[0172] After oxygen is added, the oxide semiconductor layer may be subjected to second heat treatment. By the heat treatment in step S2, impurities released from the metal can be removed from the oxide semiconductor layer. For example, The water generated by the reaction of the added oxygen with the hydrogen and hydroxyl groups released from the metal can be removed. Compared with the method of directly removing hydrogen or hydroxyl groups that are tightly bound to metals, the water produced is heated to remove The method of removing the fluorine-containing oxide is easy. The impurities are removed by the addition of oxygen and the second heat treatment, so that the oxide semiconductor layer can be further purified and electrically converted to I-type (intrinsic) or substantially I-type. .

[0173] In addition, the oxide semiconductor layer is formed in two separate steps and heat treatment is performed in two separate steps. The material of the base member that comes into contact with the oxide semiconductor layer formed for this purpose is a material such as oxide, nitride, or metal. Regardless of the thickness, the crystallographic region (non-single crystal region) with a thick film thickness, i.e., the crystallographic region with the c-axis oriented perpendicular to the film surface, For example, an oxide semiconductor layer having a crystal region with a thickness of 3 nm to 15 nm may be formed. The oxide semiconductor film of 1 is formed, the first fluorine is added, and nitrogen, oxygen, a rare gas, or dry In a dry air atmosphere, the temperature is 450°C to 850°C, preferably 550°C to 750°C. A first heat treatment is performed to obtain a first oxide having a crystalline region (including plate-like crystals) in a region including a surface. Then, a second oxide semiconductor film that is thicker than the first oxide semiconductor film is formed. A film is formed, a second fluorine addition is performed, and the film is heated at 450° C. to 850° C., preferably 600° C. A second heat treatment is performed at a temperature of 700° C. or lower, and the first oxide semiconductor film is used as a seed for crystal growth. Then, the second oxide semiconductor film is entirely crystallized, and the thickness of the second oxide semiconductor film is increased. In the second oxide semiconductor layer, an oxide semiconductor layer having a crystal region is formed, and oxygen is added to the oxide semiconductor layer. The oxygen addition may be performed before the formation of the semiconductor film. When fluorine is added to the first oxide semiconductor film, the crystal region of the first oxide semiconductor film is reduced. Therefore, in the second fluorine addition, the first oxide semiconductor It is necessary to select appropriate conditions (accelerating voltage, etc.) so that fluorine is not added to the film.

[0174] Next, a source electrode and a drain electrode are formed on the gate insulating layer 1002 and the oxide semiconductor layer 1013d. A conductive film is formed to become a drain electrode (including wiring formed in the same layer). A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. A first electrode 1015a that functions as a source electrode or a drain electrode by performing switching; After the first electrode 1015b is formed, the resist mask is removed (FIG. 12(B)). The first electrode 1015a and the second electrode 1015b are the same as those shown in the first embodiment. The same method and conditions can be used for the first electrode 515a and the second electrode 515b. For details, please refer to the description in embodiment 1.

[0175] Next, the insulating layer 100 is formed using the same method and material as the insulating layer 507 shown in the first embodiment. Form 7.

[0176] Next, a second heat treatment (oxide semiconductor When the layer is formed in two separate steps and the heat treatment is performed in two separate steps, a third heat treatment is performed. The heat treatment may be performed at a temperature of 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. When the heat treatment is performed, part of the oxide semiconductor layer is heated in a state of being in contact with the insulating layer 1007.

[0177] As described above, fluorine is added to the oxide semiconductor film, and the first heat treatment is performed after the addition of fluorine. By going through the process of carrying out the above, hydrogen, moisture, hydroxyl groups, or hydrides (also called hydrogen compounds) are eliminated. ) can be intentionally removed from the oxide semiconductor layer. It is one of the main components of the oxide semiconductor layer, which is formed by adding oxygen to the conductive film. Therefore, the oxide semiconductor layer can be highly purified and electrically i-type ( Through the above steps, the transistor 1050 is formed.

[0178] In the transistor of this embodiment, a halogen element may be contained in an oxide semiconductor layer. The halogen elements in the compound semiconductor layer easily bond with the dangling bonds of the metal atoms and terminate the dangling bonds. Therefore, the formation of carriers can be suppressed.

[0179] In addition, when a silicon oxide layer containing many defects is used as the insulating layer 1007, the silicon oxide layer formation Impurities such as hydrogen, water, or hydride contained in the oxide semiconductor layer are removed by a subsequent heat treatment. The effect of diffusing the impurities into the silicon oxide layer and further reducing the impurities contained in the oxide semiconductor layer It plays a major role.

[0180] A protective insulating layer 1008 may be further formed on the insulating layer 1007. The protective insulating layer 1008 is The same materials and methods as those for the protective insulating layer 508 described in Embodiment 1 can be used for this layer. For details, the description in Embodiment 1 can be referred to. A protective insulating layer 1008 is formed using a silicon nitride film (FIG. 12C).

[0181] In this manner, the transistor including the highly purified oxide semiconductor layer manufactured according to this embodiment The transistor has a small variation in threshold voltage. By applying the manufacturing method, a highly reliable semiconductor device can be provided. It is possible to provide a semiconductor device having a high

[0182] In addition, since the off-current can be reduced, a semiconductor device with low power consumption can be provided.

[0183] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0184] (Embodiment 4) In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS. 9. Note that the semiconductor device described in this embodiment is a It can be used as such.

[0185] The structure of a semiconductor device exemplified in this embodiment is shown in FIG. 5. A cross-sectional view of the semiconductor device is shown in FIG. ) and a top view of the semiconductor device is shown in FIG. 5(B). Note that FIG. 5(A) shows the 11 corresponds to a cross-sectional view taken along the cutting lines A1-A2 and B1-B2.

[0186] The semiconductor device shown in the example has a transistor 260 using a first semiconductor material in the lower part, A transistor 262 using a second semiconductor material and a capacitor 264 are provided in the transistor 262. The gate electrode 210 of the transistor 260 is directly connected to the first electrode 242a of the transistor 262. is connected.

[0187] The transistor 262 and the capacitor 264 are provided overlapping the transistor 260. For example, by devising the connection relationship with wiring and electrodes, Let F be the small processing dimension, and the area occupied by the memory cell be 15F 2 ~25F 2 It is also possible to It is.

[0188] The transistor 260 has a first semiconductor material and the transistor 262 has a second semiconductor material. For example, a single crystal semiconductor may be used as the first semiconductor material. The transistor 260 is designed to operate at high speed, and an oxide semiconductor is used as the second semiconductor material. By using the transistor 262, the off-state current is sufficiently reduced and charge can be held for a long time. It can be said that:

[0189] The first semiconductor material or the second semiconductor material may be, for example, an oxide semiconductor or an oxide Semiconductor materials other than oxide semiconductors may be used. For example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide. Also, organic semiconductor materials can be used.

[0190] In this embodiment, a transistor capable of high-speed operation is manufactured by using single crystal silicon as the first semiconductor material. The transistor 260 is configured by using an oxide semiconductor as the second semiconductor material, and the off-current is low. The configuration of the reduced transistor 262 will now be described.

[0191] The gate electrode 210 of the transistor 260 and the first electrode 24 of the transistor 262 The semiconductor device having the structure in which the transistor 262 is connected is suitable as a memory device. By turning off the transistor 260, the potential of the gate electrode 210 of the transistor 260 is maintained for an extremely long time. In addition, by providing the capacitance element 264, This makes it easier to hold the charge applied to the gate electrode 210 of the transistor 260, and the held information In addition, the transistor 2 made of semiconductor material capable of high-speed operation is By using 60, information can be read out at high speed.

[0192] Note that all of the transistors included in the semiconductor device exemplified in this embodiment are n-channel However, p-channel transistors may also be used. Needless to say, the technical essence of the disclosed invention is that the off-current is sufficiently low. A transistor using an oxide semiconductor and a transistor using an oxide semiconductor capable of sufficiently high speed operation The advantage of this is that it is integrated with a transistor made of a material other than silicon. The specific configuration of the semiconductor device, such as the materials used and the structure of the semiconductor device, is not limited to those shown here. There is no need to.

[0193] The transistor 260 has a channel forming region provided in a substrate 200 including a first semiconductor material. The impurity regions 220 sandwich the channel forming region 216. A metal compound region 224 in contact with the region 220 and a gate electrode 225 formed on the channel forming region 216 are The semiconductor device has a gate insulating layer 208 and a gate electrode 210 provided on the gate insulating layer 208. In the drawings, the source electrode and the drain electrode may not be explicitly shown. This state may also be called a transistor. In order to explain the connection relationship, the source electrode and drain electrode, including the source region and drain region, In other words, in the present specification, the description of the source electrode includes the source region, and reference to a drain electrode may include a drain region.

[0194] In addition, an element isolation insulating layer 206 is provided on the substrate 200 so as to surround the transistor 260. An insulating layer 228 and an insulating layer 230 are provided over the transistor 260. Although not shown, a part of the metal compound region 224 of the transistor 260 is a source electrode or a drain electrode. It is connected to the wiring 256 or other wiring via an electrode that functions as a pin electrode. In the drawings, the source electrode and the drain electrode may not be explicitly shown. Such a configuration may also be called a transistor.

[0195] In order to achieve high integration, the transistor 260 is provided with sidewall insulation as shown in FIG. On the other hand, if the characteristics of the transistor 260 are important, In this case, a sidewall insulating layer is provided on the side surface of the gate electrode 210, and the sidewall The impurity concentration of the impurity region 220 is different from that of the impurity region 220 formed in the region overlapping the insulating layer. An impurity region 220 may be provided.

[0196] In this embodiment, the substrate 200 containing the first semiconductor material is a silicon single crystal substrate. When a single crystal semiconductor substrate such as silicon is used, the read operation of the semiconductor device is This can speed up the work.

[0197] The transistor 262 includes a purified oxide semiconductor layer as a second semiconductor material. The transistor 262 has a gate insulating layer 230 on which a source electrode or a drain electrode functions. A first electrode 242a and a second electrode 242b are electrically connected to the first electrode and the second electrode. The oxide semiconductor layer 244 is connected to the gate insulating film 241. A gate electrode 248 is formed on the gate insulating layer 246 and overlaps with the oxide semiconductor layer 244. In addition, a gate electrode 248 is provided between the first electrode 242a and the oxide semiconductor layer 244. a, and a gate electrode between the second electrode 242b and the oxide semiconductor layer 244. The insulating layer 243b overlaps the bottom electrode 248a.

[0198] The insulating layer 243a and the insulating layer 243b are formed between the source electrode or the drain electrode and the gate electrode. However, the structure in which the insulating layer 243a and the insulating layer 243b are not provided reduces the capacitance generated between the insulating layer 243a and the insulating layer 243b. It is also possible to make it.

[0199] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 244, so that the oxide semiconductor layer 244 has a high purity. Specifically, for example, the oxide semiconductor layer 244 is preferably hydrated. The concentration of the element is 5×10 19 atoms / cm 3 Less than 5×10 18 atoms / c m 3 Less than or equal to 5×10 17 atoms / cm 3 The above-mentioned acids are as follows. The hydrogen concentration in the compound semiconductor layer 244 was measured by secondary ion mass spectrometry (SIMS). This is measured by the ion mass spectroscopy (IMMS). As shown above, the hydrogen concentration is sufficiently reduced and highly purified, and sufficient oxygen is supplied to prevent oxygen deficiency. In the oxide semiconductor layer 244 in which the defect levels in the energy gap caused by the above-mentioned are reduced, hydrogen and The carrier concentration due to oxygen vacancies is 1×10 12 / cm 3 Less than 1×10 11 / cm 3Less than 1.45×10 10 / cm 3 It will be less than.

[0200] In the transistor including the oxide semiconductor layer 244, the off-state current can be sufficiently reduced. For example, when the oxide semiconductor layer 244 has a thickness of 30 nm and the channel length is 2 μm, The off-state current (gate bias) per 1 μm of channel length at room temperature (25°C) -3V) is 100zA (1zA (zeptoampere) is 1×10 -21 A) The following is desirable: will be less than 10zA.

[0201] In this embodiment, fluorine is added to the oxide semiconductor layer and then heat treatment is performed to remove impurities. A highly purified oxide semiconductor layer is formed by applying a method for purifying an oxide semiconductor by removing the oxide. In this way, by using a highly purified oxide semiconductor, an extremely excellent off-current A transistor 262 having the above characteristics can be obtained. For this matter, embodiment 2 may be referred to.

[0202] In addition, in the transistor 262 of FIG. 5, in order to suppress leakage current occurring between elements due to miniaturization, In order to achieve this, the oxide semiconductor layer 244 is processed into an island shape. In the case where the oxide semiconductor layer is not processed into an island shape, This can prevent contamination of the oxide semiconductor layer 244 due to etching.

[0203] In the semiconductor device illustrated in FIG. 5, the upper surface of the gate electrode 210 of the transistor 260 is an insulating layer 2 28 and functioning as a source or drain electrode of transistor 262. The gate electrode 210 and the first electrode 242a are directly connected to each other. Although it is possible to connect the electrodes by using openings and electrodes for contacts, a direct connection structure is preferred. This makes it possible to reduce the contact area and achieve a high degree of integration of the semiconductor device.

[0204] For example, when the semiconductor device of this embodiment is used as a memory device, the memory capacity per unit area is High integration is important to increase the capacity. Also, the contacts are formed separately. The process for fabricating a semiconductor device can be simplified because the process required for forming openings and electrodes can be omitted. It is possible.

[0205] The capacitor 264 in FIG. 5 has a first electrode functioning as a source electrode or a drain electrode. The electrode 242a, the oxide semiconductor layer 244, the gate insulating layer 246, and the electrode 248b are included. That is, the first electrode 242a functions as one electrode of the capacitor 264. The electrode 248 b functions as the other electrode of the capacitor 264 .

[0206] Note that the capacitor 264 illustrated in FIG. 5 has an oxide film between the first electrode 242a and the electrode 248b. The semiconductor layer 244 and the gate insulating layer 246 are sandwiched between the semiconductor layer 244 and the gate insulating layer 246. Alternatively, the insulating layer 243a may be formed by sandwiching only the insulating layer 243b. Furthermore, if capacitance is not required, the capacitance element 26 may be It is also possible to adopt a configuration in which no. 4 is provided.

[0207] In addition, an insulating layer 250 is provided over the transistor 262 and the capacitor 264. An insulating layer 252 is provided on the gate insulating layer 246, the insulating layer 250, and the insulating An electrode 254 is provided in an opening formed in the insulating layer 252. A wiring 256 is provided on the upper surface of the substrate 241 and is electrically connected to the second electrode 242b via the electrode 254. The wiring 256 may be directly in contact with the second electrode 242b.

[0208] An electrode (not shown) connected to the metal compound region 224 and the second electrode 242b are connected to each other. In this case, the electrode connected to the metal compound region 224 and the electrode 254 are arranged so as to overlap each other. By placing the semiconductor device in this manner, a high degree of integration can be achieved.

[0209] <Method for Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the above semiconductor device will be described. A method for fabricating the transistor 260 will be described with reference to FIGS. 6 and 7. A method for manufacturing the transistor 262 and the capacitor 264 will be described with reference to FIGS. do.

[0210] <Method of manufacturing the lower transistor> First, a substrate 200 containing a semiconductor material is prepared (FIG. 6(A)). Examples of the 00 include single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, and silicon Compound semiconductor substrates such as silicon-on-germanium, SOI substrates, etc. can be used. An example in which a single crystal silicon substrate is used as the substrate 200 containing a semiconductor material will be described. vinegar.

[0211] Generally, an "SOI substrate" is a substrate that has a silicon semiconductor layer on an insulating surface. However, in this specification and the like, a semiconductor layer made of a material other than silicon on an insulating surface is In other words, the semiconductor layer of the "SOI substrate" is The SOI substrate is not limited to a silicon semiconductor layer. In addition, the SOI substrate has a layer on an insulating substrate such as a glass substrate. The term also includes a structure in which a semiconductor layer is provided on the insulating layer.

[0212] In particular, when a single crystal semiconductor substrate such as silicon is used as the substrate 200 containing a semiconductor material, In this case, it is preferable because the operation speed of the transistor 260 can be increased.

[0213] A protective layer 202 is formed on a substrate 200 to serve as a mask for forming an element isolation insulating layer. (FIG. 6(A)). The protective layer 202 is made of, for example, silicon oxide, silicon nitride, or oxynitride. An insulating layer made of a material such as silicon carbide can be used. In order to control the threshold voltage of the transistor, an impurity element that gives n-type conductivity is added. An impurity element that imparts p-type conductivity may be added to the substrate 200. In this case, for example, phosphorus or arsenic is used as an impurity that gives n-type conductivity. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. , gallium, etc. can be used.

[0214] Next, etching is performed using the protective layer 202 as a mask, and the This removes a portion of the substrate 200 from the exposed area. A semiconductor region 204 separated from the region is formed (FIG. 6(B)). Dry etching is preferably used, but wet etching may also be used. The etching gas and the etching solution can be appropriately selected depending on the material to be etched. do.

[0215] Next, an insulating layer is formed so as to cover the semiconductor region 204, and a region overlapping the semiconductor region 204 is The insulating layer is selectively removed to form an element isolation insulating layer 206 (FIG. 6(C)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, or the like. The method for removing the insulating layer is chemical mechanical polishing. There are polishing processes such as CMP (Polishing and Chemical Mechanical Polishing) and etching processes. Any of these may be used, or a combination of these may be used. After the formation of the insulating layer 204 or the element isolation insulating layer 206, the protective layer 202 is removed. .

[0216] As a method for forming the element isolation insulating layer 206, in addition to a method for selectively removing the insulating layer, Alternatively, a method of forming an insulating region by implanting an element may be used.

[0217] Next, an insulating layer is formed on the surface of the semiconductor region 204, and a layer containing a conductive material is formed on the insulating layer. Complete.

[0218] The insulating layer is to be a gate insulating layer later, and is, for example, subjected to a heat treatment ( The formation of the thin film can be achieved by performing a thermal oxidation treatment, a thermal nitridation treatment, or the like. For example, high density plasma treatment may be performed using He, Ar Any of the following: rare gases such as Kr and Xe, oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen Of course, it can be done by chemical vapor deposition (CVD) or spatula. The insulating layer may be formed by a quenching method or the like. The insulating layer may be formed of silicon oxide, oxynitride, or the like. Silicon, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide Thorium, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen is added Hafnium Silicate (HfSi x O y (x>0, y>0)), nitrogen-added ha HfAl x O y (x>0, y>0) It is desirable to have a layered structure. The thickness of the insulating layer is, for example, 1 nm or more and 100 nm or less. The thickness can be set to 10 nm or less and preferably 50 nm or less.

[0219] The layer containing a conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, a semiconductor material such as polycrystalline silicon can be used to form the conductive layer. A layer containing the material may be formed. The method of forming the layer is not particularly limited, and may be a deposition method, a CVD method, a sputtering method, or the like. Various film formation methods such as a deposition method, a deposition method, a spin coating method, etc. can be used. In this embodiment, an example in which a layer containing a conductive material is formed using a metal material is shown. Let us assume that.

[0220] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 208, A gate electrode 210 is formed (FIG. 6(C)).

[0221] Next, phosphorus (P) or arsenic (As) is added to the semiconductor region 204 to form a channel forming region. 216 and impurity region 220 are formed (FIG. 6(D)). Phosphorus or arsenic is added to form a p-type transistor. In this case, impurity elements such as boron (B) and aluminum (Al) can be added. The concentration of the impurities can be set appropriately, but when semiconductor elements are highly miniaturized, In order to achieve this, it is desirable to increase the concentration.

[0222] In addition, a sidewall insulating layer is formed around the gate electrode 210 to form a gate insulating film having a different impurity element. It is also possible to form an impurity region doped with a certain concentration.

[0223] Next, a metal layer 222 is formed so as to cover the gate electrode 210, the impurity region 220, etc. (FIG. 7(A)). The metal layer 222 is formed by a method such as vacuum deposition, sputtering, or spin coating. The metal layer 222 can be formed by using various film forming methods such as those described above. The semiconductor material is formed by using a metal material that becomes a low-resistance metal compound by reacting with the semiconductor material. Such metal materials include, for example, titanium, tantalum, and titanium. Examples include platinum, nickel, cobalt, and platinum.

[0224] Next, a heat treatment is performed to react the metal layer 222 with the semiconductor material. A metal compound region 224 is formed in contact with the region 220 (FIG. 7(A)). When polycrystalline silicon or the like is used as the electrode 210, the metal layer 222 of the gate electrode 210 A metal compound region is also formed in the portion in contact with the metal.

[0225] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region, and the conductivity is sufficiently increased. This sufficiently reduces the electrical resistance and improves the device characteristics. After forming region 224, metal layer 222 is removed.

[0226] Next, insulating layers 228 and 230 are formed to cover the respective components formed by the above-mentioned steps. The insulating layer 228 and the insulating layer 230 are formed of silicon oxide, silicon oxynitride, etc. The insulating film can be formed using a material containing an inorganic insulating material such as aluminum oxide. In addition, by using a low-k material for the insulating layer 228 and the insulating layer 230, This is preferable because it makes it possible to sufficiently reduce the capacitance caused by overlapping of the seed electrodes and wiring. In addition, the insulating layer 228 and the insulating layer 230 are porous insulating layers made of these materials. A porous insulating layer has a lower dielectric constant than a dense insulating layer, so the electric It is possible to further reduce the capacitance caused by the poles and wiring.

[0227] In addition, the insulating layer 228 or the insulating layer 230 may contain nitrogen such as silicon oxynitride or silicon nitride. The lower transistor 26 may include a layer made of an inorganic insulating material having a high content of SiO 2 . Impurities such as water and hydrogen contained in the material that makes up 0 will later form the upper transistor 262 In this case, however, the intrusion of the oxide semiconductor layer 244 can be prevented. Since it is difficult to remove layers made of inorganic insulating materials that contain a lot of nitrogen using only the CMP process, It is preferable to use an etching treatment or the like in combination.

[0228] In addition, silicon oxynitride is formed as the insulating layer 228, and silicon oxide is formed as the insulating layer 230. In this manner, the insulating layer 228 and the insulating layer 230 can be formed of silicon oxynitride or oxide. By forming the film using only inorganic insulating materials that contain a lot of oxygen, such as silicon carbide, In this process, the insulating layer 228 and the insulating layer 230 can be easily subjected to CMP processing.

[0229] Note that, here, the insulating layer 228 and the insulating layer 230 are stacked. An embodiment is not limited to this, and may have a single layer or a laminated structure of three or more layers. For example, the insulating layer 228 may be made of silicon oxynitride, and the insulating layer 230 may be made of silicon oxide. In the configuration in which a silicon oxynitride film is formed, a silicon oxynitride film is further formed between the insulating layer 228 and the insulating layer 230. It is also possible to adopt a configuration in which the following is formed.

[0230] Thereafter, as a process before the formation of the transistor 262, the insulating layer 228 and the insulating layer 230 are subjected to CM A P treatment is performed to planarize the surfaces of the insulating layer 228 and the insulating layer 230 and at the same time form a gate electrode. The top surface of 210 is exposed (FIG. 7(C)).

[0231] The CMP process may be performed once or multiple times. If polishing is to be performed, first polishing with a high polishing rate is performed, followed by finishing polishing with a low polishing rate. By combining polishing processes with different polishing rates in this way, it is possible to The flatness of the surfaces of the insulating layer 228 and the insulating layer 230 can be further improved.

[0232] In addition, the insulating layer 228 and the insulating layer 230 include an inorganic insulating material containing a large amount of nitrogen. In this case, it is difficult to remove the CMP process alone, so it is recommended to use an etching process in combination. Etching of inorganic insulating materials containing a large amount of nitrogen can be performed using dry etching, wet etching, etc. However, from the viewpoint of miniaturization of elements, dry etching is preferred. In addition, the etching rate of each insulating layer is uniform, and the gate electrode 21 is preferably 0 is determined by the etching conditions (etching gas and etching amount) so that the etching selectivity can be obtained. It is preferable to appropriately set the etching conditions (etching solution, etching time, temperature, etc.). The etching gas used in the present invention is, for example, a gas containing fluorine (trifluoromethane (CHF 3) and fluorine-containing gases such as helium (He) and argon (Ar) Gases such as fluorine-containing gases can be used.

[0233] In addition, when the upper surface of the gate electrode 210 is exposed from the insulating layer 228, it is preferable to The top surface of the pole 210 and the insulating layer 228 are flush with each other.

[0234] Before and after each of the above steps, further processes for forming electrodes, wiring, semiconductor layers, insulating layers, etc. may be performed. For example, a transistor connected to a portion of the metal compound region 224 may be included. An electrode that functions as a source electrode or a drain electrode of the capacitor 260 may be formed. A multi-layer wiring structure consisting of a laminated structure of insulating layers and conductive layers is adopted as the wiring structure, It is also possible to realize an integrated semiconductor device.

[0235] <How to make the upper transistor> Next, a conductive layer is formed on the gate electrode 210, the insulating layer 228, the insulating layer 230, etc., and the conductive layer is The conductive layer is selectively etched to form a first conductive layer that functions as a source electrode or a drain electrode. A first electrode 242a and a second electrode 242b are formed (FIG. 8(A)). and the second electrode 242b is the source electrode or the drain electrode shown in the second embodiment. The electrodes can be formed using the same materials and methods as the functional electrodes. Please refer to the description in embodiment 2 for more details.

[0236] Here, the ends of the first electrode 242a and the second electrode 242b are tapered. The ends of the first electrode 242a and the second electrode 242b are tapered. By doing so, the end portion can be easily covered by an oxide semiconductor layer to be formed later, and thus a step disconnection can be prevented. In addition, the coverage of the gate insulating layer to be formed later is improved, and discontinuity is prevented. It is possible.

[0237] Here, the taper angle is, for example, 30° or more and 60° or less. A layer having a tapered shape (for example, the first electrode 242a) is cut by cutting the cross section (perpendicular to the surface of the substrate). This refers to the inclination angle between the side and bottom surfaces of the layer when observed from a direction perpendicular to the intersecting plane.

[0238] The channel length (L) of the upper transistor is determined by the first electrode 242a and the second electrode It is determined by the distance between the lower ends of the channels 242b. When performing exposure to form a mask used in forming a transistor, the exposure is performed at a wavelength of several nm to several tens of nm. It is desirable to use extreme ultraviolet light with a short wavelength of 1.5 m. Extreme ultraviolet light exposure has high resolution and a large depth of focus. The channel length (L) of the transistor is set to 10 nm or more and 1000 nm (1 μm) or less. This makes it possible to increase the operating speed of the circuit. It is also possible to reduce the power consumption of the semiconductor device.

[0239] Here, the first electrode 242a of the transistor 262 and the gate electrode of the transistor 260 210 are directly connected (FIG. 8(A)).

[0240] Next, an insulating layer 243a is formed on the first electrode 242a, and an insulating layer 244 is formed on the second electrode 242b. The insulating layer 243a and the insulating layer 243b are formed on the first insulating layer 243a and the second insulating layer 243b, respectively (FIG. 8(B)). After forming an insulating layer covering the first electrode 242a and the second electrode 242b, the insulating layer is selected. The insulating layer 243a and the insulating layer 243b are formed by selectively etching the insulating layer 243a. The insulating layer is formed so as to overlap with a part of the gate electrode to be formed. It is possible to reduce the capacitance generated between the gate electrode and the source electrode or the drain electrode. It is.

[0241] The insulating layer 243a and the insulating layer 243b are made of silicon oxide, silicon oxynitride, silicon nitride, or oxide. The insulating layer 10 can be formed using a material containing an inorganic insulating material such as aluminum oxide. By using a low-k material for the layer 243a and the insulating layer 243b, It becomes possible to sufficiently reduce the capacitance between the electrode and the source electrode or the drain electrode. In addition, the insulating layer 243a and the insulating layer 243b are preferably made of a porous material. A porous insulating layer may be applied. A porous insulating layer has a lower dielectric constant than a dense insulating layer. This reduces the capacitance between the gate electrode and the source or drain electrode. It is possible to reduce

[0242] In addition, the capacitance between the gate electrode and the source electrode or the drain electrode is reduced. In this case, it is preferable to form the insulating layer 243a and the insulating layer 243b. It is also possible to configure it in such a way that the

[0243] Next, an oxide semiconductor layer is formed to cover the first electrode 242a and the second electrode 242b. Then, the oxide semiconductor layer is selectively etched to form the oxide semiconductor layer 244. (FIG. 8C) The oxide semiconductor layer 244 is formed using the same method as the oxide semiconductor layer described in Embodiment 2. Therefore, for details, the above-mentioned materials and methods can be used for forming the insulating film 100. The description can be taken into consideration.

[0244] As described in Embodiment 2, before the oxide semiconductor layer is formed by a sputtering method, Then, argon gas is introduced to generate plasma and reverse sputtering is performed, and the formation surface (e.g., insulating It is preferable to remove any deposits on the surface of the edge layer 230.

[0245] Fluorine is added to the formed oxide semiconductor layer, and then heat treatment (first heat treatment) is performed. The method of performing the fluorine addition treatment and the heat treatment (first heat treatment) is the same as that described in the second embodiment. Therefore, for details, the device and method shown in the second embodiment can be applied. The description can be taken into consideration.

[0246] Fluorine is added to the formed oxide semiconductor layer, and heat treatment (first heat treatment) is performed, Reducing residual impurities to produce an I-type (intrinsic semiconductor) or an oxide semiconductor layer that is as close to I-type as possible The remaining impurities are reduced, and the semiconductor becomes I-type (intrinsic semiconductor) or I-type. In the case of a transistor using an oxide semiconductor layer, the change in threshold voltage is suppressed and the off-state current is reduced. Thus, extremely excellent properties with reduced flow can be achieved.

[0247] The upper transistor of this embodiment may contain fluorine in an oxide semiconductor layer. The halogen elements in the semiconductor layer easily bond with metal atoms that have unpaired electrons, and the dangling bonds are eliminated. To terminate the metal, the metal atoms bond with hydrogen or hydroxyl groups derived from impurities to form impurity levels. This can suppress the formation of

[0248] Note that the etching of the oxide semiconductor layer is performed before the heat treatment (first heat treatment) or after the heat treatment. It may be performed either after the first heat treatment or after the second heat treatment. For this reason, it is preferable to use dry etching, but wet etching may also be used. The etching gas and etching solution must be selected appropriately depending on the material to be etched. In addition, when leakage current or the like in the element does not pose a problem, the oxide semiconductor layer can be formed as an island. It may be used without being processed into a shape.

[0249] Next, a gate insulating layer 246 is formed in contact with the oxide semiconductor layer 244, and then a gate insulating A gate electrode 248a is formed over the layer 246 in a region overlapping with the oxide semiconductor layer 244. Then, an electrode 248b is formed in a region overlapping with the first electrode 242a (FIG. 8(D)). The insulating layer 246 is formed using the same material and method as the gate insulating layer shown in the second embodiment. It is possible.

[0250] After the gate insulating layer 246 is formed, a second thermal annealing is performed in an inert gas atmosphere or an oxygen atmosphere. The second heat treatment is preferably performed in the same manner as in the second embodiment. By carrying out the second heat treatment, the electrical characteristics of the transistor can be improved. In addition, when the gate insulating layer 246 contains oxygen, the oxide Oxygen is supplied to the semiconductor layer 244 to compensate for the oxygen vacancies in the oxide semiconductor layer 244, and an I-type ( Alternatively, an oxide semiconductor layer that is an intrinsic semiconductor or an oxide semiconductor layer that is extremely close to an i-type semiconductor can be formed.

[0251] In this embodiment, the second heat treatment is performed after the gate insulating layer 246 is formed. The timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. A heat treatment may be carried out.

[0252] As described above, the oxide semiconductor layer 244 is formed by performing the first heat treatment after adding fluorine. It is possible to highly purify the material so that it contains as few impurities as possible other than its main component.

[0253] The gate electrode 248a is formed using the same material and method as the gate electrode 611 shown in the second embodiment. When the gate electrode 248a is formed, the conductive layer can be selectively formed. By etching, the electrode 248b can be formed. For this purpose, the description in embodiment 2 can be referred to.

[0254] Next, an insulating layer 250 is formed on the gate insulating layer 246, the gate electrode 248a, and the electrode 248b. Insulating layer 250 and insulating layer 252 are formed (FIG. 9(A)). The insulating layer 507 and the protective insulating layer 508 are formed using the same material and method as those of the insulating layer 507 and the protective insulating layer 508 described in the first embodiment. Therefore, for details, the description in Embodiment 1 can be referred to.

[0255] Next, the gate insulating layer 246, the insulating layer 250, and the insulating layer 252 are electrically connected to the second electrode 242b. An opening is formed so as to reach the substrate (FIG. 9(B)). The opening is formed by selectively applying a mask or the like. This is done by selective etching.

[0256] Thereafter, an electrode 254 is formed in the opening, and a wiring 25 in contact with the electrode 254 is formed on the insulating layer 252. Form 6.

[0257] The electrode 254 is formed, for example, by applying a PVD (physical vapor deposition) method or a CVD method to the area including the opening. After forming a conductive layer using a method such as etching or CMP, the conductive layer is It can be formed by removing a part of the

[0258] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The oxide film (such as a natural oxide film) on the formation surface is reduced, and the lower electrode (here, the second electrode 242 b) has the function of reducing the contact resistance with the titanium nitride film. It has a barrier function that suppresses the diffusion of conductive materials. In addition, titanium and titanium nitride are used After forming the barrier film, a copper film may be formed by plating.

[0259] When a part of the conductive layer is removed to form the electrode 254, the surface of the electrode 254 becomes flat. For example, a titanium film or titanium nitride film is thinly formed in the area including the opening. When forming a tungsten film so as to fill the opening after forming a thin film, By MP treatment, unnecessary tungsten, titanium, titanium nitride, etc. are removed, and In this way, the flatness of the surface including the electrode 254 can be improved. By doing so, it is possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc. in the subsequent processes. It becomes possible to do so.

[0260] The wiring 256 is formed using the same material and method as the wiring including the gate electrode 611 shown in the second embodiment. Therefore, for details, the description of the second embodiment should be referred to. It is possible.

[0261] Through the above steps, the transistor 262 including the purified oxide semiconductor layer 244 and the capacitor The capacitor 264 is then completed (FIG. 9C).

[0262] By using the oxide semiconductor layer 244 which has been highly purified and made intrinsic, The off-state current of the transistor can be sufficiently reduced. This makes it possible to obtain a semiconductor device capable of retaining stored contents for an extremely long period of time.

[0263] According to the method of the present embodiment exemplified above, a semiconductor material other than an oxide semiconductor is used in the lower portion. A semiconductor device having a transistor including an oxide semiconductor therein and a transistor including an oxide semiconductor therein can be created.

[0264] In addition, by directly connecting the gate electrode 210 and the first electrode 242a, the contact surface Since the area can be reduced, the semiconductor device can be highly integrated. To increase the memory capacity per unit area of ​​a semiconductor device that can be used as a memory device. This can be done.

[0265] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0266] (Embodiment 5) In this embodiment, an application example of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIG. Here, an example of a memory device will be described. In order to indicate that the transistor includes an oxide semiconductor, the symbol OS is also added. This may happen.

[0267] In the semiconductor device shown in FIG. 13(A-1), a first wiring (1st Line) and a transistor The source electrode of the transistor 700 is electrically connected to the second wiring (2nd Line). The drain electrode of the transistor 700 is electrically connected to the third wiring ( 3rd Line) and the other of the source electrode or the drain electrode of the transistor 710. The fourth line and the gate voltage of the transistor 710 are electrically connected to each other. The electrodes of the transistor 700 are electrically connected to the gate electrode of the transistor 700. One of the source electrode and the drain electrode of the transistor 710 is connected to one of the electrodes of the capacitor element 720. The fifth line and the other electrode of the capacitor 720 are electrically connected to each other. are electrically connected.

[0268] Here, a transistor including an oxide semiconductor is used as the transistor 710. Here, as an example of a transistor including an oxide semiconductor, The transistor 262 can be used. Therefore, the transistor 710 is turned off. By doing so, the potential of the gate electrode of the transistor 700 can be held for an extremely long time. By including the capacitor 720, the transistor 700 This makes it easier to hold the charge given to the gate electrode, and the stored information can be read out. Here, the capacitance element 720 may be, for example, the capacitance element shown in the above embodiment. A child 264 can be used.

[0269] The transistor 700 may include a transistor using a semiconductor material other than an oxide semiconductor. Examples of semiconductor materials other than oxide semiconductors include silicon and germanium. Silicon germanium, silicon carbide, gallium arsenide, etc. can be used. It is preferable to use a crystalline semiconductor. Alternatively, an organic semiconductor material may be used. A transistor using such a semiconductor material can easily operate at high speed. As a transistor using other semiconductor materials, for example, the transistor shown in the above embodiment can be used. A transistor 260 can be used.

[0270] As shown in FIG. 13B, a structure without the capacitor 720 is also possible. do.

[0271] In the semiconductor device shown in FIG. 13A-1, the potential of the gate electrode of the transistor 700 is held. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0272] First, writing and holding of information will be described. The transistor 710 is turned on by applying a potential to the transistor 710. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 700 and the capacitor 720 That is, a predetermined charge is applied to the gate electrode of the transistor 700. Here, we apply two different electric potentials to the charges (hereafter, the low electric potential charge). Charge Q L , the charge that gives the high potential is charge Q H Either of the following shall be given: It is also possible to apply three or more different potentials to the charge to improve the memory capacity. After that, the potential of the fourth wiring is set to a potential at which the transistor 710 is turned off. By turning off the transistor 710, the gate electrode of the transistor 700 The charge applied to is retained (retention).

[0273] Since the off-state current of the transistor 710 is extremely small, the gate electrode of the transistor 700 The charge is retained for a long period of time.

[0274] Next, the reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 700 Depending on the amount of charge held in the transistor electrode, the second wiring has a different potential. If the transistor 700 is an n-channel type, then the gate electrode of the transistor 700 is connected to Q H is given The apparent threshold V th_H is connected to the gate electrode of transistor 700. L but Given the apparent threshold V th_L This is because the temperature is lower than that of the The threshold voltage of the transistor 700 is the fifth threshold voltage required to turn the transistor 700 “on”. Therefore, the potential of the fifth wire is V th_H and V th_L By setting the potential V0 at the intermediate potential between For example, in writing, Q H If given, the fifth wire The potential of V0 (>V th_H ), transistor 700 is in the "on state." Q L is given, the potential of the fifth wire is V0( <V th_L ) even if The transistor 700 remains in the "off state." Therefore, the potential of the second wiring is not observed. The stored information can be read out.

[0275] When memory cells are arranged in an array, only the information of a desired memory cell is read. In this way, it is necessary to read the information of a specific memory cell and To prevent the information in the other memory cells from being read, a transistor 7 is placed between each memory cell. When 00 is connected in parallel, the first 1 of the memory cell that is not the object of reading is For the wiring of 5, the transistor 700 is in the “off state” regardless of the state of the gate electrode. That is, V th_H A smaller potential can be applied to each memory cell. When the transistors 700 are connected in series between the transistors, For the fifth wiring of the memory cell that does not have a gate electrode, the transistor 7 The potential at which V00 is in the "on state," that is, V th_L The larger potential is the fifth wire. Just give it to

[0276] Next, rewriting of information will be described. Rewriting of information is the same as writing and storing the above information. That is, when the transistor 710 is turned on, the potential of the fourth wiring is changed to the This causes the potential of the third wiring ( A potential related to new information is applied to the gate electrode of the transistor 700 and the capacitor 720. After that, the potential of the fourth wiring is set to a potential at which the transistor 710 is turned off. By turning off the transistor 710, the gate electrode of the transistor 700 , a charge related to new information is given.

[0277] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need to extract charge from the floating gate using high voltages, and the erase operation In other words, it is possible to suppress the decrease in the operating speed caused by the above-mentioned problem. It will be revealed.

[0278] The source electrode or drain electrode of the transistor 710 is connected to the gate of the transistor 700. The flow cell is electrically connected to a gate electrode, and is used as a non-volatile memory element. This has the same effect as the floating gate of a floating gate type transistor. In the figure, the source electrode or drain electrode of the transistor 710 and the gate of the transistor 700 The portion to which the gate electrode is electrically connected is sometimes called the floating gate portion FG. When the transistor 710 is off, the floating gate portion FG is embedded in an insulator. It can be seen that the floating gate portion FG holds electric charge. The off-state current of the transistor 710 using Since the capacitance is less than 1 / 100,000 of that of the transistor 710, the floating It is possible to ignore the loss of charge stored in the gate FG. The transistor 710 using the semiconductor material is a nonvolatile memory that can retain data even without power supply. It is possible to realize a storage device having a high degree of reliability.

[0279] For example, the off-state current of transistor 710 at room temperature is 10 zA (1 zeptoampere). is 1×10 -21 A) or less, and the capacitance value of the capacitive element 720 is about 10 fF. is at least 10 4 It is possible to hold data for more than 100 seconds. It goes without saying that this varies depending on the resistor characteristics and capacitance value.

[0280] In this case, the gate problem pointed out in the conventional floating gate type transistor is There is no problem of deterioration of the gate insulating film (tunnel insulating film). This solves the problem of gate insulating film deterioration when electrons are injected into the floating gate. This means that there is no theoretical limit to the number of times it can be written. In addition, in the conventional floating gate type transistor, writing and erasing The high voltage required for this is also unnecessary.

[0281] The semiconductor device shown in FIG. 13(A-1) includes elements such as transistors constituting the semiconductor device. It is possible to consider the elements as including resistance and capacitance as shown in FIG. 13(A-2). In other words, in FIG. 13A-2, the transistor 700 and the capacitor 720 are , resistance and capacitance. R1 and C1 are respectively , the resistance value and capacitance value of the capacitive element 720. The resistance value R1 constitutes the capacitive element 720. R2 and C2 correspond to the resistance of the insulating layer. The resistance R1 is the gate insulator when the transistor 700 is in the on state. The capacitance C2 corresponds to the resistance due to the insulating layer, and the capacitance C3 corresponds to the gate capacitance (the capacitance between the gate electrode and the source A capacitance formed between the gate electrode and the channel forming region, and a capacitance formed between the gate electrode and the channel forming region. This corresponds to the capacitance value of the capacitance formed between

[0282] The resistance between the source and drain electrodes of the transistor 710 when it is in the off state (actual If the gate leakage of the transistor 710 is sufficiently small, then In the condition, when R1 and R2 satisfy R1 ≧ ROS and R2 ≧ ROS, the charge The retention period (which can also be called the information retention period) is mainly determined by the off state of the transistor 710. It will be determined by the current.

[0283] On the other hand, if this condition is not satisfied, the off-state current of the transistor 710 is not sufficiently small. In addition, it becomes difficult to ensure a sufficient retention period. The leakage current (for example, the leakage current generated between the source electrode and the gate electrode) is large. For this reason, the semiconductor device disclosed in this embodiment has the above-mentioned characteristics. It is desirable that the above conditions be satisfied.

[0284] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1 ≧ C2. When the potential of the floating gate portion FG is controlled by the fifth wiring, This allows the potential of the line to be efficiently applied to the floating gate portion FG, The potential difference between the potentials applied to the wiring (for example, the read potential and the non-read potential) is reduced. This is because it can be suppressed.

[0285] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are formed by the gate insulating layer of the transistor 700 and the insulating layer of the capacitor element 720. The same applies to C1 and C2. Therefore, the material and thickness of the gate insulating layer, etc. It is desirable to appropriately set the above-mentioned relationship.

[0286] In the semiconductor device shown in this embodiment, the floating gate portion FG is a flash Same function as the floating gate of a floating gate type transistor such as memory However, the floating gate portion FG of this embodiment is a floating gate of a flash memory or the like. In flash memory, the control gate has fundamentally different characteristics. The voltage applied to the floating gate of the adjacent cell is high, so the effect of the potential on the floating gate of the adjacent cell is large. In order to prevent this from reaching the cell, it is necessary to maintain a certain amount of space between the cells. This is one of the factors that hinder the high integration of semiconductor devices. This is due to the fundamental principle of flash memory, which is to generate a tunnel current by applying a magnetic field. It is something.

[0287] In addition, due to the above-mentioned principle of flash memory, the deterioration of the insulating film progresses, limiting the number of times it can be rewritten. Kai (10 4 ~10 5 Another problem arises:

[0288] The semiconductor device according to the disclosed invention is a transistor including an oxide semiconductor. This operates in this way and does not use the principle of charge injection by tunnel current as described above. Unlike flash memory, high electric fields are not required to inject charges. Since there is no need to consider the effect of the high electric field caused by the control gate on adjacent cells, Integration becomes easier.

[0289] In addition, since it does not use charge injection by tunnel current, there is no cause for degradation of memory cells. In other words, it has higher durability and reliability than flash memory.

[0290] In addition, flash memory does not require a high electric field or large peripheral circuits (such as a boost circuit). This is an advantage over memory.

[0291] The relative dielectric constant εr1 of the insulating layer constituting the capacitance element 720 and the In the case where the relative dielectric constant εr2 of the insulating layer constituting the capacitance element 720 is made different from that of the insulating layer constituting the capacitance element 720, and the area S2 of the insulating layer constituting the gate capacitance in the transistor 700. It is possible to realize C1 ≧ C2 while satisfying 2·S2 ≧ S1 (preferably S2 ≧ S1). That is, it is easy to reduce the area of ​​the insulating layer that constitutes the capacitance element 720 while satisfying C1≧ Specifically, for example, the insulating film constituting the capacitance element 720 is In the layer, a film made of a high-k material such as hafnium oxide or hafnium oxide A laminated structure of a film made of high-k material such as a fluorine-containing oxide semiconductor and a film made of oxide semiconductor is used to achieve εr1 The insulating layer constituting the gate capacitance is preferably made of oxide. By adopting a recon, it is possible to make εr2 = 3 to 4.

[0292] By using such a configuration in combination, the semiconductor device according to the disclosed invention can be further improved. Integration is possible.

[0293] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of positive hole-causing transistors instead of n-type transistors. It goes without saying that a p-type transistor can be used as the carrier.

[0294] As described above, in the semiconductor device according to one embodiment of the disclosed invention, A write transistor having a small leakage current (off-state current) between the write transistors, A non-volatile memory device including a read transistor and a capacitor element using a semiconductor material different from that of the memory device. It has memory cells.

[0295] The off-current of the write transistor is 100zA ( 1×10 -19 A) or less, preferably 10zA (1×10 -20 A) The following is more preferable: For example, 1zA (1×10 -21 A) or less. In normal silicon semiconductors, Although it is difficult to obtain a very low off-state current, it is possible to obtain one by processing an oxide semiconductor under appropriate conditions. This can be achieved in a transistor that has been oxidized. It is preferable to use a transistor including a semiconductor material.

[0296] Furthermore, transistors using oxide semiconductors have a small subthreshold swing (S value). Therefore, even if the mobility is relatively low, the switching speed can be sufficiently high. Therefore, by using the transistor as a writing transistor, This makes it possible to make the rise of the write pulse applied to the write gate FG extremely steep. In addition, since the off-current is small, the amount of charge held in the floating gate FG is small. In other words, a transistor including an oxide semiconductor can be used as a writing transistor. By using it as a transistor, information can be rewritten at high speed.

[0297] There is no limit to the off-state current of the readout transistor, but the readout speed is To achieve high speed, it is desirable to use transistors that operate at high speed. It is preferable to use transistors with a switching speed of 1 nanosecond or less as the transistors for the semiconductor device. It is.

[0298] In this manner, a transistor including an oxide semiconductor is used as a writing transistor, A transistor using a semiconductor material other than an oxide semiconductor is used as a readout transistor. This makes it possible to retain information for a long period of time and read the information at high speed. It is possible to realize a semiconductor device that can be used as a memory device. .

[0299] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0300] (Embodiment 6) In this embodiment, an application example of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. This will be explained with reference to FIG.

[0301] 14(A) and 14(B) are diagrams illustrating the semiconductor device (hereinafter, referred to as a memory cell) shown in FIG. FIG. 14(A) is a circuit diagram of a semiconductor device formed using a plurality of MOSFETs 750. ) is a circuit diagram of a so-called NAND type semiconductor device in which memory cells 750 are connected in series. FIG. 14B shows a so-called NOR type semiconductor device in which memory cells 750 are connected in parallel. FIG. 2 is a circuit diagram of a conductor device.

[0302] The semiconductor device shown in FIG. 14A includes a source line SL, a bit line BL, a first signal line S1, and a plurality of The memory cell 750 includes a second signal line S2, a plurality of word lines WL, and a plurality of memory cells 750. In (A), there is one source line SL and one bit line BL. However, the present invention is not limited to this, and a configuration having a plurality of source lines SL and bit lines BL may also be used.

[0303] In each memory cell 750, the gate electrode of transistor 700 and the gate electrode of transistor 710 One of the source electrode and the drain electrode of the capacitor 720 is electrically connected to one of the electrodes of the capacitor 720. Also, the first signal line S1 and the source electrode or the drain electrode of the transistor 710 are connected to each other. The other of the gate electrodes is electrically connected to the second signal line S2 and the gate of the transistor 710. The electrode of the capacitor 720 is electrically connected to the word line WL. The other is electrically connected.

[0304] The source electrode of the transistor 700 in the memory cell 750 is connected to the adjacent memory cell The drain electrode of the transistor 700 of the memory cell 750 is electrically connected to the drain electrode of the transistor 700 of the memory cell 750. The drain electrode of the transistor 700 is connected to the drain electrode of the transistor of the adjacent memory cell 750. 700 is electrically connected to the source electrode of the memory cell 700. The drain of the transistor 700 in the memory cell 750 provided at one end of the The electrode is electrically connected to a bit line. The source electrode of the transistor 700 in the memory cell 750 at the other end is , and is electrically connected to the source line.

[0305] In the semiconductor device shown in FIG. 14A, writing and reading operations are performed row by row. The write operation is performed as follows: A transistor is connected to the second signal line S2 of the row to be written. A potential is applied to turn on the transistor 710 in the row to be written. As a result, the first signal line S1 is connected to the gate electrodes of the transistors 700 in the specified row. A potential of 0.01V is applied to the gate electrode, and a predetermined charge is applied to the gate electrode. Data can be written to the memory cells in a row.

[0306] The read operation is performed as follows: First, the word lines WL other than the row from which the read is to be performed are In other words, regardless of the charge applied to the gate electrode of transistor 700, transistor 700 A potential is applied to turn on the transistors 700 in the row other than the row to be read out. Then, the gate of the transistor 700 is connected to the word line WL of the row to be read. The on or off state of the transistor 700 is selected depending on the charge held by the electrode. Then, a constant potential is applied to the source line SL, and a constant potential is applied to the bit line The read circuit (not shown) connected to the source line BL is set to an operating state. The transistors 700 between the bit line SL and the bit line BL are turned on except for the row to be read. Since the read operation is in the read state, the conductance between the source line SL and the bit line BL is The state of the transistor 700 in the row is determined by the state (on or off). The charge on the gate electrode of the transistor 700 in the row that is to be read out causes the transistor Since the conductance is different, the potential of the bit line BL will be different accordingly. The potential of the bit line is read by the read circuit, and the memory cell of the specified row is Information can be read from the

[0307] The semiconductor device shown in FIG. 14B includes a source line SL, a bit line BL, a first signal line S1, a second The memory cell 750 includes a plurality of signal lines S2 and a plurality of word lines WL. The gate electrode of each transistor 700 and the source or drain electrode of each transistor 710 One of the electrodes of the capacitor 720 is electrically connected to one of the electrodes of the capacitor 720. The source line SL and the source electrode of the transistor 700 are electrically connected to each other, and the bit line BL and The drain electrode of the transistor 700 is electrically connected to the first signal line S 1 and the other of the source electrode and the drain electrode of the transistor 710 are electrically connected to each other. The second signal line S2 and the gate electrode of the transistor 710 are electrically connected to each other. The word line WL and the other electrode of the capacitor 720 are electrically connected to each other.

[0308] In the semiconductor device shown in FIG. 14B, writing and reading operations are performed row by row. The write operation is performed in the same manner as in the semiconductor device shown in FIG. The operation is as follows. First, a transistor is connected to the word line WL other than the row to be read. The transistor 700 is turned off regardless of the charge applied to the gate electrode of the transistor 700. Such a potential is applied to turn off the transistors 700 in the rows other than the one being read out. Then, the potential of the gate electrode of the transistor 700 is applied to the word line WL of the row to be read. A potential (read) that selects the on or off state of the transistor 700 depending on the load. A constant potential is applied to the source line SL, and a constant potential is applied to the bit line BL. A read circuit (not shown) is set in an operating state. The conductance between BL is determined by the state (on or off) of the transistor 700 in the row to be read out. That is, the state of the transistor 700 in the row to be read is determined by the The potential of the bit line BL varies depending on the charge carried by the gate electrode. The potential of the bit line is read by the read circuit, and information is read from the memory cells of the specified row. can be read out.

[0309] In the above description, the amount of information stored in each memory cell 750 is 1 bit. The structure of the memory device described in the embodiment is not limited to this. By providing three or more types of potentials to be applied to the memory cells 750, the amount of information stored in each memory cell 750 can be increased. For example, when four types of potentials are applied to the gate electrode of the transistor 700, allows each memory cell to hold two bits of information.

[0310] Next, an example of a read circuit that can be used in the semiconductor device shown in FIG. This will be explained using 15.

[0311] FIG. 15A shows a schematic diagram of a read circuit. The read circuit is made up of a transistor and a The amplifier has a sense amplifier circuit.

[0312] When reading, terminal A is connected to the bit line to which the memory cell to be read is connected. A bias potential Vbias is applied to the gate electrode of the transistor, and the potential at terminal A is The position is controlled.

[0313] The memory cell 750 exhibits different resistance values ​​depending on the data stored therein. When the transistor 700 of the selected memory cell 750 is in an on state, the resistance is low. When the transistor 700 of the selected memory cell 750 is in an off state, the memory cell is in a high resistance state. .

[0314] When the memory cell is in a high resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the sense The amplifier circuit outputs a potential corresponding to the potential of terminal A. On the other hand, when the memory cell is in a low resistance state, In this case, the potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit It outputs a potential corresponding to

[0315] In this way, by using the read circuit, data can be read from the memory cell. Note that the read circuit in this embodiment is just an example. Other circuits may be used. The read circuit may include a precharge circuit. It may be configured such that the bit lines are connected.

[0316] Fig. 15(B) shows a differential sense amplifier which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin(+) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output and becomes so. When using the differential sense amplifier in a read circuit, one of Vin(+) and Vin(- ) is connected to the input terminal A, and a reference potential Vre f is applied to the other of Vin(+) and Vin(-).

[0317] Fig. 15(C) shows a latch-type sense amplifier which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the signal Sp is set to High and the signal Sn is set to Low to cut off the power supply potential (Vdd). Then, potentials for comparison are applied to V1 and V2. After that, when the signal Sp is set to Low and the signal Sn is set to High to supply the power supply potential (Vdd), if the comparison potentials V1in and V2i n are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low , and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is High and becomes so. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When using the latch-type sense amplifier in a read circuit, one of V1 and V2 is connected to the terminal A and the output terminal via a switch, and a reference potential Vref is applied to the other of V1 and V2.

[0318] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0319] (Embodiment 7) In this embodiment, a liquid crystal display device including a transistor according to one embodiment of the present invention and a driving method thereof will be described. One embodiment of the operation method will be described with reference to FIGS.

[0320] The components of a liquid crystal display device 100 exemplified in this embodiment are shown in a block diagram in FIG. The liquid crystal display device 100 includes an image processing circuit 110, a power supply 116, a display control circuit 113, a display panel In the case of a transmissive liquid crystal display device or a semi-transmissive liquid crystal display device, a light source A backlight unit 130 is provided as a light source.

[0321] The liquid crystal display device 100 receives an image signal (image signal Data) from a connected external device. The power supply potentials (high power supply potential Vdd, low power supply potential Vss, and common potential Vcom) are When the power supply 116 is turned on, the supply of a control signal to the display control circuit 113 begins. (Start pulse SP and clock signal CK) are supplied by the display control circuit 113. do.

[0322] Note that the high power supply potential Vdd is a potential higher than the reference potential, and the low power supply potential Vss is The high power supply potential Vdd and the low power supply potential Vss are both potentials below the reference potential. It is desirable that the potential be such that the transistor can operate. The low power supply potential Vss is also sometimes called the power supply voltage.

[0323] The common potential Vcom is a fixed potential that serves as a reference for the potential of the image signal supplied to the pixel electrode. As an example, it may be the ground potential.

[0324] The image signal data can be generated by dot inversion driving, source line inversion driving, gate line inversion driving, The signal is appropriately inverted according to frame inversion driving or the like and input to the liquid crystal display device 100. If the image signal is a digital signal, a calculation (for example, detecting the difference between the image signals) can be performed. Therefore, when the image signal is an analog signal, for example, The signal is converted to a digital signal via an A / D converter or the like and supplied to the liquid crystal display device 100. It is preferable to apply the configuration.

[0325] In this embodiment, the common electrode 128 and one electrode of the capacitor 211 are applied with a fixed potential. A common potential Vcom is applied from a power source 116 via a display control circuit 113 .

[0326] The display control circuit 113 outputs the image signal processed by the image processing circuit 110 to the display panel 120. Supply of control signals (specifically, a start pulse SP and a clock signal CK, etc.) and the power supply potential (high power supply potential Vdd, low power supply potential Vdd). A power supply potential Vss and a common potential Vcom are supplied to the backlight unit 130. A control signal (specifically, a backlight control circuit 131 controls turning on and off the backlight) This is a circuit that supplies a signal to control the

[0327] The image processing circuit 110 analyzes, calculates, or processes the input image signal (image signal data). The processed image signal is output to the display control circuit 113 together with a control signal.

[0328] For example, the image processing circuit 110 analyzes the input image signal Data and determines whether it is a moving image or a still image. and outputting a control signal including the result of the determination to the display control circuit 113. In addition, the image processing circuit 110 extracts one frame of still image data from the image signal Data including a still image. The image is cut out and output to the display control circuit 113 together with a control signal indicating that it is a still image. In addition, the image processing circuit 110 can extract a moving image from the image signal Data including the moving image. A control circuit 11 detects the motion picture and displays successive frames together with a control signal indicating that the motion picture is being displayed. 3 can be output.

[0329] The image processing circuit 110 outputs the image signal data to the liquid crystal display device of this embodiment. In this embodiment, the image processing circuit 110 judges an image as a still image. The image processing circuit 110 judges the image to be a moving image and performs the operation by cutting off the This operation is called video display mode.

[0330] In addition, the image processing circuit 110 exemplified in this embodiment has a display mode switching function. The display mode switching function may be performed by selecting the display mode of the corresponding liquid crystal display regardless of the judgment of the image processing circuit 110. A user of a liquid crystal display device can change the operation mode of the liquid crystal display device manually or by using an externally connected device. This function allows you to select and switch between video display mode and still image display mode.

[0331] The above-mentioned functions are examples of the functions of the image processing circuit 110, and may be changed depending on the application of the display device. Various image processing functions can be selected and applied.

[0332] The display panel 120 has a pair of substrates (a first substrate and a second substrate). The liquid crystal element 215 is sandwiched between the pair of substrates. 121, a pixel portion 122, a terminal portion 126, and a switching element 127 are provided. A common electrode 128 (also called a common electrode or a counter electrode) is provided on the second substrate. In this embodiment, the common connection portion (also called a common contact) is the first The first substrate is connected to a common terminal on the second substrate. Pole 128 is connected.

[0333] The pixel section 122 includes a plurality of gate lines 124 (scanning lines) and source lines 125 (signal lines). A plurality of pixels 123 are surrounded by gate lines 124 and source lines 125. In the display panel exemplified in this embodiment, The gate line 124 extends from the gate line side driver circuit 121A, and the source line 125 extends from the source line side driver circuit 121B. It extends from the operating circuit 121B.

[0334] The pixel 123 has a transistor 214 as a switching element, and the transistor 214 is connected The pixel includes a capacitor element 211 and a liquid crystal element 215 (FIG. 19).

[0335] The transistor 214 has a gate electrode connected to one of the gate lines 124 provided in the pixel section 122. One of the source electrodes or the drain electrodes is connected to one of the source lines 125. The other of the source electrode and the drain electrode is connected to one of the capacitor elements 211. The electrode is connected to one electrode (pixel electrode) of the liquid crystal element 215 .

[0336] In addition, it is preferable to use a transistor with reduced off-state current as the transistor 214. In this case, the transistors described in any of the first to third embodiments are suitable. In this case, the transistor 214 in the off state stably supplies a current to the liquid crystal element 215 and the capacitor element 211. In addition, by using the transistor 214 whose off-state current is sufficiently reduced, Therefore, the pixel 123 can be configured without providing the capacitor element 211 .

[0337] With this configuration, the pixel 123 is written before the transistor 214 is turned off. This allows the written state to be maintained for a long period of time, thereby reducing power consumption.

[0338] The liquid crystal element 215 is an element that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The optical modulation of the liquid crystal is controlled by the electric field applied to the liquid crystal. The field direction varies depending on the liquid crystal material, driving method, and electrode structure, and can be selected appropriately. For example, when using a driving method in which an electric field is applied in the thickness direction (so-called vertical direction) of the liquid crystal, The pixel electrodes are provided on the first substrate and the common electrode is provided on the second substrate so as to sandwich the crystal. In addition, a driving method in which an electric field is applied to the liquid crystal in the in-plane direction of the substrate (so-called horizontal electric field) In the case of using a liquid crystal display, a pixel electrode and a common electrode may be provided on the same surface as the liquid crystal. The pixel electrodes and the common electrodes may have various opening patterns.

[0339] Examples of liquid crystals that can be used in liquid crystal elements include nematic liquid crystals, cholesteric liquid crystals, and smectic liquid crystals. tic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight Liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain Examples include polymer liquid crystal and banana-shaped liquid crystal.

[0340] The liquid crystal driving mode is TN (Twisted Nematic) mode, S TN (Super Twisted Nematic) mode, OCB (Optical ly Compensated Birefringence mode, ECB (Ele ctrically Controlled Birefringence) mode, F LC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, PD LC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, Guest host mode can be used. In addition, IPS (In-Plane-Sw fringe field switching mode, FFS (Fringe Field Switching) mode mode, MVA (Multi-domain Vertical Alignment) mode mode, PVA (Patterned Vertical Alignment) mode, ASM(Axially Symmetric aligned Micro-cell Of course, in this embodiment, the optical modulation If the element controls the transmission or non-transmission of light by the action of the liquid crystal material, the driving method, and the voltage The pole structure is not particularly limited.

[0341] Note that the liquid crystal element exemplified in this embodiment has a pixel electrode provided on a first substrate and a The vertical electric field generated between the pixel electrodes on the substrate and the common electrode facing each other causes the liquid crystal to be aligned. Controls the direction.

[0342] The terminal unit 126 receives a predetermined signal (high power supply potential Vdd, low power supply potential Vdd) output by the display control circuit 113. Potential Vss, start pulse SP, clock signal CK, image signal Data, common potential Vc om, etc.) to the drive circuit unit 121.

[0343] The driving circuit section 121 includes a gate line side driving circuit 121A and a source line side driving circuit 121B. The gate line side driving circuit 121A and the source line side driving circuit 121B have a plurality of pixels. A driving circuit for driving the pixel unit 122 and a shift register circuit (a shift register and (also referred to as "common").

[0344] The gate line side driver circuit 121A and the source line side driver circuit 121B are connected to the pixel section 122. The light emitting device may be formed on the same substrate as the light emitting device 1 or on a different substrate.

[0345] The driving circuit unit 121 also includes a high power supply potential Vdd, which is controlled by the display control circuit 113. A low power supply potential Vss, a start pulse SP, a clock signal CK, and an image signal Data are supplied. can be.

[0346] The switching element 127 may be a transistor. The gate electrode of the transistor 127 is connected to the terminal 126A. In response to the signal, the switching element 127 supplies a common potential Vcom to the common electrode 128. One of the source electrode and the drain electrode is connected to the terminal portion 126B, and the other is connected to the common electrode 128. , so that a common potential Vcom is supplied from the display control circuit 113 to the common electrode 128. The switching element 127 may be provided in the driver circuit section 121 or the pixel section 12. It may be formed on the same substrate as 2, or it may be formed on a different substrate.

[0347] In addition, the switching element 127 has a reduced off-current as described in the first to third embodiments. By using a transistor, the voltage applied to both terminals of the liquid crystal element 215 decreases over time. can be suppressed.

[0348] The common electrode 128 is a common potential supplying a common potential Vcom controlled by the display control circuit 113. The line is electrically connected at a common connection portion.

[0349] A specific example of the common connection portion is a conductive particle in which an insulating sphere is coated with a thin metal film. By this, an electrical connection between the common electrode 128 and the common potential line can be achieved. The common connection portion may be provided at a plurality of locations within the display panel 120.

[0350] The photometric circuit may be provided in the liquid crystal display device. The LCD display can detect the brightness of the environment in which it is placed. When it is found that the backlight 132 is turned on, the display control circuit 113 increases the light intensity of the backlight 132. By controlling the brightness of the LCD display, good visibility of the display screen is ensured. When it is determined that the display is being used under external light (for example, under direct sunlight outdoors), the display control circuit 1 13 controls the light intensity of the backlight 132 to reduce the amount of light consumed by the backlight 132. In this way, the display control circuit reduces the power consumption according to the signal input from the photometry circuit. 113 can control the driving method of light sources such as a backlight, a sidelight, etc.

[0351] The backlight unit 130 includes a backlight control circuit 131 and a backlight 132. The backlight 132 may be selected and combined according to the intended use of the liquid crystal display device 100. For example, a light emitting diode (LED) or the like can be used for the backlight 132. For example, a white light emitting element (such as an LED) can be arranged. A backlight signal for controlling the backlight from the display control circuit 113 and a power supply voltage are input to the display control circuit 113. Positions are provided.

[0352] If necessary, optical films (polarizing films, retardation films, anti-reflection films, etc.) The backlight used in the semi-transmissive liquid crystal display device can be used in combination. The light source such as a light may be selected and combined according to the purpose of the liquid crystal display device 100. Cathode ray tubes and light emitting diodes (LEDs) can be used. Multiple LED light sources, Alternatively, a surface light source may be formed by using a plurality of electroluminescence (EL) light sources. As the surface light source, three or more color LEDs may be used, or a white light emitting LED may be used. In addition, RGB light-emitting diodes are arranged in the backlight, and color display is performed in time division. When using the field sequential method, the color filter In some cases, it may not be set.

[0353] Next, a method for driving the liquid crystal display device 100 illustrated in FIG. 18 will be described with reference to FIGS. 19 to 22. The method of driving the liquid crystal display device described in this embodiment is based on the characteristics of the image to be displayed. This is a display method in which the rewriting frequency (or frequency) of the display panel is changed according to the display conditions. When displaying an image (moving image) in which the image signals of successive frames are different, A display mode in which the image signal is written in successive frames is used. On the other hand, the image signal of the successive frames is the same. When displaying a still image, no new image signals are input during the period when the same image is being displayed. The liquid crystal element is not written to or written to very rarely, and a voltage is applied to the liquid crystal element. The voltage applied to the liquid crystal element is set to 0.05V, while the potential of the common electrode is set to 0.05V. A display mode is used in which the voltage is held and a still image is displayed without newly supplying a potential.

[0354] The LCD device displays a combination of moving images and still images on the screen. By switching between multiple different images at high speed, the image appears as a moving image to the human eye. This refers to an image that can be recognized as a moving picture. Specifically, the image must be switched at least 60 times (60 frames) per second. By doing so, the human eye will perceive the image as a moving image with less flicker. Unlike moving images and partial moving images, it quickly switches between multiple images that are time-divided into multiple frame periods. Even if the operation is switched between the nth and (n+1)th frames, This refers to an image that does not change from frame to frame.

[0355] First, the power supply 116 of the liquid crystal display device is turned on to supply power. 13 denotes power supply potentials (high power supply potential Vdd, low power supply potential Vss, and common potential Vcom), and A control signal (a start pulse SP and a clock signal CK) is supplied to the display panel 120. do.

[0356] The image signal (image signal Data) is input to the liquid crystal display device 100 from an external device. The image processing circuit 110 of the liquid crystal display device 100 receives the input image. The image signal is analyzed. Here, the system distinguishes between video and still images and outputs different signals for video and still images. The case where the input process is performed will be described.

[0357] For example, the image processing circuit 110 detects whether the input image signal (image signal Data) is a still image or a moving image. When switching to a still image, a still image is extracted from the input image signal. The image signal (image signal When the image data changes from a still image to a video, the image signal including the video is converted to a video signal. The display control circuit 113 outputs the signal together with the control signal corresponding to the selected pixel.

[0358] Next, the state of signals supplied to the pixels will be described with reference to the equivalent circuit diagram of the liquid crystal display device shown in FIG. 19 and FIG. This will be explained using the timing chart shown in FIG.

[0359] FIG. 20 shows the clock signal G supplied from the display control circuit 113 to the gate line side driving circuit 121A. CK and a start pulse GSP. The display control circuit 113 also includes a source line side drive circuit. 12 shows a clock signal SCK and a start pulse SSP supplied to the circuit 121B. To explain the output timing of the clock signal, the waveform of the clock signal is shown in Figure 20. It is shown by a square wave.

[0360] FIG. 20 shows the potential of the source line 125 (Data line), the potential of the pixel electrode, 26A, the potential of terminal 126B, and the potential of the common electrode are shown.

[0361] In FIG. 20, a period 1401 corresponds to a period for writing an image signal for displaying a moving image. During the period 1401, an image signal and a common potential are supplied to each pixel and a common electrode of the pixel portion 122. It works like this.

[0362] The period 1402 corresponds to a period for displaying a still image. The image signal to each pixel of 22 and the common potential to the common electrode are stopped. In the period 1402 shown in FIG. 14, the configuration is such that each signal is supplied to stop the operation of the driving circuit unit. However, depending on the length of the period 1402 and the refresh rate, the image signal is periodically written. It is preferable to prevent deterioration of the image quality of a still image by writing the still image.

[0363] First, the timing chart for the period 1401 during which an image signal for displaying a moving image is written is In period 1401, a clock signal is constantly supplied as the clock signal GCK. A pulse corresponding to the vertical sync frequency is supplied as the start pulse GSP. In the period 1401, a clock signal SCK is constantly supplied. As the gate pulse SSP, a pulse corresponding to one gate selection period is supplied.

[0364] In addition, image signals DATA are supplied to the pixels of each row via source lines 125 and gate lines 12 In response to the potential of the source line 125, the potential of the source line 125 is supplied to the pixel electrode.

[0365] In addition, the display control circuit 113 connects the switching element 127 to the terminal 126A. A potential is supplied to make 127 conductive, and a common potential is supplied to the common electrode via terminal 126B. do.

[0366] Next, a timing chart for the period 1402 during which a still image is displayed will be described. In 02, the clock signal GCK, the start pulse GSP, the clock signal SCK, and the start In addition, in a period 1402, the source pulse SSP supplied to the source line 125 is stopped. The image signal Data that was being transmitted stops. The clock signal GCK and the start pulse GSP During the period 1402 when both are stopped, the transistor 214 is in a non-conducting state, and the potential of the pixel electrode becomes floating.

[0367] In addition, the display control circuit 113 connects the switching element 127 to the terminal 126A. A potential is supplied to make the common electrode 127 non-conductive, and the potential of the common electrode is set to a floating state.

[0368] In the period 1402, the potentials of the electrodes at both ends of the liquid crystal element 215, that is, the pixel electrode and the common electrode, are floated. By setting the display to the idle state, a still image can be displayed without supplying any new potential.

[0369] In addition, the clocks supplied to the gate line side driver circuit 121A and the source line side driver circuit 121B are By stopping the clock signal and the start pulse, it is possible to reduce power consumption.

[0370] In particular, the transistor 214 and the switching element 127 are transistors with reduced off-state current. The phenomenon in which the voltage applied to both terminals of the liquid crystal element 215 decreases over time due to the use of a capacitor. can be suppressed.

[0371] Next, the period when the video is switched to a still image (period 1403 in FIG. 20) and the period when the still image is switched to the video are The operation of the display control circuit during the period when the image is switched to the next image (period 1404 in FIG. 20) is shown in FIG. 21(A) and (B) are used to explain. The power supply potential Vdd, the clock signal (here GCK), the start pulse signal (here GS P), and the potential at terminal 126A are shown.

[0372] FIG. 21A shows the operation of the display control circuit during the period 1403 when a moving image is switched to a still image. The display control circuit stops the start pulse GSP (E1 in FIG. 21(A), the first step Then, after the start pulse signal GSP stops, the pulse output is After the clock signal GCK reaches the first stage, the clock signal GCK is stopped (E2 in FIG. 21(A), the second stage). Next, the high power supply potential Vdd of the power supply voltage is changed to the low power supply potential Vss (FIG. 21( E3, third step of A). Then, the potential of the terminal 126A is changed to the potential of the switching element 12 7 is set to a potential at which it becomes non-conductive (E4 in FIG. 21(A), the fourth step).

[0373] Through the above procedure, the drive circuit unit 121 can be prevented from malfunctioning. 1. The malfunction when switching from video to still image causes noise. Since noise is stored as a still image, the LCD display is equipped with a display control circuit that is less likely to malfunction. The display device can display still images with little image degradation.

[0374] Next, the operation of the display control circuit during the period 1404 when the still image is switched to the moving image is shown in FIG. The display control circuit changes the potential of the terminal 126A to a potential at which the switching element 127 is turned on. (S1 in FIG. 21B, first step). Next, the power supply voltage is set to the low power supply potential Vs s to the high power supply potential Vdd (S2 in FIG. 21(B), second step). The clock signal GCK is a longer pulse signal than the normal clock signal GCK. After applying the potential, a plurality of clock signals GCK are supplied (S3 in FIG. 21B, the third switch Next, a start pulse signal GSP is supplied (S4 in FIG. 21(B), the fourth step). Tep).

[0375] Through the above procedure, the drive circuit unit 121 can be turned on without causing a malfunction of the drive circuit unit 121. By returning the potential of each wiring to the time when the video was displayed in the correct order, the supply of the drive signal can be resumed. The driving circuit unit can be driven without any operation.

[0376] FIG. 22 shows a period 691 in which a moving image is displayed or a period 692 in which a still image is displayed. The figure shows the frequency of writing image signals for each frame period. This indicates a signal writing period, and "H" indicates a period in which the image signal is held. In addition, in FIG. 22, a period 693 represents one frame period. The period may be.

[0377] In this way, in the configuration of the liquid crystal display device of this embodiment, the still image displayed in the period 692 The image signal of the image is written in the period 694, and the image signal written in the period 694 is It is held for 92 other periods.

[0378] The liquid crystal display device exemplified in this embodiment writes image signals during a period in which a still image is displayed. As a result, it is possible to reduce the power consumption when displaying still images. do.

[0379] In addition, when displaying a still image by rewriting the same image multiple times, the change in image may be difficult to see. When the image becomes too blurred, the human eye may feel tired. Since the frequency of signal writing is reduced, it also has the effect of reducing eye fatigue.

[0380] In particular, the liquid crystal display device of the present embodiment has a reduced off-state current as shown in the first to third embodiments. By applying a transistor to each pixel and a switching element of a common electrode, This allows the capacitor to hold the voltage for a longer period (time). This makes it possible to dramatically reduce the frequency of writing, resulting in lower power consumption when displaying still images, It also has a significant effect on reducing eye fatigue.

[0381] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0382] (Embodiment 8) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 16. In this embodiment, Telephones, mobile phone devices, portable information terminals (including portable game consoles, audio playback devices, etc.) (including), digital cameras, digital video cameras, electronic paper, television equipment (television The above-described semiconductor device is applied to electronic devices such as a television receiver. This section explains what happens when

[0383] FIG. 16A shows a notebook personal computer, which includes a housing 601, a housing 605, The display unit 603 and the keyboard 604 are included. The transistor includes a transistor including an oxide semiconductor described in the above embodiment and a transistor including a semiconductor other than an oxide semiconductor. A semiconductor device is provided that is integrally provided with a transistor using the semiconductor material. Therefore, it has the characteristics of being able to retain information for a long time and read it out at high speed. This makes it possible to realize a notebook type personal computer having such a configuration.

[0384] FIG. 16B shows a personal digital assistant (PDA), and a main body 610 includes a display unit 616 and an external A terminal interface 617 and an operation button 614 are provided. The main body 610 includes a stylus 612 for operating the terminal. The transistors shown in FIG. 1 are made of an oxide semiconductor and a transistor made of a semiconductor material other than an oxide semiconductor. The semiconductor device is provided with a transistor and a A portable information terminal with features such as the ability to store and read information at high speed has been realized. can be.

[0385] FIG. 16C shows an electronic book 620 that uses electronic paper. The display unit 62 is disposed in the housing 621 and the housing 623. 5 and a display unit 627 are provided. The housing 621 and the housing 623 are connected by a shaft portion 637. The housing 621 is connected to the shaft 637, and can be opened and closed around the shaft 637. The portable terminal 620 includes a power source 631, an operation key 633, a speaker 635, and the like. At least one of the bodies 623 is a transistor including an oxide semiconductor, which is described in the above embodiment. and a transistor using a semiconductor material other than an oxide semiconductor. This allows data to be stored for a long period of time and read out at high speed. This will make it possible to create e-books with features such as:

[0386] FIG. 16D shows a mobile phone that is composed of two housings, a housing 640 and a housing 641. Furthermore, the housing 640 and the housing 641 slide and unfold as shown in FIG. It can be folded up and folded up, making it possible to make it compact and suitable for carrying. The housing 641 also includes a display panel 642, a speaker 643, a microphone 644, and a pointing device. The camera includes a display device 646, a camera lens 647, and an external connection terminal 648. The housing 640 also includes a solar cell 649 for charging the mobile phone, an external memory slot, and The display panel 642 has a touch panel function. In FIG. 16(D), a plurality of operation keys 645 displayed as an image are indicated by dotted lines. The antenna is built into the housing 641. At least one of the housings 640 and 641 The transistor including an oxide semiconductor described in the above embodiment and the transistor including a semiconductor other than an oxide semiconductor are A semiconductor device is provided that is integrally provided with a transistor using a conductive material. This allows data to be stored for a long period of time and read out quickly. A mobile phone is realized.

[0387] FIG. 16E shows a digital camera, which includes a main body 661, a display unit 667, an eyepiece unit 663, and an operation unit. It is composed of an operation switch 664, a display unit 665, a battery 666, etc. The transistor using an oxide semiconductor described in the above embodiment and the transistor using an oxide semiconductor A semiconductor device is provided that is integrally provided with a transistor using a semiconductor material other than the silicon. This allows for the special features of long-term data retention and high-speed data readout. A digital camera having the above features is realized.

[0388] FIG. 16F shows a television device 670, which includes a housing 671, a display unit 673, a stand, and the like. The television device 670 is operated by a switch provided in the housing 671. The housing 671 and the remote control operation The device 680 includes a transistor including an oxide semiconductor described in the above embodiment and a A semiconductor device is provided that is integrally provided with a transistor using a semiconductor material other than the silicon. This allows for the special features of long-term data retention and high-speed data readout. A television device having the above features is realized.

[0389] As described above, the electronic device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This has resulted in electronic devices that are small, operate at high speed, and consume low power. is realized.

[0390] (Embodiment 9) In this embodiment, the kinetic energy of the ions added using an ion implantation device or the like and I Metal in n-Ga-Zn-O oxide semiconductor (amorphous IGZO, a-IGZO) layer -Hydrogen bond energy, metal-hydroxyl bond energy, or oxygen-hydrogen bond energy in a hydroxyl bonded to a metal The energy of the halogen elements, which have high kinetic energy, was compared. By adding it to the oxide semiconductor layer, for example, the bond between the metal and hydrogen that constitutes the oxide semiconductor, Able to break the bond between a metal and a hydroxyl group, or the oxygen and hydrogen bond in a hydroxyl group that is bonded to a metal It was confirmed that the metal-hydrogen and metal- The bond energy between hydroxyl groups or between oxygen and hydrogen in a hydroxyl group bonded to a metal is The binding energy was calculated by theoretical calculation.

[0391] In the surface slab model of the a-IGZO layer, the binding energy of the metal atoms on the layer surface was calculated. The surface slab model is a surface slab model in which the desired elements are bonded together and the bond energy is calculated. In the computational cell with periodic boundary conditions, the layer with atoms and the vacuum layer without atoms are By stacking in a certain direction (for example, the z-axis direction), the existence of atoms at the interface between the two layers For example, in Figure 17, the boundary between the a-IGZO layer and the vacuum layer is In Figure 17, the surface of the a-IGZO layer is exposed. The figure shows the case where a hydroxyl group (OH group, hydroxyl group) is bonded to the atom. In the lower half of the -IGZO layer, the atoms are fixed.

[0392] Specifically, we calculated the energy of the following structure: a-IGZO surface slab model (structure 1) A structure in which hydrogen (H) atoms are bonded to the metal (In, Ga, or Zn) on the surface of structure 1. (Structure 2) is a structure in which an oxygen (O) atom is bonded to the metal (In, Ga, or Zn) on the surface of Structure 1. The structure (structure 3) and the structure 1 have hydroxyl (OH) groups on the metal (In, Ga, or Zn) on the surface. The energy of the structure (structure 4) was calculated. To calculate the energy, we use the energy of an isolated hydrogen atom (structure 5) and an isolated hydroxyl The energy of the group (structure 6) was calculated.

[0393] (Model creation procedure) Using classical molecular dynamics calculations, first-principles molecular dynamics calculations, and first-principles structure optimization, a-IGZ Using this, a surface slab model was created and the first-principles calculations were carried out again. The structure was optimized further.

[0394] (calculation conditions) Materials Explorer (Fujitsu Ltd.) was used for classical molecular dynamics calculations. The calculation cell was randomly arranged with In:Ga:Zn:O=1:1:1:4 (total 84 atoms). The density is 5.9g / cm 3 The temperature was set to 5500K in the NVT ensemble. The temperature was gradually lowered to 1500 K and annealed at 1500 K. The time step size was 0.2 fs. The time was set to 12.44 ns. The potential between the metal and oxygen and between the oxygen and oxygen was B Orn-Mayer-Huggins type is applied, and Lenaard-J The charge was In: +3, Ga: +3, Zn: +2, O: -2. .

[0395] The first-principles calculation program used was CASTEP (Accelrys). EP is a calculation program based on density functional theory, which uses pseudopotentials and plane waves. The functional is LDA, the pseudopotential is Ultrasoft, and the cutoff energy is The energy was 380 eV, and the grid number of k-points was 2 × 2 × 1.

[0396] (Definition of bond energy) The bond energy was calculated using the definition shown in Equation 1.

[0397]

number

[0398] In the formula 1, E M-H indicates the bond energy between metal and hydrogen in a-IGZO. E MO-H is the bond energy between oxygen and hydrogen of the hydroxyl group bonded to the metal in a-IGZO. Show. E M-OH represents the bond energy between the metal and hydroxyl groups in a-IGZO. E(a -IGZO_M) is an amorphous IGZO, an 84-atom slab structure (structure 1) with high energy density. E(a-IGZO_M-H) is the amorphous IGZO, 84-atom surface Energy of the structure (structure 2) in which a hydrogen atom (H) is added to a metal M (In, Ga, or Zn) E(a-IGZO_M-O) is the gold on the amorphous IGZO, 84-atom surface. Energy of the structure (structure 3) in which an oxygen atom (O) is added to group M (In, Ga, or Zn) E(a-IGZO_M-OH) is the amorphous IGZO, 84-atom surface The structure (structure 4) is a structure in which a hydroxyl (OH) group is added to a metal M (In, Ga, or Zn). E(H) represents the energy of a hydrogen atom (structure 5). E(OH) is , the energy of the hydroxyl group (structure 6) is shown.

[0399] Table 1 shows the calculated bond energy values ​​when the metal M is changed.

[0400] [Table 1]

[0401] From the above results, the acidity of the metal-hydrogen bond, the metal-hydroxyl bond, and the hydroxyl bond to the metal is The bond energies between hydrogen and oxygen are all several eV. The kinetic energy of the ions of the halogen element added in the ion doping apparatus is, for example, By using this method, the binding energy can be increased to 5 keV to 100 keV, which is higher than the above binding energy. Therefore, when a halogen element having high kinetic energy is added to an oxide semiconductor layer, For example, the bond between the metal and hydrogen that constitutes the oxide semiconductor, and the bond between the metal and hydroxyl groups can be formed by this. It has been shown that it can break the bond between an oxygen atom and a hydrogen atom in a hydroxyl group bonded to a metal or to a metal. I was tempted. [Explanation of symbols]

[0402] 100 LCD display device 110 Image processing circuit 113 Display control circuit 116 Power supply 120 Display Panel 121 Drive circuit section 121A Gate line side driving circuit 121B Source line side driver circuit 122 Pixel section 123 pixels 124 Gate Line 125 source lines 126 Terminal section 126A Terminal 126B Terminal 127 Switching element 128 Common electrode 130 Backlight section 131 Backlight control circuit 132 Backlight 200 boards 202 Protective layer 204 Semiconductor area 206 Element isolation insulating layer 208 Gate Insulation Layer 210 Gate electrode 211 Capacitive element 214 Transistor 215 Liquid crystal element 216 Channel formation region 220 Impurity region 222 Metal layer 224 Metal compound area 228 Insulating Layer 230 Insulating layer 242a electrode 242b electrode 243a Insulating layer 243b Insulating layer 244 Oxide semiconductor layer 246 Gate Insulation Layer 248a Gate electrode 248b Electrode 250 Insulation Layer 252 Insulating layer 254 electrode 256 Wiring 260 Transistors 262 Transistor 264 Capacitive element 500 boards 502 Gate insulation layer 507 Insulating layer 508 Protective insulation layer 511 Gate electrode 513a Oxide semiconductor layer 513b Oxide semiconductor layer 513c Oxide semiconductor layer 515a electrode 515b electrode 550 Transistor 600 Substrates 601 Case 602 Gate insulating layer 603 Display section 604 Keyboard 605 Case 608 Protective insulation layer 610 Main unit 611 Gate electrode 612 Stylus 613a Oxide semiconductor layer 613b Oxide semiconductor layer 613c Oxide semiconductor layer 614 Operation button 615a electrode 615b electrode 616 Display section 617 External Interface 620 e-books 621 Case 623 Case 625 Display section 627 Display section 631 Power supply 633 Operation Key 635 Speaker 637 Shaft 640 Case 641 Case 642 Display Panel 643 Speakers 644 Microphone 645 Operation Key 646 Pointing Device 647 Camera Lenses 648 External connection terminal 649 Solar Cells 650 Transistors 651 External Memory Slot 661 Main unit 663 Eyepiece 664 Operation switch 665 Display section 666 Battery 667 Display section 670 Television Equipment 671 Case 673 Display section 675 Stand 680 Remote Controlled Device 691 period 692 period 693 period 694 period 700 Transistors 710 Transistor 720 Capacitive element 750 memory cells 1000 boards 1002 Gate insulating layer 1007 Insulating layer 1008 Protective insulation layer 1011 Gate electrode 1013a Oxide semiconductor layer 1013b Oxide semiconductor layer 1013c Oxide semiconductor layer 1013d Oxide semiconductor layer 1015a electrode 1015b electrode 1050 Transistor 1401 period 1402 period 1403 period 1404 period

Claims

1. A plurality of circuits arranged in a matrix form are included, one of the circuits includes at least a first transistor including silicon, a second transistor including an oxide semiconductor, and a capacitor; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor; a gate electrode of the first transistor is electrically connected to one electrode of the capacitance element; the capacitance element has a function of holding a potential of a gate electrode of the first transistor, the second transistor is a semiconductor device having a function of holding a potential of a gate electrode of the first transistor, a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the second insulating layer and a region in contact with a top surface of the first conductive layer, the second conductive layer functioning as one of a source electrode and a drain electrode of the second transistor; an oxide semiconductor layer having a region located above the second insulating layer and including a channel formation region of the second transistor; a third insulating layer having a region in contact with an upper surface of the second conductive layer; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having a region located above the second conductive layer and functioning as the other electrode of the capacitor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the fourth conductive layer; the third conductive layer and the fourth conductive layer have the same material; the second conductive layer has a first region, the upper surface of which is in contact with the third insulating layer, and a second region, the upper surface of which is not in contact with the third insulating layer; the first region of the second conductive layer has an overlap with the third conductive layer; The second region of the second conductive layer overlaps with the fourth conductive layer.

2. A plurality of circuits arranged in a matrix form are included, one of the circuits includes at least a first transistor including silicon, a second transistor including an oxide semiconductor, and a capacitor; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor; a gate electrode of the first transistor is electrically connected to one electrode of the capacitance element; the capacitance element has a function of holding a potential of a gate electrode of the first transistor, the second transistor is a semiconductor device having a function of holding a potential of a gate electrode of the first transistor, a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the second insulating layer and a region in contact with a top surface of the first conductive layer, the second conductive layer functioning as one of a source electrode and a drain electrode of the second transistor; an oxide semiconductor layer having a region located above the second insulating layer and including a channel formation region of the second transistor; a third insulating layer having a region in contact with an upper surface of the second conductive layer; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having a region located above the second conductive layer and functioning as the other electrode of the capacitor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the fourth conductive layer; the third conductive layer and the fourth conductive layer have the same material; the second conductive layer has a first region, the upper surface of which is in contact with the third insulating layer, and a second region, the upper surface of which is not in contact with the third insulating layer; the first region of the second conductive layer has an overlap with the third conductive layer; the second region of the second conductive layer has an overlap with the fourth conductive layer; The first transistor has a channel length direction that intersects with a channel length direction of the second transistor.

3. A plurality of circuits arranged in a matrix form are included, one of the circuits includes at least a first transistor including silicon, a second transistor including an oxide semiconductor, and a capacitor; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor; a gate electrode of the first transistor is electrically connected to one electrode of the capacitance element; the capacitance element has a function of holding a potential of a gate electrode of the first transistor, the second transistor is a semiconductor device having a function of holding a potential of a gate electrode of the first transistor, a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the second insulating layer and a region in contact with a top surface of the first conductive layer, the second conductive layer functioning as one of a source electrode and a drain electrode of the second transistor; an oxide semiconductor layer having a region located above the second insulating layer and including a channel formation region of the second transistor; a third insulating layer having a region in contact with an upper surface of the second conductive layer; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having a region located above the second conductive layer and functioning as the other electrode of the capacitor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the fourth conductive layer; the third conductive layer and the fourth conductive layer have the same material; the second conductive layer has a first region, the upper surface of which is in contact with the third insulating layer, and a second region, the upper surface of which is not in contact with the third insulating layer; the first region of the second conductive layer has an overlap with the third conductive layer; the second region of the second conductive layer has an overlap with the fourth conductive layer; the first conductive layer has a region overlapping with the fourth conductive layer without the third insulating layer therebetween.

4. A plurality of circuits arranged in a matrix form are included, one of the circuits includes at least a first transistor including silicon, a second transistor including an oxide semiconductor, and a capacitor; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor; a gate electrode of the first transistor is electrically connected to one electrode of the capacitance element; the capacitance element has a function of holding a potential of a gate electrode of the first transistor, the second transistor is a semiconductor device having a function of holding a potential of a gate electrode of the first transistor, a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the second insulating layer and a region in contact with a top surface of the first conductive layer, the second conductive layer functioning as one of a source electrode and a drain electrode of the second transistor; an oxide semiconductor layer having a region located above the second insulating layer and including a channel formation region of the second transistor; a third insulating layer having a region in contact with an upper surface of the second conductive layer; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having a region located above the second conductive layer and functioning as the other electrode of the capacitor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the fourth conductive layer; the third conductive layer and the fourth conductive layer have the same material; the second conductive layer has a first region, the upper surface of which is in contact with the third insulating layer, and a second region, the upper surface of which is not in contact with the third insulating layer; the first region of the second conductive layer has an overlap with the third conductive layer; the second region of the second conductive layer has an overlap with the fourth conductive layer; the first transistor has a channel length direction intersecting a channel length direction of the second transistor; the first conductive layer has a region overlapping with the fourth conductive layer without the third insulating layer therebetween.

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