Pixel driving circuit and driving method for the same, and display panel

Abstract

SOLUTION: The present invention provides a pixel driving circuit and a driving method for the same, and a display panel. The pixel driving circuit includes a light-emitting element, a driving transistor, a pulse amplitude modulation module, and a pulse width modulation module that are electrically connected. The driving transistor is configured to generate driving current in order to drive to cause the light-emitting element to emit light. The pulse amplitude modulation module is configured to output an amplitude modulation voltage to the driving transistor in order to control an amplitude value of the driving current. The pulse width modulation module is configured to control a time for which the driving transistor outputs the driving current on the basis of a scan voltage.EFFECT: By combining the pulse amplitude modulation module and the pulse width modulation module, the uniformity of a display screen can be compensated and the arrangement of a feed forward circuit is no longer necessary, thus, this is advantageous in reducing the consumption power. The display panel includes the pixel driving circuit.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] The present application relates to the field of display technology, and more particularly to a pixel driving circuit and a driving method thereof, and a display panel. [Background technology]

[0002] Display panels using micro LEDs or sub-millimeter LEDs to realize Direct View technology have a technical problem of poor uniformity in low gray levels. To improve the problem of poor uniformity in low gray levels, a feedforward circuit is usually used to compensate for it. However, the power consumption of the feedforward circuit is high. Summary of the Invention [Problem to be solved by the invention]

[0003] The embodiments of the present invention provide a pixel driving circuit and a driving method thereof, and a display panel, which can improve the uniformity of the display screen and reduce power consumption. [Means for solving the problem]

[0004] An embodiment of the present invention provides a pixel driving circuit, comprising: a light emitting element, a driving transistor, a pulse amplitude modulation module, and a pulse width modulation module. The light emitting element is electrically connected to a first node and a first voltage terminal, respectively. The driving transistor is electrically connected to the first node, a second node, and a second voltage terminal, respectively, and is configured to generate a driving current to drive the light emitting element to emit light. The pulse amplitude modulation module is electrically connected to the driving transistor, and the pulse amplitude modulation module is configured to output an amplitude modulation voltage to the driving transistor to control an amplitude value of the driving current. The pulse width modulation module is electrically connected to the second node, the second voltage terminal, and the pulse amplitude modulation module, respectively, and the pulse width modulation module is configured to control a time when the driving transistor outputs the driving current based on a scanning voltage.

[0005] Preferably, in some embodiments of the present invention, a control terminal of the driving transistor is electrically connected to the second node, an input terminal of the driving transistor is electrically connected to the light-emitting element, and an output terminal of the driving transistor is electrically connected to the second voltage terminal.

[0006] In some embodiments of the present invention, the pulse amplitude modulation module includes a first compensation transistor, a first reset transistor, a first data transistor, a first capacitor, and a second capacitor. The control terminal of the first compensation transistor is electrically connected to a compensation control line, the input terminal of the first compensation transistor is electrically connected to the first node, and the output terminal of the first compensation transistor is electrically connected to the second node. The control terminal of the first reset transistor is electrically connected to a first reset control line, the input terminal of the first reset transistor is electrically connected to the second voltage terminal, and the output terminal of the first reset transistor is electrically connected to a third node. The control terminal of the first data transistor is electrically connected to a pulse amplitude control line, the input terminal of the first data transistor is electrically connected to a data line, and the output terminal of the first data transistor is electrically connected to the third node. The first capacitor is connected in series between the second node and the second voltage terminal, and the second capacitor is connected in series between the second node and the third node.

[0007] Preferably, in some embodiments of the present invention, the pulse amplitude modulation module further includes a second reset transistor, a control terminal of the second reset transistor electrically connected to a second reset control line, an input terminal of the second reset transistor electrically connected to the data line, and an output terminal of the second reset transistor electrically connected to a second node.

[0008] Preferably, in some embodiments of the present invention, a control terminal of the first reset transistor is electrically connected to a control terminal of the second reset transistor by the first reset control line. Preferably, a control terminal of the first reset transistor is electrically connected to a control terminal of the first compensation transistor by the first reset control line.

[0009] Preferably, in some embodiments of the present invention, the pulse width modulation module includes a first switching transistor, a second switching transistor, a second compensation transistor, a third reset transistor, a second data transistor, a third capacitor, and a fourth capacitor. The control terminal of the first switching transistor is electrically connected to a light emission control line, and the output terminal of the first switching transistor is electrically connected to the second node. The input terminal of the second switching transistor is electrically connected to the second voltage terminal, and the output terminal of the second switching transistor is electrically connected to the input terminal of the first switching transistor. The control terminal of the second compensation transistor is electrically connected to the compensation control line, and the input terminal and the output terminal of the second compensation transistor are electrically connected to the output terminal and the control terminal of the second switching transistor, respectively. The control terminal of the third reset transistor is electrically connected to the control terminal of the second compensation transistor, the input terminal of the third reset transistor is electrically connected to the second voltage terminal, and the output terminal of the third reset transistor is electrically connected to a fourth node. A control terminal of the second data transistor is electrically connected to a pulse width control line, an input terminal of the second data transistor is electrically connected to the data line, and an output terminal of the second data transistor is electrically connected to the fourth node. The third capacitor is connected in series between the fourth node and the control terminal of the second switching transistor, and the fourth capacitor is connected in series between a scan control line transmitting the scan voltage and the fourth node.

[0010] Preferably, in some embodiments of the present invention, the pulse width modulation module further includes a fourth reset transistor, a control terminal of the fourth reset transistor electrically connected to the second reset control line, an input terminal of the fourth reset transistor electrically connected to the data line, and an output terminal of the fourth reset transistor electrically connected to the control terminal of the second switching transistor.

[0011] Preferably, in some embodiments of the present invention, the first voltage signal transmitted by the first voltage terminal has a first voltage value during a period when the first switching transistor is turned on, and the first voltage signal has a second voltage value during a period when the first switching transistor is turned off, where the first voltage value is greater than the second voltage value.

[0012] Preferably, in some embodiments of the present invention, the pixel driving circuit further includes a third switching transistor, a control terminal of the third switching transistor is electrically connected to a light emitting control line, and an input terminal and an output terminal of the third switching transistor are electrically connected to the first voltage terminal and the light emitting element, respectively.

[0013] An embodiment of the present invention provides a pixel driving circuit driving method used for driving any one of the pixel driving circuits described above, the pixel driving circuit driving method including: transmitting a pulse amplitude modulation voltage to the driving transistor by the pulse amplitude modulation module, so as to cause the driving transistor to control an amplitude value of the driving current according to the pulse amplitude modulation voltage, and receiving a scanning voltage by the pulse width modulation module, so as to control a timing at which the driving transistor stops outputting the driving current and to control a time at which the driving transistor outputs the driving current.

[0014] The present invention further provides a display panel, which includes any one of the pixel driving circuits described above.

[0015] The present invention provides a pixel driving circuit and its driving method, and a display panel, the pixel driving circuit includes a light emitting element, a driving transistor, a pulse amplitude modulation module, and a pulse width modulation module. The driving transistor is electrically connected to the light emitting element, the pulse amplitude modulation module is electrically connected to the driving transistor, and the pulse width modulation module is electrically connected to the driving transistor and the pulse amplitude modulation module. The driving transistor generates a driving current to drive the light emitting element to emit light, and the pulse amplitude modulation module is configured to output an amplitude modulation voltage to the driving transistor to control the amplitude value of the driving current. The pulse width modulation module is configured to control the time when the driving transistor outputs the driving current according to the scanning voltage. The combination of the pulse amplitude modulation module and the pulse width modulation module realizes compensation for the uniformity of the display screen, does not require the placement of a feedforward circuit, and is favorable for reducing power consumption. [Brief description of the drawings]

[0016] In order to more clearly explain the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly described below. However, the drawings in the following description are only some embodiments of the present invention, and it is obvious to those skilled in the art that other drawings can be obtained from these drawings without any creative efforts.

[0017] [Figure 1A] FIG. 2 is a schematic diagram showing a structure of a pixel driving circuit according to an embodiment of the present invention. [Figure 1B] FIG. 2 is a schematic diagram showing a structure of a pixel driving circuit according to an embodiment of the present invention. [Figure 1C] FIG. 2 is a schematic diagram showing a structure of a pixel driving circuit according to an embodiment of the present invention. [Figure 1D] FIG. 2 is a schematic diagram showing a structure of a pixel driving circuit according to an embodiment of the present invention. [Figure 1E] FIG. 2 is a schematic diagram showing a structure of a pixel driving circuit according to an embodiment of the present invention. [Figure 2A] FIG. 4 is a schematic diagram showing timing according to an embodiment of the present invention. [Figure 2B] FIG. 4 is a schematic diagram showing timing according to an embodiment of the present invention. [Figure 2C] FIG. 4 is a schematic diagram showing timing according to an embodiment of the present invention. [Diagram 3] 1 is a schematic diagram showing a structure of a display panel according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, but it is clear that the described embodiments are only some of the embodiments of the present invention and are not all of the embodiments. All other embodiments that a person skilled in the art can obtain without inventive efforts based on the embodiments of the present invention belong to the protection scope of the present invention. It should be understood that the specific embodiments described in this specification are merely for illustrating and explaining the present invention and are not intended to limit the present application. In the present invention, directional terms such as "upper" and "lower" usually mean upper and lower in the actual use or operation state, unless otherwise stated, specifically in the drawing direction of the drawing. Meanwhile, "inner" and "outer" refer to the contour of the device.

[0019] 1A to 1E are schematic diagrams illustrating the structure of a pixel driving circuit according to an embodiment of the present invention. The present invention provides a pixel driving circuit, which includes a light emitting element Pi, a driving module 100, a pulse amplitude modulation module 200, and a pulse width modulation module 300.

[0020] The light emitting element Pi is electrically connected to a first node N1 and a first voltage terminal VDD, and preferably, the anode of the light emitting element Pi is electrically connected to the first voltage terminal VDD, and the cathode of the light emitting element Pi is electrically connected to the first node N1.

[0021] Preferably, the light emitting elements Pi include at least one of an organic light emitting diode, a sub-millimeter light emitting diode, and a micro light emitting diode.

[0022] The driving module 100 is electrically connected to the first node N1, the second node N2, and a second voltage terminal VSS, and is configured to generate a driving current to drive the light emitting element Pi to emit light.

[0023] Preferably, still referring to Figures 1B to 1E, the driving module 100 includes a driving transistor Tdr, a control terminal of the driving transistor Tdr electrically connected to the second node N2, an input terminal of the driving transistor Tdr electrically connected to the light-emitting element Pi, and an output terminal of the driving transistor Tdr electrically connected to the second voltage terminal VSS.

[0024] The pulse amplitude modulation module 200 is electrically connected to the driving transistor Tdr, and the pulse amplitude modulation module 200 is configured to transmit a pulse amplitude modulation voltage VPAM to the driving transistor Tdr based on a pulse amplitude control signal PAC, thereby causing the driving transistor Tdr to control the amplitude value of the driving current based on the pulse amplitude modulation voltage VPAM.

[0025] Preferably, the pulse amplitude modulation module 200 includes a first compensation unit and a first data unit. The first compensation unit is electrically connected to the driving module 100, and the first compensation unit is configured to detect and compensate the threshold voltage of the driving transistor Tdr. The first data unit transmits the pulse amplitude modulation voltage VPAM to the driving module 100 according to the pulse amplitude control signal PAC by the first compensation unit being electrically connected to the driving module 100.

[0026] Preferably, with continued reference to FIGS. 1A to 1E, the first compensation unit includes a first compensation transistor Tc1, a first reset transistor Ti1, a first capacitor C1 and a second capacitor C2.

[0027] The control terminal of the first compensation transistor Tc1 is electrically connected to a compensation control line CoL, the input terminal of the first compensation transistor Tc1 is electrically connected to the first node N1, and the output terminal of the first compensation transistor Tc1 is electrically connected to the second node N2. The first compensation transistor Tc1 connects the driving transistor Tdr to be in a diode type according to a compensation control signal Comp transmitted by the compensation control line CoL.

[0028] 1B, the control terminal of the first reset transistor Ti1 is electrically connected to a first reset control line VIL, the input terminal of the first reset transistor Ti1 is electrically connected to the second voltage terminal VSS, and the output terminal of the first reset transistor Ti1 is electrically connected to a third node N3. The first reset transistor Ti1 is configured to reset the potential of the third node N3 by transmitting a second voltage signal Vss output by the second voltage terminal VSS to the third node N3 based on a first reset control signal VI1 transmitted by the first reset control line VIL.

[0029] Preferably, during a reset period in which the first node N1 is reset and during a detection and compensation period in which the threshold voltage of the driving transistor Tdr is detected and compensated, the first reset control signal VI1 can control the first reset transistor Ti1 to maintain an on state, thereby stabilizing the potential of the second node N2 while erasing the potential information of the second node N2 written in the previous frame, preventing the threshold voltage of the driving transistor Tdr from being written to the second node N2, and completely compensating for the threshold voltage of the driving transistor Tdr during a light emission period in which the driving transistor Tdr drives the light emitting element Pi to emit light.

[0030] Preferably, in order to reduce the number of signals applied by the pixel driving circuit, reduce the number of signal lines used by the pixel driving circuit, and reduce the layout space, the control terminal of the first reset transistor Ti1 is electrically connected to the control terminal of the first compensation transistor Tc1 by the first reset control line VIL, so that the first reset transistor Ti1 and the first compensation transistor Tc1 are turned on or off based on the same control signal (i.e., the first reset transistor Ti1 and the first compensation transistor Tc1 are both turned on or off based on the compensation control signal Comp), as shown in FIG. 1C.

[0031] The first capacitor C1 is connected in series between the second node N2 and the second voltage terminal VSS, and the second capacitor C2 is connected in series between the second node N2 and the third node N3. The first capacitor C1 and the second capacitor C2 are configured to store a threshold voltage of the driving transistor Tdr when the first reset transistor Ti1 and the first compensation transistor Tc1 are turned on, so that during the light emission period, the threshold voltage of the driving transistor Tdr stored in the first capacitor C1 and the second capacitor C2 is used to realize compensation for the threshold voltage of the driving transistor Tdr, and the driving current generated by the driving transistor Tdr does not depend on the threshold voltage of the driving transistor Tdr, improving the luminance uniformity of the light emitting element Pi.

[0032] 1A to 1E, the pulse amplitude modulation module 200 further includes a second reset transistor Ti2, the control terminal of the second reset transistor Ti2 is electrically connected to a second reset control line RESL, the input terminal of the second reset transistor Ti2 is electrically connected to a data line DL, and the output terminal of the second reset transistor Ti2 is electrically connected to a second node N2. The second reset transistor Ti2 is configured to reset the potential of the second node N2 by transmitting a first reset voltage Data_0 to the second node N2 according to a second reset control signal Res transmitted by the second reset control line RESL, thereby erasing the potential information of the previous frame remaining in the second node N2. Here, the first reset voltage Data_0 may be transmitted by the data line DL.

[0033] Preferably, in order to reduce the number of signals applied by the pixel driving circuit, reduce the number of signal lines used by the pixel driving circuit, and reduce the layout space, the control terminal of the first reset transistor Ti1 is further electrically connected to the control terminal of the second reset transistor Ti2 by the first reset control line VIL, so that the first reset transistor Ti1 and the second reset transistor Ti2 are turned on or off based on the same control signal (i.e., the first reset transistor Ti1 and the second reset transistor Ti2 are both turned on or off based on a second reset control signal Res), as shown in FIG. 1D.

[0034] 1A to 1E, the first data unit includes a first data transistor Td1. A control terminal of the first data transistor Td1 is electrically connected to a pulse amplitude control line PACL, an input terminal of the first data transistor Td1 is electrically connected to a data line DL, and an output terminal of the first data transistor Td1 is electrically connected to the third node N3. The first data transistor Td1 transmits a pulse amplitude modulation voltage VPAM transmitted by the data line DL to the third node N3 based on a pulse amplitude control signal PAC transmitted by the pulse amplitude control line PACL, and is coupled to the potential of the second node N2 by a second capacitor C2, thereby controlling an on-state and an on-level of the driving transistor Tdr.

[0035] Continuing to refer to FIGS. 1A to 1E, the pulse width modulation module 300 is electrically connected to the second node N2, the second voltage terminal VSS, and the pulse amplitude modulation module 200, and the pulse width modulation module 300 is configured to control the time when the driving transistor Tdr outputs a driving current based on a scan voltage Sweep.

[0036] Preferably, the pulse width modulation module 300 includes a first switching unit, a second switching unit, a second compensation unit, a second data unit, and a scanning unit, which are electrically connected to each other. The first switching unit realizes that the second switching unit is electrically connected to the second node N2 according to a light emission control signal EM. The second switching unit is configured to transmit the second voltage signal Vss to the first switching unit, the second compensation unit is configured to detect and compensate a threshold voltage of a second switching transistor Ts2 included in the second switching unit, and the second data unit transmits a pulse width modulation voltage VPWM to the second switching unit according to a pulse width control signal PWC by the second compensation unit being electrically connected to the second switching unit.

[0037] Preferably, with continued reference to Figures 1A to 1E, the first switching unit includes a first switching transistor Ts1, a control terminal of the first switching transistor Ts1 is electrically connected to an emission control line EML, and an output terminal of the first switching transistor Ts1 is electrically connected to the second node N2.

[0038] Preferably, with continued reference to Figures 1A to 1E, the second switching unit includes a second switching transistor Ts2, an input terminal of the second switching transistor Ts2 is electrically connected to the second voltage terminal VSS, an output terminal of the second switching transistor Ts2 is electrically connected to the input terminal of the first switching transistor Ts1, and the second switching transistor Ts2 is configured to transmit the second voltage signal Vss to the input terminal of the first switching transistor Ts1.

[0039] Preferably, with continued reference to FIGS. 1A to 1E, the second compensation unit includes a second compensation transistor Tc2, a third reset transistor Ti3, a third capacitor C3 and a fourth capacitor C4.

[0040] The control terminal of the second compensation transistor Tc2 is electrically connected to the compensation control line CoL, and the input terminal and the output terminal of the second compensation transistor Tc2 are electrically connected to the output terminal and the control terminal of the second switching transistor Ts2, respectively. The second compensation transistor Tc2 is configured to connect the second switching transistor Ts2 in a diode type according to a compensation control signal Comp transmitted by the compensation control line CoL.

[0041] A control terminal of the third reset transistor Ti3 is electrically connected to a control terminal of the second compensation transistor Tc2, an input terminal of the third reset transistor Ti3 is electrically connected to the second voltage terminal VSS, and an output terminal of the third reset transistor Ti3 is electrically connected to a fourth node N4. The third reset transistor Ti3 is configured to reset the potential of the fourth node N4 by transmitting the second voltage signal Vss to the fourth node N4 based on the compensation control signal Comp.

[0042] The third capacitor C3 is connected in series between the fourth node N4 and the control terminal of the second switching transistor Ts2, and the fourth capacitor C4 is connected in series between the scan control line SWL of the scan voltage Sweep and the fourth node N4.

[0043] 1A to 1E, the second data unit preferably includes a second data transistor Td2, a control terminal of the second data transistor Td2 is electrically connected to a pulse width control line PWCL, an input terminal of the second data transistor Td2 is electrically connected to the data line DL, and an output terminal of the second data transistor Td2 is electrically connected to the fourth node N4. The second data transistor Td2 transmits a pulse width modulation voltage VPWM transmitted by the data line DL to the fourth node N4 based on a pulse width control signal PWC transmitted by the pulse width control line PWCL, and is coupled to the potential of the control terminal of the second switching transistor Ts2 by the third capacitor C3, thereby controlling an on state and an on level of the second switching transistor Ts2.

[0044] 1A to 1E, the pulse width modulation module 300 further includes a fourth reset transistor Ti4, a control terminal of the fourth reset transistor Ti4 is electrically connected to the second reset control line RESL, an input terminal of the fourth reset transistor Ti4 is electrically connected to the data line DL, and an output terminal of the fourth reset transistor Ti4 is electrically connected to the control terminal of the second switching transistor Ts2. The fourth reset transistor Ti4 is configured to reset the potential of the control terminal of the second switching transistor Ts2 by transmitting a first reset voltage Data_0 to the control terminal of the second switching transistor Ts2 according to the second reset control signal Res.

[0045] 1B to 1D, the pixel driving circuit further includes a third switching transistor Ts3, a control terminal of the third switching transistor Ts3 is electrically connected to an emission control line EML, and an input terminal and an output terminal of the third switching transistor Ts3 are electrically connected to the first voltage terminal VDD and the light emitting element Pi, respectively. The third switching transistor Ts3 is configured to control the first voltage terminal VDD based on the emission control signal EM to electrically connect to the light emitting element Pi.

[0046] 1E, preferably, the first voltage terminal VDD is directly electrically connected to the anode of the light emitting element Pi. In order to prevent erroneous light emission of the light emitting element Pi, the first voltage signal Vdd transmitted by the first voltage terminal VDD has a first voltage value during a period in which the first switching transistor Ts1 is turned on (i.e., a light emitting period), and the first voltage signal Vdd has a second voltage value during a period in which the first switching transistor Ts1 is turned off (i.e., a non-light emitting period). Here, the first voltage value is greater than the second voltage value.

[0047] As can be understood, when the first voltage terminal VDD is directly electrically connected to the anode of the light-emitting element Pi, the control terminal of the first reset transistor Ti1 may be electrically connected to a first reset control line VIL, the control terminal of the first reset transistor Ti1 may be electrically connected to the control terminal of the first compensation transistor Tc1, and the control terminal of the first reset transistor Ti1 may be electrically connected to the control terminal of the second reset transistor Ti2.

[0048] The present invention provides a pixel driving circuit driving method for driving any one of the pixel driving circuits, which includes: the pulse amplitude modulation module 200 transmits a pulse amplitude modulation voltage VPAM to the driving module 100, so that the driving module 100 controls the amplitude value of the driving current according to the pulse amplitude modulation voltage VPAM; the pulse width modulation module 300 receives a scan voltage Sweep, so that the driving transistor Tdr controls the timing at which the driving current is stopped and the driving transistor Tdr controls the time at which the driving current is output.

[0049] Figures 2A to 2C are schematic diagrams showing timing according to an embodiment of the invention, where Figure 2A is a timing chart corresponding to the pixel driving circuit shown in Figure 1B, Figure 2B is a timing chart corresponding to the pixel driving circuit shown in Figures 1C to 1D, and Figure 2C is a timing chart corresponding to the pixel driving circuit shown in Figure 1E.

[0050] The operation principle of the pixel driving circuit shown in Figures 1A to 1E, in which each transistor included in the pixel driving circuit is an N-type, will be described with reference to the timing charts shown in Figures 2A to 2C. Here, the operation cycle for driving the pixel driving circuit includes a reset period t1, a detection compensation period t2, a data writing period, and a light emission period t4.

[0051] In the reset period t1, the second reset control signal Res is at a high level, and the emission control signal EM, the pulse width control signal PWC, the pulse amplitude control signal PAC, and the compensation control signal Comp are at a low level. When the second reset transistor Ti2 and the fourth reset transistor Ti4 are turned on, the data line DL transmits a first reset voltage Data_0 to the control terminal of the second switching transistor Ts2 (i.e., the fifth node N5) and the control terminal of the driving transistor Tdr (i.e., the second node N2), so that the potential of the fifth node N5 and the potential of the second node N2 become the first reset voltage Data_0, thereby realizing the reset of the potential of the control terminal of the second switching transistor Ts2 and the control terminal of the driving transistor Tdr. Since the first reset voltage Data_0 is at a high level, the second switching transistor Ts2 and the driving transistor Tdr are turned on.

[0052] Here, in the pixel driving circuit shown in FIG. 1B, the first reset control signal VI1 is at a high level. In the pixel driving circuit shown in FIG. 1D, the first reset control signal VI1 (i.e., the second reset control signal Res) is at a high level. In the pixel driving circuit shown in FIG. 1B and FIG. 1D, the first reset transistor Ti1 is turned on based on the first reset control signal VI1, and the second voltage signal Vss is transmitted to the third node N3 to reset the third node N3 and erase the potential information of the third node N3 remaining in the previous frame. In the pixel driving circuit shown in FIG. 1C, the first reset control signal VI1 (i.e., the compensation control signal Comp) is at a low level, and the first reset transistor Ti1 is turned off.

[0053] In the detection compensation period t2, the compensation control signal Comp is at a high level, the second reset control signal Res, the emission control signal EM, the pulse width control signal PWC, and the pulse amplitude control signal PAC are at a low level, and the first compensation transistor Tc1, the second compensation transistor Tc2, and the third reset transistor Ti3 are turned on based on the compensation control signal Comp. Since the driving transistor Tdr and the second switching transistor Ts2 have already been turned on in the reset period t1, the potential of the second node N2 drops due to the second voltage signal Vss, and the driving transistor Tdr is turned off until the voltage of the second node N2 becomes equal to the sum of the second voltage signal Vss and the threshold voltage of the driving transistor Tdr (i.e., VN2=Vss+Vth_Tdr, where Vth_Tdr represents the threshold voltage of the driving transistor Tdr). As the third reset transistor Ti3 is turned on, the fourth node N4 is reset by the second voltage signal Vss, the potential of the control terminal of the second switching transistor Ts2 drops by the second voltage signal Vss, and the second switching transistor Ts2 is turned off until the voltage of the control terminal of the second switching transistor Ts2 becomes equal to the sum of the second voltage signal Vss and the threshold voltage of the second switching transistor Ts2 (i.e., VN5=Vss+Vth_Ts2, where Vth_Ts2 represents the threshold voltage of the second switching transistor Ts2).

[0054] Here, in the pixel driving circuit shown in FIG. 1B, the first reset control signal VI1 is at a high level, and the first reset transistor Ti1 remains on, thereby constantly resetting the third node N3 by the second voltage signal Vss, erasing the potential information left by the second node N2 in the previous frame, and preventing the threshold voltage of the driving transistor Tdr from being written to the second node N2, ensuring that the driving transistor Tdr can be fully compensated in the light emitting period t4. In the pixel driving circuit shown in FIG. 1C, the first reset control signal VI1 (i.e., the compensation control signal Comp) is at a high level, and the first reset transistor Ti1 is turned on, and the third node N3 is reset by the second voltage signal Vss, thereby erasing the potential information left by the third node N3 in the previous frame. In the pixel driving circuit shown in FIG. 1D, the first reset control signal VI1 (i.e., the second reset control signal Res) is at a low level, and the first reset transistor Ti1 is turned off, causing the third node N3 to be in a floating state. Meanwhile, when the voltage of the second node N2 changes from Data_0 in the reset period t1 to Vth_Tdr-Data_0+Vss in the detection compensation period t2, the voltage difference between the third node N3 and the second node N2 needs to be constant, so the voltage of the third node N3 changes from Vss to Vth_Tdr-Data_0+2Vss due to the influence of the voltage change of the second node N2.

[0055] The data write period includes a pulse width modulated voltage write period t31 and a pulse amplitude modulated voltage write period t32.

[0056] During the pulse-width modulation voltage writing period t31, the pulse-width control signal PWC is at a high level, and the second reset control signal Res, the emission control signal EM, the pulse amplitude control signal PAC, and the compensation control signal Comp are at a low level. The second data transistor Td2 is turned on based on the pulse-width control signal PWC, and the pulse-width modulation voltage VPWM is transmitted to the fourth node N4 by the data line DL. Since the scan voltage Sweep transmitted by the scan control line SWL is SWEEP_0, the voltage difference across the fourth capacitor C4 is VPWM-SWEEP_0. Thereafter, the pulse-width control signal PWC goes to a low level, the second data transistor Td2 is turned off, and the voltage difference across the fourth capacitor C4 is maintained at VPWM-SWEEP_0. Next, the scan voltage drops from SWEEP_0 to 0V, so that the voltage of the fourth node N4 is coupled by the fourth capacitor C4 and changes from VPWM to VPWM-SWEEP_0, causing the potential difference between the control terminal of the second switching transistor Ts2 and the scan control line SWL to be Vth_Ts2+Vss+VPWM-SWEEP_0. Here, in order not to turn on the second switching transistor Ts2, Vth_Ts2+Vss+VPWM-SWEEP_0 needs to be smaller than the threshold voltage of the second switching transistor Ts2.

[0057] During the voltage write period t32 of the pulse amplitude modulation, the pulse amplitude control signal PAC is at a high level, and the second reset control signal Res, the emission control signal EM, the pulse width control signal PWC, and the compensation control signal Comp are at a low level. The first data transistor Td1 is turned on based on the pulse amplitude control signal PAC, and the pulse amplitude modulation voltage VPAM is transmitted to the third node N3 by the data line DL, thereby causing the voltage of the third node N3 to be C4*VPAM / (C1+C4), and the potential of the second node N2 is coupled by the second capacitor C2 to be Vth_Tdr+C4*VPAM / (C1+C4).

[0058] Here, in the pixel driving circuit shown in FIG. 1B, the first reset control signal VI1 is at a low level during the data write period, and the first reset transistor Ti1 is turned off. In the pixel driving circuit shown in FIG. 1C, the first reset control signal VI1 (i.e., the compensation control signal Comp) is at a low level, and the first reset transistor Ti1 is turned off. In the pixel driving circuit shown in FIG. 1D, the first reset control signal VI1 (i.e., the second reset control signal Res) is at a low level, the first reset transistor Ti1 is turned off, the voltage of the third node N3 is VPAM during the voltage write period t32 of the pulse amplitude modulation, the voltage change value of the third node N3 with respect to the reset period t1 during the data write period is VPAM-Vth_Tdr+Data_0-2Vss, and the change value of the second node N2 is Vth_Tdr+Vss+C4*voltage change value of the third node / (C1+C4).

[0059] In the pixel driving circuit shown in FIG. 1E, in order to avoid erroneous emission of the light-emitting element Pi, the first voltage transmitted by the first voltage terminal VDD has a second voltage value in the reset period t1, the detection compensation period t2, and the data writing period.

[0060] In the light-emitting period t4, the light-emitting control signal EM is at a high level, the second reset control signal Res, the pulse width control signal PWC, the compensation control signal Comp, and the pulse amplitude control signal PAC are at a low level, and the first switching transistor Ts1 is turned on. In the pixel driving circuit shown in Figures 1B to 1D, the third switching transistor Ts3 is turned on, and the driving transistor Tdr generates a driving current to drive the light-emitting element Pi to emit light. In the pixel driving circuit shown in Figure 1E, the first voltage signal Vdd transmitted by the first voltage terminal VDD has a first voltage value, whereby the driving transistor Tdr generates a driving current to drive the light-emitting element Pi to emit light.

[0061] Here, in the light emission period t4, the driving transistor Tdr operates in the saturation region. In the pixel driving circuit shown in FIG. 1B, the driving current I transmitted through the driving transistor Tdr is [μCox(W / L)(Vg-Vs-Vth)^2] / 2=[μCox(W / L)(C4*VPAM / (C1+C4)-Vss)^2] / 2. Therefore, the driving current does not depend on the threshold voltage of the driving transistor Tdr and the threshold voltage of the second switching transistor Ts2. Correspondingly, it can be seen that the driving current corresponding to the pixel driving circuit shown in FIG. 1C to FIG. 1E does not depend on the threshold voltage of the driving transistor Tdr.

[0062] The scan voltage Sweep may be gradually increased in the light emitting period t4, so that the potential of the control terminal of the second switching transistor Ts2 is continuously increased until the potential of the control terminal of the second switching transistor Ts2 turns on the second switching transistor Ts2. The second voltage signal Vss transmitted by the second voltage terminal VSS is transmitted to the second node N2 by the second switching transistor Ts2 and the first switching transistor Ts1, so as to turn off the driving transistor Tdr and control the light emitting element Pi to stop emitting light.

[0063] The pixel driving circuit and driving method thereof provided by the embodiments of the present invention combine pulse amplitude modulation and pulse amplitude modulation to prevent the driving current from being affected by the threshold voltage, thereby improving the uniformity of the display screen and eliminating the feedforward circuit, which is favorable for maintaining relatively low power consumption, and reducing the impact of process differences and long-term driving sensitivity on the display effect.

[0064] FIG. 3 is a schematic diagram showing the structure of a display panel according to an embodiment of the present invention, and the present invention further provides a display panel, which includes any one of the pixel driving circuits described above.

[0065] Preferably, the display panel includes a passive light-emitting display panel such as a liquid crystal display panel, and the light-emitting elements Pi included in the pixel driving circuit can be used for backlighting.

[0066] Preferably, the display panel includes a self-emissive display panel, and the light-emitting element Pi included in the pixel driving circuit can be used for a sub-pixel.

[0067] In this specification, the principle and embodiments of the present invention are described using specific examples, but the description of the above examples is intended only to help understand the method of the present invention and its core idea. In addition, those skilled in the art can change the specific embodiments and application scope according to the idea of ​​the present invention. In summary, it should be understood that the contents of this specification are not intended to limit the present invention. [Explanation of symbols]

[0068] 100: Drive module 200: Pulse Amplitude Modulation Module 300: Pulse Width Modulation Module C1: First capacitor C2: Second capacitor C3: Third capacitor C4: Fourth capacitor N1: First node N2: Second node N3: Third node N4: Fourth node N5: 5th node Pi: Light emitting element Tc1: First compensation transistor Tc2: Second compensation transistor Td1: First data transistor Td2: Second data transistor Tdr: Drive transistor Ti1: First reset transistor Ti2: Second reset transistor Ti3: Third reset transistor Ti4: Fourth reset transistor Ts1: First switching transistor Ts2: Second switching transistor Ts3: Third switching transistor

Claims

1. a light emitting element electrically connected to the first node and the first voltage terminal, a driving transistor electrically connected to the first node, the second node, and a second voltage terminal, respectively, and configured to generate a driving current to drive the light emitting element to emit light; a pulse amplitude modulation module electrically connected to the driving transistor and configured to output an amplitude modulation voltage to the driving transistor to control an amplitude value of the driving current; a pulse width modulation module electrically connected to the second node, the second voltage terminal, and the pulse amplitude modulation module, respectively, and configured to control a time when the driving transistor outputs the driving current based on a scanning voltage; Pixel driving circuit.

2. a control terminal of the driving transistor is electrically connected to the second node, an input terminal of the driving transistor is electrically connected to the light emitting element, and an output terminal of the driving transistor is electrically connected to the second voltage terminal; 2. A pixel driving circuit as claimed in claim 1.

3. The pulse amplitude modulation module includes: a first compensation transistor, a control terminal of the first compensation transistor being electrically connected to a compensation control line, an input terminal of the first compensation transistor being electrically connected to the first node, and an output terminal of the first compensation transistor being electrically connected to the second node; a first reset transistor, a control terminal of the first reset transistor being electrically connected to a first reset control line, an input terminal of the first reset transistor being electrically connected to the second voltage terminal, and an output terminal of the first reset transistor being electrically connected to a third node; a first data transistor, a control terminal of the first data transistor being electrically connected to a pulse amplitude control line, an input terminal of the first data transistor being electrically connected to a data line, and an output terminal of the first data transistor being electrically connected to the third node; a first capacitor connected in series between the second node and the second voltage terminal; a second capacitor connected in series between the second node and the third node; 3. A pixel driving circuit as claimed in claim 2.

4. the pulse amplitude modulation module further includes a second reset transistor; a control terminal of the second reset transistor electrically connected to a second reset control line, an input terminal of the second reset transistor electrically connected to the data line, and an output terminal of the second reset transistor electrically connected to a second node; 4. A pixel driving circuit according to claim 3.

5. a control terminal of the first reset transistor is electrically connected to a control terminal of the second reset transistor by the first reset control line, or a control terminal of the first reset transistor is electrically connected to a control terminal of the first compensation transistor by the first reset control line; 5. A pixel driving circuit according to claim 4.

6. The pulse width modulation module includes: a first switching transistor, a control terminal of the first switching transistor being electrically connected to a light emission control line and an output terminal of the first switching transistor being electrically connected to the second node; a second switching transistor, an input terminal of the second switching transistor being electrically connected to the second voltage terminal and an output terminal of the second switching transistor being electrically connected to the input terminal of the first switching transistor; a second compensation transistor, a control terminal of the second compensation transistor being electrically connected to the compensation control line, and an input terminal and an output terminal of the second compensation transistor being electrically connected to an output terminal and a control terminal of the second switching transistor, respectively; a third reset transistor, a control terminal of the third reset transistor electrically connected to the control terminal of the second compensation transistor, an input terminal of the third reset transistor electrically connected to the second voltage terminal, and an output terminal of the third reset transistor electrically connected to a fourth node; a second data transistor, a control terminal of the second data transistor being electrically connected to a pulse width control line, an input terminal of the second data transistor being electrically connected to the data line, and an output terminal of the second data transistor being electrically connected to the fourth node; a third capacitor connected in series between the fourth node and a control terminal of the second switching transistor; a fourth capacitor connected in series between a scanning control line transmitting the scanning voltage and the fourth node; 4. A pixel driving circuit according to claim 3.

7. the pulse width modulation module further includes a fourth reset transistor; a control terminal of the fourth reset transistor electrically connected to a second reset control line, an input terminal of the fourth reset transistor electrically connected to the data line, and an output terminal of the fourth reset transistor electrically connected to a control terminal of the second switching transistor; 7. A pixel driving circuit according to claim 6.

8. a first voltage signal transmitted by the first voltage terminal has a first voltage value during a period in which the first switching transistor is turned on, and the first voltage signal has a second voltage value during a period in which the first switching transistor is turned off; wherein the first voltage value is greater than the second voltage value.

7. A pixel driving circuit according to claim 6.

9. the pixel driving circuit further includes a third switching transistor; a control terminal of the third switching transistor is electrically connected to a light emission control line, and an input terminal and an output terminal of the third switching transistor are electrically connected to the first voltage terminal and the light emitting element, respectively; 2. A pixel driving circuit as claimed in claim 1.

10. A method for driving a pixel driving circuit used to drive the pixel driving circuit according to any one of claims 1 to 9, comprising the steps of: transmitting a pulse amplitude modulated voltage to the driving transistor by a pulse amplitude modulated module, so as to cause the driving transistor to control an amplitude value of a driving current according to the pulse amplitude modulated voltage; receiving a scanning voltage by a pulse width modulation module to control when the driving transistor stops outputting the driving current and to control the time when the driving transistor outputs the driving current; A method for driving a pixel driving circuit.

11. A pixel driving circuit comprising the pixel driving circuit of claim 1 . Display panel.

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