Selective passivation and selective deposition

Abstract

To provide a selective deposition method high in selectivity.SOLUTION: A method comprises: selectively depositing a material on a first surface of a base material to a second surface of a different material composition; selectively forming an inhibitor, such as a polyimide layer from a gas phase reaction substance on the first surface to the second surface; selectively depositing a target layer on the second surface from the gas phase reaction substance to the first surface. The first surface can be metal; the second surface is a dielectric; and the use of a technology described in the specification can selectively deposit a material, such as a dielectric transition metal oxide and nitride on metallic surfaces relative dielectric surfaces.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] background The present disclosure relates generally to selective deposition of a material on a first surface of a substrate against a second surface of a different material composition. [Background technology]

[0002] The shrinking of device dimensions in semiconductor manufacturing calls for new and innovative processing methods. Traditionally, patterning in semiconductor processing involves subtractive methods, where a blanket layer is deposited, masked by photolithographic techniques, and etched through openings in the mask. Further patterning is also known, where a masking step precedes the deposition of the material of interest, such as patterning using lift-off techniques or damascene processes. In most cases, expensive multi-step lithographic techniques are employed for patterning.

[0003] Selective deposition has become of increasing interest among semiconductor manufacturers because selective deposition can simplify patterning. Selective deposition can be very beneficial in a variety of ways. Significantly, selective deposition can reduce lithography steps, lowering processing costs. Selective deposition can also enhance scaling in narrow features by enabling bottom-up filling. Electrochemical deposition is a form of selective deposition that can selectively form metals on conductive elements. Chemical vapor deposition (CVD) and atomic layer deposition (ALD) are deposition techniques that are surface-sensitive techniques, and therefore have been investigated as suitable candidates for selective deposition. Selective ALD has been proposed, for example, in U.S. Pat. No. 6,391,785.

[0004] One of the challenges in selective deposition is selectivity, as often the deposition process is not high enough to achieve the selectivity goal. Surface pretreatment sometimes makes it possible to either inhibit or encourage deposition on one or both surfaces, but often such treatments themselves require lithography to apply the treatment or to remain only on the treated surfaces.

[0005] Thus, there is a need for a more practical process that achieves selective deposition. Summary of the Invention

[0006] In one aspect, a method provides selective deposition on a first surface of a substrate relative to a second surface of the substrate, the first and second surfaces having different compositions, the method comprising, in sequence, selectively forming an inhibitor layer from a gas-phase reactant on the first surface relative to the second surface, baking the inhibitor layer, and selectively depositing a layer of interest from the gas-phase reactant on the second surface relative to the passivation layer.

[0007] In some embodiments, the method further comprises treating the first and second surfaces prior to selectively forming the inhibitor layer. In some embodiments, the method comprises treating comprising exposing the substrate to a plasma. In some embodiments, treating comprises exposing the substrate to a silane, such as an alkylaminosilane. In some embodiments, treating comprises exposing the substrate to N-(trimethylsilyl)dimethylamine (TMSDMA) or trimethylchlorosilane. In some embodiments, the method further comprises cleaning the second surface to remove any inhibitor after selectively forming the inhibitor layer. In some embodiments, the method comprises cleaning comprising treating with a hydrogen plasma. In some embodiments, baking comprises heating the substrate to a temperature of about 300-400° C.

[0008] In some embodiments, the method further comprises cleaning the first and second surfaces after selectively depositing the layer of interest. In some embodiments, the cleaning comprises treating the surfaces with a hydrogen plasma. In some embodiments, the method further comprises selectively forming the inhibitor layer comprises selectively depositing an organic layer on the first surface. In some embodiments, the organic layer is a polyimide layer.

[0009] In some embodiments, the layer of interest is selectively deposited by an atomic layer deposition process. In some embodiments, the first surface comprises a metal or metallic material and the second surface comprises a dielectric material.

[0010] In some embodiments, the layer of interest comprises a metal oxide. In some embodiments, the metal oxide comprises zirconium oxide, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, or other transition metal oxides or mixtures thereof. In some embodiments, the metal oxide comprises a dielectric transition metal oxide. In some embodiments, the metal oxide is aluminum oxide. In some embodiments, the aluminum oxide is deposited using an aluminum precursor comprising trimethylaluminum (TMA), dimethylaluminum chloride, aluminum trichloride (AlCl3), dimethylaluminum isopropoxide (DMAI), or triethylaluminum (TEA). In some embodiments, the aluminum oxide is deposited using an aluminum precursor comprising a heteroleptic aluminum compound comprising an alkyl group and another ligand, such as a halide, e.g., Cl. In some embodiments, the aluminum oxide is deposited using an aluminum precursor comprising an aluminum alkyl compound comprising two different alkyl groups as ligands. In some embodiments, the aluminum compound is deposited using an aluminum precursor comprising a metalorganic aluminum compound or an organometallic aluminum compound.

[0011] In some embodiments, the layer of interest comprises a metal nitride. In some embodiments, the metal nitride is titanium nitride. In some embodiments, the titanium nitride is deposited by a vapor deposition process from TiCl4 and NH3.

[0012] In another aspect, a cluster tool is provided for selective deposition of a layer of interest on a first surface of a substrate relative to a second surface of the substrate, where the first and second surfaces have different compositions, the cluster tool including a first module configured to pretreat the substrate, a second module configured to treat the substrate with a plasma, a third module configured for deposition of an inhibitor on the first surface of the substrate relative to the second surface of the substrate, and a fourth module configured for deposition of the layer of interest.

[0013] In another aspect, a system is provided for selective deposition of a dielectric on a second surface of a substrate relative to a first surface of the substrate, the system including a first chamber configured for selective deposition of an organic passivation layer and for partial etchback of the organic passivation layer, and a second chamber configured for selective deposition of a dielectric on a second surface relative to the first surface of the substrate.

[0014] In another aspect, a system is provided for selective deposition of a film of interest on a first surface of a substrate relative to a second surface of the substrate, the system including a first chamber configured for pre-treatment of the substrate and for an etching process, a second chamber configured for selective deposition of an organic passivation layer, and a third chamber configured for selective deposition of a film of interest on the first surface of the substrate relative to the second surface of the substrate.

[0015] In some embodiments, the third chamber is further configured for a bake process. In some embodiments, the system further includes a fourth chamber configured for a bake process. [Brief description of the drawings]

[0016] [Figure 1]FIG 1A is a cross-sectional view of a portion of a substrate having first and second surfaces of different compositions according to a first embodiment. FIG 1B is a cross-sectional view of the substrate of FIG 1A after selective passivation of the first surface. FIG 1C is a cross-sectional view of the substrate of FIG 1B after selective deposition onto the second surface. FIG 1D is a cross-sectional view of the substrate of FIG 1C after removal of the passivation material from the first surface. [Diagram 2] FIG 2A is a cross-sectional view of a portion of a substrate having first and second surfaces of different compositions with a passivation barrier material formed on the second surface according to a second embodiment. FIG 2B is a cross-sectional view of the substrate of FIG 2A after selective passivation of the first surface. FIG 2C is a cross-sectional view of the substrate of FIG 2B after removal of the passivation barrier material from the second surface. FIG 2D is a cross-sectional view of the substrate of FIG 2C after selective deposition on the second surface. FIG 2E is a cross-sectional view of the substrate of FIG 2D after removal of the passivation material from the first surface. [Diagram 3] 3A is a cross-sectional view of the substrate of FIG. 2D after selectively depositing additional material on the second surface according to a third embodiment, and FIG. 3B is a cross-sectional view of the substrate of FIG. 3A after removing passivation material from the first surface. [Figure 4-1] FIG. 4A is a flow diagram generally illustrating a process for selectively depositing an organic passivation layer. [Figure 4-2] FIG. 4B is a flow diagram generally illustrating an atomic layer deposition (ALD) process for selectively depositing an organic layer. [Diagram 5] FIG. 5 is a schematic diagram of an apparatus configured for selective deposition of a polymer layer and in situ etch-back from unwanted surfaces. [Figure 6] FIG. 6 is a flow diagram generally illustrating a process for selectively depositing a dielectric layer on a second surface after selective passivation of a first surface with an organic material, according to an embodiment. [Figure 7]FIG. 7 is a flow diagram utilizing a cross-sectional view of a portion of a substrate having first and second surfaces of different compositions, generally illustrating the effect of the degree of etch back on the passivation material on the relationship between the interface of the first and second surfaces and the dielectric layer formed. [Figure 8] FIG. 8 is a flow diagram utilizing a cross-sectional view of a portion of a substrate having first and second surfaces of different compositions, generally illustrating the effect of the thickness of a passivation layer on the relationship between the interface of the first and second surfaces and the dielectric layer that is formed. [Figure 9] FIG. 9 is a flow diagram utilizing a cross-sectional view of a portion of a substrate having first and second surfaces of different compositions, generally illustrating the effect of dielectric thickness on the relationship between the interface of the first and second surfaces and the dielectric layer formed. [Figure 10-1] Figure 10A is a cross-sectional view of a portion of a substrate having planar first and second surfaces of different compositions, with a passivation layer and a dielectric layer selectively deposited on the first and second surfaces, respectively. Figure 10B is a cross-sectional view of a portion of a substrate having first and second surfaces of different compositions, with the first surface recessed relative to the second surface, with a passivation layer and a dielectric layer selectively deposited on the first and second surfaces, respectively. [Figure 10-2] Figure 10C is a cross-sectional view of a portion of a substrate having first and second surfaces of different compositions, the first surface being elevated relative to the second surface, and a passivation layer and a dielectric layer being selectively deposited on the first and second surfaces, respectively. Figure 10D is a cross-sectional view of a portion of a substrate having first and second surfaces of different compositions, the first surface being recessed relative to the second surface, and a passivation layer and a dielectric layer being selectively deposited on the first and second surfaces, respectively. [Figure 11-1] Figure 11A is a cross-sectional view of a portion of a substrate with an embedded metal feature, and Figure 11B is a cross-sectional view of the substrate of Figure 22A after formation of a metal cap that defines a first surface. [Figure 11-2]Figure 11C is a cross-sectional view of the substrate of Figure 22B after selective passivation deposition and etch-back, leaving the passivation film on the metal cap, exposing the edge of the metal cap. Figure 11D is a cross-sectional view of the substrate of Figure 22C after selectively depositing a dielectric material on the low-k surface of the substrate, where the deposited dielectric resists etching of the low-k material and overlaps the metal cap. [Figure 11-3] FIG. 11E is a cross-sectional view of the substrate of FIG. 22D after removal of the passivation layer. [Figure 12-1] FIG. 12A is a flow diagram showing a cross-sectional view of a portion of a substrate having first and second surfaces of different compositions, generally illustrating selective passivation of the first surface, etch-back to leave the passivation overlapping the second surface, and selective deposition of a dielectric etch mask onto the remainder of the second surface. [Figure 12-2] FIG. 12B is a cross-sectional view of the substrate of FIG. 23A after removing the passivation layer, leaving a gap between the first surface and a dielectric etch mask, and selectively etching the exposed low-k material in the gap and depositing it to leave a void in the substrate. [Figure 13] FIG. 13 is a flow diagram illustrating a process flow for selective deposition. [Figure 14] FIG. 14 is a flow diagram illustrating a process flow for selective deposition on three-dimensional structures such as trenches or vias. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Disclosed are methods and apparatus for selectively depositing a material on a second surface relative to a first surface, the first and second surfaces being different in material. For example, one of the surfaces can have a metallic material and the other surface can include an inorganic dielectric material. In embodiments described herein, an organic passivation layer is selectively deposited on the first surface relative to the second surface. In some embodiments, the first surface includes a metal and the second surface is a dielectric, and in other embodiments, the first surface is a dielectric and the second surface is a metal. A layer of interest is then selectively deposited on the second surface relative to the organic passivation layer. In some embodiments, the layer of interest can be an Al2O3 layer. In some embodiments, the layer of interest can be a TiN layer. Additionally, a layer can be selectively deposited on the layer of interest on the second surface relative to the organic passivation layer.

[0018] In one embodiment, the first surface comprises a metallic surface, such as an elemental metal or metal alloy, while the second surface comprises an inorganic dielectric surface, such as a low-k material. Examples of low-k materials include silicon oxide-based materials, including grown or deposited silicon dioxide, doped and / or porous oxides, native oxides on silicon, and the like. A polymer passivation layer is selectively deposited on the metallic surface relative to the inorganic dielectric surface. A layer of interest is then selectively deposited on the inorganic dielectric surface. The layer of interest may comprise a metallic element. Examples of layers of interest include dielectrics such as zirconium oxide (e.g., ZrO2), hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), titanium nitride (e.g., TiN), and titanium oxide (e.g., TiO2). A process is provided for selectively depositing such materials on silicon oxide-based surfaces relative to polymer surfaces.

[0019] In a second embodiment, the first surface comprises an inorganic dielectric surface, such as a low-k material, while the second surface comprises a metallic surface, such as an elemental metal or metal alloy. Examples of low-k materials include silicon oxide-based materials, including grown or deposited silicon dioxide, doped and / or porous oxides, native oxides on silicon, and the like. A polymeric passivation layer is selectively deposited on the inorganic dielectric surface relative to the metallic surface. Prior to depositing the polymeric passivation layer, the metallic surface may be provided with a passivation barrier layer, such as a self-assembled monolayer (SAM). The passivation barrier layer may be subsequently removed to facilitate selectivity of the polymer deposition on the inorganic dielectric surface and to allow selective deposition of a layer of interest on the metallic surface relative to the polymeric passivation layer. The layer of interest may comprise an elemental metal. Examples of layers of interest include metal layers (see, e.g., U.S. Patent No. 8,956,971, issued February 17, 2015, and U.S. Patent No. 9,112,003, issued August 18, 2015), metal nitride layers (e.g., titanium nitride), and metal oxide layers (e.g., zirconium oxide, hafnium oxide, titanium oxide, and aluminum oxide). A process is provided for selectively depositing such materials onto metallic surfaces relative to polymeric surfaces.

[0020] In a third embodiment, the process of the second embodiment is performed to provide a layer of interest selectively on a metallic surface relative to a polymer passivated inorganic dielectric surface. A further layer of interest is then selectively deposited on the layer of interest while leaving the inorganic dielectric surface passivated with a polymer. For example, the layer of interest may comprise a metallic layer, while the further layer of interest comprises a metal oxide layer (e.g. zirconium oxide, hafnium oxide, titanium oxide). A process is provided for selectively depositing such materials on metallic surfaces relative to polymer surfaces.

[0021] The polymeric passivation layer may be removed from the first surface after selectively depositing a layer of interest on the second surface. For example, an oxidation process may selectively remove the polymeric material. Conditions are chosen to avoid damage to surrounding materials on the substrate.

[0022] Also provided are embodiments that control the edge shape and edge location of selectively deposited layers relative to other features on the substrate, such as the boundary between an underlying metallic surface and a dielectric surface, thus providing control over the relative positioning of selective layer edges without the need for expensive lithographic patterning. Examples illustrate applications of such control, including where selective layers overlap with a material that minimizes deposition, where selective layers are formed with gaps that space the layer from the material that minimizes deposition, and where the edges of selective layers line up with the boundary between two underlying dissimilar materials.

[0023] Base material surface In accordance with some aspects of the present disclosure, selective deposition may be used to deposit a film of interest on a first surface relative to a second surface. The two surfaces may have different material properties that allow for selective formation of organic materials on their surfaces, such as selective deposition of a polymer layer on the first surface relative to the second surface, thereby allowing for subsequent selective deposition of a layer of interest on the second surface relative to the organic passivated first layer.

[0024] For example, in the embodiments described herein, one of the surfaces may be a conductive (e.g., metal or metallic) surface of the substrate, while the other surface may be a non-conductive (e.g., inorganic dielectric) surface of the substrate. In some embodiments, the non-conductive surface comprises -OH groups, such as a silicon oxide based surface (e.g., low-k materials, including grown and deposited silicon oxide materials, as well as native oxides on silicon). In some embodiments, the non-conductive surface may additionally comprise -H termination, such as an HF-soaked Si surface or an HF-soaked Ge surface. In such embodiments, the surface of interest would be considered to comprise both the -H termination and the material below the -H termination.

[0025] In any of the above mentioned examples, the difference in the materials of the two surfaces is such that a vapor deposition method can selectively deposit an organic passivation layer on the first surface relative to the second surface. In some embodiments, cyclic vapor deposition is used, for example, using a cyclic CVD process or an atomic layer deposition (ALD) process. In some embodiments, the selectivity of the organic passivation layer can be achieved without a passivation / blocking agent on the surface to receive a smaller portion of the organic layer, and / or without a catalytic agent on the surface to receive a larger portion of the organic layer. For example, in an embodiment where the first surface is metallic and the second surface is dielectric, a polymer can be selectively deposited directly on the metallic surface relative to an inorganic dielectric surface. In other embodiments, when the first surface is dielectric and the second surface is metallic, the second surface is first treated to inhibit polymer deposition on the second surface. For example, a passivation blocking self-assembled monolayer (SAM) can be first formed on the metallic surface counterpart to facilitate selective deposition of a polymer passivation layer on a dielectric surface, such as an inorganic dielectric surface, relative to the SAM covered second metallic surface. After the selective deposition of the organic passivation is completed, a further selective deposition of a material of interest, such as a metal oxide or metal layer, may be performed on the second, non-passivated surface relative to the first, passivated surface.

[0026] For embodiments in which one surface comprises a metal while the other surface does not comprise a metal, unless otherwise indicated, when a surface is referred to herein as a metal surface, it may be a metallic or metallic surface. In some embodiments, the metallic or metallic surface may comprise a metal, a metal oxide and / or a mixture thereof. In some embodiments, the metallic or metallic surface may comprise a surface oxidation. In some embodiments, the metallic or metallic material of the metallic or metallic surface is conductive with or without surface oxidation. In some embodiments, the metallic or metallic surface comprises one or more transition metals. In some embodiments, the metallic or metallic surface comprises one or more of Al, Cu, Co, Ni, W, Nb, Fe, or Mo. In some embodiments, the metallic surface comprises titanium nitride. In some embodiments, the metallic or metallic surface comprises one or more noble metals, such as Ru. In some embodiments, the metallic or metallic surface comprises a conductive metal oxide, nitride, carbide, boride, or a combination thereof. For example, the metallic or metallic surface may comprise RuO x , NbC x , NbB x , NiO x , CoO x , NbO x , MoO x , WO x , W.N.C. x , TaN or TiN.

[0027] In some embodiments, the metal or metallic surface comprises cobalt (Co), copper (Cu), tungsten (W) or molybdenum (Mo). In some embodiments, the metal or metallic surface may be any surface that can receive or accommodate a first or second precursor utilized in a selective deposition process of either an organic passivation layer or a layer of interest, depending on the embodiment, as described herein.

[0028] In some embodiments, an organic passivation material such as a polyimide is selectively deposited on a metal surface such as a Co, Cu, W, or Mo surface. In some embodiments, the selective deposition of the organic passivation material on the metal surface occurs at a growth rate of about 0.5 Å / cycle to about 20 Å / cycle, about 1 Å / cycle to about 15 Å / cycle, about 1.5 Å / cycle to about 10 Å / cycle, or about 2 Å / cycle to about 8 Å / cycle. In some embodiments, the growth rate of the organic passivation material on the metal surface is greater than about 0.5 Å / cycle, greater than about 1 Å / cycle, greater than about 3 Å / cycle, or greater than about 5 Å / cycle, while at the upper end, the growth rate of some embodiments is less than about 20 Å / cycle, less than about 15 Å / cycle, less than about 10 Å / cycle, or less than about 8 Å / cycle. In some embodiments, the selectivity of the metal surface relative to the second surface is maintained at these growth rates.

[0029] In some embodiments, the organic passivation material is selectively deposited on a metal oxide surface relative to other surfaces. The metal oxide surface may be, for example, WO x , TiO x In some embodiments, the metal oxide surface is an oxidized surface of a metallic material. In some embodiments, the metal oxide surface is created by oxidizing at least the surface of the metallic material using an oxygen compound, such as a compound comprising O3, H2O, H2O2, O2, oxygen atoms, oxygen plasma, or oxygen radicals, or a mixture thereof. In some embodiments, the metal oxide surface is a native oxide formed on the metallic material.

[0030] In some embodiments, the second surface may comprise a metal surface including a passivation barrier layer thereon, i.e., in some embodiments, the second surface may comprise a metal surface comprising a material that inhibits deposition of a passivation layer, e.g., a self-assembled monolayer (SAM), onto the metal surface.

[0031] In some embodiments, an organic passivation material is selectively deposited on a first metal oxide surface, which is an oxidized surface of a metallic material, relative to a second dielectric surface.

[0032] In some embodiments, one of the first and second surfaces is a metal or metallic surface of the substrate, and the other surface is a dielectric surface of the substrate. The term dielectric is used herein for simplicity in distinguishing it from other surfaces, i.e., metal or metallic surfaces. Those skilled in the art will understand that not all non-conductive surfaces are dielectric surfaces, and conversely, not all metallic surfaces are conductive. For example, a metal or metallic surface may comprise an oxidized metal surface that is non-conductive or has a very high resistivity. The selective deposition process taught herein can be deposited on such non-conductive metallic surfaces with minimal deposition on the dielectric surfaces that are passivated, and a similar selective deposition process can be deposited on the dielectric surfaces with minimal deposition on the non-conductive metallic surfaces that are passivated.

[0033] In some embodiments, the substrate may be pretreated or cleaned prior to or at the beginning of the selective deposition process. In some embodiments, the substrate may be exposed to a plasma cleaning process prior to or at the beginning of the selective deposition process. In some embodiments, the plasma cleaning process may not include ion bombardment or may include relatively small ion bombardment. For example, in some embodiments, the substrate surface may be exposed to a plasma, radicals, excited species, and / or atomic species prior to or at the beginning of the selective passivation layer deposition process. In some embodiments, the substrate surface may be exposed to a hydrogen plasma, radicals, or atomic species prior to or at the beginning of the selective passivation layer deposition process.

[0034] In some embodiments, a non-plasma pretreatment process is performed. For example, in some embodiments, the substrate surface may be exposed to a silicon reactant, such as N-(trimethylsilyl)dimethylamine (TMSDMA) or trimethylchlorosilane. The reactant may be provided in a single long pulse, or in a sequence of multiple shorter pulses. In some embodiments, the reactant is provided in 1 to 25 pulses of about 1 to about 60 seconds. Between pulses, the reaction chamber may be purged with an inert gas. The purge may be, for example, for about 1 to 30 seconds.

[0035] In some embodiments, the surface has the formula (R I )3Si(NR II R III ), wherein R I is a linear or branched C1-C5 alkyl group, or a linear or branched C1-C4 alkyl group, R II is a linear or branched C1-C5 alkyl group, a linear or branched C1-C4 alkyl group, or hydrogen, and R III is a linear or branched C1 to C5 alkyl group, or a linear or branched C1 to C4 alkyl group.

[0036] In some embodiments, the surface has the general formula (R I ) 3SiA, wherein R I is a linear or branched C1-C5 alkyl group, or a linear or branched C1-C4 alkyl group, and A is any ligand that reacts with silicon-containing surfaces, i.e., the silane bonds to the surface through ligand A, or ligand A forms a bond to the surface, but then ligand A may migrate away from the surface and / or the silane.

[0037] The temperature of the pretreatment process may be, for example, about 100 to about 300° C. The pressure during the pretreatment process may be, for example, about 10 -5The pressure may be up to about 760 Torr, or in some embodiments, about 1 to 10 Torr, or about 0.1 to about 10 Torr. In some embodiments, the pretreatment or cleaning process may be performed in situ, i.e., in the same reaction chamber as the selective deposition process. However, in some embodiments, the pretreatment or cleaning process may be performed in a separate reaction chamber. In some embodiments, the reaction chamber in which the pretreatment process is performed is part of a cluster tool that includes one or more additional reaction chambers. For example, such a cluster tool may include additional reaction chambers for the deposition of the inhibitor, etching and / or deposition of the film of interest. In some embodiments, the cluster tool includes separate modules for pretreatment, inhibitor deposition, post-deposition plasma cleaning of the inhibitor (etch), deposition of the layer of interest, and post-plasma deposition cleaning. In some embodiments, the same module may be used for more than one process. For example, the same module may be used for pretreatment, post-deposition of the inhibitor, and post-deposition plasma cleaning of the layer of interest. In some embodiments, the cluster tool includes a first pretreatment module, a plasma cleaning module, an inhibitor deposition module, and a module for depositing a layer of interest.

[0038] Selectivity Those skilled in the art will appreciate that selective deposition can be fully selective or partially selective. A partially selective process may result in a fully selective layer with a post-deposition etch that removes all of the deposited material from all of surface B without removing all of the deposited material from all of surface A. Selective deposition does not need to be fully selective to obtain the desired benefits, as a simple etch-back process may leave a fully selective structure behind without the need for expensive masking processes.

[0039] The selectivity of deposition on surface A relative to surface B may be expressed as a ratio calculated by [(deposition on surface A)-(deposition on surface B)] / (deposition on surface A). Deposition may be measured in any of a variety of ways. For example, deposition may be expressed as a measured thickness of deposited material or as a measured amount of deposited material. In the embodiments described herein, selective deposition of an organic passivation layer may be performed on a first surface (A) relative to a second surface (B). A layer of interest is then selectively deposited on the second surface (A) relative to the organic passivation layer (B) on the first surface.

[0040] In some embodiments, the selectivity of the selective deposition of the passivation layer on the first surface (relative to the second surface) and / or the selectivity of the layer of interest on the second surface (relative to the passivation layer on the first surface) is greater than about 10%, greater than about 50%, greater than about 75%, greater than about 85%, greater than about 90%, greater than about 93%, greater than about 95%, greater than about 98%, greater than about 99%, or even greater than about 99.5%. In the embodiments described herein, the selectivity of the organic passivation layer deposition can vary with the duration or thickness of the deposition. Surprisingly, it has been found that the selectivity increases with the duration of the deposition for the vapor-phase polymer layer deposition described herein. In contrast, typical selective deposition based on differential nucleation on different surfaces tends to be less selective with greater duration or thickness of the deposition.

[0041] In some embodiments, deposition occurs only on the first surface and not on the second surface. In some embodiments, deposition on surface A of the substrate relative to surface B of the substrate is at least about 80% selective, which may be sufficiently selective for some particular applications. In some embodiments, deposition on surface A of the substrate relative to surface B of the substrate is at least about 50% selective, which may be sufficiently selective for some particular applications. In some embodiments, deposition on surface A of the substrate relative to surface B of the substrate is at least about 10% selective, which may be sufficiently selective for some particular applications. Those skilled in the art will appreciate that a partially selective process may result in a completely selective structural layer due to a post-deposition etch that removes all of the deposited material from all of surface B without removing all of the deposited material from all of surface A. Furthermore, as will be better understood from the description of Figures 17-23B below, a post-deposition etch may also help tailor the location and / or shape of the selectively deposited layer.

[0042] In some embodiments, the organic layer deposited on the first surface of the substrate may have a thickness of less than about 50 nm, less than about 20 nm, less than about 10 nm, less than about 5 nm, less than about 3 nm, less than about 2 nm, or less than about 1 nm, while the ratio of material deposited on the first surface of the substrate to material deposited on the second surface of the substrate may be about 200:1 or more, about 100:1 or more, about 50:1 or more, about 25:1 or more, about 20:1 or more, about 15:1 or more, about 10:1 or more, about 5:1 or more, about 3:1 or more, or about 2:1 or more.

[0043] In some embodiments, the selectivity of the selective deposition processes described herein may depend on the material composition of the materials defining the first and / or second surfaces of the substrate. For example, in some embodiments where the first surface comprises a BTA-passivated Cu surface and the second surface comprises a natural or chemical silicon dioxide surface, the selectivity may be greater than about 8:1 or greater than about 15:1. In some embodiments, where the first surface comprises a metal or metal oxide and the second surface comprises a natural or chemical silicon dioxide surface, the selectivity may be greater than about 5:1 or greater than about 10:1.

[0044] Selective Deposition on Dielectrics 1A-1D generally illustrate a first embodiment of selectively passivating a first surface relative to a second surface, followed by selective deposition onto the second surface relative to the passivated first surface. In the illustrated embodiment, the first surface comprises a metallic material, the second surface comprises an inorganic dielectric material, and the material to be deposited on the second surface comprises a dielectric material.

[0045] 1A illustrates a substrate having exposed significantly different surfaces. For example, a first surface can comprise or be defined by a metal, such as cobalt (Co), copper (Cu), tungsten (W) or molybdenum (Mo). A second surface can comprise or be defined by an inorganic dielectric, such as a low-k layer (usually a silicon oxide-based layer) or a silicon surface having a native oxide (also a form of silicon oxide) formed on the surface.

[0046] FIG. 1B shows the substrate of FIG. 1A after selective deposition of a passivation layer onto the first surface. For example, the passivation layer may be a polymer layer that selectively deposits onto the metallic surface of the first layer. Methods for selectively depositing a polymer layer by vapor deposition techniques are disclosed in U.S. Patent Application No. 15 / 170,769, filed June 1, 2016, the entire disclosure of which is incorporated herein by reference for all purposes. Further information and examples of selective deposition of a polymer layer that serves as a passivation layer are provided below.

[0047] In some embodiments, the selectively deposited polymer is a polyimide. In some embodiments, the deposited polymer is a polyamide. Other examples of deposited polymers include dimers, trimers, polyurea layers, polythiophene polyurethanes, polythioureas, polyesters, polyimines, other polymer forms or mixtures of the above materials. The organic material deposited includes polyamic acid, which may be a precursor to the formation of a polymer. The selectively deposited layer can be a mixture including a polymer and a polyamic acid, and for the purposes of this disclosure, would be considered to be a polymer.

[0048] In some embodiments, selective deposition of a polymer, e.g., a polyimide, on a first metal-containing surface, such as a Cu surface, occurs at a growth rate of about 0.5 Å / cycle to about 20 Å / cycle, about 1 Å / cycle to about 15 Å / cycle, about 1.5 Å / cycle to about 10 Å / cycle, or about 2 Å / cycle to about 8 Å / cycle. In some embodiments, the growth rate of a polymer, e.g., a polyimide, on a first metal-containing surface, such as a Cu surface, is greater than about 0.5 Å / cycle, greater than about 1 Å / cycle, greater than about 3 Å / cycle, or greater than about 5 Å / cycle, while at the upper end, the growth rate of some embodiments is less than about 20 Å / cycle, less than about 15 Å / cycle, less than about 10 Å / cycle, or less than about 8 Å / cycle. Selectivity is maintained at these growth rates in some embodiments.

[0049] In some embodiments, selective deposition of polyimide on Cu surfaces occurs at growth rates of about 0.5 Å / cycle to about 20 Å / cycle, about 1 Å / cycle to about 15 Å / cycle, about 1.5 Å / cycle to about 10 Å / cycle, or about 2 Å / cycle to about 8 Å / cycle. In some embodiments, the growth rate of polyimide on Cu surfaces is greater than about 0.5 Å / cycle, greater than about 1 Å / cycle, greater than about 3 Å / cycle, or greater than about 5 Å / cycle, while at the higher end, the growth rate of some embodiments is less than about 20 Å / cycle, less than about 15 Å / cycle, less than about 10 Å / cycle, or less than about 8 Å / cycle. Selectivity is maintained at these growth rates in some embodiments.

[0050] As noted above, any organic material that is deposited on the second surface (in this example the inorganic dielectric surface) may be removed by an etch-back process. In some embodiments, an etching process following selective deposition of an organic layer may remove deposited organic material from both the first and second surfaces of the substrate. In some embodiments, the etching process may be isotropic.

[0051] In some embodiments, the etching process may remove the same amount or thickness of material from the first and second surfaces. That is, in some embodiments, the etch rate of the organic material deposited on the first surface may be substantially similar to the etch rate of the organic material deposited on the second surface. Due to the selective nature of the deposition processes described herein, the amount of organic material deposited on the second surface of the substrate is substantially less than the amount of material deposited on the first surface of the substrate. Thus, the etching process may completely remove the deposited organic material from the second surface of the substrate, while the deposited organic material may remain on the first surface of the substrate. A suitable process for etching a polymer is described below in conjunction with FIG. 1D.

[0052] FIG. 1C shows the substrate of FIG. 1B after selective deposition of a layer of interest X on a second surface (in this example, an inorganic dielectric surface) relative to a passivation layer on a first surface (in this example, a metallic surface). The layer of interest X can be a dielectric material such as a metal oxide, for example zirconium oxide, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, or other transition metal oxides or mixtures thereof. In some embodiments, the metal oxide is a dielectric transition metal oxide or a mixture of dielectric transition metal oxides. In some embodiments, the layer of interest X can be a metal nitride, such as titanium nitride. Methods for selectively depositing such metal oxide layers by vapor deposition techniques using hydrophobic precursors to aid in selectivity to organic passivation layers are disclosed in U.S. Provisional Patent Application No. 62 / 332,396, filed May 5, 2016, the entire disclosure of which is incorporated herein by reference for all purposes. Further information and examples of selective deposition of metal oxides and other layers of interest are provided below.

[0053] As mentioned above, any X material deposited on the passivation layer on the first surface may be removed by an etch-back process. Because the layer of interest is selectively deposited on the second surface, any X material remaining on the passivation surface will be thinner than the passivation layer formed on the metallic surface. Thus, the etch-back process may be controlled to remove all of the X material on the passivation layer without removing all of the layer of interest from above the dielectric surface. This repeated selective deposition and etch-back may result in an increase in the thickness of the X material on the dielectric with each cycle of deposition and etching. This repeated selective deposition and etch-back may also result in an increase in the overall selectivity of the X material on the dielectric, since each cycle of deposition and etching leaves behind a clean passivation layer on which selective X deposition is poorly nucleated. Alternatively, any X material may be removed during the subsequent removal of the passivation layer in a lift-off process, i.e., during the example situation described below in connection with FIG. 1D. As is known in the art, a lift-off process removes overlying material by chipping away at the underlying material by removal. Any X material formed on the passivation layer in a short selective deposition process tends to be discontinuous, allowing the etchant access to the underlying material to be removed. A lift-off etch does not require complete removal of the passivation layer to remove all of the unwanted X material from the passivation layer surface, as the X material may be removed from the passivation layer surface in cyclic selective deposition and removal using either direct etching or lift-off methods.

[0054] FIG. 1D illustrates the substrate of FIG. 1C after removing the passivation layer from the first surface. In some embodiments, the etching process may include exposing the substrate to a plasma. In some embodiments, the plasma may comprise oxygen atoms, oxygen radicals, oxygen plasma, or combinations thereof. In some embodiments, the plasma may comprise hydrogen atoms, hydrogen radicals, hydrogen plasma, or combinations thereof (see, e.g., Example 2 below for selective deposition of a passivation layer). In some embodiments, the plasma may also comprise a noble gas species, e.g., Ar species or He species. In some embodiments, the plasma may consist essentially of noble gas species. In some examples, the plasma may comprise other species, e.g., nitrogen atoms, nitrogen radicals, nitrogen plasma, or combinations thereof. In some embodiments, the etching process may include exposing the substrate to an etchant comprising oxygen, e.g., O3. In some embodiments, the substrate may be exposed to the etchant at a temperature between about 30° C. and about 500° C., or between about 100° C. and about 400° C. In some embodiments, the etchant may be provided in one continuous pulse or in multiple shorter pulses. As noted above, removal of the passivation layer may be used either in complete removal of the passivation layer, or in partial removal of the passivation layer in cyclic selective deposition and removal such that any remaining X material is lifted off from above the passivation layer.

[0055] As discussed above, in some embodiments, O3 (e.g., O3 / N2) may be used in the etching process to remove the organic passivation layer. In some embodiments, the etching process may be performed at a substrate temperature of about 20° C. to about 500° C. In some embodiments, the etching process may be performed at a substrate temperature of about 50° C. to about 300° C. In some embodiments, the etching process may be performed at a substrate temperature of about 100° C. to about 250° C. In some embodiments, the etching process may be performed at a substrate temperature of about 125° C. to about 200° C. In some embodiments, the etching process may be performed at a rate of about 0.05 nm / min to about 50.0 nm / min. In some embodiments, the etching process may be performed at a rate of about 0.1 nm / min to about 5.0 nm / min. In some embodiments, the etching process may be performed at a rate of about 0.2 nm / min to about 2.5 nm / min. In some embodiments for single wafer or small batch (e.g., 5 wafers or less) processing, a low O3 concentration etch process may be used, which is performed at 0.01 Torr to 200 Torr, or about 0.1 Torr to 100 Torr (e.g., 2 Torr). The oscillation of the etchant may be between 0.01 sec and 20 sec, between 0.05 sec and 10 sec, or between 0.1 sec and 2 sec (e.g., 0.5 sec pulse / 0.5 sec O3 purge). The O3 flow rate may range from 0.01 slm to 1 slm, or from 0.01 slm to 0.250 slm. The inert (e.g., N2) carrier gas flow rate may range from 0.1 slm to 20 slm, or from 0.5 slm to 5 slm (e.g., 1.2 slm). In some embodiments, a high O3 concentration etch process may be used, which is performed at 1-100 Torr, or 5-20 Torr (e.g., 9 Torr) with longer exposure per cycle. For example, O3 exposure time can be between 0.1 sec and 20 s, or between 0.5 sec and 5 sec (e.g., 1 sec pulse / 1 sec O3 purge).The O3 flow rate for such high O3 concentration processes can be between 0.1 slm and 2.0 slm, or between 0.5 slm and 1.5 slm (e.g., 750 sccm), with an inert (e.g., N2) diluent at a flow rate of 0.1 slm to 20 slm, or 0.5 slm to 5 slm (e.g., 1.2 slm).

[0056] In some embodiments, a bake step can be performed after the etch. The bake may be performed in the same reactor as the deposition of the organic material, the same reactor as the etch process, the same reactor in which the layer of interest is subsequently deposited, or in a separate reactor from one or more of those aspects of the process. In some embodiments, the bake process is performed in a reaction chamber that is part of a cluster tool, and the substrate is moved to one or more different reaction chambers of the cluster tool for further processing after the bake.

[0057] In some embodiments, the substrate is baked for about 1 to about 15 minutes. In some embodiments, the substrate is baked at a temperature of about 200 to about 500° C. In some embodiments, the baking step includes two or more steps in which the substrate is baked at a first temperature for a first time and then baked at a second temperature for a second time.

[0058] Additional treatments, such as thermal or chemical treatments, may be performed before, after, or during the aforementioned processes. For example, the treatments may modify the surface or remove portions of metal, silicon oxide, polymer passivation, and metal oxide surfaces that are exposed at various stages of the process. In some embodiments, the substrate may be pretreated or cleaned before or at the beginning of the selective deposition process. In some embodiments, the substrate may be exposed to a plasma cleaning process before or at the beginning of the selective deposition process. In some embodiments, the plasma cleaning process may not include ion bombardment or may include relatively small ion bombardment. For example, in some embodiments, the substrate surface may be exposed to a plasma, radicals, excited species, and / or atomic species before or at the beginning of the selective deposition process. In some embodiments, the substrate surface may be exposed to a hydrogen plasma, radicals, or atomic species before or at the beginning of the selective deposition process. In some embodiments, the pretreatment or cleaning process may be performed in the same reaction chamber as the selective deposition process, however, in some embodiments, the pretreatment or cleaning process may be performed in a separate reaction chamber.

[0059] Selective deposition on metals 2A-2E generally illustrate a second embodiment of selectively passivating a first surface relative to a second surface, followed by selective deposition onto the second surface relative to the passivated first surface. In the illustrated embodiment, the first surface comprises an inorganic dielectric material, the second surface comprises a metallic surface, and the material to be deposited on the second surface comprises a dielectric material or a metal.

[0060] FIG. 2A illustrates a substrate similar to FIG. 1A, but with a significantly different surface. However, in this embodiment, the surfaces are described in reverse terms. In particular, the second surface can comprise or be defined by a metallic material, such as cobalt (Co), copper (Cu), tungsten (W) or molybdenum (Mo). The first surface can comprise an inorganic dielectric, such as a low-k layer (usually a silicon oxide-based layer), or a silicon surface with a native oxide (also in the form of silicon oxide) formed on the surface. A passivation barrier layer is formed on the second surface. It should be noted that the term "blocking" is not meant to imply that the subsequent selective deposition of a passivation layer is completely blocked by the passivation barrier layer. Rather, the passivation barrier layer on the second surface is only required to inhibit the deposition of the passivation layer, so that it has a lower growth rate compared to the growth rate on the first surface.

[0061] In one embodiment, the passivation barrier layer comprises a self-assembled monolayer (SAM). The SAM may be selectively formed on the second (metallic) surface without being formed on the first (dielectric) surface. Sulfur-containing SAMs have been advantageously found to be effective in minimizing the buildup of a passivation layer thereon.

[0062] 2B illustrates selective formation of a passivation layer (e.g., an organic passivation layer) on a first surface, in this case an inorganic dielectric layer, against a passivation barrier layer on a second surface. As noted in the above-incorporated patent application Ser. No. 15 / 170,769, filed Jun. 1, 2016, the deposition process described herein can deposit a polymer on an inorganic dielectric and can also selectively (i.e., at differential deposition rates) on different types of silicon oxide. In this embodiment, the sulfur-containing SAM can inhibit polymer deposition on the SAM and act as a passivation layer for subsequent deposition, such that the polymer can selectively form on the first surface.

[0063] FIG. 2C shows the substrate of FIG. 2B after removing the passivation barrier layer from above the second surface. For example, the sulfur-containing SAM material can be removed by a heat treatment at a lower temperature than would remove a polymer layer such as polyimide. Thus, the passivation layer is selectively left on the first surface while exposing the second surface. In this embodiment, the structure is similar to FIG. 1B, except that the passivated first surface is an inorganic dielectric and the second surface is a metallic surface.

[0064] Figure 2D shows the substrate of Figure 2C after selective deposition of a layer of interest X on the second surface relative to the passivation layer on the first surface. As discussed in connection with the first embodiment and described in Provisional Patent Application No. 62 / 332,396, filed May 5, 2016, incorporated above, metal oxides can be selectively deposited on several different surfaces using vapor deposition techniques and hydrophobic precursors to aid in selectivity to the organic passivation layer. Further information and examples of selective deposition of metal oxides and other layers of interest are provided below.

[0065] Alternatively, the layer of interest, X, is a metal layer. U.S. Patent No. 8,956,971, issued February 17, 2015, and U.S. Patent No. 9,112,003, issued August 18, 2015, the entire disclosures of which are incorporated herein by reference for all purposes, teach processes for selectively depositing metallic materials onto metallic surfaces relative to other material surfaces, including organic surfaces.

[0066] Figure 2E shows the substrate of Figure 2D after removal of the passivation layer from the first surface, leaving a dielectric selectively formed on the metal or on metal on metal. The passivation layer may be removed as described above in connection with the first embodiment, such as by O3 etching.

[0067] 3A-3B generally illustrate a third embodiment in which a first surface is selectively passivated relative to a second surface, followed by selective deposition onto the second surface relative to the passivated first surface. In the illustrated embodiment, the process of FIGS. 2A-2D is performed first.

[0068] FIG. 3A shows the substrate of FIG. 2D after further selective deposition. If the layer of interest X is a metallic material, further selective deposition may form a dielectric material as a second layer of interest Y over the first layer of interest, selective to the organic passivation layer. As discussed above in connection with the first and second embodiments and described in the above-incorporated Provisional Patent Application No. 62 / 332,396, filed May 5, 2016, vapor deposition techniques and hydrophobic precursors may be used to selectively deposit metal oxides onto several different surfaces to aid in selectivity to the organic passivation layer. Further information and examples of selective deposition of metal oxides and other layers of interest are provided below.

[0069] 3B shows the substrate of FIG. 3A after removal of the passivation layer from the first surface, leaving behind a dielectric selectively formed on the metal. The passivation layer may be removed as described above in connection with the first embodiment, such as by O3 etching.

[0070] Like the first embodiment, the second and third embodiments may involve additional treatments, such as thermal or chemical treatments, carried out before, after, or during the processes described above.

[0071] Selective Deposition of Passivation Layers As disclosed in the incorporated U.S. Patent Application No. 15 / 170,769, filed June 1, 2016, vapor deposition techniques can be applied to organic passivation layers, as well as polymers such as polyimide layers, polyamide layers, polyamide layers, polyurethane layers, polythiophene layers, and others, to name a few. CVD of polymer layers can produce better thickness control, mechanical flexibility, conformal coverage, and biocompatibility compared to the application of liquid precursors. Sequential deposition processing of polymers can produce high growth rates in small research-scale reactors. Similar to CVD, sequential deposition processes can produce better thickness control, mechanical flexibility, and conformality. The terms "sequential deposition" and "cyclic deposition" are used herein to apply to processes in which a substrate is exposed to different precursors in an alternating or sequential manner, whether the reaction mechanism resembles ALD, CVD, MLD, or a hybrid thereof.

[0072] Referring to FIG. 4A, in some embodiments, at block 11, a substrate is provided that includes a first surface and a second surface. The first and second surfaces may have different material properties as discussed herein. In some embodiments, the first surface may be a conductive surface, e.g., a metal or metallic surface, and the second surface may be a dielectric surface (see, e.g., FIGS. 1A-1D). In some embodiments, the first surface may be a dielectric surface and the second surface may be a different, second dielectric surface. In some embodiments, the first surface may be a dielectric surface, e.g., a silicon oxide based material, and the second surface may be a passivation blocking material such as a SAM (see, e.g., FIGS. 2A-3B).

[0073] In some embodiments, the first precursor may be evaporated at a first temperature to form a first vapor phase precursor. In some embodiments, the first precursor vapor is transported through a gas line to the substrate at a second temperature. In some embodiments, the second transport temperature is higher than the first evaporation temperature. In some embodiments, the substrate contacts the first vapor phase precursor, i.e., reactant, at block 12 during a first exposure period. In some embodiments, the substrate may contact the first vapor phase precursor at a third temperature, higher than the first temperature.

[0074] In some embodiments, the exposure period of the first precursor is about 0.01 seconds to about 60 seconds, about 0.05 seconds to about 30 seconds, about 0.1 seconds to about 10 seconds, or about 0.2 seconds to about 5 seconds. The optimal exposure period can be easily determined by those skilled in the art based on the particular circumstances. A batch reactor may be used, and in some embodiments, an exposure period longer than 60 seconds may be used.

[0075] In some embodiments, the substrate contacts a second vapor phase precursor, i.e., reactant, at block 13 during a second exposure period. In some embodiments, the second precursor may be evaporated at a fourth temperature to form a second vapor phase precursor. In some embodiments, the vapor of the second reactant is transported through a gas line to the substrate at a second temperature. In some embodiments, the fifth transport temperature is higher than the first evaporation temperature. In some embodiments, the substrate may contact the second vapor phase precursor at a sixth temperature, higher than the fourth temperature. In some embodiments, the sixth temperature may be substantially the same as the third temperature at which the first vapor phase precursor contacts the substrate.

[0076] In some embodiments, the exposure period of the second precursor is about 0.01 seconds to about 60 seconds, about 0.05 seconds to about 30 seconds, about 0.1 seconds to about 10 seconds, or about 0.2 seconds to about 5 seconds. The optimal exposure period can be easily determined by those skilled in the art based on the particular circumstances. In some embodiments, exposure periods longer than 60 seconds can be used when a batch reactor can be used.

[0077] In block 14, an organic layer is selectively deposited on the first surface relative to the second surface. One skilled in the art will appreciate that the selective deposition of the organic layer is the result of the contacting actions 12-13 described above, rather than separate actions. In some embodiments, the contacting actions 12-13 described above may be considered as a single deposition cycle. Such a selective deposition cycle may be repeated until deposition is terminated (block 16) while leaving a layer of sufficient thickness on the substrate (block 15). The selective deposition cycle may include additional actions, which need not be in the same order or performed exactly the same way in each repetition, and may be easily extended to more complex deposition techniques. For example, the selective deposition cycle may include additional reactant supply processes, such as supplying and removing (to the substrate) additional reactants, in each or selected cycles. Although not shown, the process may additionally include treating the deposited layer to form a polymer (e.g., UV treatment, annealing, etc.). The selectively formed organic layer, as described above, may act as a passivation layer, inhibiting deposition thereon and increasing the selectivity of the subsequent selective deposition of a layer of interest.

[0078] Referring to FIG. 4B, the vapor deposition process of FIG. 4A may include an atomic layer deposition process in some embodiments. In block 21, a substrate is provided that includes a first surface and a second surface. The first and second surfaces may have different material properties. In some embodiments, the first surface may be a conductive surface, e.g., a metal surface or a metallic surface, and the second surface may be a dielectric surface (see, e.g., FIGS. 1A-1D). In some embodiments, the first surface may be a dielectric surface and the second surface may be a different, second dielectric surface. In some embodiments, the first surface may be a dielectric surface, e.g., a silicon oxide-based material, and the second surface may be a passivation blocking material such as a SAM (see, e.g., FIGS. 2A-3B).

[0079] In some embodiments, the sequential deposition method for selective deposition of an organic passivation layer includes evaporating a first organic precursor to form a first precursor vapor at block 22 at a first temperature. In some embodiments, the first precursor vapor is transported to the substrate through a gas line at a second temperature. In some embodiments, the second transport temperature is higher than the first evaporation temperature. In some embodiments, during a first exposure period in block 23, the substrate contacts the first precursor in the gas phase. In some embodiments, the first precursor or a species thereof chemically adsorbs on the substrate in a self-saturating or self-limiting manner. The gas line can be any conduit that transports the first precursor vapor from a source to the substrate. In some embodiments, the substrate may be exposed to the first precursor vapor at a third temperature, higher than the first temperature.

[0080] In some embodiments, the exposure period of the first precursor is about 0.01 seconds to about 60 seconds, about 0.05 seconds to about 30 seconds, about 0.1 seconds to about 10 seconds, or about 0.2 seconds to about 5 seconds. The optimal exposure period can be easily determined by those skilled in the art based on the particular circumstances. In some embodiments, exposure periods longer than 60 seconds can be used when a batch reactor can be used.

[0081] Thereafter, in block 24, excess first precursor vapor (and any volatilized reaction byproducts) may be removed from contact with the substrate. Such removal may be accomplished, for example, by purging, pumping down, moving the substrate away from the chamber or area in which the substrate is exposed to the first reactant, or a combination thereof. In some embodiments, the removal period of the first precursor, e.g., the purge period, is from about 0.01 seconds to about 60 seconds, from about 0.05 seconds to about 30 seconds, from about 0.1 seconds to about 10 seconds, or from about 0.2 seconds to about 5 seconds. The optimal removal period may be readily determined by one of ordinary skill in the art based on the particular circumstances. In some embodiments, removal periods longer than 60 seconds may be used where a batch reactor may be used.

[0082] In some embodiments, the second precursor may be evaporated at a fourth temperature to form a second gas phase precursor at block 25. In some embodiments, vapor of the second reactant is transported through a gas line to the substrate at a second temperature. In some embodiments, the fifth transport temperature is greater than the first evaporation temperature. In some embodiments, the substrate may contact the second gas phase precursor at a sixth temperature, greater than the fourth temperature. In some embodiments, the sixth temperature may be substantially the same as the third temperature at which the first gas phase precursor contacts the substrate. In some embodiments, the substrate may be exposed to the second precursor vapor during a second exposure period at block 26. In some embodiments, the second reactant may react with an adsorbed species of the first reactant on the substrate.

[0083] In some embodiments, the exposure period of the first precursor is about 0.01 seconds to about 60 seconds, about 0.05 seconds to about 30 seconds, about 0.1 seconds to about 10 seconds, or about 0.2 seconds to about 5 seconds. The optimal exposure period can be easily determined by those skilled in the art based on the particular circumstances. In some embodiments, exposure periods longer than 60 seconds can be used when a batch reactor can be used.

[0084] In some embodiments, excess second precursor vapor (and any volatilized reaction by-products) is removed from contact with the substrate in block 27 so that the first reactant vapor and the second reactant vapor do not mix. In some embodiments, the deposition process of the organic layer does not use plasma and / or radicals and may be considered a thermal evaporation process. In some embodiments, the removal period, e.g., the purge period, of the second precursor is about 0.01 seconds to about 60 seconds, about 0.05 seconds to about 30 seconds, about 0.1 seconds to about 10 seconds, or about 0.2 seconds to about 5 seconds. The optimal removal period may be easily determined by one of ordinary skill in the art based on the particular circumstances. In some embodiments, removal periods longer than 60 seconds may be used when a batch reactor may be used.

[0085] In block 28, an organic layer is selectively deposited on the first surface relative to the second surface. One skilled in the art will appreciate that the selective deposition of the organic layer is a result of the contacting action described above, rather than separate actions. In some embodiments, the contacting and removing (and / or cessation of supply) actions of blocks 23-27 may be considered a single deposition cycle. In some embodiments, the deposition cycle may be repeated until an organic layer of a desired thickness is selectively deposited. Such selective deposition cycles may be repeated (block 29) until deposition is terminated (block 30) while leaving a layer of sufficient thickness on the substrate. The selective deposition cycle may include additional acts, which need not be in the same order or performed exactly the same way in each repetition, and may be easily extended to more complex deposition techniques. For example, the selective deposition cycle may include additional reactant supply processes, such as supplying and removing additional reactants, in each or selected cycles. Although not shown, the process may additionally include treating the deposited layer to form a polymer (e.g., UV treatment, annealing, etc.).

[0086] A variety of reactants may be used for the above process. For example, in some embodiments, the first precursor or reactant is an organic reactant, such as a diamine, e.g., 1,6-diaminohexane (DAH), or any other monomer with two reactive groups. In some embodiments, the second reactant or precursor is also an organic reactant that can react with the adsorbed species of the first reactant under deposition conditions. For example, the second reactant may be an anhydride, such as furan-2,5-dione (maleic anhydride). The anhydride may comprise a dianhydride, e.g., pyromellitic dianhydride (PMDA), or any other monomer with two reactive groups that will react with the first reactant.

[0087] In some embodiments, the substrate is contacted with the first precursor before contacting with the second precursor. Thus, in some embodiments, the substrate is contacted with an amine, such as a diamine, for example, 1,6-diaminohexane (DAH), before contacting with another precursor. However, in some embodiments, the substrate may be contacted with the second precursor before contacting with the first precursor. Thus, in some embodiments, the substrate is contacted with an anhydride, such as furan-2,5-dione (maleic anhydride), or a dianhydride, for example, pyromellitic dianhydride (PMDA), before contacting with another precursor.

[0088] In some embodiments, different reactants may be used to tailor the properties of the layer, for example, 4,4'-oxydianiline or 1,4-diaminobenzene may be used to deposit the polyimide layer instead of 1,6-diaminohexane to obtain a more robust structure with higher aromaticity and increased dry etch resistance.

[0089] In some embodiments, the reactants do not contain metal atoms. In some embodiments, the reactants do not contain metalloid atoms. In some embodiments, one of the reactants comprises a metal atom or a metalloid atom. In some embodiments, the reactants contain carbon and hydrogen and one or more of the following elements N, O, S, P, or halides such as Cl or F. In some embodiments, the first reactant may comprise, for example, adipoyl chloride (AC).

[0090] The deposition conditions can vary depending on the reactants selected and can be optimized by selection. In some embodiments, the reaction temperature can be selected from a range of about 80° C. to about 250° C. In some embodiments, the reaction chamber pressure can be selected from a range of about 1 mTorr to about 1000 Torr, about 10 -5The reaction pressure may be up to 760 Torr, or in some embodiments, about 1 to 10 Torr. In some embodiments, for example, when the selectively deposited organic layer comprises a polyamide, the reaction temperature may be selected from a range of about 80° C. to about 150° C. In some embodiments, when the selectively deposited organic layer comprises a polyamide, the reaction temperature may be greater than about 80° C., 90° C., 100° C., 110° C., 120° C., 130° C., 140° C., or 150° C. In some embodiments, when the selectively deposited organic layer comprises a polyimide, the reaction temperature may be greater than about 160° C., 180° C., 190° C., 200° C., or 210° C.

[0091] For example, for sequential deposition of polyimide using PMDA and DAH in a single wafer deposition tool, the substrate temperature can be selected from the range of about 150° C. to about 250° C. or about 170° C. to about 210° C., and the pressure can be selected from the range of between about 1 mTorr to about 760 Torr, or about 100 mTorr to about 100 Torr.

[0092] In some embodiments, reactants used in the selective deposition processes described herein may have the general formula:

[0093] (1)R 1 (NH2)2 In the formula, R 1may be an aliphatic carbon chain comprising 1-5 carbon atoms, 2-5 carbon atoms, 2-4 carbon atoms, 5 or less carbon atoms, 4 or less carbon atoms, 3 or less carbon atoms, or 2 carbon atoms. In some embodiments, the bonds between the carbon atoms in the reactants or precursors may be single bonds, double bonds, triple bonds, or some combination thereof. Thus, in some embodiments, the reactants may comprise two amino groups. In some embodiments, the amino groups of the reactants may occupy one or both terminal positions on the aliphatic carbon chain. However, in some embodiments, the amino groups of the reactants may not occupy either terminal position on the aliphatic carbon chain. In some embodiments, the reactants may comprise a diamine. In some embodiments, the reactants may comprise an organic precursor selected from the group of 1,2-diaminoethane (diaminoethanel), 1,3-diaminopropane (diaminopropanel), 1,4-diaminobutane (diaminobutanel), 1,5-diaminopentane (diaminopentanel), 1,2-diaminopropane (diaminopropanel), 2,3-butanediamine, 2,2-dimethyl-1,3-propanediamine (propanediaminel).

[0094] In some embodiments, reactants used in the selective deposition processes described herein may have the general formula:

[0095] (2)R 2 (COCl)2 In the formula, R 2may be an aliphatic carbon chain with 1-3 carbon atoms, 2-3 carbon atoms, or 3 or less carbon atoms. In some embodiments, the bonds between the carbon atoms in the reactants or precursors may be single bonds, double bonds, triple bonds, or some combination thereof. In some embodiments, the reactants may comprise chlorides. In some embodiments, the reactants may comprise diacyl chlorides. In some embodiments, the reactants may comprise organic precursors selected from the group of oxalyl chloride (I), malonyl chloride, and fumaryl chloride.

[0096] In some embodiments, the reactants comprise an organic precursor selected from the group of 1,4-diisocyanatobutane or 1,4-diisocyanatobenzene. In some embodiments, the reactants comprise an organic precursor selected from the group of alkyl dioyl dichlorides, such as terephthaloyl dichloride, hexanedioyl dichloride, octanedioyl dichloride, nonanedioyl dichloride, decanedioyl dichloride, or terephthaloyl dichloride. In some embodiments, the reactants comprise an organic precursor selected from the group of 1,4-diisothiocyanatobenzene or terephthalaldehyde. In some embodiments, the vaporized reactants can also be diamines, such as 1,4-diaminobenzene, decane-1,10-diamine, 4-nitrobenzene-1,3-diamine, 4,4'-oxydianiline, or ethylenediamine. In some embodiments, the reactants can be terephthalic acid bis(2-hydroxyethyl) ester. In some embodiments, the reactant may be a carboxylic acid, for example, an alkyl-, alkenyl-, alkadienyl-dicarboxylic acid or tricarboxylic acid, such as ethanedioic acid, propanedioic acid, butanedioic acid, pentanedioic acid, or propane-1,2,3-tricarboxylic acid. In some embodiments, the reactant may be an aromatic carboxylic acid or dicarboxylic acid, such as benzoic acid, benzene-1,2-dicarboxylic acid, benzene-1,4-dicarboxylic acid, or benzene-1,3-dicarboxylic acid. In some embodiments, the reactant may comprise one or more OH-groups bonded to a hydrocarbon. In some embodiments, the reactant may be selected from the group of diols, triols, aminophenols, such as 4-aminophenol, benzene-1,4-diol, or benzene-1,3,5-triol. In some embodiments, the reactant may be 8-quinolinol. In some embodiments, the reactant may comprise an alkenylchlorosilane, such as an alkenyltrichlorosilane, such as 7-octenyltrichlorosilane.

[0097] In some embodiments, the reactants may have a vapor pressure of greater than about 0.5 Torr, 0.1 Torr, 0.2 Torr, 0.5 Torr, 1 Torr, or greater at a temperature of about 20° C. or room temperature. In some embodiments, the reactants may have a boiling point of less than about 400° C., less than 300° C., less than about 250° C., less than about 200° C., less than about 175° C., less than about 150° C., or less than about 100° C.

[0098] Selective Deposition of Layers of Interest on Organic Surfaces As described in incorporated U.S. Provisional Patent Application No. 62 / 332,396, filed May 5, 2016, selective deposition of metallic materials and metal oxides on organic materials, such as the passivation layers disclosed herein, may be facilitated using hydrophobic reactants. After selectively forming a passivation layer on a first surface, in some embodiments, a metal oxide is selectively deposited on a second surface by alternately and sequentially contacting the substrate with a first hydrophobic reactant comprising a metal of the metal oxide and a second reactant comprising oxygen. In some embodiments, the second reactant is water or H2O2. In some embodiments, the substrate is contacted sequentially with the first and second reactants in a manner similar to the sequence of FIG. 4A, except that a non-organic material is selectively deposited on or above the second surface (see, e.g., FIGS. 1A-3B).

[0099] The hydrophobic reactant comprises one or more hydrophobic ligands. In some embodiments, the hydrophobic reactant comprises two to four hydrophobic ligands. For a hydrophobic reactant comprising a metal of valence / oxidation state n, in some embodiments the hydrophobic precursor comprises n-1 or n-2 hydrophobic ligands.

[0100] In some embodiments, the at least one hydrophobic ligand comprises only C and H. In some embodiments, the at least one hydrophobic ligand comprises C, H and Si or Ge, but no additional elements.

[0101] In some embodiments, the hydrocarbon ligand comprises one or more of the following: C1-C10 hydrocarbons (single, double or triple bonds) o-Alkyl C1-C5 alkyl Me, Et, Pr, i Pr, Bu, t Bu o-Alkenyl C1-C6 alkenyl Cyclic hydrocarbons C3~C8 Cyclopentadienyl Cycloheptadienyl Cycloheptatrienyl Cyclohexyl Their derivatives o Aromatic · C6 aromatic rings and their derivatives★

[0102] In some embodiments, the hydrophobic reactant does not comprise a hydrophilic ligand. However, in some embodiments, the hydrophobic reactant may comprise one or two hydrophilic ligands. In some embodiments, the hydrophilic ligand comprises a nitrogen, oxygen, and / or halogen group.

[0103] In some embodiments, the hydrophilic ligand is an alkylamine (where each R is alkyl, which may be hydrogen, -NR2). In some embodiments, the hydrophilic ligand may be -NMe2, -NEtMe, or -NEt2.

[0104] In some embodiments, the hydrophilic ligand is, for example, -OMe, -OEt, -O i Pr, -O t and alkoxides such as Bu.

[0105] In some embodiments, the hydrophilic ligand comprises a halide, such as chloride, fluoride or other halide.

[0106] In some embodiments, the hydrophobic precursor has the formula: o L n MXy , in the formula, In some embodiments, n is 1 to 6; In some embodiments, n is 1-4 or 3-4. In some embodiments, y is 0 to 2; In some embodiments, y is 0-1. L is a hydrophobic ligand, In some embodiments, L is a Cp or C1-C4 alkyl ligand. X is a hydrophilic ligand; In some embodiments, X is an alkylamine, alkoxide, or halide ligand. M is a metal (including group 13 elements, B, Ga), In some embodiments, M has an oxidation state of +I up to +VI. o In some embodiments, M has an oxidation state of +IV to +V. In some embodiments, M can be a transition metal. In some embodiments, M is Ti, Ta, Nb, W, Mo, Hf, Zr, V or Cr. In some embodiments, M is Hf, Zr, Ta or Nb. In some embodiments, M is Zr. In some embodiments, M is Co, Fe, Ni, Cu or Zn. In some embodiments, the metal is not W or Mo. In some embodiments, M can be a rare earth metal. In some embodiments, M is La, Ce, or Y. In some embodiments, M can be a metal from group 2-13. In some embodiments, M is Ba, Sr, Mg, Ca or Sc. In some embodiments, M is not a precious metal.

[0107] More generally, in some embodiments, the selective ALD process employs a metal precursor. In some embodiments, the metal of the metal precursor may be selected from the group comprising Al, Ti, Ta, Nb, W, Mo, Hf, Zr, V, Cr, Co, Fe, Ni, Cu, Zn, La, Ce, Y, Ba, Sr, Mg, Ca, or Sc, or mixtures thereof. In some embodiments, the metal may be Al.

[0108] In some embodiments, the hydrophobic reactant is bis(methylcyclopentadienyl)methoxymethylzirconium(IV) ((CpMe)2-Zr-(OMe)Me).

[0109] In some embodiments, the hydrophobic reactant is bis(methylcyclopentadienyl)methoxymethylhafnium(IV) ((CpMe)2-Hf-(OMe)Me).

[0110] In other embodiments, the selective ALD process uses an Al precursor. Examples of Al precursors include trimethylaluminum (TMA), aluminum trichloride (AlCl3), dimethylaluminum isopropoxide (DMAI), and triethylaluminum (TEA). In some embodiments, the aluminum precursor is a heteroleptic aluminum compound. In some embodiments, the heteroleptic aluminum compound includes an alkyl group and another ligand, such as a halide, for example, Cl. In some embodiments, the aluminum compound is dimethylaluminum chloride. In some embodiments, the aluminum precursor is an alkyl precursor that includes two different alkyl groups as ligands. In some embodiments, the aluminum precursor is a metal organic compound. In some embodiments, the aluminum precursor is an organometallic compound.

[0111] In some embodiments, the second reactant provides one or more elements to the material to be selectively deposited, for example, the second reactant can be an oxygen precursor used to deposit a metal oxide, or a nitrogen precursor used to deposit a metal nitride.

[0112] In some embodiments, the second reactant comprises an oxygen precursor.

[0113] In some embodiments, the second reactant comprises HO.

[0114] In some embodiments, the second reactant comprises O3.

[0115] In some embodiments, the second reactant comprises H2O2.

[0116] In some embodiments, the second reactant comprises oxygen plasma, oxygen ions, oxygen radicals, atomic O, or excited species of oxygen.

[0117] In some embodiments, the second reactant comprises a nitrogen precursor.

[0118] In some embodiments, the second reactant comprises NH3.

[0119] In some embodiments, the second reactant comprises N2H4.

[0120] In some embodiments, the second reactant comprises nitrogen containing plasma, ions, radicals, atomic N or excited species comprising N. In some embodiments, the nitrogen reactant may comprise a mixture with the corresponding hydrogen species.

[0121] In some embodiments, other reactants may be utilized that provide elements other than N or O to the material being deposited. These reactants may be used in addition to the N or O second reactants, or may themselves serve as the second reactant. For example, a sulfur reactant may be used to deposit sulfides, in some embodiments a carbon reactant may be used to deposit carbon, or a silicon reactant may be used to deposit silicides.

[0122] In some embodiments, a second (or additional) reactant may be used to aid in the deposition of a metal or metallic film, such as an elemental metal film. For example, in some embodiments, a hydrogen reactant may be used.

[0123] Alternatively, as described with respect to Figure 2D, a metallic conductive film of interest may be selectively deposited on a second surface, a metallic surface, relative to an organic passivation layer. For example, U.S. Patent No. 8,956,971, issued February 17, 2015, and U.S. Patent No. 9,112,003, issued August 18, 2015, the entire disclosures of which are incorporated herein by reference for all purposes, teach a process for selectively depositing a metallic material on a metallic surface relative to a non-metallic surface, including an organic material. As described above with respect to Figure 3A, a further dielectric layer, a metal oxide material, may be selectively formed on the selectively formed metallic material layer prior to removal of the organic passivation layer.

[0124] In some embodiments, a thin film comprising a material of interest, such as aluminum oxide (e.g., Al2O3) or titanium nitride (e.g., TiN), is selectively deposited on one or more first dielectric or low-k surfaces relative to one or more second metal surfaces, such as copper, cobalt, titanium nitride, or tungsten surfaces. An exemplary process is shown in FIG.

[0125] In step 1A of FIG. 13, a substrate including a low-k surface and a metal surface is pretreated. As described above, in some embodiments, the pretreatment may include exposing the substrate to a plasma, such as a hydrogen plasma. In some embodiments, a non-plasma pretreatment process is performed. For example, in some embodiments, the substrate surface may be exposed to a silicon reactant, such as N-(trimethylsilyl)dimethylamine (TMSDMA) or trimethylchlorosilane. The reactant may be provided in a single long pulse, or in a sequence of multiple shorter pulses. In some embodiments, the reactant is provided in 1-25 pulses of about 1-60 seconds. Between pulses, the reaction chamber may be purged with an inert gas. The purge may be, for example, for about 1-30 seconds.

[0126] In some embodiments, the surface has the formula (R I )3Si(NR II R III ), wherein R I is a linear or branched C1-C10 hydrocarbon group, or a linear or branched C1-C5 alkyl group, or a linear or branched C1-C4 alkyl group; R II is a linear or branched C1-C10 hydrocarbon group, a linear or branched C1-C5 alkyl group, a linear or branched C1-C4 alkyl group, or hydrogen, and R III is a linear or branched C1 to C10 hydrocarbon group, or a linear or branched C1 to C5 alkyl group, or a linear or branched C1 to C4 alkyl group.

[0127] In some embodiments, the surface has the general formula (R I ) 3SiA, wherein R I is a linear or branched C1-C10 hydrocarbon group, or a linear or branched C1-C5 alkyl group, or a linear or branched C1-C4 alkyl group, and A is any ligand that reacts with silicon-containing surfaces, i.e., the silane bonds to the surface through ligand A, or ligand A forms a bond to the surface, but then ligand A may migrate away from the surface and / or the silane.

[0128] The temperature of the pretreatment process may be, for example, about 100 to about 300° C. The pressure during the pretreatment process may be, for example, about 10 -5 to about 760 Torr, or in some embodiments, from about 1 to 10 Torr, or from about 0.1 to about 10 Torr. In some embodiments, the pretreatment or cleaning process may be performed in situ, i.e., in the same reaction chamber as the selective deposition process.

[0129] In step 1B, an inhibitor, such as an organic material, such as polyimide, is selectively deposited on the metal surface. The inhibitor may be deposited as described herein. In some embodiments, the deposition temperature is about 160 to about 220° C. The reaction chamber pressure is, for example, about 10 -5 The pressure may be from about 1 to about 760 Torr, or in some embodiments, from about 1 to about 10 Torr, or from about 1 to about 25 Torr. In some embodiments, the deposition cycle to deposit the polyimide inhibitor is performed about 1 to about 1000 times.

[0130] In some embodiments, the polyimide inhibitor is deposited by alternately and sequentially contacting the substrate with DAH and PDMA, which may be alternately and sequentially delivered to the reaction space in pulses with pulse lengths of about 0.1-10 s, followed by a purge of about 0.1-10 s between pulses.

[0131] In step 1C, a clean-up process is performed to remove any inhibitors present on the low-k surface. The clean-up process may include an H2 plasma treatment. The clean-up process may be performed as described herein. In some embodiments, the clean-up process is performed at a temperature between about room temperature and about 400° C. A plasma power of about 10-1000 W or about 25-250 W may be used to generate a plasma with a flow rate of flowing H2, for example, about 10-500 sccm. The cleaning time after inhibitor deposition may be, for example, about 1-600 seconds.

[0132] In step 1D, a bake is performed. The bake can, for example, densify the inhibition layer and make it more robust, for example, to higher temperature processes that follow. In some embodiments, the bake is performed at a temperature of about 100 to about 800° C., for example, about 300 to about 600° C. In some embodiments, the bake step is performed at a temperature greater than 300° C. In some embodiments, the bake step is performed at a temperature of about 400° C. In some embodiments, the bake time is about 1 to about 15 minutes. The bake can include two steps, a first step at a lower temperature and a second step at a higher temperature. For example, the bake can include a first step at a temperature of about 250° C. and a second step at a temperature of about 400° C. In some embodiments, the first and second steps are performed for the same length of time. In other embodiments, they are performed for different lengths of time.

[0133] In some embodiments, the bake is performed in the same reactor as the subsequent selective deposition of the material of interest. In some embodiments, the bake is performed in the same reactor as the deposition of the inhibitor. In some embodiments, the bake is performed in a separate reaction chamber.

[0134] In step 1E, a material is selectively deposited on the dielectric surface relative to the metal surface containing the inhibitor by a deposition process. The selective deposition may be as described herein.

[0135] In some embodiments, the aluminum oxide is deposited in step 1E by alternately contacting the substrate with an aluminum reactant and an oxygen reactant. The aluminum reactant may include trimethylaluminum (TMA), aluminum trichloride (AlCl3), dimethylaluminum isopropoxide (DMAI), and triethylaluminum (TEA). In some embodiments, the aluminum precursor is a heteroleptic aluminum compound. In some embodiments, the heteroleptic aluminum compound includes an alkyl group and another ligand, such as a halide, for example, Cl. In some embodiments, the aluminum compound is dimethylaluminum chloride. In some embodiments, the aluminum precursor is an alkyl precursor that includes two different alkyl groups as ligands. In some embodiments, the aluminum precursor is a metal organic compound. In some embodiments, the aluminum precursor is an organometallic compound. The oxygen reactant may include, for example, water or H2O2. In some embodiments, the aluminum oxide may be deposited by an atomic layer deposition process in which the substrate is alternately and sequentially contacted with dimethylaluminum isopropoxide (DMAI) and water or H2O2. In some embodiments, the temperature in the reaction chamber during aluminum oxide deposition is about 150 to about 350° C. The reactant pulse time may be about 0.1 to about 10 seconds, and the purge time between reactant pulses may also be about 0.1 to about 10 seconds. The reaction chamber pressure may be, for example, about 10 -5 It may be up to about 760 Torr, or in some embodiments, from about 1 to 10 Torr.

[0136] In some embodiments, titanium nitride is deposited in step 1E by contacting the substrate with alternating titanium and nitrogen reactants. The titanium reactant may include, for example, TiCl4. The nitrogen reactant may include, for example, NH3. In some embodiments, TiN may be deposited by an atomic layer deposition process in which the substrate is alternately and sequentially contacted with TiCl4 and NH3. In some embodiments, the temperature in the reaction chamber during titanium nitride deposition is about 250 to about 500° C. The titanium reactant pulse time may be about 0.2 to about 10 seconds, and the nitrogen reactant pulse time may be about 0.1 to about 10 seconds. The purge time between reactant pulses may also be about 0.1 to about 10 seconds. The reaction chamber pressure may be, for example, about 10 -5 〜about 760 Torr, or in some embodiments, about 1-10 Torr. The titanium nitride layer was deposited using the process flow shown in FIG.

[0137] In step 1F, the substrate is subjected to a post-deposition cleaning step to remove inhibitors from the metal surface, such as treatment with H2 plasma. The cleaning step may include H2 plasma treatment. The cleaning process may be carried out as described herein. In some embodiments, the cleaning step is carried out at a temperature between about room temperature and about 400° C. A plasma power of about 10-2000 W, 25-1000 W, or 25-250 W may be used to generate the plasma with a flowing H2, e.g., flow rate of about 10-500 sccm. The cleaning time after deposition of the layer of interest may be, for example, about 1-600 seconds.

[0138] In some embodiments, a thin film comprising a material of interest, such as aluminum oxide (e.g., Al2O3) or titanium nitride (e.g., TiN), is selectively deposited on a first surface of a three-dimensional structure relative to one or more second surfaces. The three-dimensional structure may include, for example, vias or trenches. In some embodiments, an inhibitor, such as a polyimide layer, is non-selectively deposited on the three-dimensional structure. The inhibitor is then patterned to expose areas where selective deposition is desired. For example, anisotropic etching can be used to remove the layer from the surface where deposition is desired. Vapor deposition is then performed to deposit the layer of interest in the areas not covered by the inhibitor.

[0139] An exemplary process for selective deposition on a three-dimensional structure is shown in FIG. 14. A structure including a trench or via opening is shown. As shown in step 2A, an inhibitor is conformally deposited on the feature. The inhibitor may be deposited as described herein. For example, polyimide may be evaporated as described herein. In step 2B, the inhibitor is removed from the bottom of the trench by anisotropic etching. After etching, as shown in step 2C, the inhibitor is baked and a layer of interest is selectively deposited on the exposed surfaces at the bottom of the trench relative to the surfaces including the inhibitor. Finally, as shown in step 2D, the inhibitor material is removed from the remaining surfaces. Although not shown, additional pretreatment steps may be performed as described herein.

[0140] Passivation Barrier As noted above, the self-assembled monolayer (SAM) may act to inhibit the deposition of an organic passivation layer and therefore promote the selective deposition of an organic passivation layer onto other surfaces. Therefore, the term "blocking" is merely a label and does not necessarily imply the deposition of a 100% inactive organic passivation layer. As noted elsewhere herein, even imperfect selectivity may be sufficient to obtain a completely selective structure after the etch-back process.

[0141] In one embodiment, a passivation barrier layer is formed on the second surface to inhibit deposition to provide a sulfur-containing SAM. In one embodiment, the second surface is a metallic surface. In one embodiment, the metallic surface is pretreated by an acid treatment prior to SAM formation.

[0142] deposition equipment Examples of suitable reactors that can be used in the selective deposition processes described herein include commercially available ALD equipment. In addition to ALD reactors, many other types of reactors that allow for the growth of organic passivation layers can be used, including CVD reactors, VDP reactors, and MLD reactors.

[0143] 1A-1D may be accomplished in up to five processes: (1) pretreatment, (2) deposition of a selective organic passivation layer on a first surface, (3) partial etchback of any organic material from above the second surface, also referred to as a "clean-up" etch, (4) selective dielectric deposition on the second surface, and (5) removal of the organic passivation layer from above the first surface.

[0144] In one embodiment, the sequence measures may be minimized by combining (2) the deposition of the selective organic passivation layer and (3) the partial etchback in one chamber using a cluster chamber, followed by (4) the selective dielectric deposition on the second surface. Pretreatment may either be performed on a separate platform (e.g., a wet bench) or omitted by adjusting the specific recipe. Removal of the organic passivation layer may be performed in a separate ashing tool, such as those often used for the removal of photoresist and other organic materials, or in a deposition chamber using the same or similar chemistry used for the partial etchback of the organic materials. Thus, the deposition step and the intervening etchback may be performed in a platform with two reactors containing either four or eight processing stations for polyimide deposition and etchback, and two reactors containing either four or eight processing stations for the selective dielectric deposition.

[0145] In some embodiments, the cluster tool includes three or more reaction chambers. For example, a first chamber may be used for one or both of the pretreatment and etching processes. A second chamber may be used for the deposition of an organic layer, and a third chamber may be used for the selective deposition of a film of interest. The bake process may be performed in situ in the same chamber as the selective deposition of the film of interest, or may be performed in a different chamber.

[0146] In some embodiments, as shown in Figure 13, the selective deposition process described herein can be carried out in at least six steps: (Step 1A) pretreatment, (Step 1B) selective inhibitor deposition, such as deposition of an organic layer deposition on a first surface, (Step 1C) partial etch back of any organic material from above the second surface, also referred to as a "clean-up" etch, (Step 1D) baking of the organic layer, (Step 1E) selective deposition on the second surface, and (Step 1F) removal of the organic layer from above the first surface.

[0147] Referring to FIG. 5, an apparatus 100 for in situ polymer deposition and etch back of organic materials is provided. The apparatus 100 includes a reaction chamber defining a reaction space 115 configured to accommodate at least one substrate 120. The apparatus 100 also includes a first reactant container 105 configured to vaporize a first organic reactant 110 to form a first reactant vapor. A gas line 130 fluidly connects the first reactant container 105 to the reaction space 115, which may accommodate the substrate 120 therein. The gas line 130 is configured to selectively transport the first reactant vapor from the first reactant container 105 to an intake manifold 135 to the reaction space 115. The apparatus 100 also includes a second reactant container 140 that holds a second reactant 145. In some embodiments, the second reactant 145 is naturally gaseous, while in other embodiments, the second reactant container 140 is also configured to vaporize the second reactant 145 from a naturally liquid or solid state. The second reactant container 140 is in selective fluid communication with the inlet manifold 135. The inlet manifold 135 may include a shared distribution plenum spanning the width of the chamber, in a showerhead or cross-flow configuration, or may maintain separate paths to the reaction space 120 for the separate reactants. For sequential deposition embodiments, it may be desirable to keep the reactant inlet paths separate until insertion into the reaction space 115 to avoid reaction along the surfaces of a common flow path for multiple reactants, which may lead to particle generation. In some embodiments, the apparatus may include additional containers for providing additional reactants.

[0148] The illustrated apparatus 100 also includes a plasma source 147. Although illustrated generally as attached to the reaction space 115, one skilled in the art will appreciate that the plasma source may be a remote plasma source that is external to the reaction space 115, or may be an in-situ plasma generator for generating a DC plasma (e.g., capacitively coupled) within the reaction space 115. Alternatively or additionally, an ozone generator may be used to remove organic materials.

[0149] One or more additional gas sources 150 are in selective fluid communication with the first reactant container 105, the reaction space 115, and the plasma source 147 (to the extent separate from the reaction space 115). The gas sources 150 may include inert gases, which may serve as purge gases and carrier gases for the plasma etchback, as well as other gases (e.g., Ar / H2). A supply of inert gas from a gas source may also be in selective fluid communication with the second reactant container 140, as shown, and any other desired reactant containers, to serve as a carrier gas.

[0150] The control system 125 communicates with the valves of the gas distribution system according to the organic passivation layer deposition and etchback methods and described herein. The control system 125 typically includes at least one processor and memory programmed for the desired process. In sequential deposition processes, the valves are operated to alternately and repeatedly expose the substrate to reactants, whereas in simultaneous delivery of reactants in conventional CVD processes, the valves may be operated to simultaneously expose the substrate to mutually reactive reactants.

[0151] An exhaust port 155 from the reaction space 115 communicates with a vacuum pump 165 through an exhaust line 160. A control system 125 is configured to operate the vacuum pump 165 to maintain a desired operating pressure and to exhaust excess reactant vapors and by-products through the exhaust port 155.

[0152] The control system 125 may also control pressures and temperatures in various components of the apparatus 100. For example, the control system may be programmed to maintain the substrate 120 at a temperature suitable for the process being performed. In one embodiment, the control system 125 is also configured to maintain the first reactant 110 in the first reactant container 105 at a temperature A and the substrate 120 in the reaction space 115 at a temperature B, where temperature B is lower than temperature A. In an embodiment, the control system 125 or a separate temperature control is also configured to maintain the gas line 130 at a temperature C, where temperature C is higher than temperature A.

[0153] Thus, the apparatus 100 includes solid source containers 105, 140 (e.g., one container for diamine and one container for dianhydride precursor) for vaporizing and supplying the above-mentioned reactants for polymer deposition. The plasma source 147 is in communication with a gas source 150 including a source of H2 and an inert gas (e.g., a noble gas such as argon or helium). In addition, the apparatus 100 includes a control system 125 that is programmed to supply gases and operate the plasma source to perform the polymer deposition and hydrogen plasma etch-back described herein. The control system 125 maintains the substrate 120 at a temperature in the range of 180°C to 220°C, or about 190°C to 210°C, such that the polymer deposition and etch-back can be performed sequentially at the same temperature without removing the substrate 120 from the reaction space 115. The etch-back may be for 0.5 to 600 seconds, 1 to 120 seconds, 1 to 60 seconds, 1 to 20 seconds, 2 to 15 seconds, and 5 to 15 seconds. As another example, a pulsed ozone (O3) etch process can be used for the etch-back process. As one skilled in the art would understand, the processing conditions may be modified for a slower and more controlled etch for partial etch-back that minimizes over-etching of the desired passivation layer on the first surface. In fact, the etch rate is highly dependent on the etch temperature for O3 etching of polymers. Since the etching process is usually very short, combining selective deposition of a passivation layer with partial etch-back would not significantly increase the processing time of a single chamber. The same equipment and etchant may also be used for removal of the passivation layer.

[0154] The apparatus 100 configured for polymer deposition and etch-back can be a showerhead reactor with solid source containers for DAH (evaporation temperature about 40° C.) and PMDA (evaporation temperature about 170° C.). In one embodiment, the plasma source 147 comprises an in-situ DC plasma (e.g., capacitively coupled) device that supplies argon and H2 for in-situ etch-back. In another embodiment, the apparatus 100 can be a cross-flow reactor rather than a showerhead reactor, but still have the above-mentioned with solid source containers 105, 140 and DC plasma capabilities. In another embodiment, the plasma source 147 comprises a remote plasma coupled to the reaction space 115 to provide a product of the plasma with an Ar / H2 plasma. In another embodiment, the plasma source 147 can be replaced with an ozone generator coupled to the reaction space 115. For example, a remote plasma generator or a remote ozone generator can be connected to the showerhead reactor.

[0155] The polymer deposition apparatus 100 desirably includes an auto-cleaning capability to keep the reaction space 115 and exhaust line 160 clean even after multiple depositions. In some embodiments, the in-situ or remote Ar / H2 plasma source 147 described above for etch-back may be operated without a fabrication substrate and only periodically (rather than every wafer), and therefore may be suitable for periodic chamber cleaning, possibly at higher power or higher temperature. Alternatively, the polymer deposition chamber may be provided with a remote plasma supplied with NF3 etching, or an ozone supply for periodic chamber cleaning. In some embodiments, the chamber cleaning process may be operated without a fabrication substrate and only periodically (rather than every wafer), and therefore the O3 / N2 supply may be suitable for periodic chamber cleaning, possibly at higher power or temperature, compared to the polymer partial etch-back or removal process.

[0156] Line end position Referring to FIG. 6, in some embodiments, selective deposition on the second surface may be achieved by selective passivation of the first surface after selective deposition of a dielectric, such as ZrO2, on the second surface, as described above. In the illustrated flow chart, the first surface may be metallic (e.g., a buried metal feature in an interlayer dielectric, i.e., ILD, of an integrated circuit) and the second surface may be a dielectric (e.g., an ILD). The passivation may comprise a polymer or other organic material that is selectively deposited on the first surface, relative to some of the second surface, in step 1. This is followed by an etchback of the polymer, sometimes referred to as a "clean-up" etch that completes the selectivity, to remove the polymer that may have been deposited on the second surface in step 2, without removing all of the polymer from the first surface. A dielectric material is selectively deposited on the second surface in step 3, as the polymer acts as a passivation layer. Any number of suitable dielectric materials may be used in step 3. In some embodiments, the dielectric material may be selected from ZrO2 and other metal oxides such as transition metal oxides or aluminum oxide, or other dielectric oxides, including mixtures that have etch selectivity over SiO2-based materials, or slow etch rates in the context of etching SiO2-based materials. Some such metal oxides may have high k values, higher than 5, or even higher than 10, yet are thin and located in a position that avoids significant parasitic capacitance in metallization structures, and advantageously allow masking of the surface against selective etching of silicon oxide materials. In other embodiments, the dielectric may be a silicon oxide-based material, but may be thicker to act as an etch mask, as described herein. In step 4 of FIG. 6, the polymer passivation is removed from the first surface.

[0157] FIG. 7 illustrates the effect of etch-back time to remove passivation (e.g., polymer or other organic layer) from the second surface on the formed dielectric layer. More specifically, by selecting the extent of the intermediate polymer etch-back process, the location of the edge of the selectively formed dielectric layer can be controlled relative to the interface between the underlying metallic surface and the dielectric surface. In an embodiment, as seen in the first row of the diagram in FIG. 7, a polymer is deposited on the first surface relative to a portion of the second surface as previously described in step 1 of FIG. 6. As seen in the polymer as deposition diagram, the deposition of the polymer on the first surface creates a surface with a thicker polymer layer above the first surface, with a relatively thinner polymer layer above the second surface, resulting in a polymer thickness at the interface between the first and second surfaces that slopes downward from the first surface to the second surface. Subsequently, as previously described in step 2 of FIG. 6, a polymer etch-back may be performed for various durations (or the same duration with different etch rates, such as by different temperatures or etchant concentrations, or different durations and different etch rates) to control the thickness and shape of the polymer layer, as seen in rows 2 to 6 of the first column of the diagram in FIG. 7. The etch-back may be isotropic or anisotropic. In some embodiments, as seen in row 2 of the diagram in FIG. 7, the polymer etch time is minimal and the polymer etch does not remove enough polymer to expose the second surface. In this case, since both the first and second surfaces are covered with a passivation layer, subsequent selective dielectric deposition will not work and even if a small amount of dielectric is deposited, it will be removed in a lift-off process by removing the passivation layer. In some embodiments, as seen in row 3 of the diagram in FIG. 7, the polymer etch time is selected to remove most of the formed polymer from the second surface, but leave a polymer layer tip that extends onto the second surface beyond the boundary of the first and second surfaces. In this case, subsequent selective deposition of the dielectric and removal of the polymer leaves a gap between the edges of the deposited dielectric and the interface of the first and second surfaces.In some embodiments, the polymer etch time is selected to remove the formed polymer from the second surface, leaving the polymer layer edge aligned with the boundary of the first and second surfaces, as seen in the fourth row of the diagram in FIG. 18. In this case, subsequent selective deposition of dielectric and removal of the polymer leaves the bottom surface edge of the deposited dielectric aligned with the boundary of the first and second surfaces. In some embodiments, the polymer etch time is selected to remove the polymer from the second surface and a portion of the polymer from the first surface, as seen in the fifth row of the diagram in FIG. 7, leaving a first gap between the top of the polymer layer and the boundary of the first and second surfaces. In this case, subsequent selective deposition of dielectric and removal of the polymer leaves the deposited dielectric extending beyond the boundary of the first and second surfaces and overlapping the first surface, as seen in the sixth row of the diagram in FIG. 7. If the polymer etch time is performed long enough that the polymer etch completely removes the polymer from both the first and second surfaces, the subsequent dielectric deposition is not selective.

[0158] Therefore, as previously described in steps 3 and 4 of FIG. 6, selective deposition of a selective dielectric and partial polymer etchback may be performed to create various relationships between the edge of the selectively deposited dielectric layer on the second surface and the interface between the first and second surfaces, depending on the extent of the passivation etchback after selective deposition of the passivation, as seen in the right-most images in rows 2 through 6 of the third column of the diagram in FIG. 6. In some embodiments, no dielectric layer is formed because the polymer layer has passivated the second surface, as seen in row 2 of the diagram in FIG. 7. In some embodiments, a gap exists between the dielectric on the second surface and the first surface, as seen in row 3 of the diagram in FIG. 7. In some embodiments, the dielectric layer edge lines up with the boundary of the first and second surfaces, as seen in row 4 of the diagram in FIG. 7. In some embodiments, the dielectric layer overlaps the first surface, as seen in row 5 of the diagram in FIG. 7. In some arrangements, such as that shown in the sixth row of the diagram in FIG. 18, a polymer layer does not passivate the first surface, so that a dielectric layer is formed on both the first and second surfaces.

[0159] FIG. 8 illustrates the effect of the deposition thickness of the passivation layer on the dielectric layer formed. More specifically, the location of the edge of the selectively formed dielectric layer may be controlled relative to the boundary between the underlying metallic surface and the dielectric surface by selecting the thickness of the intermediate polymer passivation layer. As the deposition thickness of the passivation layer increases, the thickness of the passivation layer on both the first and second surfaces increases. However, because the passivation layer is selectively deposited on the first surface, the increase in passivation thickness on the second surface is less than the increase in passivation thickness on the first surface. Thus, the passivation etchback, dielectric deposition, and passivation removal will create a selective dielectric layer at various locations relative to the boundary of the first and second surfaces. In some embodiments, a passivation layer is deposited that creates a gap between the selectively deposited dielectric layer edge and the boundary of the first and second surfaces, as seen in the first column of the diagram in FIG. 8. In some embodiments, as seen in the second column of diagrams in FIG. 8, a thicker polymer layer is deposited that creates a larger gap between the selectively deposited dielectric layer edge and the first surface.

[0160] FIG. 9 illustrates the effect of the thickness of the selectively deposited dielectric on the relative position of the formed dielectric layer and the boundary of the first and second surfaces. More specifically, by selecting the thickness of the selective dielectric layer, the position of the edge of the selectively formed dielectric layer can be controlled with respect to the boundary of the underlying metallic surface and the dielectric surface. As the thickness of the selectively deposited dielectric layer on the second surface increases, the dielectric overhang edge extends further and further past the boundary of the first and second surfaces. In some embodiments, a dielectric layer is deposited that creates a particular overhang structure, as seen in the first column of the diagrams in FIG. 9. In some embodiments, a thicker dielectric layer is deposited that creates a larger overhang, as seen in the second column of the diagrams in FIG. 9. In some embodiments, an even thicker dielectric layer is deposited that creates an even larger dielectric overhang on the first surface, as seen in the third column of the diagrams in FIG. In certain subsequent processes, such as anisotropic processing (e.g., anisotropic reactive ion etching), the extent of the overhang may shade portions of the first surface and protect them from subsequent processing.

[0161] Thus, in some embodiments, the dielectric layer is mostly selectively formed on a dielectric surface similar to FIG. 1D, but is selectively deposited to create an overhang and / or overlap with the metallic feature. In some embodiments, the dielectric layer does not include an overhang or overlap, and the edge of the dielectric selectively deposited on the dielectric may line up with the edge of the metallic feature, or there may be a gap between the edge of the selectively deposited dielectric layer and the metallic feature. Because of the selective deposition techniques taught herein, the selectively deposited dielectric layer may have features characteristic of selective deposition without using traditional masking and etching to pattern the dielectric layer. For example, the edge of the dielectric layer may taper at a slope of less than 45 degrees, rather than having vertical or steeply sloping sidewalls typical of photolithographically patterned layers. This characteristic etch shape may remain regardless of whether the selectively deposited layer is exposed to a cleanup etch or partial etchback.

[0162] 10A-10D illustrate how topography affects the relationship of the selectively deposited dielectric to the interface of the first and second surfaces.

[0163] 10A illustrates a planar structure resulting in an edge of a selectively deposited dielectric 2502 lining up with the boundary of the first and second surfaces. For example, a first surface passivated by a passivation layer 2504, which is a polymeric material, can be defined by a metallic material such as buried metal 2506, and a second surface can be defined by a low-k dielectric such as an inter-layer dielectric (ILD) 2508. The passivation layer 2504 is selectively deposited on the first surface, and the dielectric layer 2502 is selectively deposited on the second surface, with the edge of the dielectric layer 2502 lining up with the boundary of the first and second surfaces.

[0164] 10B illustrates a first surface recessed relative to a second surface. As above, the first surface may comprise a metallic material 2506 recessed within a low-k dielectric material 2508 that defines the second surface. A passivation layer 2504 is selectively formed on the first surface within the recess. A dielectric layer 2502 is deposited on the second surface and on the recess walls, such that an end of the dielectric layer 2502 meets the surface of the passivation layer 2504. Removal of the passivation layer 2504 results in the dielectric layer 2502 being selectively formed on the second surface, but will overlap the first surface (e.g., metallic features 2506).

[0165] 10C illustrates a first surface that is elevated relative to a second surface. The first surface may be defined by a metallic material 2506 that is embedded in and protrudes above the second surface, which may be a low-k dielectric material 2508. A passivation layer 2504 is deposited over the first surface including the protruding sidewalls, and therefore at least partially over the second surface. A dielectric layer 2502 is deposited over the second surface, but is spaced from the first surface by the thickness of the passivation material 2504 on the sidewalls. Thus, after removal of the passivation layer 2504, there is a gap between the dielectric layer 2502 and the first surface (e.g., the protruding metallic feature 2606).

[0166] Figure 10D illustrates a recessed first surface of some embodiments similar to Figure 21B but with a thicker passivation layer 2504 filling the recess. In this case, after removal of the passivation layer 2504, a gap remains between the dielectric layer 2502 selectively deposited on the second surface and the first surface. In this case, the gap takes the form of a vertical sidewall of the second surface, which is then exposed to subsequent processing.

[0167] Thus, Figures 7-10D illustrate variables that may be adapted to adjust the position of the selectively deposited dielectric 2502 (e.g., on the second surface of the dielectric) relative to the interface between the first and second surfaces (e.g., between the metallic feature 2506 and the low-k dielectric 2508). In particular, Figure 7 illustrates how the extent or time of etchback of the passivation layer may affect the relative position, Figure 8 illustrates how the thickness of the selectively deposited passivation layer may affect the relative position, Figure 9 illustrates how the thickness of the selectively deposited dielectric layer may affect the relative position, and Figures 10A-10D illustrate how the topography of the first and second surfaces may affect the relative position. Thus, these variables may be adapted to affect whether the selectively deposited dielectric on the second surface is aligned with, has a gap to, or overlaps the first surface.

[0168] Application of the Example 11A-11E illustrate, in some embodiments, devices and processes for producing devices with improved electrical isolation. Figure 11A illustrates a partially assembled integrated circuit similar to the planar structure shown in Figure 10A with an embedded metallic feature 2606 defining a first surface that is coplanar with a second surface defined by a surrounding low-k material 2608. The metallic feature comprises a first material, further comprising Cu 2610 and a TaN barrier material 2612, positioned within the first low-k dielectric material 2608.

[0169] Figure 11B illustrates the device of Figure 11A followed by a conductive barrier layer 2614 over the first material. In some embodiments, the barrier layer 2614 may be W. Although shown as protruding, in some embodiments the barrier material 2614 over the Cu 2610 lines or vias may be embedded in and flush with the surrounding low-k material 2608.

[0170] 11C illustrates the device of FIG. 11B following selective deposition of a passivation layer 2604 over the first surface defined by the metallic barrier layer 2614(W), with the edges of the first surface exposed. In some embodiments, the passivation layer 2604 may be an organic material such as a polymer. In some embodiments, the selective deposition of the passivation layer 2604 is followed by an etch-back of the passivation layer material sufficient to expose some of the metallic first surface.

[0171] 11D illustrates the device of FIG. 11C following selective deposition of a dielectric layer 2602 on a second surface overlapping the metallic first surface. In some embodiments, the dielectric layer 2602 may be a high-k material. In some embodiments, the high-k material may be ZrO2. In some embodiments, the selective dielectric layer 2602 may be a low-k material such as SiOC, Al2O3, and SiN. In some embodiments, the selectively deposited dielectric material 2602 may act as an etch stop for a subsequent etch through the low-k material 2608 to open a trench or via that exposes the metallic barrier material 2614.

[0172] FIG. 11E illustrates the device of FIG. 11D following removal of the polymer passivation layer 2604, thereby exposing the underlying metal layer surface (in this case, the metal layer surface of the barrier material 2614). The selective dielectric 2602 overlaps the metallic first surface defined by the barrier layer 2614, reducing the risk of shorting when a subsequent metallic feature (e.g., an overlying metal line or metal via) is formed on the barrier layer 2614. In particular, a low-k material is deposited over the structure of FIG. 11E, and an opening is created and filled with metal. The opening is created by masking and low-k etching, and an etch stop on the selectively deposited dielectric (e.g., ZrO2). Misalignment is protected by the overlap of the selectively deposited dielectric 2602 with the metallic feature defined by the barrier layer 2614, due to condition selection during passivation, etchback, dielectric deposition, and / or topography. In that way, the overlap avoids contact with adjacent metallic features or undesired etching of the lower low-k material 2608. Note that the selectively deposited dielectric material 2602 may remain in the final integrated circuit device after serving as an etch stop between ILD layers. Although high-k materials are typically avoided in metallization processes, parasitic capacitance is minimal. The minimal parasitic capacitance is due to the dominant location of the high-k material over the low-k material, and the thickness of the high-k material is a function of that, and the advantage of the high selectivity of this dielectric capping layer over the high-k material outweighs the slight parasitic capacitance introduced by the material selection. Of course, high etch selectivity may also be achieved with lower low-k materials, as they are selectively deposited over the ILD.

[0173] 12A-12B illustrate devices and processes for creating devices with air gaps that, in some embodiments, may be desirable for various reasons, such as reducing parasitic capacitance between closely spaced metallic features (e.g., metal lines) in an integrated circuit. FIG. 12A illustrates a planar surface of a partially assembled integrated circuit of some embodiments, similar to the device previously shown in FIG. 10A. The initial structure may be a first surface defined by metallic features 2706 (e.g., Cu lines with dielectric and barrier liners) surrounded by a second surface defined by a dielectric material 2608 (e.g., low-k ILD). A passivation layer 2704 is selectively deposited on the first surface, and an etchback is performed to expose the second surface while leaving the passivation layer 2704 on the first surface and partially on the second surface. A dielectric 2702 is selectively deposited on the second surface, with the dielectric layer ends spaced apart from the boundary of the first and second surfaces onto the second surface. FIG. 12B illustrates the device of FIG. 12A after the passivation layer 2704 has been removed to expose the first surface and partially expose the second surface previously covered by the first material, leaving gaps 2710 between the selectively deposited dielectric material and the first surface (metallic features 2706). The exposed second material is then selectively etched to form cavities 2712 in those gaps 2710 next to the metallic features. In some embodiments, the selectively etched second material is SiO. In some embodiments, the selective etch is an HBr dry etch. While an HBr dry etch may selectively etch silicon oxide at about 6-8 nm / min, certain other materials etch slower, such as silicon nitride (<0.3 nm / min) and zirconium oxide (<0.3 nm / min), and would be unlikely to etch tungsten without chlorine (e.g., Cl2) or sulfur hexafluoride (e.g., SF6). Deposition of a third material 2714 that is sufficiently poorly conformal, such as a standard low-k material, leaves voids 2716 in the low-k material 2708 adjacent to the sides of the metallic features 2706. As is known in the art, the air cavities lower the overall k value of the ILD and reduce the parasitic capacitance between the metallic features.

[0174] Although specific embodiments and examples have been discussed, those skilled in the art will recognize that the scope of the claims extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses and obvious modifications and their equivalents.

Claims

1. 1. A method of selective deposition on a first surface of a substrate relative to a second surface of the substrate, the first and second surfaces having different compositions, the method comprising, in sequence: selectively forming an inhibitor layer on the second surface from a gas phase reactant on the first surface; baking the inhibitor layer; and selectively depositing a layer of interest from a vapor phase reactive material on said second surface relative to the passivation layer.

2. The method of claim 1 further comprising treating the first and second surfaces prior to selectively forming the inhibitor layer.

3. The method of claim 2 , wherein treating comprises exposing the substrate to a plasma.

4. The method of claim 2 , wherein treating comprises exposing the substrate to a silane, such as an alkylaminosilane.

5. The method of claim 4, wherein treating comprises exposing the substrate to N-(trimethylsilyl)dimethylamine (TMSDMA) or trimethylchlorosilane.

6. 3. The method of claim 2, further comprising washing the second surface after selectively forming the inhibitor layer to remove any inhibitor.

7. The method of claim 6 , wherein cleaning comprises treatment with a hydrogen plasma.

8. The method of claim 1, wherein baking comprises heating the substrate to a temperature of about 300-400°C.

9. The method of claim 1 , further comprising cleaning the first and second surfaces after selectively depositing the layer of interest.

10. The method of claim 9 , wherein cleaning comprises treating the surface with a hydrogen plasma.

11. The method of claim 1 , wherein selectively forming an inhibitor layer comprises selectively depositing an organic layer on the first surface.

12. The method of claim 11 , wherein the organic layer is a polyimide layer.

13. The method of claim 1 , wherein the layer of interest is selectively deposited by an atomic layer deposition process.

14. The method of claim 1 , wherein the first surface comprises a metal or metallic material and the second surface comprises a dielectric material.

15. The method of claim 1 , wherein the layer of interest comprises a metal oxide.

16. 16. The method of claim 15, wherein the metal oxide comprises zirconium oxide, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, or other transition metal oxides or mixtures thereof.

17. The method of claim 15 , wherein the metal oxide comprises a dielectric transition metal oxide.

18. The method of claim 15 , wherein the metal oxide comprises aluminum oxide.

19. The aluminum oxide may be trimethylaluminum (TMA), dimethylaluminum chloride, or aluminum trichloride (AlCl ３ 20. The method of claim 18, wherein the aluminum precursor is deposited using aluminum precursors including dimethylaluminum isopropoxide (DMAI) or triethylaluminum (TEA).

20. 20. The method of claim 18, wherein the aluminum oxide is deposited using an aluminum precursor that includes a heteroleptic aluminum compound that includes an alkyl group and another ligand such as a halide, e.g., Cl.

21. 20. The method of claim 18, wherein the aluminum oxide is deposited using an aluminum precursor comprising an aluminum alkyl compound that contains two different alkyl groups as ligands.

22. 20. The method of claim 18, wherein the aluminum compound is deposited using an aluminum precursor comprising a metal organoaluminum compound or an organometallic aluminum compound.

23. The method of claim 1 , wherein the layer of interest comprises a metal nitride.

24. 24. The method of claim 23, wherein the metal nitride is titanium nitride.

25. The titanium nitride is TiCl ４ and N.H. ３ 25. The method of claim 24, wherein the film is deposited by a deposition process from

26. 1. A cluster tool for selective deposition of a layer of interest on a second surface of a substrate relative to a first surface of the substrate, wherein the first and second surfaces have different compositions, the cluster tool comprising: a first module configured to pre-treat the substrate; a second module configured to treat the substrate with a plasma; a third module configured for deposition of an inhibitor on the first surface of the substrate relative to the second surface of the substrate; and a fourth module configured for deposition of the layer of the target.

27. 1. A system for selectively depositing a dielectric material on a second surface of a substrate relative to a first surface of the substrate, the system comprising: a first chamber configured for selective deposition of an organic passivation layer and partial etchback of said organic passivation layer; a second chamber configured for selective deposition of the dielectric material onto the second surface relative to the first surface of the substrate.

28. 1. A system for selective deposition of a film of interest onto a second surface of a substrate relative to a first surface of the substrate, the system comprising: a first chamber configured to pretreat the substrate and for an etching process; a second chamber configured for selective deposition of an organic passivation layer; a third chamber configured for selective deposition of the film of interest on a second surface of the substrate relative to the first surface of the substrate.

29. 30. The system of claim 28, wherein the third chamber is further configured for a bake process.

30. 30. The system of claim 28, further comprising a fourth chamber configured for a bake process.

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