Apparatus and method for controlling ion energy distribution

Abstract

To provide an apparatus and a method for controlling ion energy distribution during plasma processing.SOLUTION: An apparatus includes a substrate support including a substrate electrode that applies a substrate voltage to a substrate, a recessed edge ring electrode that applies an edge ring voltage to an edge ring, a substrate voltage control circuit coupled to the substrate electrode, and an edge ring voltage control circuit coupled to the edge ring electrode. The substrate electrode, the edge ring electrode, or both, are coupled to a power module configured to actively control an energy distribution function width of ions reaching the substrate, the edge ring, or both, to control the energy distribution function width of the ions during substrate processing.SELECTED DRAWING: Figure 5A

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to apparatus and methods for plasma processing of a substrate, and more particularly to apparatus and methods for controlling ion energy distribution during plasma processing. [Background technology]

[0002] During plasma processing of a substrate, ions play an important role in the surface treatment, etching, and deposition of the substrate. Ions impacting the substrate surface may have various energies, described by the ion energy distribution function (IEDF). Control over the IEDF can be an important factor in various substrate processing schemes. However, controlling the IEDF remains a challenge. For example, when a periodically alternating voltage is applied to the electrodes of the chamber, a plasma sheath may develop above the substrate. Ions flowing toward the substrate are accelerated by the plasma sheath voltage, which is correlated with the voltage applied to the electrodes. At the same time, the ion current may charge the substrate and change the substrate potential, which in turn affects the plasma sheath voltage such that the IEDF at the substrate surface is also affected, e.g., widened. State-of-the-art methods for controlling the IEDF in such cases and others are based on inefficient iterative loops.

[0003] New and improved methods of controlling IEDF are needed. Summary of the Invention

[0004] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to apparatus and methods for plasma processing of a substrate, and more particularly to apparatus and methods for controlling ion energy distribution during plasma processing.

[0005] In one embodiment, a method for controlling an ion energy distribution function (IEDF) is provided. The method includes injecting a voltage to an electrode of a process chamber by activating a primary pulser coupled to an IEDF width control module, and measuring a current of the IEDF width control module and a voltage or voltage derivative of the IEDF width control module. The method further includes calculating an ion current of the process chamber and a volume of the process chamber based on the current and the voltage or voltage derivative of the IEDF width control module. The method further includes determining a set point for a DC voltage of the primary pulser, a set point for a voltage or voltage derivative of the IEDF width control module, or both, and adjusting the DC voltage of the primary pulser, the voltage or voltage derivative of the IEDF width control module, or both to the determined set points to control the width of the IEDF.

[0006] In another embodiment, an apparatus for controlling ion energy distribution is provided. The apparatus includes a substrate support having a body with a substrate support portion with an embedded substrate electrode for applying a substrate voltage to the substrate. The body further includes an edge ring portion disposed adjacent the substrate support portion with an embedded edge ring electrode for applying an edge ring voltage to the edge ring. The apparatus further includes a substrate voltage control circuit coupled to the substrate electrode and an edge ring voltage control circuit coupled to the edge ring electrode. The substrate electrode is coupled to a power module configured to actively control an energy distribution function width of ions reaching the substrate, or the edge ring electrode is coupled to a power module configured to actively control an energy distribution function width of ions reaching the edge ring, or a combination thereof. The substrate voltage control circuit, the edge ring voltage control circuit, or both, comprises a main pulser coupled to a current return path, the current return path is coupled to the power module and the process chamber, the power module comprises a voltage source, a current source, or a combination thereof.

[0007] In another embodiment, an apparatus for controlling ion energy distribution is provided. The apparatus includes a substrate support having a body with a substrate support portion with an embedded substrate electrode for applying a substrate voltage to the substrate. The body further includes an edge ring portion disposed adjacent the substrate support portion with an embedded edge ring electrode for applying an edge ring voltage to the edge ring. The apparatus further includes a substrate voltage control circuit coupled to the substrate electrode and an edge ring voltage control circuit coupled to the edge ring electrode. The substrate electrode is coupled to a power module configured to actively control an energy distribution function width of ions reaching the substrate, or the edge ring electrode is coupled to a power module configured to actively control an energy distribution function width of ions reaching the edge ring, or a combination thereof. The substrate voltage control circuit, the edge ring voltage control circuit, or both, comprises a primary pulser coupled to a power module, the power module coupled to the process chamber, the power module comprising a voltage source, a current source, or a combination thereof.

[0008] In another embodiment, an apparatus for controlling ion energy distribution is provided. The apparatus includes a substrate support having a body with a substrate support portion with an embedded substrate electrode that applies a substrate voltage to the substrate. The body further includes an edge ring portion disposed adjacent the substrate support portion with an embedded edge ring electrode that applies an edge ring voltage to the edge ring. The apparatus further includes a substrate voltage control circuit coupled to the substrate electrode and an edge ring voltage control circuit coupled to the edge ring electrode. The substrate electrode is coupled to a power module configured to actively control an energy distribution function width of ions reaching the substrate, or the edge ring electrode is coupled to a power module configured to actively control an energy distribution function width of ions reaching the edge ring, or a combination thereof. The substrate voltage control circuit, the edge ring voltage control circuit, or both, comprises a primary pulser coupled to a power module, the power module coupled to the process chamber, the power module in parallel with the substrate chucking and bias compensation module, the power module comprising a voltage source, a current source, or a combination thereof.

[0009] In order that the above-listed features of the present disclosure may be understood in detail, the present disclosure as outlined above may be described in more detail with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only illustrate exemplary embodiments of the present disclosure and therefore should not be considered as limiting its scope, since the present disclosure may admit of other equally effective implementations. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional view of an example processing chamber in accordance with at least one embodiment of the present disclosure. [Diagram 2] 1 is a schematic diagram of an example processing chamber in accordance with at least one embodiment of the present disclosure. [Figure 3A]1 is an example graph illustrating three different bias voltage waveforms on a substrate in accordance with at least one embodiment of the present disclosure. [Figure 3B] FIG. 3B illustrates an example plot of IEDF counter-ion energy for three different bias voltage waveforms on the substrate shown in FIG. 3A, in accordance with at least one embodiment of the present disclosure. [Figure 4A] FIG. 2 is a schematic diagram of an example circuit in accordance with at least one embodiment of the present disclosure. [Figure 4B] FIG. 2 is a schematic diagram of an example circuit in accordance with at least one embodiment of the present disclosure. [Figure 4C] FIG. 2 is a schematic diagram of an example circuit in accordance with at least one embodiment of the present disclosure. [Figure 4D] FIG. 2 is a schematic diagram of an example circuit in accordance with at least one embodiment of the present disclosure. [Figure 5A] FIG. 2 is an example circuit schematic diagram illustrating an IEDF width control circuit that drives electrodes of a substrate support assembly, in accordance with at least one embodiment of the present disclosure. [Figure 5B] FIG. 5B illustrates an example plot of a V2 voltage waveform and a substrate voltage waveform for the example schematic circuit diagram shown in FIG. 5A, in accordance with at least one embodiment of the present disclosure. [Figure 5C] FIG. 2 illustrates an example control circuit in accordance with at least one embodiment of the present disclosure. [Figure 5D] FIG. 2 illustrates an example control circuit in accordance with at least one embodiment of the present disclosure. [Figure 5E] FIG. 2 illustrates an example sawtooth voltage output in accordance with at least one embodiment of the present disclosure. [Figure 6A] FIG. 2 is an example circuit schematic diagram illustrating an IEDF width control circuit that drives electrodes of a substrate support assembly, in accordance with at least one embodiment of the present disclosure. [Figure 6B] FIG. 2 illustrates an example control circuit in accordance with at least one embodiment of the present disclosure. [Figure 6C] FIG. 2 illustrates an example control circuit in accordance with at least one embodiment of the present disclosure. [Figure 7]FIG. 2 is an example circuit schematic diagram illustrating an IEDF width control circuit that drives electrodes of a substrate support assembly, in accordance with at least one embodiment of the present disclosure. [Figure 8] FIG. 2 is an example circuit schematic diagram illustrating an IEDF width control circuit that drives electrodes of a substrate support assembly, in accordance with at least one embodiment of the present disclosure. [Figure 9] FIG. 2 is an example circuit schematic diagram illustrating an IEDF width control circuit that drives electrodes of a substrate support assembly, in accordance with at least one embodiment of the present disclosure. [Figure 10] FIG. 2 is an example circuit schematic diagram illustrating an IEDF width control circuit that drives electrodes of a substrate support assembly, in accordance with at least one embodiment of the present disclosure. [Figure 11] 1 is a flowchart illustrating a method for controlling IEDF width in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] To facilitate understanding, the same reference numbers have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially utilized on other embodiments without additional recitation.

[0012] The embodiments of the present disclosure generally relate to apparatus and methods for plasma processing of substrates, and more particularly, to apparatus and methods for controlling ion energy distribution during plasma processing. The methods and apparatus, e.g., circuits, described herein allow control over the shape (e.g., narrow or adjustable width) of the voltage waveform of a pulsed DC power supply. The embodiments described herein further allow control over the ion energy distribution function (IEDF), including, for example, monoenergetic ion acceleration.

[0013] The IEDF is a parameter for etching high aspect ratio features. In general, a pulsed DC bias can provide a narrower IEDF compared to a sinusoidal RF bias due to the following mechanism: Because ions are accelerated by an electric field that varies less in time within the pulsed DC period, the energy acquired by the ions in the sheath also varies less in time than with a varying sinusoidal RF bias. As a result, ions accelerated by a pulsed DC bias have a narrower IEDF than a sinusoidal RF bias. However, the ion current from the bulk plasma to the substrate distorts the voltage waveform at the substrate, widening the ion energy distribution. The methods and apparatus described herein can, for example, compensate for this ion current and actively control the width of the ion energy distribution.

[0014] Conventional methods and apparatus use an iterative control loop to control the width of the ion energy distribution. Before the control algorithm converges, the estimation of the plasma parameters (e.g., ion current, sheath thickness, and IEDF width) is inaccurate. Furthermore, controlling the width of the IEDF by using iterations is slow and the control algorithm may not converge.

[0015] In contrast, the methods and apparatus described herein utilize a single, non-iterative loop to determine the ion current and compensation current to achieve a given IEDF width. Thus, the methods and apparatus described herein reach a desired state of the IEDF, e.g., a narrow IEDF, faster than the state of the art, e.g., by not using iterations in determining the compensation current solution.

[0016] Briefly, in some embodiments, the substrate support includes a body, the body including a substrate support portion and / or an edge ring portion. A substrate electrode is embedded in the substrate support portion for applying a substrate voltage to the substrate. A substrate voltage control circuit is coupled to the substrate electrode. The edge ring portion includes an embedded edge ring electrode that applies an edge ring voltage to the edge ring. The edge ring voltage control circuit is coupled to the edge ring electrode. At least one shaped DC pulse source is coupled to the substrate voltage control circuit and / or the edge ring voltage control circuit. The substrate voltage circuit and / or the edge ring voltage control circuit are adjustable. For example, ion energy distribution is adjusted and controlled by adjusting a voltage amplitude via adjustment of the substrate voltage control circuit and / or the edge ring voltage control circuit.

[0017] In some embodiments, the IEDF width control circuitry is coupled to the substrate support. The IEDF width control circuitry can be integrated within the main pulsed DC power supply, or can be a separate module, or can be a module integrated with the bias compensation module.

[0018] Processing system configuration example FIG. 1 is a schematic cross-sectional view of a processing chamber 100 according to at least one embodiment of the present disclosure. The processing chamber 100 is configured to practice the schemes described herein. In this embodiment, the processing chamber is a plasma processing chamber, such as a reactive ion etching (RIE) plasma chamber. In some other embodiments, the processing chamber is a plasma-enhanced deposition chamber, such as a plasma-enhanced chemical vapor deposition (PECVD) chamber, a plasma-enhanced physical vapor deposition (PEPVD) chamber, or a plasma-enhanced atomic layer deposition (PEALD) chamber. In some other embodiments, the processing chamber is a plasma processing chamber, or a plasma-based ion implantation chamber, such as a plasma doping (PLAD) chamber.

[0019] The processing chamber 100 includes a chamber body 101 and a lid 102 disposed thereon, which together define an interior volume 124. The chamber body 101 is typically coupled to an electrical ground 103. A substrate support assembly 104 is disposed within the interior volume and supports a substrate 105 thereon during processing. An edge ring 106 is positioned on the substrate support assembly 104 and surrounds the periphery of the substrate 105. The processing chamber 100 also includes an inductively coupled plasma apparatus 107 for generating a plasma of reactive species within the processing chamber 100, and a controller 108 adapted to control the systems and subsystems of the processing chamber 100. In some embodiments, the inductively coupled plasma apparatus 107 can be replaced by a grounded showerhead, and RF power is delivered from an electrode below the substrate to generate a capacitively coupled plasma.

[0020] The substrate support assembly 104 is disposed in the interior volume 124. The substrate support assembly 104 generally includes a substrate support 152. The substrate support 152 includes an electrostatic chuck 150 including a substrate support portion 154 configured to underlie and support a substrate 105 to be processed and an edge ring portion 156 configured to support an edge ring 106. The substrate support assembly 104 may further include a heater assembly 169. The substrate support assembly 104 may also include a cooling base 131. Alternatively, the cooling base 131 may be separate from the substrate support assembly 104. The substrate support assembly 104 may be removably coupled to a support pedestal 125. The support pedestal 125 is mounted to the chamber body 101. The support pedestal 125 may optionally include a fixture plate 180. The substrate support assembly 104 may be periodically removed from the support pedestal 125 to allow for servicing of one or more components of the substrate support assembly 104. Lift pins 146 are disposed through the substrate support assembly 104 to facilitate substrate transfer as is known in the art.

[0021] The equipment plate 180 is configured to receive a number of fluid connections from the electrostatic chuck 150 and the cooling base 131. The equipment plate 180 is also configured to receive a number of electrical connections from the electrostatic chuck 150 and the heater assembly 169. The electrical connections can run externally or internally to the substrate support assembly 104, with the equipment plate 180 providing an interface for connecting to the respective terminations.

[0022] The substrate electrode 109 is embedded within the substrate support portion 154 of the electrostatic chuck 150 for applying a substrate voltage to the substrate 105 disposed on the top surface 160 of the substrate support assembly 104. The edge ring electrode 111 is embedded within the edge ring portion 156 for applying an edge ring voltage to the edge ring 106. The edge ring IEDF width control circuit 155 is coupled to the edge ring electrode 111. The substrate IEDF width control circuit 158 ​​is coupled to the substrate electrode 109. In one embodiment, the first shaped DC pulse voltage source 159 is coupled to one or both of the edge ring IEDF width control circuit 155 and the substrate IEDF width control circuit 158. In another embodiment, the first shaped DC voltage source 159 is coupled to the edge ring IEDF width control circuit 155 and the second shaped DC voltage source 161 is coupled to the substrate IEDF width control circuit 158 ​​as shown in FIG. 1. The edge ring IEDF width control circuit 155 and the substrate IEDF width control circuit 158 ​​are independently adjustable. The substrate electrode 109 is further coupled to a chuck power supply 115 to facilitate chucking of the substrate 105 to the upper surface 160 by the electrostatic chuck 150 during processing.

[0023] The inductively coupled plasma device 107 is disposed above the lid 102 and is configured to inductively couple RF power to gases within the process chamber 100 to generate a plasma 116. The inductively coupled plasma device 107 includes a first coil 118 and a second coil 120 disposed above the lid 102. The relative position, diameter ratio, and / or number of turns of each coil 118, 120 can be adjusted as desired to control the profile or density of the plasma 116 formed. The first and second coils 118, 120 are each coupled to an RF power supply 121 through a matching network 122 via an RF feed structure 123. The RF power supply 121 can illustratively generate up to (but is not limited to) about 4000 W at a tunable frequency ranging from 50 kHz to 13.56 MHz, although other frequencies and powers can be utilized as desired for a particular application.

[0024] In some examples, a power divider 126, such as a voltage divider capacitor, may be provided between the RF feed structure 123 and the RF power supply 121 to control the relative amount of RF power provided to the first and second coils 118, 120, respectively. In other embodiments, a capacitively coupled plasma device (not shown) may be used above the lid 102. A heater element 128 may be disposed on the lid 102 to facilitate heating the interior of the process chamber 100. The heater element 128 may be disposed between the lid 102 and the first and second coils 118, 120. In some examples, the heater element 128 includes a resistive heating element and is coupled to a power supply 130, such as an AC power supply, configured to provide sufficient energy to control the temperature of the heater element 128 within a desired range.

[0025] In operation, a substrate 105, such as a semiconductor substrate or other substrate suitable for plasma processing, is placed on the substrate support assembly 104. Substrate lift pins 146 are movably disposed on the substrate support assembly 104 to assist in transferring the substrate 105 onto the substrate support assembly 104. After positioning the substrate 105, a process gas is supplied from the gas panel 132 through the inlet port 134 into the interior volume 124 of the chamber body 101. The process gas is ignited into a plasma 116 in the process chamber 100 by applying power from an RF power supply 121 to the first and second coils 118, 120. The pressure in the interior volume 124 of the process chamber 100 can be controlled using a valve 136 and a vacuum pump 138.

[0026] The processing chamber 100 includes a controller 108 that controls the operation of the processing chamber 100 during processing. The controller 108 includes a central processing unit (CPU) 140, a memory 142, and support circuits 144 for the CPU 140 to facilitate control of the components of the processing chamber 100. The controller 108 can be any form of general-purpose computer processor that can be used in industrial facilities to control various chambers and sub-processors. The memory 142 stores software (source or object code) that can be executed or run to control the operation of the processing chamber 100 in the manner described herein. The controller 108 is configured to control a first shaped DC voltage source 159, a second shaped DC voltage source 161, an edge ring IEDF width control circuit 155, and a substrate IEDF width control circuit 158.

[0027] 2 is a schematic diagram of a processing chamber 200, in accordance with at least one embodiment of the present disclosure, configured to practice the schemes described herein. Like processing chamber 100, processing chamber 200 is a plasma processing chamber, such as those described above.

[0028] The processing chamber 200 includes a substrate 105 disposed on a substrate support assembly 104 as described in FIG. 1. An edge ring 106 is positioned on the substrate support assembly 104 and surrounds the periphery of the substrate 105. Although not shown, a capacitively coupled plasma device is disposed above the substrate (typically above the chamber lid). The capacitively coupled plasma device may include an ion suppressor and a showerhead, and RF power is delivered from an electrode below the substrate to generate the capacitively coupled plasma. A controller 108 is adapted to control the systems and subsystems of the processing chamber. The controller 108 includes a central processing unit (CPU) 140, a memory 142, and support circuits 144 for the CPU 140 to facilitate control of the components of the processing chamber 100. The controller 108 may be any form of general purpose computer processor that may be used in an industrial facility to control various chambers and sub-processors. The memory 142 stores software (source or object code) that can be executed or invoked to control operation of the process chamber 100 in the manner described herein. The controller 108 is configured to control the first shaped DC voltage source 159, the second shaped DC voltage source 161, the edge ring IEDF width control circuit 155, and / or the substrate IEDF width control circuit 158. Figures 4A-4D, described below, show different configurations for connecting the IEDF width control module to the pulser.

[0029] The substrate support assembly 104, fixture plate 180, substrate electrode 109, and edge ring electrode 111 may be the same as discussed in FIG. 1. Edge ring IEDF width control circuit 155 is coupled to edge ring electrode 111. Substrate IEDF width control circuit 158 ​​is coupled to substrate electrode 109. In one embodiment, a first shaped DC pulse voltage source 159 is coupled to one or both of edge ring IEDF width control circuit 155 and substrate IEDF width control circuit 158. In another embodiment, the first shaped DC voltage source 159 is coupled to edge ring IEDF width control circuit 155 and a second shaped DC voltage source 161 is coupled to substrate IEDF width control circuit 158. Edge ring IEDF width control circuit 155 and substrate IEDF width control circuit 158 ​​are independently adjustable. Substrate electrode 109 is further coupled to a chuck power source 115 to facilitate chucking of substrate 105 to upper surface 160 by electrostatic chuck 150 during processing.

[0030] Operation of the process chamber 200 and processing of the substrate 105 can be performed in a similar manner as the process chamber 100. In some embodiments, the processing system configuration includes an ion suppressor positioned inside the process chamber that controls the type and amount of plasma excited species that reach the substrate. In some embodiments, the ion suppressor unit is a perforated plate that may also act as an electrode for the plasma generation unit. In these and other embodiments, the ion suppressor can be a showerhead that distributes gas and excited species to a reaction region in contact with the substrate. In some embodiments, ion suppression is achieved by a perforated plate ion suppressor and a showerhead through which the plasma excited species pass to reach the reaction region.

[0031] When a voltage is applied to the substrate (or wafer) by the shaped DC voltage source 159, a waveform develops. Figure 3A shows different bias voltage waveforms. The waveform includes two phases: an ion current phase and a sheath collapse phase. At the beginning of the ion current phase, a high voltage sheath is created above the substrate by the drop in the wafer voltage, which accelerates the positive ions toward the substrate. The positive ions tend to deposit a positive charge on the substrate surface and gradually increase the substrate voltage in a positive direction. If a square wave is provided by the shaped DC voltage source 159, the ion current toward the substrate creates a positive slope in the substrate voltage, as shown by trace 305. The voltage difference between the beginning and end of the ion current phase determines the IEDF width. The larger the voltage difference, the wider the IEDF width (Figure 3B). To achieve monoenergetic ions and a narrower IEDF width, an operation is performed to flatten the substrate voltage waveform (e.g., trace 310) of the ion current phase. In some embodiments, a voltage can be applied to achieve a particular IEDF width, as shown by the substrate waveform of trace 315.

[0032] At the end of the ion current phase, the substrate voltage is raised to the bulk plasma voltage and the sheath collapses, transferring electrons from the plasma to the substrate surface, neutralizing the positive charge on the substrate surface, and thus resetting the substrate surface for the next cycle.

[0033] In some embodiments, the first and second shaped DC voltage sources 159 and 161 are positive pulsers. The positive pulsers generate pulses of positive voltage, which correspond to a sheath collapse phase. When each positive pulse is turned off, an ion current phase begins. In some embodiments, the first and second shaped DC voltage sources 159 and 161 are negative pulsers. The negative pulsers generate pulses of negative voltage, which correspond to an ion current phase. When each negative pulse is turned off, a sheath collapse phase begins.

[0034] Circuit example Figure 4A is a schematic diagram of an example circuit 465. As described below, in some embodiments, the example circuit shown in Figure 4A corresponds to the circuit diagrams of Figures 5A and 6A. Figures 5A and 6A differ, for example, by the circuitry of the second power module.

[0035] The example circuit 465 includes a pulsed DC power supply 466 coupled through a series inductor 468 and resistor 469 to a second power module 470. The second power module 470 modulates the width of the ion energy distribution function (IEDF). An optional blocking capacitor 471 may be present between the plasma chamber load 472 and the remainder of the circuit 465. A controller, not shown, which may be implemented by hardware, software, firmware, or a combination thereof, is utilized to control the various components shown in FIG. 4A.

[0036] The shaped DC power supply 466 generates a voltage waveform with two voltage levels: a low voltage level and a high voltage level. The low voltage level corresponds to the ion current phase. The high voltage level corresponds to the sheath collapse phase. In the ion current phase, the second power module 470 modulates the slope of the voltage versus time, shown as traces 305, 310, and 315 in FIG. 3A. As shown in FIG. 3B, different slopes result in different IEDF widths. The flattest slope (trace 305 in FIG. 3A) corresponds to the narrowest IEDF width in FIG. 3B.

[0037] FIG. 4B is a schematic diagram of an example circuit 475. As shown, FIG. 4B differs from FIG. 4A by replacing the series inductor 468 and resistor 469 with a switch 479. The switch 479 is connected in series with the pulsed DC power supply 476 and the second power module 478. During the ion current phase, the switch 479 is closed. During the sheath collapse phase, the switch can be either open or closed. A controller, not shown, which may be realized by hardware, software, firmware, or a combination thereof, is utilized to control the various components shown in FIG. 4B.

[0038] FIG. 4C is a schematic diagram of an example circuit 485. As described below, in some embodiments, the example circuit 485 shown in FIG. 4C corresponds to the circuit diagrams of FIG. 7A and FIG. 8. The example circuit 485 includes a shaped DC voltage source 486 coupled to ground. An optional blocking capacitor 487 may be present between the shaped DC voltage source 486 and a second power module 488. The second power module 488 modulates the width of the IEDF. The second power module 488 is further coupled to a plasma chamber load 489. A controller (not shown), which may be realized by hardware, software, firmware, or a combination thereof, is utilized to control the various components shown in FIG. 4C.

[0039] The shaped DC voltage source 486 generates a voltage waveform with two voltage levels: a low voltage level and a high voltage level. The low voltage level corresponds to the ion current phase. The high voltage level corresponds to the sheath collapse phase. In the ion current phase, the second power module 488 creates a voltage ramp versus time. The resulting voltage waveform on the substrate is the sum of the output voltages of the shaped DC voltage source 486 and the second power module 488, which can be modulated, thereby modulating the IEDF width.

[0040] FIG. 4D is a schematic diagram of an example circuit 490 according to at least one embodiment of the present disclosure. As described below, in some embodiments, the example circuit 490 corresponds to the circuit diagrams of FIGS. 9 and 10. The example circuit 490 includes a shaped DC voltage source 491 coupled to ground, a second power module 492, and a substrate chucking and bias compensation module 493. A switch 495 is connected in series with the substrate chucking and bias compensation module 493. The second power module 492 and the substrate chucking and bias compensation module 493 are connected in parallel, with one end coupled to the shaped DC voltage source 491 and the other end coupled to a plasma chamber load 494. The second power module 492 modulates the width of the IEDF. The second power module 492 and the substrate chucking and bias compensation module 493 are further coupled to the plasma chamber load 494. A controller (not shown), which may be implemented in hardware, software, firmware, or a combination thereof, is utilized to control the various components shown in FIG. 4D.

[0041] The shaping DC voltage source 491 generates a voltage waveform with two voltage levels, a low voltage level and a high voltage level. The low voltage level corresponds to the ion current phase. The high voltage level corresponds to the sheath collapse phase. In the ion current phase, the second power module 492 creates a voltage ramp with respect to time. The resulting voltage waveform on the substrate is the sum of the output voltages of the shaping DC voltage source 491 and the second power module 492, which can be modulated, thereby modulating the IEDF width. The switch 495 is open in the ion current phase, so the chucking and bias compensation module 493 does not modulate the voltage of the plasma chamber load. In the sheath collapse phase, the switch 495 is closed and the chucking and bias compensation module 493 resets the substrate chucking voltage to a set point.

[0042] FIG. 5A is a schematic circuit diagram illustrating one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 500 that drives the substrate electrode 109 and / or edge ring electrode 111 of the substrate support assembly 104. The circuit 500 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in FIG. 3A). The main pulser 502 can be the first or second shaped DC voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled to a current return path 503. The current return path 503 includes an inductor 504 coupled in series with a resistor 506 to an IEDF width control module 508 (e.g., the second power module in FIGS. 4A and 4B). The IEDF width control module 508 modulates the ion energy distribution function (IEDF) width.

[0043] The IEDF width control module 508 can be modeled as a circuit comprising a transistor-transistor logic (TTL) signal 510 coupled in parallel with a switch 512, an optional diode 514, an optional capacitance 516 coupled to ground 517, and a third shaped DC pulsed voltage source 518. The diode 514 is a flyback diode that protects the switch 512 and the third shaped DC pulsed voltage source 518. In some embodiments, a capacitance 520 exists between the current return path 503 and the chamber volume 536. The capacitance 536 can be, for example, an impedance between the substrate electrode 109 and the substrate or between the edge ring electrode 111 and the edge ring. In some embodiments, the capacitance is also coupled to the substrate chucking and bias compensation module 522.

[0044] The substrate chucking and bias compensation module 522 is a circuit including a diode 524 coupled in series to a resistor 526, a DC voltage source 528, and a resistor 530 coupled in series to a capacitance 532 and a ground 534. The capacitance 536 is further coupled to a stray capacitance 538, and to a plasma sheath 540. The substrate chucking and bias compensation module 522 is further coupled to the stray capacitance 538. The plasma sheath 540 may be modeled (plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel to a current source 544, and a diode 546 coupled to a ground 548. In some embodiments, the series inductor 504 and resistor 506 in the current return path can be replaced by a switch 179 (FIG. 4B). The switch 179 is closed during the ion current phase.

[0045] In use, for the configuration shown in FIG. 5A, the third shaped DC pulse voltage source 518 acts as an active knob to control the slope of the voltage waveform in the ion current phase. The switch 512 is controlled by a TTL signal 510 synchronized with the main pulser 502, as shown in plot 550 of FIG. 5B. The switch 512 can be closed before the voltage of the main pulser 502 rises to enter the sheath collapse phase. The switch 512 can be kept closed during the sheath collapse phase to connect the current return path 503 to ground. After the voltage of the main pulser 502 drops to enter the ion current phase, the switch 512 can be opened during the ion current phase so that the third shaped DC pulse voltage source 518 functions to modulate the IEDF. The optional capacitance 516 can be used to adjust the sensitivity of the substrate voltage waveform to the third shaped DC pulse voltage source 518. Capacitance 542 is the plasma sheath capacitance, which is different for different processing conditions, and current source 544 is the ion current toward the substrate, which is also variable. Capacitance 536 and stray capacitance 538 are capacitances associated with the chamber and are constant. Capacitance 520 is the blocking capacitor and is also constant.

[0046] As shown in Figures 5C and 5D, during the ion current phase, when the IEDF width control module 508 (Figure 5A) is actively controlling the substrate or edge ring waveform, the active components of the circuit model include the ion current 544 (I0), the sheath capacitance 542 (C1), the chamber capacitance 536 (C2), the stray capacitance 538 (C3), the blocking capacitance 520 (C4), and the optional capacitance 516 (C5) in parallel with the third shaped DC pulse voltage source 518 (V1). Since the inductor 504 and resistor 506 in the current return path have little effect on the IEDF width modulation, the inductor 504 and resistor 506 are treated as shorts in the control circuit 560 in Figure 5C and the control circuit 570 in Figure 5D.

[0047] The intrinsic factor that widens the IEDF is the ion current I0, which gradually increases the voltage of the substrate by depositing a positive charge on the substrate, causing the ion energy bombarding the substrate to drop (e.g., trace 305 in FIG. 3A). The amount of IEDF widening depends, for example, on the ion current I0, the sheath capacitance C1, and / or other capacitances associated with the chambers C2, C3, and C4, and the power supply modules V1 and C5 of the control circuit 560, 570. Values ​​of all components of this control circuit (FIG. 5C) are determined to compensate for the ion current effect of IEDF widening and / or to actively control the IEDF width. The capacitances associated with the chamber and the power supply modules C2-C5 can be determined by product specifications or estimates using dimensions of the chamber parts, or by previous measurements such as direct impedance measurements using a multimeter or extracting capacitance values ​​from S-parameter or Z-parameter measurements. The ion current I0 and sheath capacitance C1 vary with varying plasma processing conditions and are determined by real-time measurements during the plasma process. The shaped DC pulse voltage source V1 has a sawtooth voltage output (FIG. 5E). The slope dV1 / dt of the voltage output can be varied to determine the ion current I0 and the sheath capacitance C1 and / or modulate the IEDF width. In the configuration of FIG. 5A, the output voltage of the shaped DC pulse voltage source V1 during the sheath collapse phase is zero, as shown by trace 584. Traces 582 and 586 show other possible waveforms for the shaped DC pulse voltage source V1, as described below.

[0048] The method of IEDF modulation includes two parts: (1) determining the ion current I0 and sheath capacitance C1, and (2) determining the slope dV1 / dt of the shaped DC pulse voltage source to achieve the target IEDF width. Since the sawtooth voltage source V1 and the shaped DC voltage source 159 or 161 supply power to the substrate 105 or edge ring 106, the IEDF width at the substrate or edge ring is the change in the substrate or edge ring voltage from the beginning to the end of the ion current phase (FIGS. 3A and 3B). In the control circuit 560 of FIG. 5C and the control circuit 570 of FIG. 5D, the IEDF width corresponds to the change in voltage across the sheath capacitance C1 from the beginning to the end of the ion current phase, which is determined by the charge or discharge current I1 through the sheath capacitance C1. ΔV=I1×T / C1 (1) where ΔV is the IEDF width and T is the duration of the ion current step. To obtain a target IEDF width (ΔV), the sheath volume C1 and the desired current I1 through the sheath volume should be determined.

[0049] To determine the sheath capacitance C1 and the ion current I0, the current vs. voltage relationship in the control circuit is analyzed. As shown, the currents passing through the capacitors C1-C4 are labeled I1-I4, and the arrows in the circuit schematic point in the positive direction. Based on Kirchhoff's current law, the ion current I0 is equal to the sum of the currents passing through the capacitors C1 and C2. I0=I1+I2 (2)

[0050] The current through capacitor C2 is equal to the sum of the currents through capacitors C3 and C4. I2=I3+I4 (3)

[0051] Based on Kirchhoff's voltage law, the voltage sum of the closed loop C1, C2, and C3 is zero. The time derivative of the voltage sum of C1, C2, and C3 is also zero. Let the voltage at the intersection of capacitors C2 and C3 be V3. The time derivative of the voltage across capacitor C3 is dV3 / dt=I3 / C3. A similar relationship exists for capacitors C1 and C2, and Kirchhoff's voltage law gives us equation (4). I1 / C1=I2 / C2+I3 / C3 (4)

[0052] By applying Kirchhoff's voltage law to the closed loop between capacitors C3 and C4 and voltage source V1, equation (5) is obtained. I3 / C3=I4 / C4+dV1 / dt (5)

[0053] In equations (2)-(5), C2, C3, and C4 are pre-determined by product specifications or estimates based on the dimensions of the chamber parts, or by previous measurements, such as direct measurement of impedance using a multimeter or extracting capacitance values ​​from S-parameter or Z-parameter measurements. Current I4 can be measured directly by a sensor, such as a current probe and / or an integrated voltage-current (VI) sensor. Voltage V3 can be measured directly by a sensor, such as a voltage probe and / or an integrated VI sensor. Current I3 can be calculated as I3=C3×dV3 / dt. The voltage slope dV1 / dt is user controlled and known, such as zero or 1 volt per nanosecond (V / nsec). By setting the shaped DC pulse voltage source V1 to two different slopes dV1 / dt and dV1' / dt, the currents I4, I4', and the time derivatives of the voltages dV3 / dt, dV3' / dt can be determined. The set of equations (2) to (5) for the two slopes dV1 / dt and dV1' / dt forms eight equations, and the solution of these equations gives the sheath capacitance TIFF2025028884000002.tif28170 and the ion current of the following formula. TIFF2025028884000003.tif18170

[0054] To obtain a target IEDF width (ΔV), the total current through the sheath capacitor C1 is: I1=C1×ΔV / T (8)

[0055] By substituting equations (6) to (8) into equations (2) to (5), the voltage slope of the sawtooth voltage source V1 that achieves the IDEF width ΔV is given. TIFF2025028884000004.tif16170

[0056] For the narrowest IEDF (ΔV=0), the voltage slope of the sawtooth voltage source V1 is: TIFF2025028884000005.tif18170

[0057] FIG. 6A is a schematic circuit diagram illustrating one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 600 that drives the substrate electrode 109 and / or edge ring electrode 111 of the substrate support assembly 104. The circuit 600 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in FIG. 3A). The main pulser 502 can be the first or second shaped DC voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled to a current return path 503. The current return path 503 includes an inductor 504 coupled to an IEDF width control module 602 (e.g., the second power module in FIGS. 4A and 4B) in series with a resistor 506. The IEDF width control module 602 modulates the IEDF width. The IEDF width control module 602 may be modeled as a circuit that includes a TTL signal 510 coupled in parallel with a switch 512, a diode 514, an optional capacitance 516 coupled to ground 517, and a DC voltage source 604 coupled in series with a resistor 606, unlike the configuration of FIG. 5A. The diode 514 is a flyback diode that protects the switch 512 and the DC voltage source 604. In some embodiments, a blocking capacitance 520 exists between the current return path 503 and the chamber volume 536. The capacitance 536 can be, for example, an impedance between the substrate electrode 109 and the substrate or between the edge ring electrode 111 and the edge ring. In some embodiments, a substrate chucking and bias compensation module 522 is also coupled to the blocking capacitance 520 and the chamber volume 536. The substrate chucking and bias compensation module 522 is further coupled to a stray capacitance 538. The substrate chucking and bias compensation module 522 is a circuit including a diode 524 coupled in series with a resistor 526 , a DC voltage source 528 , and a resistor 530 coupled in series with a capacitor 532 and ground 534 .

[0058] The plasma sheath 540 may be modeled (the plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel with a current source 544 and a diode 546 coupled to ground 548 .

[0059] In use, in the configuration shown in FIG. 6A, in contrast to the configuration shown in FIG. 5A, where the third shaped DC pulse voltage source 518 acts as an active knob to control the slope of the voltage waveform in the ion current phase, the DC voltage source 604 acts together with the resistor 606 as an active knob to control the slope of the substrate or edge ring voltage waveform in the ion current phase. The switch 512 can be controlled by a TTL signal 510 synchronized with the main pulser 502 as shown in FIG. 5B. The switch 512 can be closed before the voltage of the main pulser 502 rises to enter the sheath collapse phase. The switch 512 can be kept closed during the sheath collapse phase to connect the current return path 503 to ground. After the voltage of the main pulser 502 falls to enter the ion current phase, the switch 512 can be opened in the ion current phase so that the DC voltage source 604 functions to modulate the IEDF. The optional capacitance 516 can be used to adjust the sensitivity of the substrate voltage waveform to the DC voltage source 604. Capacitance 542 is the plasma sheath capacitance and is variable. Current source 544 is the ion current to the substrate and is also varied. Capacitance 536 can be, for example, the capacitance between the substrate electrode 109 and the substrate or between the edge ring electrode 111 and the edge ring. Capacitance 538 can be the capacitance between the substrate electrode 109 and ground or between the edge ring electrode 111 and ground. Capacitance 520 is the blocking capacitor and is also fixed.

[0060] As shown in Figures 6B and 6C, during the ion current phase, when the IEDF width control module 602 (Figure 6A) is actively controlling the substrate or edge ring waveform, the active components of the circuit model include the ion current 544 (I0), the sheath capacitance 542 (C1), the chamber capacitance 536 (C2), the stray capacitance 538 (C3), the blocking capacitance 520 (C4), and any capacitance 516 (C5) in parallel with the DC voltage source 604 (V0) and the resistor 606 (R). Since the inductor 504 and resistor 506 in the current return path have little effect on the IEDF width modulation, the inductor 504 and resistor 506 are treated as shorts in the control circuit 650 of Figure 6B and the control circuit 660 of Figure 6C. The control circuit of Figure 6A is shown in Figure 6B, and the control circuit of Figure 7A, described below, is shown in Figure 6C.

[0061] The intrinsic factor that widens the IEDF is the ion current I0, which deposits a positive charge on the substrate, gradually increasing the voltage of the substrate and causing the ion energy bombarding the substrate to drop (trace 305 in FIG. 3A). The amount of IEDF widening depends, for example, on the ion current I0, the sheath capacitance C1, and other capacitances associated with the chamber (C2, C3, and C4), and the power supply modules (V0, R, and C5) of the control circuit 650 and control circuit 660 of FIG. 6B and FIG. 6C, respectively. Values ​​of all components of the control circuit 650 and control circuit 660 are determined to compensate for the ion current effect of the IEDF widening and to actively control the IEDF width. The capacitances associated with the chamber and power supply modules C2-C5 can be determined by product specifications or estimates using the dimensions of the chamber parts, or by previous measurements such as direct measurement of impedance using a multimeter or extracting capacitance values ​​from S-parameter or Z-parameter measurements. The resistor R is also pre-determined by product specifications or by direct measurement utilizing a multimeter. The ion current I0 and sheath capacitance C1 vary with varying plasma processing conditions and are determined by real-time measurements during the plasma process. The DC voltage source V0 is an active control knob and can be varied to determine the ion current I0, determine the sheath capacitance C1, and / or modulate the IEDF width.

[0062] The method of IEDF modulation includes two parts: (1) determining the ion current I0 and sheath capacitance C1, and (2) determining the DC voltage V0 to achieve the target IEDF width. The IEDF width is the spread of the substrate or edge ring voltage from the beginning to the end of the ion current phase (FIGS. 3A and 3B). In the control circuit 650 of FIG. 6B and the control circuit 660 of FIG. 6C, the IEDF width corresponds to the change in voltage across the sheath capacitance C1 from the beginning to the end of the ion current phase, which is determined by the charge or discharge current I1 through the sheath capacitance C1. In TIFF2025028884000006.tif17170, ΔV is the IEDF width and T is the duration of the ion current stage. To obtain the target IEDF width (ΔV), the sheath capacitance C1 and the desired current I1 through the sheath capacitance should be determined.

[0063] To determine the sheath capacitance C1 and the ion current I0, the relationship between current and voltage in the control circuit is analyzed. Here, for example, the currents passing through capacitors C1 to C5 are called I1 to I5, and the arrows in the circuit schematic diagram point to the positive direction. The voltage at the intersection of capacitors C2 and C3 is V3. There is a threshold voltage with respect to the DC voltage source V0 called Vth. When it is below that, the diode D3 bypasses the series connection of the DC voltage source V0 and the resistor R, so the output voltage of the IEDF width control module is zero. Vth depends on the plasma conditions and can be determined experimentally, for example, by gradually increasing the DC voltage V0 until the point where the current I4 or the voltage V3 is affected by the DC voltage output V0.

[0064] When V0 < Vth, based on Kirchhoff's current law, the ion current I0 is equal to the sum of the currents through capacitors C1 and C2. I0 = I1 + I2 (12)

[0065] The current through capacitor C2 is equal to the sum of the currents through capacitors C3 and C4. I2 = I3 + I4 (13)

[0066] Based on Kirchhoff's voltage law, the sum of the voltages of the closed loop C1, C2, and C3 is zero. The time derivative of the sum of the voltages of C1, C2, and C3 is also zero. The time derivative of the voltage across capacitor C3 is dV3 / dt = I3 / C3. The same relationship applies to capacitors C1 and C2. By using Kirchhoff's voltage law for capacitors C1 and C2, Equation (14) is obtained. I1 / C1 = I2 / C2 + I3 / C3 (14)

[0067] Applying Kirchhoff's voltage law to the closed loop of capacitors C3 and C4 and the diode bypass IEDF width control module gives equation (15). I3 / C3=I4 / C4 (15)

[0068] If V0>Vth, then equations (12)-(14) still apply. By applying Kirchhoff's voltage law to the closed loop of capacitors C3, C4, and C5, we obtain equation (16). I3 / C3=I4 / C4+I5 / C5 (16)

[0069] By applying Kirchhoff's voltage law to the closed loop of capacitor C5, DC voltage source V0, and resistor R, equation (17) is obtained. TIFF2025028884000007.tif17170 where (I4-I5) is the current through DC voltage source V0 and resistor R when diode D3 is inactive.

[0070] In some embodiments, there is no capacitor C5. In such cases, equation (17) does not exist and equation (16) becomes: I3 / C3=I4 / C4+R×dI4 / dt (18)

[0071] In equations (12)-(18), C2, C3, C4, and C5 are pre-determined by product specifications or estimates based on the dimensions of the chamber parts, or by previous measurements such as direct measurement of impedance using a multimeter or extracting capacitance values ​​from S-parameter or Z-parameter measurements. Current I4 can be measured directly by a sensor such as a current probe and / or an integrated VI sensor. Voltage V3 can be measured directly by a sensor such as a voltage probe and / or an integrated VI sensor. Current I3 can be calculated as I3=C3×dV3 / dt. DC voltage V0 is user controlled and known, such as setting the DC voltage output V0 to a value from zero to several kV. By setting DC voltage V0 to two different values ​​V0 and V0′, at least one of which is higher than a threshold voltage Vth, the currents I4, I4′, and the time derivatives of the voltages dV3 / dt, dV3′ / dt can be determined. Solving the set of equations (12)-(18) results in the sheath capacitance C1, TIFF2025028884000008.tif27170 and the ion current I0 of the following formula. I0=(C1 / C2+C1 / C3+1)×I3+(C1 / C2+1)×I4 (20)

[0072] By substituting the sheath capacitance C1 and ion current I0 into the set of equations (12)-(18), the currents I1-I5 can be calculated for any DC voltage V0.

[0073] By substituting the expression for I1 into equation (11) with the known capacitances C1-C5, resistance R, and DC voltage V0, the relationship between the IEDF width (ΔV) and the DC voltage V0 can be obtained. Therefore, the required DC voltage V0 is determined for the target IEDF width (ΔV).

[0074] In some embodiments, resistor R is sufficiently large (e.g., about 10 kΩ) so that the current through DC voltage source V is approximately constant in time during the ion current stage and is equal to V / R. In these embodiments, equation (17) becomes: I4=I5+V0 / R (21)

[0075] By solving equations (12), (13), (14), (16), and (21), the total current through the sheath capacitor C1 is obtained as equation (22). TIFF2025028884000009.tif18170 formula, k=C3C4+C4C5+C5C3 It is.

[0076] Using equation (8) for this approximate example of a constant current I1, the DC voltage V0 utilized to obtain the target IEDF width (ΔV) can be found using equation (23). TIFF2025028884000010.tif15170

[0077] For the narrowest IEDF (ΔV=0), the DC voltage V0 is given by: TIFF2025028884000011.tif15170

[0078] 7A is a schematic circuit diagram illustrating one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 700 that drives the substrate electrode 109 and / or edge ring electrode 111 of the substrate support assembly 104. The circuit 700 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop of FIG. 3A). The main pulser 502 can be the first or second shaped DC voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled directly or through a capacitance 701 to an IEDF width control module 702 (e.g., the second power module of FIG. 4C).

[0079] The IEDF width control module 702 may be modeled as a circuit including a TTL signal 704 coupled in parallel to a switch 706. The TTL signal 704 is coupled in series to a ground 716. The switch 706 is coupled in parallel to a diode 708, a DC voltage source 710, and an optional capacitance 714. The DC voltage source 710 is coupled in series to a resistor 712. The IEDF width control module 702 is coupled to a chamber volume 536. The capacitance 536 can be, for example, an impedance between the substrate electrode 109 and the substrate or between the edge ring electrode 111 and the edge ring. In some embodiments, the IEDF width control module 702 is also coupled to the substrate chucking and bias compensation module 522 described above. The substrate chucking and bias compensation module 522 is further coupled to a stray capacitance 538. Substrate chucking and bias compensation module 522 is a circuit including a diode 524 coupled in series with a resistor 526, a DC voltage source 528, and a resistor 530 coupled in series with a capacitor 532 and ground 534. Diode 708 is a flyback diode that protects switch 706 and DC voltage source 710.

[0080] The plasma sheath 540 may be modeled (the plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel with a current source 544 and a diode 546 coupled to ground 548 .

[0081] In use, for the configuration shown in FIG. 7A, the DC voltage source 710 acts in conjunction with resistor 712 as an active knob to control the slope of the voltage waveform in the ion current phase. The switch 706 can be controlled by a TTL signal 704 synchronized with the main pulser 502 as shown in the plot of FIG. 5B. The switch 706 can be closed before the voltage of the main pulser 502 rises to enter the sheath collapse phase. The switch 512 can remain closed during the sheath collapse phase. After the voltage of the main pulser 502 drops to enter the ion current phase, the switch 706 can be opened so that the DC voltage source 710 functions to modulate the IEDF in the ion current phase. An optional capacitance 714 can be used to adjust the sensitivity of the substrate voltage waveform to the DC voltage source 710. The control mechanism of FIG. 7A is similar to that of FIG. 6A. One difference is that the control circuit of FIG. 7A is shown in FIG. 6C above, and the control circuit of FIG. 6A is shown in FIG. 6B.

[0082] 8 is a schematic circuit diagram illustrating one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 800 that drives the substrate electrode 109 and / or edge ring electrode 111 of the substrate support assembly 104. The circuit 800 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in FIG. 3A). The main pulser 502 can be the first or second shaped DC voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled directly or through a capacitance 701 to an IEDF width control module 802 (e.g., the second power module in FIG. 4C).

[0083] The IEDF width control module 802 may be modeled as a circuit comprising a TTL signal 704 coupled in parallel to a switch 706. The TTL signal 704 is also coupled in series to ground 716. The switch 706 is coupled in parallel to a diode 708, a third shaped DC pulse voltage source 804, and an optional capacitance 714. The IEDF width control module 802 is coupled to a chamber volume 536. The capacitance 536 can be, for example, an impedance between the substrate electrode 109 and the substrate or between the edge ring electrode 111 and the edge ring. In some embodiments, the IEDF width control module 802 is also coupled to the substrate chucking and bias compensation module 522 described above. The substrate chucking and bias compensation module 522 is a circuit including a diode 524 coupled in series to a resistor 526, a DC voltage source 528, and a resistor 530 coupled in series to a capacitance 532 and ground 534. The diode 708 is a flyback diode that protects the switch and the third shaped DC pulse voltage source 804 .

[0084] The substrate chucking and bias compensation module 522 is further coupled to the chamber volume 536. The plasma sheath 540 may be modeled (plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel with a current source 544 and a diode 546 coupled to ground 548.

[0085] In use, in the configuration shown in FIG. 8, the third shaped DC pulse voltage source 804 acts as an active knob to control the slope of the voltage waveform in the ion current phase, in contrast to the configuration shown in FIG. 7A, in which the DC voltage source 710, together with the resistor 712, acts as an active knob to control the slope of the voltage waveform in the ion current phase. The switch 706 can be controlled by a TTL signal 704 synchronized with the main pulser 502, as shown in the plot of FIG. 5B. The switch 706 can be closed before the voltage of the main pulser 502 rises to enter the sheath collapse phase. The switch 706 remains closed during the sheath collapse phase. After the voltage of the main pulser 502 falls to enter the ion current phase, the switch 706 can be opened so that the third shaped DC pulse voltage source 804 functions to modulate the IEDF in the ion current phase. The optional capacitance 714 can be used to adjust the sensitivity of the substrate voltage waveform to the third shaped DC pulse voltage source 804. The control mechanism of Figure 8 is similar to that of Figure 5A, with one difference being that the control circuit of Figure 8 is shown in Figure 5D above, while the control circuit of Figure 5A is shown in Figure 5C.

[0086] 5A, 6A, 7, and 8, it is contemplated that the substrate chucking and bias compensation module may be connected to the circuit in any suitable manner without departing from the scope of the embodiments described herein. It is also contemplated that the substrate chucking and bias compensation module may include additional or different components without departing from the scope of the embodiments described herein.

[0087] 9 is a schematic circuit diagram illustrating one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 900 that drives the substrate electrode 109 and / or edge ring electrode 111 of the substrate support assembly 104. The circuit 900 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in FIG. 3A). The main pulser 502 can be the first or second shaped DC pulse voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled to an IEDF width control module 902 (e.g., the second power module in FIG. 4D).

[0088] The IEDF width control module 902 may be modeled as a circuit including a TTL signal 904 coupled in parallel with a switch 906. The TTL signal 904 is also coupled in series to ground 916. The switch 906 is coupled in parallel to a diode 908. The combination of the TTL signal 904, the switch 906, and the diode 908 controls whether a substrate chucking and bias compensation module 920 is connected to another portion of the circuit. The substrate chucking and bias compensation module 920 is a circuit including a capacitance 926 coupled in parallel to a resistor 922 and a DC voltage source 924. The substrate chucking and bias compensation module 920 is coupled in series with the assembly of the TTL signal 904, the switch 906, and the diode 908. The substrate chucking and bias compensation module 920 and the switch 906 are collectively coupled in parallel to a DC voltage source 910 in series with a resistor 912, and also connected in parallel to an optional capacitor 914. Diode 908 is a flyback diode that protects switch 906 and DC voltage sources 910 and 924 .

[0089] Capacitance 536 may be between stray capacitance 538 and plasma sheath 540, which can be, for example, an impedance between the substrate electrode 109 and the substrate, or between the edge ring electrode 111 and the edge ring. The IEDF width control module 902 and the substrate chucking and bias compensation module 920 are both coupled to either the substrate electrode 109 and / or the edge ring electrode 111. The IEDF width control module 902 is also coupled to stray capacitance 538. The plasma sheath 540 may be modeled (plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel with a current source 544, and a diode 546 coupled to ground 548.

[0090] In use, for the configuration shown in FIG. 9, the DC voltage source 910 acts with resistor 912 as an active knob to control the slope of the voltage waveform in the ion current phase. The switch 906 can be controlled by a TTL signal 904 synchronized with the main pulser 502 as shown in FIG. 5B. The switch 906 can be closed before the voltage of the main pulser 502 rises to enter the sheath collapse phase. The switch 512 can be kept closed during the sheath collapse phase, which connects the substrate chucking and bias compensation module 920 to another part of the circuit to reset the substrate chucking voltage to a set point. After the voltage of the main pulser 502 drops to enter the ion current phase, the switch 906 can be opened so that the DC voltage source 910 functions to modulate the IEDF during the ion current phase. An optional capacitor 914 can be used to adjust the sensitivity of the substrate voltage waveform to the DC voltage source 910. The control mechanism of FIG. 9 is similar to FIG. 6B described above. One difference is that capacitor C4 has been removed.

[0091] 10 is a schematic circuit diagram illustrating one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 1000 that drives the electrodes 109, 111 of the substrate support assembly 104. The circuit 1000 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in FIG. 3A). The main pulser 502 can be the first or second shaped DC pulse voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled to an IEDF width control module 1002 (e.g., the second power module in FIG. 4D).

[0092] The IEDF width control module 1002 may be modeled as a circuit including a TTL signal 904 coupled in parallel with a switch 906. The TTL signal 904 is also coupled in series to ground 916. The switch 906 is coupled in parallel to a diode 908. The combination of the TTL signal 904, the switch 906, and the diode 908 controls whether the substrate chucking and bias compensation module is connected to another part of the circuit. The substrate chucking and bias compensation module 920 is a circuit including a capacitance 926 coupled in parallel to a resistor 922 and a DC voltage source 924. The diode 908 is a flyback diode that protects the switch, the DC voltage source 910, and the DC voltage source 924. The substrate chucking and bias compensation module 920 is coupled in series with the assembly of the TTL signal 904, the switch 906, and the diode 908. The substrate chucking and bias compensation module 920 and the switch 906 are collectively coupled in parallel to the DC pulsed voltage source 1004 and in parallel to the optional capacitor 914 .

[0093] Capacitance 536 may be between stray capacitance 538 and plasma sheath 540, which can be, for example, an impedance between the substrate electrode 109 and the substrate, or between the edge ring electrode 111 and the edge ring. The IEDF width control module 1002 and the substrate chucking and bias compensation module 920 are both coupled to either the substrate electrode 109 and / or the edge ring electrode 111. The IEDF width control module 1002 is also coupled to stray capacitance 538. The plasma sheath 540 may be modeled (plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel with a current source 544, and a diode 546 coupled to ground 548.

[0094] In use, in the configuration shown in FIG. 10, the shaped DC pulse voltage source 1004 acts as an active knob to control the slope of the voltage waveform in the ion current phase, in contrast to the configuration shown in FIG. 9, in which the DC voltage source 910, together with the resistor 912, acts as an active knob to control the slope of the voltage waveform in the ion current phase. The switch 906 can be controlled by a TTL signal 904 synchronized with the main pulser 502, as shown in the plot of FIG. 5B. The switch 906 can be closed before the voltage of the main pulser 502 rises to enter the sheath collapse phase. The switch 512 can be kept closed during the sheath collapse phase, which connects the substrate chucking and bias compensation module to another part of the circuit and resets the substrate chucking voltage to a set point. After the voltage of the main pulser 502 drops to enter the ion current phase, the switch 906 can be opened so that the DC voltage source 910 functions to modulate the IEDF during the ion current phase. The optional capacitor 914 can be used to adjust the sensitivity of the substrate voltage waveform to the shaped DC pulse voltage source 1004 .

[0095] The control mechanism in Figure 10 is similar to Figure 5A. One difference is that capacitor C4 is removed. Another difference is that the output voltage of the shaped DC pulse voltage source 1004 during the sheath collapse phase is held at the output voltage of the substrate chucking and bias compensation module 920 instead of zero, as shown in trace 582 (positive chucking voltage) and trace 586 (negative chucking voltage) in Figure 5E.

[0096] Example method 11 is a flow chart of a method 1100 of controlling IEDF width using edge ring IEDF width control circuit 155 and / or substrate IEDF width control circuit 158 ​​in accordance with at least one embodiment of the present disclosure. Method 1100 can be implemented using one or more of the circuit configurations shown in Figures 5-10. Method 1100 also provides a method of operating processing chamber 100 or processing chamber 200.

[0097] The method 1100 begins with applying or otherwise introducing a voltage to a suitable processing chamber by activating, i.e., turning on, a primary pulser (e.g., primary pulser 502) coupled to a power module (e.g., IEDF width control module). Here, a voltage is introduced to a substrate electrode, e.g., substrate electrode 109, and / or an edge ring electrode, e.g., edge ring electrode 111. A bias voltage on the substrate electrode and / or edge ring electrode develops in an ion current phase, accelerating ions with an energy of, e.g., the sheath voltage multiplied by the charge of the ion. In a collisionless sheath model, most of the ions can reach this maximum energy when they impact the substrate electrode and / or edge ring electrode. However, the voltage on the substrate electrode and / or edge ring electrode increases over time, e.g., by the ion current depositing positive charges on the substrate electrode and / or edge ring electrode, reducing the sheath voltage and spreading out the ion energy.

[0098] In operation 1110, the current of the power module (e.g., IEDF width control module) and / or the voltage or voltage derivative of the IEDF width control module are measured under two or more conditions to determine the sheath capacitance C1 and / or the ion current I0. Here, the measured current can be the current I4, which is the current through the capacitor C4 of Figures 5A, 6A, 7, and 8. Additionally or alternatively, the measured current can be the output current of the main pulser of Figures 9 and 10. The voltage derivative can be dV3 / dt. The measurement can be performed at the ion current stage. The two or more conditions can be achieved by setting the active knobs of the IEDF width control module (e.g., DC voltage source V0 and / or shaped DC pulse voltage source dV1 / dt) to two different values.

[0099] As an example, for the configurations of Figures 5, 8, and 10, the shaped DC pulse voltage source can be set to any two different slopes dV1 / dt in the ion current stage. As another example, for the configurations of Figures 6, 7, and 9, when I4 is affected by the DC voltage V0, the DC voltage V0 can be gradually increased while monitoring I4 to a point. This DC voltage is a threshold voltage Vth. At least one of the two set points for the DC voltage source V0 is greater than Vth. That is, measuring the current of the IEDF width control module, the voltage or voltage derivative of the IEDF width control module, or both includes setting the DC voltage source, the shaped DC pulse voltage source, or both to a first value, and setting the DC voltage source, the shaped DC pulse voltage source, or both to a second value.

[0100] In act 1115, the ion current I0 and the sheath capacitance C1 are calculated based on equations (6) and (7) for the configurations of Figures 5, 8, and 10, or equations (19) and (20) for the configurations of Figures 6, 7, and 9. The inputs to the calculations are: I3=C3×dV3 / dt; I3'=C3×dV3' / dt; and I4, I4'. The values ​​of C3 and C3' are known, and the values ​​of dV3 / dt, dV3' / dt, I4, and I4' are measured in act 1110. Thus, I3 and I3' can be calculated.

[0101] In operation 1120, a desired set point for the DC voltage (V0) of the main pulser, a desired set point for the voltage (V1) or voltage derivative (dV1 / dt) of the IEDF width control module, or both, is determined to achieve the target IEDF width (ΔV). This determination is based, for example, on determining the desired setting of the IEDF width control module to achieve a user-specified ion energy distribution width (ΔV). The slope (dV1 / dt) of the DC voltage (V0) of the main pulser and the shaped DC pulse voltage (V1) can be determined from equations (23) and (9), respectively. In operation 1125, the DC voltage (V0) and / or the voltage (V1) or voltage derivative (dV1 / dt) of the IEDF width control module are adjusted to the determined set points.

[0102] In contrast to conventional processes for controlling the IEDF, the methods described herein do not involve looping to determine the desired set point of the IEDF width control module. However, in some embodiments, looping can be used to determine the desired set point. In such embodiments, the controller can monitor I4 and V3 in the ion current stage to detect any changes in plasma conditions and adjust the set point of the IEDF width control module accordingly.

[0103] The methods and apparatus, e.g., circuits, described herein allow control over the shape (e.g., narrow or adjustable width) of the pulsed DC substrate voltage waveform. The embodiments described herein further allow control over ion energy distribution, including, e.g., monoenergetic ion acceleration.

[0104] Although the embodiments of the present disclosure have been illustrated and described, as is apparent from the general description and specific embodiments above, various modifications can be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not intended to be limited thereby. Similarly, the term "comprises" is considered synonymous with the term "includes". Similarly, whenever a configuration, element, or group of elements is followed by the transitional phrase "comprises", it is understood that the same configuration or group of elements is also contemplated when accompanied by the transitional phrases "consisting essentially of", "consisting of", "selected from the group consisting of", or "is", either before or after the recitation of the configuration, element, or multiple elements.

[0105] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the disclosure, the scope of which is determined by the following claims.

Claims

1. 1. A method for controlling a width of an ion energy distribution function (IEDF), comprising: Inducing a voltage to an electrode of the processing chamber by activating a primary pulser coupled to an IEDF width control module; Measuring the current of the IEDF width control module and the voltage or voltage differential of the IEDF width control module; calculating an ion current of the process chamber and a volume of the process chamber based on the current and the voltage or the voltage derivative of the IEDF width control module; determining a set point for the DC voltage of the main pulser, a set point for the voltage or voltage derivative of the IEDF width control module, or both; and adjusting the DC voltage of the main pulser, the voltage or the voltage derivative of the IEDF width control module, or both, to the determined set point to control the width of the IEDF.

2. The method of claim 1 , wherein the electrode is a substrate electrode.

3. The method of claim 1 , wherein the electrode is an edge ring electrode.

4. Measuring the current of the IEDF width control module and the voltage differential of the IEDF width control module; setting the DC voltage of the IEDF width control module to two different values; and setting the voltage or voltage differential of the IEDF width control module to two different values.

5. a substrate electrode for applying a substrate voltage to the substrate; an edge ring electrode for applying an edge ring voltage to the edge ring; a substrate voltage control circuit coupled to the substrate electrode; an edge ring voltage control circuit coupled to the edge ring electrode; the substrate electrode is coupled to a power module configured to actively control an energy distribution function width of ions reaching the substrate; the edge ring electrode is coupled to a power module configured to actively control an energy distribution function width of ions reaching the edge ring; or It is a combination of these, The substrate support, wherein the substrate voltage control circuit, the edge ring voltage control circuit, or both, comprises a main pulser coupled to a current return path, the current return path being coupled to the power module and to a processing chamber, the power module comprising a voltage source, a current source, or a combination thereof.

6. The substrate support of claim 5 , wherein only the substrate electrode is coupled to the power module.

7. The substrate support of claim 5 , wherein only the edge ring electrode is coupled to the power module.

8. The substrate support of claim 5 , wherein the power module comprises a transistor logic signal coupled in parallel with a switch, an optional diode, and a shaped DC pulse voltage source.

9. The substrate support of claim 8 , wherein the shaped DC pulse voltage source controls a slope of a voltage waveform of the substrate voltage, a slope of a voltage waveform of the edge ring voltage, or a combination thereof.

10. 6. The substrate support of claim 5, wherein the power module comprises a transistor logic signal coupled in parallel with a switch, a diode, and a DC voltage source coupled in series with a resistor.

11. The substrate support of claim 10 , wherein the DC voltage source coupled in series with the resistor controls a slope of a voltage waveform of the substrate voltage, a slope of a voltage waveform of the edge ring voltage, or a combination thereof.

12. a substrate electrode for applying a substrate voltage to the substrate; an edge ring electrode for applying an edge ring voltage to the edge ring; a substrate voltage control circuit coupled to the substrate electrode; an edge ring voltage control circuit coupled to the edge ring electrode; the substrate electrode is coupled to a power module configured to actively control an energy distribution function width of ions reaching the substrate; the edge ring electrode is coupled to a power module configured to actively control an energy distribution function width of ions reaching the edge ring; It is a combination of these, the substrate voltage control circuit, the edge ring voltage control circuit, or both; a main pulser coupled to the power module, the power module being coupled to a process chamber, the power module comprising a voltage source, a current source, or a combination thereof; or A substrate support comprising: a main pulser coupled to the power module, the power module being coupled to a processing chamber, the power module being in parallel with a substrate chucking and bias compensation module, the power module comprising a voltage source, a current source, or a combination thereof.

13. The substrate support of claim 12 wherein a blocking capacitance is coupled to both the main pulser and the power module.

14. The substrate support of claim 12 , wherein only the substrate electrode is coupled to the power module.

15. The substrate support of claim 12 , wherein only the edge ring electrode is coupled to the power module.

16. 13. The substrate support of claim 12, wherein the power module comprises a transistor logic signal coupled in parallel with a switch, the switch coupled in parallel with a diode and a DC voltage source, the DC voltage source coupled in series with a resistor.

17. The substrate support of claim 16 , wherein the DC voltage source coupled in series with the resistor controls a slope of a voltage waveform of the substrate voltage, a slope of a voltage waveform of the edge ring voltage, or a combination thereof.

18. 13. The substrate support of claim 12, wherein the power module comprises a transistor logic signal coupled in parallel with a switch, the switch coupled in parallel with a diode and a shaped DC pulse voltage source.

19. The substrate support of claim 18 , wherein the shaped DC pulse voltage source controls a slope of a voltage waveform of the substrate voltage.

20. The substrate support of claim 18 , wherein the shaped DC pulse voltage source controls a slope of a voltage waveform of the edge ring voltage.

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