Semiconductor device

Abstract

To provide a semiconductor device with favorable electrical characteristics, provide a semiconductor device with high reliability, and provide a semiconductor device with stable electric characteristics.SOLUTION: A semiconductor device comprises a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The semiconductor layer, the second insulating layer and the conductive layer are laminated on the first insulating layer in this order. The semiconductor layer contains indium and oxygen and has a composition falling within a range obtained by connecting first coordinates (1:0:0), second coordinates (2:1:0), third coordinates (14:7:1), fourth coordinates (7:2:2), fifth coordinates (14:4:21), sixth coordinates (2:0:3), and the first coordinates in this order with a straight line in a ternary diagram showing atomic ratios of indium to an element M and zinc. In addition, the element M is any one or more of gallium, aluminum, yttrium, and tin.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] As a semiconductor material applicable to transistors, oxide semiconductors using metal oxides have been attracting attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel among the plurality of oxide semiconductor layers contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing the field effect mobility (sometimes simply referred to as mobility, or μFE).

[0004] Non-Patent Documents 1 and 2 disclose an oxide semiconductor material of InGaO3(ZnO)m (m: natural number).

[0005] Metal oxides that can be used for the semiconductor layer can be formed by sputtering or the like, and therefore can be used for the semiconductor layer of transistors that constitute large display devices. In addition, since it is possible to use a part of the production equipment for transistors using polycrystalline silicon or amorphous silicon by improving it, capital investment can be reduced. In addition, transistors using metal oxides have higher field-effect mobility than those using amorphous silicon, and therefore a high-performance display device provided with a driver circuit can be realized. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-7399 A [Non-patent literature]

[0007] [Non-Patent Document 1] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-Patent Document 2] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-178 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with stable electrical characteristics.An object of one embodiment of the present invention is to provide a highly reliable display device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device having a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The semiconductor layer, the second insulating layer, and the conductive layer are stacked in this order on the first insulating layer. The semiconductor layer preferably contains indium and oxygen, and has a composition within a range that is connected by straight lines in this order from the first coordinate (1:0:0), the second coordinate (2:1:0), the third coordinate (14:7:1), the fourth coordinate (7:2:2), the fifth coordinate (14:4:21), the sixth coordinate (2:0:3), and the first coordinate in a triangular diagram showing the atomic ratio of indium, the element M, and zinc. The element M is at least one of gallium, aluminum, yttrium, and tin.

[0011] One embodiment of the present invention is a semiconductor device having a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The semiconductor layer, the second insulating layer, and the conductive layer are stacked in this order on the first insulating layer. The semiconductor layer contains indium and oxygen, and preferably has a composition within a range that is connected by straight lines in this order from the first coordinate (7:1:0), the second coordinate (2:1:0), the third coordinate (14:7:1), the fourth coordinate (7:2:2), the fifth coordinate (14:4:21), the sixth coordinate (2:0:3), the seventh coordinate (7:0:1), and the first coordinate in a triangular diagram showing the atomic ratio of indium, the element M, and zinc. The element M is at least one of gallium, aluminum, yttrium, and tin.

[0012] One embodiment of the present invention is a semiconductor device having a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The semiconductor layer, the second insulating layer, and the conductive layer are stacked in this order on the first insulating layer. The semiconductor layer contains indium, zinc, and oxygen, and preferably has a composition within a range that is connected by straight lines in this order from the first coordinate (44:11:10), the second coordinate (4:1:6), the third coordinate (2:0:3), the fourth coordinate (11:0:2), and the first coordinate in a triangular diagram showing the atomic ratio of indium, the element M, and zinc. The element M is at least one of gallium, aluminum, yttrium, and tin.

[0013] One embodiment of the present invention is a semiconductor device having a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The semiconductor layer, the second insulating layer, and the conductive layer are stacked in this order on the first insulating layer. The semiconductor layer contains indium, zinc, and oxygen, and preferably has a composition within a range that is connected by straight lines in this order from the first coordinate (44:11:10), the second coordinate (4:1:4), the third coordinate (1:0:1), the fourth coordinate (11:0:2), and the first coordinate in a triangular diagram showing the atomic ratio of indium, the element M, and zinc. The element M is at least one of gallium, aluminum, yttrium, and tin.

[0014] In the above-described semiconductor device, it is preferable that the semiconductor layer has a region that does not overlap with the conductive layer, and that the region contains at least one of phosphorus, boron, magnesium, aluminum, and silicon.

[0015] In the above-described semiconductor device, the second insulating layer is preferably in contact with the region.

[0016] The semiconductor device further includes a third insulating layer, which is preferably in contact with the upper and side surfaces of the conductive layer, the side surfaces of the second insulating layer, and the upper and side surfaces of the semiconductor layer. It is also preferable that the second insulating layer contains oxygen and the third insulating layer contains nitrogen.

[0017] In the above-described semiconductor device, the second insulating layer preferably contains silicon oxide, and the third insulating layer preferably contains silicon nitride. Effect of the Invention

[0018] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics, a highly reliable semiconductor device, a semiconductor device with stable electrical characteristics, or a highly reliable display device can be provided.

[0019] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B are diagrams illustrating the composition of metal oxides. [Diagram 2] 2A and 2B are diagrams illustrating the composition of metal oxides. [Diagram 3] 3A and 3B are diagrams illustrating the composition of metal oxides. [Figure 4] FIG. 4 is a diagram illustrating the composition of metal oxides. [Diagram 5] Fig. 5A is a diagram for explaining the classification of IGZO crystal structures, Fig. 5B is a diagram for explaining the XRD spectrum of silica glass, and Fig. 5C is a diagram for explaining the XRD spectrum of crystalline IGZO. [Figure 6] 6A and 6B are examples of transistor configurations. [Figure 7] 7A and 7B are examples of transistor configurations. [Figure 8] Figure 8A is a top view of the transistor, and Figures 8B and 8C are cross-sectional views of the transistor. [Figure 9] Figure 9A is a top view of the transistor, and Figures 9B and 9C are cross-sectional views of the transistor. [Figure 10] Figure 10A is a top view of a transistor, and Figures 10B and 10C are cross-sectional views of the transistor. [Figure 11] Figure 11A is a top view of the transistor, and Figures 11B and 11C are cross-sectional views of the transistor. [Figure 12] 12A, 12B, 12C and 12D are cross-sectional views of a transistor. [Figure 13] 13A, 13B, 13C and 13D are cross-sectional views of a transistor. [Figure 14] 14A, 14B, 14C, 14D, and 14E illustrate a method for manufacturing a transistor. [Figure 15] 15A, 15B, 15C, and 15D illustrate a method for manufacturing a transistor. [Figure 16] 16A and 16B illustrate a method for manufacturing a transistor. [Figure 17] 17A, 17B, 17C, and 17D illustrate a method for manufacturing a transistor. [Figure 18] 18A, 18B and 18C are top views of the display device. [Figure 19] FIG. 19 is a cross-sectional view of the display device. [Figure 20] FIG. 20 is a cross-sectional view of the display device. [Figure 21] FIG. 21 is a cross-sectional view of the display device. [Figure 22] FIG. 22 is a cross-sectional view of the display device. [Diagram 23] Fig. 23A is a block diagram of a display device, and Fig. 23B and Fig. 23C are circuit diagrams of the display device. [Figure 24] Figures 24A, 24C and 24D are circuit diagrams of the display device, and Figure 24B is a timing chart of the display device. [Diagram 25] 25A and 25B show configuration examples of a display module. [Figure 26]26A and 26B show configuration examples of electronic devices. [Figure 27] 27A, 27B, 27C, 27D, and 27E show configuration examples of electronic devices. [Figure 28] 28A, 28B, 28C, 28D, 28E, 28F, and 28G show configuration examples of electronic devices. [Figure 29] 29A, 29B, 29C, and 29D show configuration examples of electronic devices. [Diagram 30] FIG. 30 shows the results of XRD analysis. [Diagram 31] FIG. 31 is a diagram showing ID-VG characteristics of a transistor. [Diagram 32] FIG. 32 is a diagram showing the mobility of a transistor. [Diagram 33] FIG. 33 shows the results of TDS analysis. [Diagram 34] FIG. 34 is a diagram showing ID-VG characteristics of a transistor. [Diagram 35] FIG. 35 is a diagram showing ID-VG characteristics of a transistor. [Diagram 36] FIG. 36 is a diagram showing the reliability of a transistor. [Figure 37] FIG. 37 is a diagram showing ID-VG characteristics of a transistor. [Figure 38] FIG. 38 is a diagram showing ID-VG characteristics of a transistor. [Figure 39] FIG. 39 is a diagram showing ID-VG characteristics of a transistor. [Diagram 40] FIG. 40 is a diagram showing ID-VG characteristics of a transistor. [Diagram 41] FIG. 41 is a diagram showing ID-VG characteristics of a transistor. [Diagram 42] FIG. 42 is a diagram showing ID-VG characteristics of a transistor. [Diagram 43] FIG. 43 is a diagram showing ID-VG characteristics of a transistor. [Diagram 44] FIG. 44 is a diagram showing ID-VG characteristics of a transistor. [Diagram 45] FIG. 45 is a diagram showing ID-VG characteristics of a transistor. [Figure 46] FIG. 46 is a diagram showing ID-VG characteristics of a transistor. [Figure 47] FIG. 47 is a diagram showing ID-VG characteristics of a transistor. [Figure 48] FIG. 48 is a diagram showing ID-VG characteristics of a transistor. [Figure 49] FIG. 49 is a diagram showing ID-VG characteristics of a transistor. [Figure 50] FIG. 50 is a diagram showing ID-VG characteristics of a transistor. [Figure 51] FIG. 51 is a diagram showing ID-VG characteristics of a transistor. [Figure 52] FIG. 52 is a diagram showing the reliability of a transistor. [Diagram 53] FIG. 53 shows the results of XRD analysis of metal oxides. [Figure 54] FIG. 54 shows the results of XRD analysis of metal oxides. [Figure 55] FIG. 55 is a diagram showing the band gap of metal oxides. [Figure 56] Fig. 56A is a diagram showing the carrier concentration of a metal oxide, and Fig. 56B is a diagram showing the Hall mobility of a metal oxide. [Figure 57] Fig. 57A is a diagram showing the carrier concentration of a metal oxide, and Fig. 57B is a diagram showing the Hall mobility of a metal oxide. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0022] In each figure described in this specification, the size, layer thickness, or area of ​​each component may be exaggerated for clarity.

[0023] The ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion of components and are not intended to limit the numbers.

[0024] In this specification, the terms "above" and "below" indicating the position are used for convenience in describing the positional relationship between components with reference to the drawings. The positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0025] In this specification and the like, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, the terms source and drain can be used interchangeably.

[0026] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of a current flowing through a semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Note that, depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be determined to be one.

[0027] In this specification, "electrically connected" includes a case where a connection is made via "something having some electrical action." Here, the "something having some electrical action" is not particularly limited as long as it allows transmission and reception of an electrical signal between the objects to be connected. For example, "something having some electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

[0028] In this specification and the like, the terms "film" and "layer" can be interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchangeable with the terms "conductive film" and "insulating film".

[0029] In this specification, unless otherwise specified, the off-state current refers to the drain current when the transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when the transistor is in an off state (also called a non-conducting state or a cut-off state) when the voltage V gs is the threshold voltage V th (For p-channel transistors, V th The term "higher" refers to a state of being.

[0030] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one aspect of an output device.

[0031] In this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0032] In this specification and the like, a touch panel, which is one aspect of a display device, has a function of displaying an image or the like on a display surface and a function as a touch sensor that detects that a detectable object such as a finger or a stylus touches, presses, or approaches the display surface. Thus, the touch panel is one aspect of an input / output device.

[0033] The touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function. The touch panel can have a display panel and a touch sensor panel. Alternatively, the touch panel can have a function as a touch sensor inside or on the surface of the display panel.

[0034] In this specification and the like, a touch panel substrate on which a connector and / or an IC are mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

[0035] (Embodiment 1) In this embodiment, a metal oxide that can be suitably used for a semiconductor device according to one embodiment of the present invention will be described.

[0036] A semiconductor device according to one embodiment of the present invention includes a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor in a channel formation region. The use of a metal oxide is preferable because a transistor can have good switching characteristics and an extremely low off-state current as compared with a semiconductor made of silicon or the like.

[0037] Here, the composition of the metal oxide has a large effect on the electrical characteristics and reliability of the transistor. The metal oxide preferably contains indium. Furthermore, the metal oxide preferably has a high indium content. By increasing the indium content of the metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a transistor using a metal oxide with a high indium content for a channel formation region has high field effect mobility and can pass a large current. In addition, a semiconductor device using the transistor can be driven at high speed. Therefore, in a display device including such a semiconductor device, a transistor for a pixel portion and a transistor for use in a driver circuit portion can be formed over the same substrate. Furthermore, by using such a transistor for the pixel portion, a high-quality image can be provided.

[0038] The metal oxide preferably contains element M in addition to indium. It is preferable that element M has a high bond energy with oxygen. In particular, it is preferable that element M has a higher bond energy with oxygen than indium. By containing element M, which has a higher bond energy with oxygen than indium, oxygen vacancies are less likely to be formed in the metal oxide. As element M, one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium can be used. In particular, as element M, one or more of gallium, aluminum, yttrium, and tin can be used. In addition, element M has a function of increasing the energy gap of the metal oxide.

[0039] Gallium can be particularly preferably used as the element M. The metal oxide contains gallium, which has a higher bond energy with oxygen than indium, so that oxygen vacancies are less likely to be formed in the metal oxide. If many oxygen vacancies exist in the metal oxide used in the channel formation region, this leads to a decrease in the electrical characteristics and reliability of the transistor. Therefore, by using a metal oxide containing indium and gallium, a transistor with high field effect mobility and high reliability can be realized.

[0040] The metal oxide preferably contains zinc in addition to indium. Alternatively, the metal oxide preferably contains indium, element M, and zinc. Zinc has a function of increasing the crystallinity of the metal oxide. A crystalline metal oxide can be suitably used for the channel formation region. For example, a metal oxide having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystal (nc) structure, or the like, which will be described later, can be used for the channel formation region. By using a crystalline metal oxide for the channel formation region, the defect level density in the channel formation region can be reduced, and a highly reliable transistor can be realized.

[0041] The higher the crystallinity of the metal oxide, the lower the density of defect states in the film. On the other hand, by using a metal oxide with low crystallinity for the channel formation region, a transistor capable of passing a large current can be realized.

[0042] <Metal oxide composition> The composition of the metal oxide will be specifically described below. In the following, the atomic ratio of indium, element M, and zinc in the metal oxide will be shown as the composition.

[0043] The preferred range of the atomic ratio of indium, element M, and zinc in the metal oxide is shown in Figures 1A, 1B, 2A, and 2B. Figures 1A, 1B, 2A, and 2B show the atomic ratio of indium, element M, and zinc using an equilateral triangle with indium, element M, and zinc as vertices, and are also called triangular diagrams, triangular coordinate diagrams, or triangular diagrams. Note that Figures 1A, 1B, 2A, and 2B do not show the atomic ratio of oxygen.

[0044] First, the atomic ratio of each element will be described with reference to Figures 3A, 3B, and 4. Figures 3A, 3B, and 4 respectively show examples of metal oxides having element X, element Y, and element Z. The triangular diagrams shown in Figures 3A, 3B, and 4 show an equilateral triangle with points X, Y, and Z as vertices, and a coordinate point W (α:β:γ) as an example of the composition of the metal oxide.

[0045] The coordinate point W (α:β:γ) indicates that the atomic ratio of element X, element Y, and element Z is X:Y:Z=α:β:γ. The closer to each vertex, the higher the atomic ratio of each element is, and the farther away, the lower the atomic ratio is. Here, the coordinate of point X is (1:0:0), and the atomic ratio of element X, element Y, and element Z is X:Y:Z=1:0:0, that is, the metal oxide has element X, and does not have either element Y or element Z. The coordinate of point Y is (0:1:0), and the atomic ratio of element X, element Y, and element Z is X:Y:Z=0:1:0, that is, the metal oxide has element Y, and does not have either element X or element Z. The coordinate of point Z is (0:0:1), and the atomic ratio of element X, element Y, and element Z is X:Y:Z=0:0:1, that is, the metal oxide has element Z, and does not have either element X or element Y.

[0046] In this specification, the atomic ratio of element X, element Y, and element Z may be expressed as X:Y:Z. Also, the ratio of the total atomic number of element X and element Y to the atomic number of element Z may be expressed as (X+Y):Z. Other combinations of elements may be expressed in the same manner.

[0047] FIG. 3A shows lines LNx, LNy, and LNz. Line LNx is a straight line connecting point Dx (0:β:γ) that divides the length of side YZ by γ:β and point X. Line LNx can also be said to be a set of points where the atomic ratio of element Y to element Z satisfies Y:Z=β:γ. Line LNy is a straight line connecting point Dy (α:0:γ) that divides the length of side XZ by γ:α and point Y. Line LNy can also be said to be a set of points where the atomic ratio of element X to element Z satisfies X:Z=α:γ. Line LNz is a straight line connecting point Dz (α:β:0) that divides the length of side XY by β:α and point Z. Line LNz can also be said to be a set of points where the atomic ratio of element X to element Y satisfies X:Y=α:β. Moreover, the lines LNx, LNy, and LNz all intersect with the coordinate point W (α:β:γ).

[0048] In this specification, a "straight line connecting point A and point B" can be replaced with a "line segment connecting point A and point B."

[0049] Here, the coordinate point W(α:β:γ) can also be said to be the intersection of the line LNx and the line LNy. The coordinate point W(α:β:γ) can also be said to be the intersection of the line LNy and the line LNz. The coordinate point W(α:β:γ) can also be said to be the intersection of the line LNx and the line LNz.

[0050] In addition, side XY is a set of points where the ratio of the total number of atoms of element X and element Y to the number of atoms of element Z satisfies (X+Y):Z=1:0. In other words, side XY indicates that the metal oxide has at least one of element X or element Y, and does not have element Z. Side YZ is a set of points where the ratio of the total number of atoms of element X to element Y and element Z satisfies X:(Y+Z)=0:1. In other words, side YZ indicates that the metal oxide has at least one of element Y or element Z, and does not have element X. Side XZ is a set of points where the ratio of the total number of atoms of element X and element Z to element Y satisfies (X+Z):Y=1:0. In other words, side XZ indicates that the metal oxide has at least one of element X or element Z, and does not have element Y.

[0051] As a specific example, the case where the coordinate point W is (5:1:3) will be described. For the coordinate point W (5:1:3), the ratio of the length of the line segment XDz to the length of the line segment DzY is 1:5. The ratio of the length of the line segment YDx to the length of the line segment DxZ is 3:1. The ratio of the length of the line segment XDy to the length of the line segment DyZ is 3:5. Furthermore, the line LNx is a set of points where the atomic ratio of the element Y to the element Z satisfies Y:Z = 1:3. The line LNy is a set of points where the atomic ratio of the element X to the element Z satisfies X:Z = 5:3. The line LNz is a set of points where the atomic ratio of the element X to the element Y satisfies X:Y = 5:1.

[0052] Figure 3B shows lines PEx, PEy, and PEz. Line PEx is a perpendicular line drawn from coordinate point W (α:β:γ) to side YZ. Line PEy is a perpendicular line drawn from coordinate point W (α:β:γ) to side XZ. Line PEz is a perpendicular line drawn from coordinate point W (α:β:γ) to side XY. Here, the ratio of the length of line PEx to the length of line PEy to the length of line PEz is α:β:γ.

[0053] As a specific example, a case where the coordinate point W is (5:1:3) will be described. When the coordinate point W is (5:1:3), the ratio of the length of the line PEx to the length of the line PEy and the length of the line PEz is 5:1:3.

[0054] FIG. 4A shows lines PAx, PAy, and PAz. Line PAx is a straight line parallel to side YZ and intersects with coordinate point W (α:β:γ). Line PAy is a straight line parallel to side XZ and intersects with coordinate point W (α:β:γ). Line PAz is a straight line parallel to side XY and intersects with coordinate point W (α:β:γ). Line PAx can also be said to be a set of points where the ratio of the total number of atoms of element X to element Y and element Z satisfies X:(Y+Z)=α:(β+γ). Line PAy can also be said to be a set of points where the ratio of the total number of atoms of element X and element Z to the number of atoms of element Y satisfies (X+Z):Y=(α+γ):β. Line PAz can also be said to be a set of points where the ratio of the total number of atoms of element X and element Y to the number of atoms of element Z satisfies (X+Y):Z=(α+β):γ.

[0055] As a specific example, a case where coordinate point W is (5:1:3) will be described. In the case of coordinate point W (5:1:3), line PAx is a set of points where the ratio between the number of atoms of element X and the total number of atoms of elements Y and Z satisfies X:(Y+Z)=5:4. Line PAy is a set of points where the ratio between the number of atoms of element X and element Z and the total number of atoms of element Y satisfies (X+Z):Y=8:1. Line PAz is a set of points where the ratio between the number of atoms of element X and element Y and the number of atoms of element Z satisfies (X+Y):Z=2:1.

[0056] The composition of a metal oxide that can be suitably used for a channel formation region of a transistor will be specifically described below.

[0057] [Metal oxide composition 1] The metal oxide preferably contains indium and oxygen. The metal oxide may further contain one or more of element M and zinc. The composition of the metal oxide that can be suitably used for the channel formation region of the transistor is shown in FIG. 1A. The atomic ratio of indium, element M, and zinc in the metal oxide is preferably included in range 11 in the triangular diagram shown in FIG. 1A. The range 11 is inside a polygon that connects coordinate point A (1:0:0), coordinate point B (2:1:0), coordinate point C (14:7:1), coordinate point D (7:2:2), coordinate point E (14:4:21), coordinate point F (2:0:3), and the coordinate point A with straight lines in this order. The range 11 includes each coordinate point and each side. By using a metal oxide having a composition included in range 11 for the channel formation region, a transistor with high reliability and high field effect mobility can be obtained.

[0058] In addition, when the element M contains a plurality of elements, the ratio of the total number of atoms of these elements is used as the atomic ratio of the element M. For example, when the element M contains gallium and tin, the ratio of the total number of atoms of gallium and tin is used as the atomic ratio of the element M.

[0059] Here, coordinate point B (2:1:0) is the intersection of line L1, which is a set of points that satisfy (In+M):Zn=1:0, and line L2, which is a set of points that satisfy In:M=2:1. Coordinate point C (14:7:1) is the intersection of the aforementioned line L2 and line L3, which is a set of points that satisfy In:(M+Zn)=7:4. Coordinate point C is also the intersection of the aforementioned line L2 and line L4, which is a set of points that satisfy In:Zn=14:1. Coordinate point D (7:2:2) is the intersection of the aforementioned line L3 and line L5, which is a set of points that satisfy In:Zn=7:2. Coordinate point D is also the intersection of the aforementioned line L3 and line L6, which is a set of points that satisfy In:M=7:2. Coordinate point E (14:4:21) is the intersection of the aforementioned line L6 and line L7, which is a set of points that satisfy In:Zn=2:3. Coordinate point F (2:0:3) is the intersection of the above-mentioned line L7 and line L8, which is a set of points that satisfy (In+Zn):M=1:0.

[0060] In this specification, the ratio of the number of atoms of indium, element M, and zinc may be written as In:M:Zn. Also, the ratio of the total number of atoms of indium and element M to the number of atoms of zinc may be written as (In+M):Zn. The same applies to other combinations of each element.

[0061] Side AB is on the aforementioned line L1, side BC is on the aforementioned line L2, side CD is on the aforementioned line L3, side DE is on the aforementioned line L6, side EF is on the aforementioned line L7, and side FA is on the aforementioned line L8. In other words, it can be said that range 11 is inside the polygon surrounded by lines L1, L2, L3, L6, L7, and L8.

[0062] As shown in range 11, the composition of the metal oxide preferably satisfies line L2, In:M=2:1, or has an indium content higher than In:M=2:1. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 2 or more. Metal oxides with a high indium content have high carrier mobility (electron mobility), and a transistor using a metal oxide with a high indium content in the channel formation region has high field-effect mobility and can pass a large current.

[0063] However, if the content of element M is high, the defect level increases, and the threshold voltage may fluctuate greatly in a reliability test. One of the indicators for evaluating the reliability of a transistor is the GBT (Gate Bias Temperature) stress test, in which an electric field is applied to the gate. Among them, a test in which a positive potential is applied to the gate with respect to the source potential and drain potential and the test is held at high temperature is called the PBTS (Positive Bias Temperature Stress) test, and a test in which a negative potential is applied to the gate and the test is held at high temperature is called the NBTS (Negative Bias Temperature Stress) test. In addition, the PBTS test and the NBTS test, which are conducted under irradiation with light such as white LED light, are called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0064] In particular, in n-type transistors using metal oxides, a positive potential is applied to the gate when the transistor is in the on-state (state in which current is flowing), so the amount of variation in threshold voltage in the PBTS test is one of the important items to pay attention to as an index of transistor reliability.

[0065] Here, by using a metal oxide that does not contain element M or has a low content of element M, it is possible to reduce the amount of variation in threshold voltage in the PBTS test. Furthermore, when element M is contained, it is preferable that the content of element M is smaller than the content of indium in the composition of the metal oxide. Furthermore, it is preferable that the ratio In / M of the number of indium atoms to the number of atoms of element M is 2 or more. This makes it possible to realize a highly reliable transistor.

[0066] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the more significant the degradation in the PBTS test. However, the generation of the defect levels can be suppressed by reducing the content of element M in the part of the semiconductor layer that contacts the gate insulating layer.

[0067] The following are some possible reasons why PBTS degradation can be suppressed by not including element M or by reducing the content of element M. Element M contained in the semiconductor layer has the property of attracting oxygen more easily than other metal elements (e.g., indium and zinc). Therefore, it is presumed that element M bonds with excess oxygen in the insulating layer at the interface between a metal oxide film containing a large amount of element M and an insulating layer containing oxide, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause the threshold voltage to fluctuate.

[0068] Therefore, by using a metal oxide in which the ratio of the number of indium atoms to the number of atoms of element M, In / M, is 2 or more for the channel formation region, the generation of defect levels can be suppressed, resulting in a transistor with high reliability and high field-effect mobility.

[0069] As shown in range 11, the composition of the metal oxide preferably satisfies line L3 of In:(M+Zn)=7:4, or has a higher indium content than In:(M+Zn)=7:4. In other words, the ratio In / (M+Zn) of the number of indium atoms to the total number of atoms of elements M and zinc is preferably 7 / 4 or more. Metal oxides with a high indium content have high carrier mobility (electron mobility), and a transistor using a metal oxide with a high indium content in the channel formation region has high field-effect mobility and can pass a large current. Therefore, a transistor with high field-effect mobility can be obtained by using a metal oxide having an atomic ratio in the above-mentioned range in the channel formation region.

[0070] As shown in range 11, the composition of the metal oxide preferably satisfies line L6 of In:M=7:2 or has a higher indium content than In:M=7:2. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 7 / 2 or more. By using a metal oxide having an atomic ratio in the above-mentioned range for the channel formation region, it is possible to suppress the generation of defect levels and provide a transistor with high reliability and high field-effect mobility.

[0071] As shown in range 11, the composition of the metal oxide preferably satisfies the line L7 of In:Zn=2:3, or has a higher indium content than In:Zn=2:3. In other words, the ratio of the number of indium atoms to the number of zinc atoms, In / Zn, is preferably 2 / 3 or more. If the zinc content is high, the metal oxide may become polycrystalline. Since the crystal grain boundaries of the polycrystalline metal oxide become defect levels and become carrier traps or carrier generation sources, a transistor using a polycrystalline metal oxide may have large fluctuations in electrical characteristics and low reliability. Therefore, by setting the atomic ratio within the above-mentioned range, the metal oxide can be prevented from becoming polycrystalline. In addition, by using the metal oxide in the channel formation region, a highly reliable transistor can be obtained.

[0072] As the metal oxide, an In-M-Zn oxide having a composition falling within range 11 can be used. As the In-M-Zn oxide, for example, In:M:Zn=5:1:1, In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or a combination thereof may be suitably used. Also, indium oxide can be used as the metal oxide. Also, In-M oxide can be used as the metal oxide. For example, In:M=2:1, In:M=7:2, In:M=5:1, In:M=7:1, In:M=10:1, or a mixture thereof can be suitably used as the In-M oxide. Also, In-Zn oxide can be used as the metal oxide. For example, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, In:Zn=14:1, or a mixture thereof can be suitably used as the In-Zn oxide.

[0073] Examples of analytical methods for the composition of metal oxides include energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), and inductively coupled plasma-atomic emission spectroscopy (ICP-AES). Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0074] When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be about 40% or more and 90% or less of the atomic ratio of zinc contained in the target. Here, it is preferable that the target used is polycrystalline.

[0075] [Metal oxide composition 2] The metal oxide preferably contains at least one of element M and zinc, indium, and oxygen. FIG. 1B shows a composition of a metal oxide that can be suitably used for a channel formation region of a transistor. The atomic ratio of indium, element M, and zinc in the metal oxide is preferably included in range 13 in the triangular diagram shown in FIG. 1B. The range 13 is inside a polygon that connects coordinate point G (7:1:0), coordinate point B (2:1:0), coordinate point C (14:7:1), coordinate point D (7:2:2), coordinate point E (14:4:21), coordinate point F (2:0:3), coordinate point H (7:0:1), and the coordinate point G in this order with straight lines. The range 13 includes each coordinate point and each side. By using a metal oxide having a composition included in range 13 for the channel formation region, a transistor with high reliability and high field effect mobility can be obtained.

[0076] Here, coordinate point G (7:1:0) is the intersection of line L1, which is a set of points that satisfy (In+M):Zn=1:0, and line L9, which is a set of points that satisfy In:(M+Zn)=7:1. Coordinate point H (7:0:1) is the intersection of line L9 and line L8, which is a set of points that satisfy (In+Zn):M=1:0. The above description can be referred to for coordinate points B to F, so detailed description will be omitted.

[0077] Side GB is on the aforementioned line L1, side BC is on the aforementioned line L2, side CD is on the aforementioned line L3, side DE is on the aforementioned line L6, side EF is on the aforementioned line L7, side FH is on the aforementioned line L8, and side HG is on the aforementioned line L9. In other words, it can be said that range 13 is inside the polygon surrounded by lines L1, L2, L3, L6, L7, L8, and L9.

[0078] As shown in range 13, the composition of the metal oxide preferably satisfies the line L9 of In:(M+Zn)=7:1, or has a lower In content than In:(M+Zn)=7:1. In other words, the ratio In / (M+Zn) of the number of indium atoms to the total number of atoms of the elements M and zinc is preferably 7 or less. If the indium content is high, the metal oxide may have a bixbyite crystal structure. Alternatively, the metal oxide may have a crystal structure in which a bixbyite crystal structure and a layered crystal structure coexist. When a plurality of crystal structures coexist, a crystal grain boundary may be formed between different crystal structures. Since the crystal grain boundary becomes a defect level and becomes a carrier trap or a carrier generation source, a transistor using a metal oxide having a crystal grain boundary may have a large fluctuation in electrical characteristics and may be low in reliability. Therefore, by setting the atomic ratio in the above-mentioned range, the metal oxide is suppressed from having a bixbyite crystal structure and is likely to have a layered crystal structure. In addition, by using the metal oxide in the channel formation region, a highly reliable transistor can be obtained.

[0079] As shown in range 13, the composition of the metal oxide preferably satisfies line L2 of In:M=2:1 or has an indium content higher than In:M=2:1. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 2 or more. By using a metal oxide having an atomic ratio in the above-mentioned range for the channel formation region, it is possible to suppress the generation of defect levels and provide a transistor with high reliability and high field-effect mobility.

[0080] As shown in range 13, the composition of the metal oxide preferably satisfies line L3 of In:(M+Zn)=7:4 or has a higher indium content than In:(M+Zn)=7:4. In other words, the ratio In / (M+Zn) of the number of indium atoms to the total number of atoms of elements M and zinc is preferably 7 / 4 or more. By using a metal oxide having an atomic ratio in the above range for the channel formation region, a transistor with high field effect mobility can be obtained.

[0081] As shown in range 13, the composition of the metal oxide preferably satisfies line L6 of In:M=7:2 or has a higher indium content than In:M=7:2. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 7 / 2 or more. By using a metal oxide having an atomic ratio in the above-mentioned range for the channel formation region, it is possible to suppress the generation of defect levels and provide a transistor with high reliability and high field-effect mobility.

[0082] As shown in range 13, the composition of the metal oxide preferably satisfies line L7 of In:Zn=2:3, or has a higher indium content than In:Zn=2:3. In other words, the ratio of the number of indium atoms to the number of zinc atoms, In / Zn, is preferably 2 / 3 or more. By setting the atomic ratio within the above range, the metal oxide can be prevented from becoming polycrystalline. Furthermore, by using the metal oxide in the channel formation region, a highly reliable transistor can be obtained.

[0083] As the metal oxide, an In-M-Zn oxide having a composition falling within range 13 can be used. As the In-M-Zn oxide, for example, In:M:Zn=5:1:1, In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or a combination thereof may be suitably used. Also, as the metal oxide, an In-M oxide can be used. As the In-M oxide, for example, In:M=2:1, In:M=7:2, In:M=5:1, In:M=7:1, or a mixture thereof can be suitably used. As the metal oxide, an In-Zn oxide can be used. As the In-Zn oxide, for example, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, or a mixture thereof can be suitably used.

[0084] [Metal oxide composition 3] The metal oxide preferably contains indium, zinc, and oxygen. The metal oxide may further contain an element M. FIG. 2A shows a composition of a metal oxide that can be suitably used for a channel formation region of a transistor. The atomic ratio of indium, element M, and zinc in the metal oxide is preferably included in range 15 in the triangular diagram shown in FIG. 2A. Range 15 is within a polygon that connects coordinate points I (44:11:10), J (4:1:6), F (2:0:3), K (11:0:2), and I in this order with straight lines. Note that range 15 includes each coordinate point and each side. By using a metal oxide having a composition included in range 15 for a channel formation region, a transistor with high reliability and high field effect mobility can be obtained.

[0085] Here, coordinate point I (44:11:10) is the intersection of line L10, which is a set of points that satisfy In:M = 4:1, and line L11, which is a set of points that satisfy (In + M):Zn = 11:2. Coordinate point J (4:1:6) is the intersection of the aforementioned line L7 and line L10. Coordinate point K (11:0:2) is the intersection of the aforementioned line L11 and line L8. As the above description can be referred to for coordinate point F, detailed description will be omitted.

[0086] Side IJ is on the aforementioned line L10, side JF is on the aforementioned line L7, side FK is on the aforementioned line L8, and side KI is on the aforementioned line L11. In other words, it can be said that range 15 is inside the polygon surrounded by lines L10, L7, L8, and L11.

[0087] As shown in range 15, the composition of the metal oxide preferably satisfies line L10 of In:M=4:1 or has a higher In content than In:M=4:1. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 4 or more. By using a metal oxide having an atomic ratio in the above-mentioned range for the channel formation region, it is possible to suppress the generation of defect levels and provide a transistor with high reliability and high field-effect mobility.

[0088] As shown in range 15, the composition of the metal oxide preferably satisfies line L7 of In:Zn=2:3, or has a higher indium content than In:Zn=2:3. In other words, the ratio of the number of indium atoms to the number of zinc atoms, In / Zn, is preferably 2 / 3 or more. By setting the atomic ratio within the above range, the metal oxide can be prevented from becoming polycrystalline. Furthermore, by using the metal oxide in the channel formation region, a highly reliable transistor can be obtained.

[0089] As shown in range 15, the composition of the metal oxide preferably satisfies line L11 (In+M):Zn=11:2, or has a zinc content higher than (In+M):Zn=11:2. In other words, the ratio of the total number of atoms of indium and element M to the number of zinc atoms (In+M) / Zn is preferably 11 / 2 or less. Metal oxides tend to have a layered crystal structure due to the presence of zinc. Also, the higher the zinc content, the more crystalline the metal oxide becomes.

[0090] As the metal oxide, an In-M-Zn oxide having a composition included in range 15 can be used. As the In-M-Zn oxide, for example, In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or a composition close to these can be suitably used. In-Zn oxide can also be used as the metal oxide. As the In-Zn oxide, for example, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, or a combination close to these can be suitably used.

[0091] The metal oxide has a composition within the above-mentioned range and is preferably a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a nanocrystalline oxide semiconductor (nc-OS), or a cloud-aligned composite oxide semiconductor (CAC-OS).

[0092] Here, CAC-OS and CAAC-OS, which are metal oxides that can be used in transistors, are described.

[0093] [Constitution of Metal Oxide] CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the whole material has a function as a semiconductor. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of flowing electrons (or holes) as carriers, and the insulating function is a function of not flowing electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0094] CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected in a cloud shape with a blurred periphery.

[0095] In the CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may each be dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.

[0096] CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In this configuration, when carriers are made to flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily on the component having the wide gap, and carriers also flow in the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force in the on state of the transistor, that is, a large on-current and a high field effect mobility can be obtained.

[0097] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0098] [Metal oxide structure] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors other than those. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS, amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0099] When focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of crystal structures in oxide semiconductors will be described with reference to FIG. 5A. FIG. 5A is a diagram for explaining the classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0100] As shown in FIG. 5A, IGZO is broadly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Crystalline includes c-axis aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). Crystalline does not include single crystal and poly crystal, which will be described later. Crystal includes single crystal and poly crystal.

[0101] The structure in the bold frame in Fig. 5A belongs to the new crystalline phase. This structure is in the boundary region between amorphous and crystalline. In other words, this structure is completely different from the energetically unstable amorphous and crystalline structures.

[0102] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) pattern. Here, the XRD spectra of quartz glass and IGZO (also called crystalline IGZO) having a crystal structure classified as Crystalline are shown in Figure 5B and Figure 5C. Figure 5B shows the XRD spectrum of quartz glass, and Figure 5C shows the XRD spectrum of crystalline IGZO. The composition of the crystalline IGZO shown in Figure 5C is In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the crystalline IGZO shown in Figure 5C is 500 nm.

[0103] As shown by the arrows in Figure 5B, the peaks in the XRD spectrum of silica glass are nearly symmetrical. On the other hand, as shown by the arrows in Figure 5C, the peaks in the XRD spectrum of crystalline IGZO are asymmetrical. The asymmetrical peaks in the XRD spectrum clearly indicate the presence of crystals. In other words, if the peaks in the XRD spectrum are not symmetrical, it cannot be said to be amorphous. Note that Figure 5C clearly shows nanocrystals at or near 2θ=31°. It is presumed that the asymmetry in the peaks in the XRD spectrum is due to the nanocrystals.

[0104] Specifically, as shown in FIG. 5C, crystalline IGZO has a peak at or near 2θ=34° in the XRD spectrum. Microcrystals have a peak at or near 2θ=31°. When an oxide semiconductor film is evaluated using an X-ray diffraction pattern, the spectrum width on the lower angle side is wider than the peak at or near 2θ=34°, as shown in FIG. 5C. This suggests that the oxide semiconductor film contains microcrystals having a peak at or near 2θ=31°.

[0105] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a portion where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0106] Nanocrystals are basically hexagonal, but may be non-regular hexagonal. In addition, the lattice arrangement may be pentagonal or heptagonal due to the distortion. In CAAC-OS, no clear grain boundary can be confirmed even in the vicinity of the distortion. In other words, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms in the ab-plane direction is not dense and the bond distance between atoms changes due to the substitution of metal elements.

[0107] A crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor or a decrease in field-effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0108] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M can be substituted for each other, and when element M in an (M, Zn) layer is substituted for indium, it can also be represented as an (In, M, Zn) layer. When indium in an In layer is substituted for element M, it can also be represented as an (In, M) layer.

[0109] CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, it can be said that a decrease in electron mobility due to crystal grain boundaries is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. In addition, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0110] The nc-OS has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0111] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0112] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0113] [Transistor Having Oxide Semiconductor] Next, the case where the oxide semiconductor is used for a transistor will be described.

[0114] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0115] An oxide semiconductor having a low carrier concentration is preferably used for the transistor. In order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic semiconductor or a substantially high-purity intrinsic semiconductor.

[0116] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore may also have a low density of trap states.

[0117] A charge trapped in the trap states of an oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0118] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0119] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0120] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0121] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is preferably reduced to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0122] When an oxide semiconductor contains nitrogen, electrons that serve as carriers are generated, the carrier concentration increases, and the semiconductor tends to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, it is preferable that the amount of nitrogen in the oxide semiconductor is as small as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0123] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0124] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0125] [Metal oxide composition 4] The metal oxide preferably contains indium, zinc, and oxygen. The metal oxide may further contain an element M. FIG. 2B shows a composition of a metal oxide that can be suitably used for a channel formation region of a transistor. The atomic ratio of indium, element M, and zinc in the metal oxide is preferably included in range 17 in the triangular diagram shown in FIG. 2B. Range 17 is within a polygon that connects coordinate point I (44:11:10), coordinate point L (4:1:4), coordinate point M (1:0:1), coordinate point K (11:0:2), and the coordinate point I in this order with straight lines. Note that range 17 includes each coordinate point and each side. By using a metal oxide having a composition included in range 17 for a channel formation region, a transistor with high reliability and high field effect mobility can be obtained.

[0126] Here, coordinate point L (4:1:4) is the intersection of line L10 and line L12, which is a set of points that satisfy In:Zn=1:1. Coordinate point M (1:0:1) is the intersection of line L12 and line L8. The above description can be referred to for coordinate points I and K, so detailed description will be omitted.

[0127] Side IL is on the aforementioned line L10, side LM is on the aforementioned line L12, side MK is on the aforementioned line L8, and side KI is on the aforementioned line L11. In other words, it can be said that range 17 is inside the polygon surrounded by lines L10, L12, L8, and L11.

[0128] As shown in range 17, the composition of the metal oxide preferably satisfies line L10 of In:M=4:1 or has a higher In content than In:M=4:1. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 4 or more. By using a metal oxide having an atomic ratio in the above-mentioned range for the channel formation region, it is possible to suppress the generation of defect levels and provide a transistor with high reliability and high field-effect mobility.

[0129] As shown in range 17, the composition of the metal oxide preferably satisfies line L12 of In:Zn=1:1, or has a higher indium content than In:Zn=1:1. In other words, the ratio of the number of indium atoms to the number of zinc atoms, In / Zn, is preferably 1 or more. By setting the atomic ratio within the above range, the metal oxide can be prevented from becoming polycrystalline. Since the metal oxide is less likely to become polycrystalline, the margin of the formation conditions of the metal oxide can be expanded. Furthermore, by using the metal oxide in the channel formation region, a highly reliable transistor can be obtained.

[0130] As shown in range 17, the composition of the metal oxide preferably satisfies line L11 (In+M):Zn=11:2, or has a zinc content higher than (In+M):Zn=11:2. In other words, the ratio (In+M) / Zn of the total number of atoms of indium and element M to the number of zinc atoms is preferably 11 / 2 or less. Metal oxides having an atomic number within the aforementioned range have high crystallinity. Furthermore, by using the metal oxide in the channel formation region, a highly reliable transistor can be obtained.

[0131] As the metal oxide, an In-M-Zn oxide having a composition included in range 17 can be used. As the In-M-Zn oxide, for example, In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10, or a composition close to these can be suitably used. In-Zn oxide can also be used as the metal oxide. As the In-Zn oxide, for example, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, or a combination close to these can be suitably used.

[0132] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0133] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0134] (Embodiment 2) In this embodiment, a configuration example of a semiconductor device to which the metal oxide described in Embodiment 1 is applied will be described. In this embodiment, a transistor using a metal oxide for a semiconductor layer in which a channel is formed will be described as an example of a semiconductor device. In the following, a transistor will be described as an example.

[0135] <Configuration example 1> [Configuration Example 1-1] FIG. 6A shows a schematic cross-sectional view of transistor 10 in the channel length direction.

[0136] The transistor 10 includes an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, and a conductive layer 112. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode.

[0137] A conductive film containing a metal or an alloy is preferably used for the conductive layer 112 because the electric resistance can be low. Note that a conductive film containing an oxide may be used for the conductive layer 112.

[0138] The metal oxide layer 114 has a function of supplying oxygen to the insulating layer 110. When a conductive film containing a metal or alloy that is easily oxidized is used as the conductive layer 112, the metal oxide layer 114 can also function as a barrier layer that prevents the conductive layer 112 from being oxidized by oxygen in the insulating layer 110. Note that the metal oxide layer 114 may be removed before the conductive layer 112 is formed, so that the conductive layer 112 and the insulating layer 110 are in contact with each other.

[0139] The insulating layer 103 is preferably formed using an insulating film containing an oxide. In particular, it is preferable to use an oxide film for a portion in contact with the semiconductor layer .

[0140] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) exhibiting semiconductor characteristics. For the semiconductor layer 108, a metal oxide having the composition described in Embodiment 1 is preferably used. By using the metal oxide for a channel formation region, a transistor with high reliability and high field-effect mobility can be obtained.

[0141] A region of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel formation region. The semiconductor layer 108 preferably has a pair of low-resistance regions 108n sandwiching the channel formation region. The low-resistance regions 108n have a higher carrier concentration than the channel formation region and function as a source region and a drain region.

[0142] The low-resistance region 108n can also be referred to as a region having a lower resistance than the channel formation region, a region having a high carrier concentration, a region having a large amount of oxygen vacancies, a region having a high hydrogen concentration, or a region having a high impurity concentration.

[0143] The insulating layer 110 has a layered structure in which an insulating film 110a, an insulating film 110b, and an insulating film 110c are stacked in this order from the insulating layer 103 side. The insulating film 110a has a region in contact with a channel formation region of the semiconductor layer 108. The insulating film 110c has a region in contact with the metal oxide layer 114. The insulating film 110b is located between the insulating films 110a and 110c.

[0144] Each of the insulating films 110a, 110b, and 110c is preferably an insulating film containing an oxide. In this case, the insulating films 110a, 110b, and 110c are preferably formed successively in the same film formation apparatus.

[0145] For example, the insulating film 110a, the insulating film 110b, and the insulating film 110c can be an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.

[0146] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a stacked structure of oxide insulating films and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 has an insulating film that can release oxygen. For example, oxygen can be supplied to the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like in an oxygen atmosphere on the insulating layer 110 after the film formation, or forming an oxide film on the insulating layer 110 in an oxygen atmosphere.

[0147] For example, the insulating films 110a, 110b, and 110c can be formed by using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. Examples of the CVD method include a plasma enhanced chemical vapor deposition (PECVD) method, a thermal CVD method, etc.

[0148] In particular, it is preferable that the insulating films 110a, 110b, and 110c are formed by the plasma CVD method.

[0149] Since the insulating film 110a is formed over the semiconductor layer 108, it is preferable that the insulating film 110a be formed under conditions that minimize damage to the semiconductor layer 108. For example, the insulating film 110a can be formed under conditions where the film formation rate (also referred to as the film formation rate) is sufficiently low.

[0150] For example, when a silicon oxynitride film is formed as the insulating film 110a by a plasma CVD method, damage to the semiconductor layer 108 can be made extremely small by forming the film under low power conditions.

[0151] The deposition gas used to deposit the silicon oxynitride film may be a source gas containing a deposition gas containing silicon, such as silane or disilane, and an oxidizing gas, such as oxygen, ozone, nitrous oxide, or nitrogen dioxide, etc. In addition to the source gas, a dilution gas, such as argon, helium, or nitrogen, may be included.

[0152] For example, by reducing the ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter simply referred to as the flow rate ratio), the film-forming rate can be reduced, and a dense film with few defects can be formed.

[0153] The insulating film 110b is preferably formed under conditions that provide a faster film formation rate than the insulating film 110a, which can improve productivity.

[0154] For example, the insulating film 110b can be formed under conditions in which the flow rate ratio of the deposition gas is made higher than that of the insulating film 110a, thereby enabling the insulating film 110b to be formed under conditions in which the film formation rate is increased.

[0155] The insulating film 110c is preferably an extremely dense film with reduced surface defects and low adsorption of impurities such as water contained in the air. For example, like the insulating film 110a, the insulating film 110c can be formed under conditions where the film formation rate is sufficiently low.

[0156] Since the insulating film 110c is formed over the insulating film 110b, the insulating film 110c has a smaller effect on the semiconductor layer 108 during its formation than the insulating film 110a. Therefore, the insulating film 110c can be formed under higher power conditions than the insulating film 110a. By reducing the flow rate ratio of the deposition gas and forming the insulating film at relatively high power, a dense film with reduced surface defects can be obtained.

[0157] That is, a stacked film formed under conditions in which the insulating film 110b, the insulating film 110a, and the insulating film 110c have the highest film formation rate can be used for the insulating layer 110. Moreover, in the insulating layer 110, the etching rates of the insulating film 110b, the insulating film 110a, and the insulating film 110c are highest in this order under the same wet etching or dry etching conditions.

[0158] The insulating film 110b is preferably formed thicker than the insulating films 110a and 110c. By forming the insulating film 110b, which has the fastest film formation speed, thick, the time required for the film formation process of the insulating layer 110 can be shortened.

[0159] Here, since the boundary between the insulating films 110a and 110b and the boundary between the insulating films 110b and 110c may be unclear, these boundaries are indicated by dashed lines in Fig. 6A etc. Note that since the insulating films 110a and 110b have different film densities, these boundaries may be observed as differences in contrast in a transmission electron microscope (TEM) image of a cross section of the insulating layer 110. Similarly, the boundary between the insulating films 110b and 110c may also be observed as differences in contrast.

[0160] It is preferable to use a metal oxide film having crystallinity for the semiconductor layer 108. For example, a metal oxide film having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a microcrystalline (nc) structure, or the like, which will be described later, can be used. By using a metal oxide film having crystallinity for the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0161] The higher the crystallinity of the semiconductor layer 108, the more the density of defect states in the film can be reduced. On the other hand, by using a metal oxide film with low crystallinity, a transistor capable of passing a large current can be realized.

[0162] The crystallinity of the semiconductor layer 108 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), electron diffraction (ED), or the like.

[0163] When a metal oxide film is formed by a sputtering method, the higher the substrate temperature (stage temperature) during film formation, the higher the crystallinity of the metal oxide film that can be formed. Also, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during film formation (also called the oxygen flow rate ratio), the higher the crystallinity of the metal oxide film that can be formed.

[0164] [Configuration Example 1-2] 6B is a schematic cross-sectional view of a transistor 10A. The transistor 10A is different from the transistor 10 described above mainly in that the configuration of the semiconductor layer 108 is different.

[0165] The semiconductor layer 108 included in the transistor 10A has a stacked structure in which a semiconductor layer 108a and a semiconductor layer 108b are stacked from the insulating layer 103 side. The semiconductor layer 108a and the semiconductor layer 108b are preferably formed using the metal oxide film described in Embodiment 1. Alternatively, at least one of the semiconductor layer 108a and the semiconductor layer 108b is preferably formed using the metal oxide film described in Embodiment 1.

[0166] For simplicity, the low-resistance region of the semiconductor layer 108a and the low-resistance region of the semiconductor layer 108b are collectively referred to as the low-resistance region 108n and are shown with the same hatching pattern. In reality, the compositions of the semiconductor layer 108a and the semiconductor layer 108b are different, so that the electrical resistivity, carrier concentration, amount of oxygen vacancy, hydrogen concentration, impurity concentration, and the like of the low-resistance region 108n may differ.

[0167] The semiconductor layer 108b is in contact with the top surface of the semiconductor layer 108a and the bottom surface of the insulating film 110a. The metal oxide film that can be used for the semiconductor layer 108 described in Embodiment 1 can be used for the semiconductor layer 108b.

[0168] On the other hand, the semiconductor layer 108a can be made of a metal oxide film having a higher atomic ratio of element M than the semiconductor layer 108b.

[0169] Since the element M has a stronger bond with oxygen than indium, oxygen vacancies are less likely to be formed by using a metal oxide film with a high atomic ratio of the element M for the semiconductor layer 108a. The presence of many oxygen vacancies in the semiconductor layer 108a leads to deterioration in the electrical characteristics and reliability of the transistor. Therefore, by using a metal oxide film with a higher atomic ratio of the element M than the semiconductor layer 108b for the semiconductor layer 108a, a transistor 10A with good electrical characteristics and high reliability can be realized.

[0170] It is preferable to use a metal oxide film having a region in which the atomic ratio of zinc is equal to that of the semiconductor layer 108b or a region in which the atomic ratio of zinc is lower than that of the semiconductor layer 108b as the semiconductor layer 108a. By using a metal oxide film in which oxygen vacancies are unlikely to occur as the semiconductor layer 108a, deterioration in the NBTIS test can be reduced.

[0171] 6B, a metal oxide film having a relatively high content of element M is used for the semiconductor layer 108a located on the insulating layer 103 side, thereby reducing oxygen vacancies in the semiconductor layer 108. Furthermore, a metal oxide film having a low content of element M or no element M is used for the semiconductor layer 108b located on the insulating layer 110 side, thereby reducing the density of defects at the interface between the semiconductor layer 108 and the insulating layer 110, thereby providing a transistor having both extremely high electrical characteristics and extremely high reliability.

[0172] Here, it is preferable to form the semiconductor layer 108b thinner than the semiconductor layer 108a. Even if the semiconductor layer 108b is an extremely thin film, for example, 0.5 nm to 10 nm, the density of defects at the interface with the insulating layer 110 can be reduced. On the other hand, by making the semiconductor layer 108a, which is less likely to have oxygen vacancies, relatively thick, a transistor with higher reliability can be realized.

[0173] For example, the thickness of the semiconductor layer 108a is preferably 1.5 to 20 times the thickness of the semiconductor layer 108b, more preferably 2 to 15 times, and even more preferably 3 to 10 times. The thickness of the semiconductor layer 108b is preferably 0.5 to 30 nm, more preferably 1 to 20 nm, and even more preferably 2 to 10 nm.

[0174] The semiconductor layer 108a and the semiconductor layer 108b are preferably formed using a metal oxide film having the above-mentioned crystallinity. Both the semiconductor layer 108a and the semiconductor layer 108b may be formed using a metal oxide film having high crystallinity or a metal oxide film having low crystallinity. Alternatively, the semiconductor layer 108a and the semiconductor layer 108b may have different crystallinity. For example, the semiconductor layer 108a may be formed using a film having higher crystallinity than the semiconductor layer 108b, and the semiconductor layer 108b may be formed using a film having higher crystallinity than the semiconductor layer 108a. The crystallinity of the metal oxide film used for the semiconductor layer 108a and the semiconductor layer 108b can be determined based on the required electrical characteristics and reliability of the transistor and the specifications of a film formation apparatus and the like.

[0175] [Configuration Example 1-3] 7A is a schematic cross-sectional view of a transistor 10B. The transistor 10B is different from the transistor 10 described above mainly in that the insulating layer 103 has a different configuration and that the transistor 10B has a conductive layer 106.

[0176] The conductive layer 106 has a region overlapping with the semiconductor layer 108, the insulating layer 110, the metal oxide layer 114, and the conductive layer 112 with the insulating layer 103 interposed therebetween. The conductive layer 106 functions as a first gate electrode (also referred to as a backgate electrode). The insulating layer 103 functions as a first gate insulating layer. In this case, the conductive layer 112 functions as a second gate electrode, and the insulating layer 110 functions as a second gate insulating layer.

[0177] For example, the transistor 10B can increase the current that can flow in an on state by applying the same potential to the conductive layer 112 and the conductive layer 106. Alternatively, the transistor 10B can apply a potential to one of the conductive layer 112 and the conductive layer 106 for controlling the threshold voltage and apply a potential to the other for controlling the on and off state of the transistor 10B.

[0178] The insulating layer 103 has a layered structure in which an insulating film 103a, an insulating film 103b, an insulating film 103c, and an insulating film 103d are stacked from the conductive layer 106 side. The insulating film 103a is in contact with the conductive layer 106. The insulating film 103d is in contact with the semiconductor layer 108.

[0179] The insulating layer 103 functioning as the second gate insulating layer preferably satisfies one or more of the following requirements: high withstand voltage, low film stress, little release of hydrogen or water, few defects in the film, and suppression of diffusion of metal elements contained in the conductive layer 106, and most preferably satisfies all of these requirements.

[0180] Of the four insulating films included in the insulating layer 103, the insulating film 103a, the insulating film 103b, and the insulating film 103c located on the conductive layer 106 side are preferably insulating films containing nitrogen. On the other hand, the insulating film 103d in contact with the semiconductor layer 108 is preferably an insulating film containing oxygen. In addition, the four insulating films included in the insulating layer 103 are preferably formed in succession without exposure to air by using a plasma CVD apparatus.

[0181] For example, an insulating film containing nitrogen, such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a hafnium nitride film, can be used as the insulating film 103a, the insulating film 103b, and the insulating film 103c. In addition, an insulating film that can be used for the insulating layer 110 can be used as the insulating film 103c.

[0182] The insulating films 103a and 103c are preferably dense films that can prevent diffusion of impurities from below. The insulating film 103a is preferably a film that can block metal elements contained in the conductive layer 106, and the insulating film 103c is preferably a film that can block hydrogen and water contained in the insulating film 103b. Therefore, the insulating film 103a and the insulating film 103c can be insulating films formed at a lower deposition rate than the insulating film 103b.

[0183] On the other hand, the insulating film 103b is preferably an insulating film that is formed under conditions of low stress and high deposition rate. The insulating film 103b is preferably formed thicker than the insulating films 103a and 103c.

[0184] For example, even if the insulating films 103a, 103b, and 103c are each made of silicon nitride films formed by plasma CVD, the insulating film 103b has a lower film density than the other two insulating films. This can be observed as a difference in contrast in a transmission electron microscope image of the cross section of the insulating layer 103. Note that the boundaries between the insulating films 103a and 103b, and between the insulating films 103b and 103c may be unclear, and therefore are shown by dashed lines in FIG. 7A and other figures.

[0185] The insulating film 103d in contact with the semiconductor layer 108 is preferably a dense insulating film whose surface is less susceptible to adsorption of impurities such as water. In addition, it is preferable to use an insulating film with as few defects as possible and in which impurities such as water and hydrogen are reduced. For example, the insulating film 103d can be an insulating film similar to the insulating film 110c of the insulating layer 110.

[0186] Note that in the case where a metal film or an alloy film whose constituent elements are unlikely to diffuse into the insulating layer 103 is used as the conductive layer 106, a structure in which three insulating films, the insulating film 103b, the insulating film 103c, and the insulating film 103d, are stacked may be used without providing the insulating film 103a.

[0187] By using the insulating layer 103 having such a stacked structure, a highly reliable transistor can be realized.

[0188] [Configuration Example 1-4] 7B is a schematic cross-sectional view of a transistor 10C. The transistor 10C is an example in which the conductive layer 106 and the insulating layer 103 illustrated in the transistor 10B illustrated in the above-mentioned Configuration example 1-3 are applied to the transistor 10A illustrated in the above-mentioned Configuration example 1-2.

[0189] With such a structure, a transistor with favorable electrical characteristics and extremely high reliability can be realized.

[0190] <Configuration example 2> A more specific example of the configuration of a transistor will be described below.

[0191] [Configuration Example 2-1] 8A is a top view of the transistor 100, FIG. 8B corresponds to a cross-sectional view of the cut surface taken along dashed line A1-A2 in FIG. 8A, and FIG. 8C corresponds to a cross-sectional view of the cut surface taken along dashed line B1-B2 in FIG. 8A. Note that in FIG. 8A, some of the components of the transistor 100 (such as a gate insulating layer) are omitted. The dashed line A1-A2 direction corresponds to the channel length direction, and the dashed line B1-B2 direction corresponds to the channel width direction. Note that, as in FIG. 8A, the top views of the transistors in the following drawings are also illustrated with some of the components omitted.

[0192] The transistor 100 is provided over a substrate 102 and includes an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 118, and the like. The island-shaped semiconductor layer 108 is provided over the insulating layer 103. The insulating layer 110 is provided in contact with an upper surface of the insulating layer 103 and an upper surface and side surfaces of the semiconductor layer 108. The metal oxide layer 114 and the conductive layer 112 are stacked in this order over the insulating layer 110 and have a portion overlapping with the semiconductor layer 108. The insulating layer 118 is provided to cover an upper surface of the insulating layer 110, a side surface of the metal oxide layer 114, and an upper surface of the conductive layer 112.

[0193] The insulating layer 103 has a multilayer structure in which an insulating film 103a, an insulating film 103b, an insulating film 103c, and an insulating film 103d are stacked from the substrate 102 side. The insulating layer 110 has a multilayer structure in which an insulating film 110a, an insulating film 110b, and an insulating film 110c are stacked from the semiconductor layer 108 side.

[0194] 8A and 8B, the transistor 100 may include a conductive layer 120a and a conductive layer 120b over an insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode and a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the low-resistance region 108n through an opening 141a and an opening 141b provided in the insulating layer 118 and the insulating layer 110, respectively.

[0195] Part of the conductive layer 112 functions as a gate electrode. Part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer .

[0196] The conductive layer 112 and the metal oxide layer 114 are processed so that their top surface shapes roughly match each other.

[0197] In this specification, the phrase "top surface shapes roughly match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, and in this case, it is also called "top surface shapes roughly match."

[0198] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing toward the conductive layer 112. The metal oxide layer 114 also functions as a barrier film that prevents hydrogen and water contained in the conductive layer 112 from diffusing toward the insulating layer 110. The metal oxide layer 114 is preferably made of a material that is less permeable to oxygen and hydrogen than the insulating layer 110, for example.

[0199] The metal oxide layer 114 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112, even when the conductive layer 112 is made of a metal material that easily absorbs oxygen, such as aluminum or copper. Even when the conductive layer 112 contains hydrogen, the metal oxide layer 114 can prevent hydrogen from diffusing from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0200] An insulating material or a conductive material can be used for the metal oxide layer 114. When the metal oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductive properties, it functions as a part of the gate electrode.

[0201] It is preferable to use an insulating material having a higher dielectric constant than silicon oxide as the metal oxide layer 114. In particular, it is preferable to use an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like, because the driving voltage can be reduced.

[0202] A conductive oxide such as indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can also be used as the metal oxide layer 114. In particular, a conductive oxide containing indium is preferable because of its high conductivity.

[0203] For the metal oxide layer 114, it is preferable to use an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be applied to the semiconductor layer 108. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as that of the semiconductor layer 108 for the metal oxide layer 114, because this allows the use of a common device.

[0204] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.

[0205] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions 108n sandwiching the region. The region of the semiconductor layer 108 overlapping with the conductive layer 112 functions as a channel formation region of the transistor 100. On the other hand, the low-resistance region 108n functions as a source region or drain region of the transistor 100.

[0206] The low-resistance region 108n can also be referred to as a region having a lower resistance than the channel formation region, a region with a high carrier concentration, a region with a high density of oxygen defects, a region with a high impurity concentration, or an n-type region.

[0207] The low-resistance region 108n of the semiconductor layer 108 is a region containing an impurity element. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and rare gases. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable that the low-resistance region 108n contains boron or phosphorus. Two or more of these elements may be contained.

[0208] As described later, the process of adding impurities to the low-resistance region 108n can be performed through the insulating layer 110 by using the conductive layer 112 as a mask.

[0209] The low resistance region 108n has an impurity concentration of 1×10 19 atoms / cm 3 More than 1×10 23 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 5×10 or more 22 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 More than 1×10 22 atoms / cm 3 It is preferred to include a region in which:

[0210] The concentration of impurities contained in the low-resistance region 108n can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), etc. When using XPS analysis, the concentration distribution in the depth direction can be known by combining ion sputtering from the front side or rear side with XPS analysis.

[0211] In the low-resistance region 108n, the impurity element is preferably present in an oxidized state. For example, it is preferable to use an element that is easily oxidized, such as boron, phosphorus, magnesium, aluminum, or silicon, as the impurity element. Since such an element that is easily oxidized can be stably present in an oxidized state by bonding with oxygen in the semiconductor layer 108, even if a high temperature (for example, 400° C. or higher, 600° C. or higher, or 800° C. or higher) is applied in a later process, the element is prevented from being desorbed. Furthermore, the impurity element removes oxygen from the semiconductor layer 108, so that many oxygen vacancies are generated in the low-resistance region 108n. The oxygen vacancies are bonded with hydrogen in the film to become a carrier supply source, so that the low-resistance region 108n has an extremely low resistance state.

[0212] For example, when boron is used as an impurity element, the boron contained in the low-resistance region 108n may exist in a state of being bonded to oxygen. This can be confirmed by observing a spectrum peak due to the B2O3 bond in an XPS analysis. In addition, in an XPS analysis, a spectrum peak due to the state in which the boron element exists alone is not observed, or the peak intensity is so small that it is buried in background noise observed near the lower limit of measurement.

[0213] The insulating layer 110 has a region in contact with a channel formation region of the semiconductor layer 108, that is, a region overlapping with the conductive layer 112. The insulating layer 110 also has a region in contact with a low-resistance region 108n of the semiconductor layer 108 and not overlapping with the conductive layer 112.

[0214] The region of the insulating layer 110 overlapping with the low-resistance region 108n may contain the above-mentioned impurity element. In this case, like the low-resistance region 108n, the impurity element in the insulating layer 110 is preferably present in a state of being bonded to oxygen. Since such an element that is easily oxidized can be stably present in an oxidized state by bonding with oxygen in the insulating layer 110, desorption is suppressed even when a high temperature is applied in a later process. In particular, when the insulating layer 110 contains oxygen (also referred to as excess oxygen) that can be desorbed by heating, the excess oxygen and the impurity element are bonded to be stabilized, so that it is possible to suppress the supply of oxygen from the insulating layer 110 to the low-resistance region 108n. Furthermore, a part of the insulating layer 110 containing the oxidized impurity element is in a state where oxygen is difficult to diffuse, so that it is possible to suppress the supply of oxygen to the low-resistance region 108n from above the insulating layer 110 through the insulating layer 110, and it is also possible to prevent the resistance of the low-resistance region 108n from increasing.

[0215] The insulating layer 118 functions as a protective layer for protecting the transistor 100. For example, an inorganic insulating material such as an oxide or a nitride can be used as the insulating layer 110. More specifically, an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, or hafnium aluminate can be used.

[0216] [Configuration Example 2-2] 9A is a top view of the transistor 100A, FIG. 9B is a cross-sectional view of the transistor 100A in the channel length direction, and FIG. 9C is a cross-sectional view of the transistor 100A in the channel width direction.

[0217] The transistor 100A differs from the transistor in structural example 2-1 mainly in that a conductive layer 106 is provided between the substrate 102 and the insulating layer 103. The conductive layer 106 has a region overlapping with the semiconductor layer 108 and the conductive layer 112.

[0218] In the transistor 100A, the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode), and the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode). Part of the insulating layer 110 functions as a second gate insulating layer, and part of the insulating layer 103 functions as a first gate insulating layer.

[0219] A portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that for ease of explanation, the portion of the semiconductor layer 108 that overlaps with the conductive layer 112 may be referred to as a channel formation region hereinafter; however, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 112 and overlaps with the conductive layer 106 (a portion including the low-resistance region 108n).

[0220] 9C, the conductive layer 106 may be electrically connected to the conductive layer 112 through the metal oxide layer 114, the insulating layer 110, and the opening 142 provided in the insulating layer 103. This allows the conductive layer 106 and the conductive layer 112 to be given the same potential.

[0221] The conductive layer 106 can be formed using a material similar to that of the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, it is preferable to use a material containing copper for the conductive layer 106 because wiring resistance can be reduced.

[0222] 9A and 9C, in the channel width direction, the conductive layer 112 and the conductive layer 106 preferably protrude outward beyond the end portion of the semiconductor layer 108. In this case, as shown in FIG 9C, the entire semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 via the insulating layer 110 and the insulating layer 103.

[0223] With such a structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. In particular, it is preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. This makes it possible to effectively apply an electric field for inducing a channel in the semiconductor layer 108, thereby increasing the on-state current of the transistor 100A. This also enables miniaturization of the transistor 100A.

[0224] Note that the conductive layer 112 and the conductive layer 106 may not be connected to each other. In this case, a constant potential may be applied to one of a pair of gate electrodes, and a signal for driving the transistor 100A may be applied to the other of the pair of gate electrodes. In this case, the threshold voltage when the transistor 100A is driven by the other gate electrode can also be controlled by the potential applied to one gate electrode.

[0225] [Configuration Example 2-3] 10A is a top view of the transistor 100B, FIG. 10B is a cross-sectional view of the transistor 100B in the channel length direction, and FIG. 10C is a cross-sectional view of the transistor 100B in the channel width direction.

[0226] The transistor 100B differs from the transistor 100 illustrated in Structural example 2-1 mainly in that the insulating layer 110 has a different configuration and that an insulating layer 116 is included.

[0227] The insulating layer 110 is processed so that its top surface shape generally matches those of the conductive layer 112 and the metal oxide layer 114. The insulating layer 110 can be formed by processing using a resist mask for processing the conductive layer 112 and the metal oxide layer 114, for example.

[0228] The insulating layer 116 is provided in contact with the top surface and side surfaces of the semiconductor layer 108 that are not covered with the conductive layer 112, the metal oxide layer 114, and the insulating layer 110. The insulating layer 116 is provided to cover the top surface of the insulating layer 103, the side surfaces of the insulating layer 110, the side surfaces of the metal oxide layer 114, and the top surface and side surfaces of the conductive layer 112.

[0229] The insulating layer 116 has a function of lowering the resistance of the low-resistance region 108n. As the insulating layer 116, an insulating film that can supply impurities to the low-resistance region 108n by heating during or after the formation of the insulating layer 116 can be used. Alternatively, an insulating film that can cause oxygen vacancies in the low-resistance region 108n by heating during or after the formation of the insulating layer 116 can be used.

[0230] For example, an insulating film that functions as a supply source for supplying impurities to the low-resistance region 108n can be used as the insulating layer 116. In this case, the insulating layer 116 is preferably a film that releases hydrogen by heating. By forming such an insulating layer 116 in contact with the semiconductor layer 108, impurities such as hydrogen can be supplied to the low-resistance region 108n, and the resistance of the low-resistance region 108n can be reduced.

[0231] The insulating layer 116 is preferably a film formed using a gas containing an impurity element such as hydrogen as a deposition gas. By lowering the substrate temperature of the insulating layer 116, a large amount of impurity elements can be effectively supplied to the semiconductor layer 108. The substrate temperature of the insulating layer 116 is preferably, for example, from 200° C. to 500° C., more preferably from 220° C. to 450° C., further preferably from 230° C. to 430° C., and further preferably from 250° C. to 400° C.

[0232] Deposition of the insulating layer 116 under reduced pressure and by heating can promote desorption of oxygen from the regions that will become the low-resistance regions 108n in the semiconductor layer 108. Supplying impurities such as hydrogen to the semiconductor layer 108 in which many oxygen vacancies are formed increases the carrier density in the low-resistance regions 108n, and the resistance of the low-resistance regions 108n can be more effectively reduced.

[0233] For example, an insulating film containing a nitride, such as silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, or aluminum nitride oxide, can be suitably used as the insulating layer 116. In particular, silicon nitride has a blocking property against hydrogen and oxygen, and can therefore prevent both diffusion of hydrogen from the outside to the semiconductor layer and elimination of oxygen from the semiconductor layer to the outside, thereby realizing a highly reliable transistor.

[0234] The insulating layer 116 may be an insulating film having a function of absorbing oxygen in the semiconductor layer 108 and generating oxygen vacancies. In particular, the insulating layer 116 is preferably formed using a metal nitride such as aluminum nitride.

[0235] When using a metal nitride, it is preferable to use a nitride of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is particularly preferable to include aluminum or titanium. For example, an aluminum nitride film formed by a reactive sputtering method using aluminum as a sputtering target and a gas containing nitrogen as a deposition gas can be made into a film having extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of the deposition gas. Therefore, by providing an insulating film containing such a metal nitride in contact with a semiconductor layer, not only can the resistance of the semiconductor layer be reduced, but also oxygen can be suitably prevented from being released from the semiconductor layer and hydrogen can be suitably prevented from diffusing into the semiconductor layer.

[0236] When aluminum nitride is used as the metal nitride, the thickness of the insulating layer containing the aluminum nitride is preferably 5 nm or more. Even with such a thin film, it is possible to achieve both high blocking properties against hydrogen and oxygen and a function of reducing the resistance of the semiconductor layer. The thickness of the insulating layer may be as thick as desired, but in consideration of productivity, it is preferable to set the thickness to 500 nm or less, preferably 200 nm or less, and more preferably 50 nm or less.

[0237] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlNx (x is a real number greater than 0 and equal to or less than 2, preferably, x is a real number greater than 0.5 and equal to or less than 1.5) is preferably used. This allows the film to have excellent insulating properties and excellent thermal conductivity, thereby improving the dissipation of heat generated when the transistor 100B is driven.

[0238] Alternatively, the insulating layer 116 can be an aluminum titanium nitride film, a titanium nitride film, or the like.

[0239] By providing such an insulating layer 116 in contact with the low-resistance region 108n, the insulating layer 116 can absorb oxygen in the low-resistance region 108n and form oxygen vacancies in the low-resistance region 108n. In addition, by performing heat treatment after forming such an insulating layer 116, a large number of oxygen vacancies can be formed in the low-resistance region 108n, and the resistance can be reduced. In addition, when a film containing a metal oxide is used for the insulating layer 116, the insulating layer 116 may absorb oxygen in the semiconductor layer 108, and as a result, a layer containing an oxide of a metal element (e.g., aluminum) contained in the insulating layer 116 may be formed between the insulating layer 116 and the low-resistance region 108n.

[0240] Here, when a metal oxide film containing indium is used as the semiconductor layer 108, a region where indium oxide is precipitated or a region with a high indium concentration may be formed near the interface of the low-resistance region 108n on the insulating layer 116 side. This allows the low-resistance region 108n to have an extremely low resistance. The presence of such a region may be observed by an analysis method such as X-ray photoelectron spectroscopy (XPS).

[0241] [Configuration Example 2-4] 11A is a top view of the transistor 100C, FIG. 11B is a cross-sectional view of the transistor 100C in the channel length direction, and FIG. 11C is a cross-sectional view of the transistor 100C in the channel width direction.

[0242] The transistor 100C is an example of the transistor 100B in Structural Example 2-3, which is provided with the conductive layer 106 functioning as a second gate electrode in Structural Example 2-2.

[0243] With such a structure, a transistor with high on-state current can be obtained, or a transistor whose threshold voltage can be controlled can be obtained.

[0244] <Modification 1 of Configuration Example 2> Although the semiconductor layer 108 is a single layer in the above-described Structure Examples 2-1 to 2-4, it is preferable that the semiconductor layer 108 have a stacked structure in which the semiconductor layer 108a and the semiconductor layer 108b are stacked.

[0245] A transistor 100_a shown in Fig. 12A is an example in which the semiconductor layer 108 of the transistor 100 illustrated in Configuration example 2-1 has a stacked structure. In Fig. 12A, a cross section in the channel length direction is shown to the left of the dashed dotted line, and a cross section in the channel width direction is shown to the right of the dashed dotted line.

[0246] Similarly, a transistor 100A_a shown in FIG. 12B, a transistor 100B_a shown in FIG. 12C, and a transistor 100C_a shown in FIG. 12D are examples of the transistor 100A, the transistor 100B, and the transistor 100C, respectively, in which the semiconductor layer 108 has a stacked structure.

[0247] <Modification 2 of Configuration Example 2> As mentioned above, the metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 may be removed after supplying oxygen to the insulating layer 110 .

[0248] A transistor 100_b illustrated in FIG. 13A is an example of the transistor 100_a illustrated in FIG. 12A from which the metal oxide layer 114 has been removed.

[0249] Similarly, a transistor 100A_b shown in FIG. 13B, a transistor 100B_b shown in FIG. 13C, and a transistor 100C_b shown in FIG. 13D are examples of the transistor 100A_a, the transistor 100B_a, and the transistor 100C_a, respectively, from which the metal oxide layer 114 has been removed.

[0250] <Production method example 1> An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below, taking the transistor 100A described in Structure Example 2-2 as an example.

[0251] The thin films (insulating film, semiconductor film, conductive film, etc.) constituting the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. Examples of CVD include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD is metal organic chemical vapor deposition (MOCVD).

[0252] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0253] When processing the thin film constituting the semiconductor device, it can be processed using a photolithography method or the like. In addition, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method, or the like. Also, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0254] There are two typical photolithography methods. One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape.

[0255] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0256] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0257] 14 to 16 show cross sections of the transistor 100A in the channel length direction and the channel width direction at each stage of a manufacturing process.

[0258] [Formation of Conductive Layer 106] A conductive film is formed on a substrate 102 and processed by etching to form a conductive layer 106 that functions as a gate electrode (FIG. 14A).

[0259] At this time, it is preferable to process the conductive layer 106 so that the end portion thereof has a tapered shape, as shown in Fig. 14A. This can improve the step coverage of the insulating layer 103 to be formed next.

[0260] By using a conductive film containing copper as the conductive layer 106, wiring resistance can be reduced. For example, when the conductive film is applied to a large display device or a display device with high resolution, it is preferable to use a conductive film containing copper. Even when a conductive film containing copper is used for the conductive layer 106, the insulating layer 103 prevents copper from diffusing toward the semiconductor layer 108, so that a highly reliable transistor can be realized.

[0261] [Formation of insulating layer 103] Subsequently, the insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 14B). The insulating layer 103 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0262] Here, the insulating layer 103 is formed by stacking an insulating film 103a, an insulating film 103b, an insulating film 103c, and an insulating film 103d.

[0263] In particular, it is preferable to form the insulating films constituting the insulating layer 103 by the PECVD method. The method for forming the insulating layer 103 can be the same as that described in the above configuration example 1.

[0264] After the insulating layer 103 is formed, a treatment for supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere may be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by a plasma ion doping method or an ion implantation method.

[0265] [Formation of Semiconductor Layer 108] Next, a metal oxide film 108f is formed on the insulating layer 103 (FIG. 14C).

[0266] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.

[0267] The metal oxide film 108f is preferably a dense film with as few defects as possible. The metal oxide film 108f is preferably a high-purity film in which impurities such as hydrogen and water are reduced as much as possible. In particular, it is preferable to use a metal oxide film having crystallinity as the metal oxide film 108f.

[0268] When forming the metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). The higher the oxygen flow ratio, the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-current can be obtained.

[0269] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and the denser the metal oxide film can be formed, whereas the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film can be formed.

[0270] The deposition conditions for the metal oxide film are a substrate temperature of room temperature or higher and 250° C. or lower, preferably room temperature or higher and 200° C. or lower, and more preferably room temperature or higher and 140° C. or lower. For example, a substrate temperature of room temperature or higher and lower than 140° C. is preferable because it increases productivity. In addition, by depositing a metal oxide film at room temperature or without intentionally heating the substrate, the crystallinity can be reduced.

[0271] Before forming the metal oxide film 108f, it is preferable to perform one or more of a treatment for removing water, hydrogen, organic components, and the like adsorbed on the surface of the insulating layer 103, and a treatment for supplying oxygen into the insulating layer 103. For example, a heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, a plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, oxygen can be supplied to the insulating layer 103 by a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). When a plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while organic substances on the surface of the insulating layer 103 are suitably removed. After such a treatment, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 103 to the air.

[0272] In addition, in the case where the semiconductor layer 108 has a stacked structure in which a plurality of semiconductor layers are stacked, it is preferable to form a metal oxide film first and then form a next metal oxide film in succession without exposing the surface of the first metal oxide film to the air.

[0273] Then, a part of the metal oxide film 108f is etched to form an island-shaped semiconductor layer 108 (FIG. 14D).

[0274] The metal oxide film 108f may be processed by wet etching or dry etching, or both. When the metal oxide film 108f is processed, a part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be etched and thinned. For example, the insulating film 103d of the insulating layer 103 may be removed by etching, and the surface of the insulating film 103c may be exposed.

[0275] Here, heat treatment is preferably performed after the metal oxide film 108f is formed or after processing into the semiconductor layer 108. The heat treatment can remove hydrogen or water contained in or adsorbed on the surface of the metal oxide film 108f or the semiconductor layer 108. The heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (for example, reduce defects, improve crystallinity, etc.).

[0276] The heat treatment can also supply oxygen from the insulating layer 103 to the metal oxide film 108f or the semiconductor layer 108. In this case, it is preferable to perform the heat treatment before processing into the semiconductor layer 108.

[0277] The temperature of the heat treatment can typically be 150° C. or higher and lower than the strain point of the substrate, or 200° C. or higher and 500° C. or lower, or 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower.

[0278] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, the heat treatment can be performed in the atmosphere containing oxygen after the heat treatment. Alternatively, the heat treatment can be performed in a dry air atmosphere. Note that it is preferable that the heat treatment atmosphere does not contain hydrogen, water, or the like as much as possible. The heat treatment can be performed using an electric furnace, an RTA (Rapid Thermal Anneal) device, or the like. The heat treatment time can be shortened by using an RTA device.

[0279] If the heat treatment is unnecessary, it is not necessary to perform it. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later step. Also, there are cases where the heat treatment may be combined with a high-temperature treatment in a later step (e.g., a film formation step, etc.).

[0280] [Formation of insulating layer 110] Subsequently, insulating layer 110 is formed to cover insulating layer 103 and semiconductor layer 108 (FIG. 14E).

[0281] Here, the insulating layer 110 is formed by stacking an insulating film 110a, an insulating film 110b, and an insulating film 110c.

[0282] In particular, it is preferable to form each of the insulating films constituting the insulating layer 110 by the PECVD method. The description of the above-mentioned configuration example 1 can be applied to the method of forming each of the layers constituting the insulating layer 110.

[0283] Before the insulating layer 110 is formed, it is preferable to perform plasma treatment on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced, and a highly reliable transistor can be realized. This is particularly preferable when the surface of the semiconductor layer 108 is exposed to the air during the period from the formation of the semiconductor layer 108 to the formation of the insulating layer 110. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. In addition, it is preferable to perform the plasma treatment and the formation of the insulating layer 110 in succession without exposure to the air.

[0284] Here, heat treatment is preferably performed after the insulating layer 110 is formed. Hydrogen or water contained in the insulating layer 110 or adsorbed to the surface of the insulating layer 110 can be removed by the heat treatment. In addition, defects in the insulating layer 110 can be reduced.

[0285] The heat treatment conditions may be as described above.

[0286] If the heat treatment is unnecessary, it is not necessary to perform it. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later step. Also, there are cases where the heat treatment may be combined with a high-temperature treatment in a later step (e.g., a film formation step, etc.).

[0287] [Formation of Metal Oxide Film 114f] Subsequently, a metal oxide film 114f is formed on the insulating layer 110 (FIG. 15A).

[0288] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. In this way, oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f.

[0289] When the metal oxide film 114f is formed by a sputtering method using an oxide target containing a metal oxide similar to that for the semiconductor layer 108, the above description can be used.

[0290] For example, the metal oxide film 114f may be formed by reactive sputtering using oxygen as a deposition gas and a metal target. When aluminum is used as the metal target, an aluminum oxide film can be formed.

[0291] During deposition of the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber is, the more oxygen can be supplied to the insulating layer 110. The oxygen flow rate ratio or oxygen partial pressure is, for example, preferably 50% or more and 100% or less, more preferably 65% ​​or more and 100% or less, further preferably 80% or more and 100% or less, and further preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and to set the oxygen partial pressure in the deposition chamber as close to 100% as possible.

[0292] In this manner, by forming the metal oxide film 114f by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f, and oxygen can be prevented from being released from the insulating layer 110. As a result, an extremely large amount of oxygen can be trapped in the insulating layer 110.

[0293] After the metal oxide film 114f is formed, heat treatment is preferably performed. By the heat treatment, oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108. By performing heating while the insulating layer 110 is covered with the metal oxide film 114f, oxygen is prevented from being released from the insulating layer 110 to the outside, and a large amount of oxygen can be supplied to the semiconductor layer 108. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0294] The heat treatment conditions may be as described above.

[0295] If the heat treatment is unnecessary, it is not necessary to perform it. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later step. Also, there are cases where the heat treatment may be combined with a high-temperature treatment in a later step (e.g., a film formation step, etc.).

[0296] After the metal oxide film 114f is formed or after the heat treatment, the metal oxide film 114f may be removed.

[0297] [Formation of opening 142] Next, the metal oxide film 114f, the insulating layer 110, and a part of the insulating layer 103 are etched to form an opening 142 that reaches the conductive layer 106 (FIG. 15B). This allows the conductive layer 106 and the conductive layer 112 to be formed later to be electrically connected to each other through the opening 142.

[0298] [Formation of Conductive Layer 112 and Metal Oxide Layer 114] Subsequently, a conductive film 112f which becomes the conductive layer 112 is formed on the metal oxide film 114f (FIG. 15C).

[0299] The conductive film 112f is preferably formed using a low-resistance metal or alloy material, a material that does not easily release hydrogen and from which hydrogen does not easily diffuse, and a material that does not easily oxidize.

[0300] For example, the conductive film 112f is preferably formed by a sputtering method using a sputtering target containing a metal or an alloy.

[0301] For example, the conductive film 112f is preferably a stacked film in which a conductive film which is resistant to oxidation and through which hydrogen does not easily diffuse and a conductive film with low resistance are stacked.

[0302] Then, the conductive film 112f and the metal oxide film 114f are partly etched to form the conductive layer 112 and the metal oxide layer 114. The conductive film 112f and the metal oxide film 114f are preferably processed using the same resist mask. Alternatively, the metal oxide film 114f may be etched using the etched conductive layer 112 as a hard mask.

[0303] It is particularly preferable to use a wet etching method for etching the conductive film 112f and the metal oxide film 114f.

[0304] This makes it possible to form the conductive layer 112 and the metal oxide layer 114 whose top surface shapes are roughly the same.

[0305] In this manner, by forming a structure in which the upper surface and side surfaces of the semiconductor layer 108 and the insulating layer 103 are covered without etching the insulating layer 110, it is possible to prevent a part of the semiconductor layer 108 or the insulating layer 103 from being etched and thinned when the conductive film 112f, etc. are etched.

[0306] [Supply of impurity elements] Next, a process of supplying (also referred to as adding or injecting) the impurity element 140 to the semiconductor layer 108 through the insulating layer 110 is performed using the conductive layer 112 as a mask ( FIG. 15D ). This makes it possible to form a low-resistance region 108n in a region of the semiconductor layer 108 that is not covered with the conductive layer 112. At this time, the conductive layer 112 serves as a mask in a region of the semiconductor layer 108 that overlaps with the conductive layer 112, and the impurity element 140 is not supplied thereto.

[0307] The impurity element 140 can be preferably supplied by a plasma ion doping method or an ion implantation method. These methods can control the concentration profile in the depth direction with high precision by the ion acceleration voltage, dose amount, etc. By using the plasma ion doping method, productivity can be improved. In addition, by using the ion implantation method using mass separation, the purity of the supplied impurity element can be increased.

[0308] In the supplying process of the impurity element 140, it is preferable to control the process conditions so that the concentration is highest at the interface between the semiconductor layer 108 and the insulating layer 110, or in a portion close to the interface in the semiconductor layer 108, or in a portion close to the interface in the insulating layer 110. This makes it possible to supply the impurity element 140 at an optimal concentration to both the semiconductor layer 108 and the insulating layer 110 in a single process.

[0309] Examples of the impurity element 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and rare gases. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon.

[0310] As the source gas of the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, typically, B2H6 gas or BF3 gas can be used. When supplying phosphorus, typically, PH3 gas can be used. Also, a mixed gas in which these source gases are diluted with a rare gas may be used.

[0311] Other examples of the source gas that can be used include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. The ion source is not limited to gas, and a solid or liquid that has been heated and vaporized may also be used.

[0312] The addition of the impurity element 140 can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 110 and the semiconductor layer .

[0313] For example, when boron is added by ion implantation or plasma ion doping, the acceleration voltage can be, for example, in the range of 5 kV to 100 kV, preferably 7 kV to 70 kV, and more preferably 10 kV to 50 kV. The dose can be, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than or equal to 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 Less than or equal to 1×10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 It can be in the following range:

[0314] When phosphorus ions are added by ion implantation or plasma ion doping, the acceleration voltage can be, for example, in the range of 10 kV to 100 kV, preferably 30 kV to 90 kV, and more preferably 40 kV to 80 kV. The dose can be, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than or equal to 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 Less than or equal to 1×10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 It can be in the following range:

[0315] The method of supplying the impurity element 140 is not limited to this, and may be, for example, a plasma treatment or a treatment using thermal diffusion by heating. In the case of the plasma treatment, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing the plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, or the like can be used.

[0316] In one embodiment of the present invention, the impurity element 140 can be supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystallinity, damage to the semiconductor layer 108 when the impurity element 140 is supplied can be reduced, and loss of crystallinity can be suppressed. Therefore, this is preferable in the case where electrical resistance increases due to a decrease in crystallinity.

[0317] [Formation of insulating layer 118] Subsequently, an insulating layer 118 is formed covering the insulating layer 110, the metal oxide layer 114, and the conductive layer 112 (FIG. 16A).

[0318] When the insulating layer 118 is formed by the plasma CVD method, if the substrate temperature is too high, impurities contained in the low-resistance region 108n and the like may diffuse to the peripheral portion including the channel formation region of the semiconductor layer 108, and the electrical resistance of the low-resistance region 108n may increase. Therefore, the substrate temperature during the formation of the insulating layer 118 may be determined taking these factors into consideration.

[0319] For example, the substrate temperature of the insulating layer 118 is preferably from 150° C. to 400° C., more preferably from 180° C. to 360° C., and further preferably from 200° C. to 250° C. By forming the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0320] After the insulating layer 118 is formed, heat treatment may be performed. The heat treatment may make the low-resistance region 108n more stably low-resistance. For example, the heat treatment may cause the impurity element 140 to diffuse appropriately and become locally uniform, forming the low-resistance region 108n having an ideal impurity element concentration gradient. Note that if the temperature of the heat treatment is too high (for example, 500° C. or higher), the impurity element 140 may diffuse into the channel formation region, which may cause deterioration in the electrical characteristics and reliability of the transistor.

[0321] The heat treatment conditions may be as described above.

[0322] If the heat treatment is unnecessary, it is not necessary to perform it. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later step. Also, if there is a high-temperature process (e.g., a film formation process) in a later step, the heat treatment may be combined with the heat treatment.

[0323] [Formation of Openings 141a and 141b] Next, the insulating layer 118 and the insulating layer 110 are partially etched to form the opening 141a and the opening 141b that reach the low-resistance region 108n.

[0324] [Formation of Conductive Layer 120a and Conductive Layer 120b] Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b, and the conductive film is processed into a desired shape to form the conductive layers 120a and 120b (FIG. 16B).

[0325] Through the above steps, the transistor 100A can be manufactured. For example, when the transistor 100A is used in a pixel of a display device, a subsequent step of forming one or more of a protective insulating layer, a planarization layer, a pixel electrode, and a wiring may be added.

[0326] This concludes the description of Preparation Method 1.

[0327] Note that when the transistor 100 illustrated in Configuration Example 2-1 is manufactured, the step of forming the conductive layer 106 and the step of forming the opening 142 in the above-described Manufacturing Method Example 1 may be omitted. The transistor 100 and the transistor 100A can be formed over the same substrate through the same steps.

[0328] <Production method example 2> The following describes an example in which some steps are different from those in Manufacturing Method Example 1. Here, the transistor 100C illustrated in Configuration Example 2-4 is taken as an example.

[0329] In the following, explanations of the parts that overlap with the above-mentioned Preparation Method Example 1 will be omitted, and differences will be explained in detail.

[0330] First, the conductive layer 106, the insulating layer 103, the semiconductor layer 108, the insulating layer 110, the metal oxide film 114f, and the conductive film 112f are formed in this order in a manner similar to that of Manufacturing Method Example 1. A cross-sectional view at this stage is shown in FIG.

[0331] Next, the conductive film 112f and the metal oxide film 114f are partially etched to form the conductive layer 112 and the metal oxide layer 114, and further, the insulating layer 110 is partially etched to expose a part of the semiconductor layer 108 (FIG. 17B). This makes it possible to form the conductive layer 112, the metal oxide layer 114, and the insulating layer 110, which have approximately the same top surface shape.

[0332] The insulating layer 110 is preferably etched using a resist mask for etching the conductive film 112f. The insulating layer 110 may be etched in the same step as the etching of the conductive film 112f and the metal oxide film 114f, or may be etched by a different etching method after the etching of the conductive film 112f and the metal oxide film 114f.

[0333] For example, the conductive film 112f and the metal oxide film 114f can be etched by a wet etching method using the same etchant, and then the insulating layer 110 can be etched by a dry etching method. In particular, when the conductive film 112f and the metal oxide film 114f are processed by a dry etching method, a reaction product containing metal is generated, which may contaminate the semiconductor layer 108 and the insulating layer 110. Therefore, it is preferable to process the conductive film 112f and the metal oxide film 114f by a wet etching method before etching the insulating layer 110.

[0334] Depending on the etching conditions, the ends of the conductive layer 112, the metal oxide layer 114, and the insulating layer 110 may not coincide with each other. For example, the end of at least one of the conductive layer 112 and the metal oxide layer 114 may be located inside or outside the end of the insulating layer 110.

[0335] When the insulating layer 110 is etched, a part of the exposed semiconductor layer 108 may be etched and thinned. At this time, the semiconductor layer 108 may have a shape in which the thickness of the low-resistance region 108n is thinner than the thickness of the channel formation region.

[0336] During etching of the insulating layer 110, a part of the insulating layer 103 that is not covered by the semiconductor layer 108 may be etched and thinned. For example, the insulating film 103d of the insulating layer 103 may disappear.

[0337] Next, an insulating layer 116 is formed in contact with the exposed portion of the semiconductor layer 108, followed by the formation of an insulating layer 118 (FIG. 17C). By forming the insulating layer 116, the exposed portion of the semiconductor layer 108 has a low resistance, and a low-resistance region 108n is formed.

[0338] As the insulating layer 116, an insulating film that releases an impurity element having a function of reducing the resistance of the semiconductor layer 108 can be used. In particular, it is preferable to use an inorganic insulating film such as a silicon nitride film, a silicon nitride oxide film, or a silicon oxynitride film that can release hydrogen. In this case, it is preferable to use a plasma CVD method using a deposition gas containing hydrogen, because hydrogen can be supplied to the semiconductor layer 108 even during the deposition of the insulating layer 116.

[0339] For example, when silicon nitride is used as the insulating layer 116, it is preferable to form the insulating layer 116 by a PECVD method using a mixed gas containing a silicon-containing gas such as silane and a nitrogen-containing gas such as ammonia or nitrous oxide as a deposition gas. At this time, it is preferable that the silicon nitride film to be formed contains hydrogen. This makes it easy to reduce the resistance of a part of the semiconductor layer 108 by diffusing hydrogen in the insulating layer 116 into the semiconductor layer 108.

[0340] The insulating layer 116 can also be an insulating film having a function of generating oxygen vacancies in the semiconductor layer 108. In particular, it is preferable to use an insulating film containing a metal nitride. For example, it is preferable to form the insulating layer 116 by a reactive sputtering method using a sputtering target containing a metal and a mixed gas of nitrogen gas and a rare gas or the like as a deposition gas. This makes it easy to control the film quality of the insulating layer 116 by controlling the flow rate ratio of the deposition gas.

[0341] For example, when an aluminum nitride film formed by reactive sputtering using an aluminum target is used as the insulating layer 116, the flow rate of nitrogen gas relative to the total flow rate of the film formation gas is preferably 30% or more and 100% or less, more preferably 40% or more and 100% or less, and even more preferably 50% or more and 100% or less.

[0342] Here, the insulating layers 116 and 118 are preferably formed in succession without exposure to the air.

[0343] Heat treatment may be performed after the insulating layer 116 or the insulating layer 118 is formed. The heat treatment can promote a decrease in resistance of the low-resistance region 108n.

[0344] The heat treatment conditions may be as described above.

[0345] If the heat treatment is unnecessary, it is not necessary to perform it. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later step. Also, there are cases where the heat treatment may be combined with a high-temperature treatment in a later step (e.g., a film formation step, etc.).

[0346] Next, openings 141a and 141b are formed in the insulating layers 118 and 116, respectively, so as to reach the low-resistance regions 108n.

[0347] Next, the conductive layer 120a and the conductive layer 120b are formed on the insulating layer 118 in the same manner as in Manufacturing Method Example 1 (FIG. 17D).

[0348] Through the above steps, the transistor 100C can be manufactured.

[0349] Note that when the transistor 100B illustrated in Structure Example 2-3 is manufactured, the steps of forming the conductive layer 106 and the opening 142 in the above-described Manufacturing Method Example 2 may be omitted. The transistors 100B and 100C can be formed over the same substrate through the same steps.

[0350] <Components of Semiconductor Device> The components included in the semiconductor device of this embodiment will be described below.

[0351] 〔substrate〕 There are no significant limitations on the material of the substrate 102, but the substrate must have at least sufficient heat resistance to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may be used as the substrate 102.

[0352] A flexible substrate may be used as the substrate 102, and the semiconductor device may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the semiconductor device. The peeling layer can be used to separate the semiconductor device from the substrate 102 after a part or whole of the semiconductor device is completed thereon, and to transfer the semiconductor device to another substrate. In this case, the semiconductor device can be transferred to a substrate having poor heat resistance or a flexible substrate.

[0353] [Conductive Film] The conductive layer 112 and the conductive layer 106 which function as a gate electrode, and the conductive layer 120a which functions as one of a source electrode or a drain electrode, and the conductive layer 120b which functions as the other electrode can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, or an alloy containing the above-mentioned metal elements or an alloy combining the above-mentioned metal elements.

[0354] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b may be formed of an oxide conductor or a metal oxide film, such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, or In-Ga-Zn oxide.

[0355] Here, an oxide conductor (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. A metal oxide that has become a conductor can be called an oxide conductor.

[0356] The conductive layer 112 or the like may have a stacked structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. In this case, it is preferable to use a conductive film containing an oxide conductor on the side in contact with an insulating layer that functions as a gate insulating film.

[0357] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b preferably contain one or more of the above-mentioned metal elements selected from titanium, tungsten, tantalum, and molybdenum. In particular, a tantalum nitride film is preferably used. The tantalum nitride film is conductive, has high barrier properties against copper, oxygen, or hydrogen, and releases little hydrogen from itself, and therefore can be preferably used as a conductive film in contact with the semiconductor layer 108 or in the vicinity of the semiconductor layer 108.

[0358] [Semiconductor Layer] When the semiconductor layer 108 is an In-M-Zn oxide, the atomic ratio of metal elements in a sputtering target used to form the In-M-Zn oxide film is, for example, In:M:Zn=5:1:1, In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1:1, In In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or a mixture thereof can be suitably used. In addition, when the semiconductor layer 108 is indium oxide, indium oxide can be used as a sputtering target for forming the indium oxide film. When the semiconductor layer 108 is an In-M oxide, the atomic ratio of metal elements in a sputtering target used to form the In-M oxide can be, for example, In:M=2:1, In:M=7:2, In:M=5:1, In:M=7:1, In:M=10:1, or a ratio close to these. When the semiconductor layer 108 is an In-Zn oxide, the atomic ratio of metal elements in a sputtering target used to form the In-Zn oxide can be, for example, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, In:Zn=14:1, or a ratio close to these.

[0359] It is preferable to use a target containing a polycrystalline oxide as the sputtering target because it is easy to form the semiconductor layer 108 having crystallinity. Note that the atomic ratio of the semiconductor layer 108 to be formed varies within ±40% of the atomic ratio of the metal elements contained in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn=5:1:3<atomic ratio>, the composition of the semiconductor layer 108 to be formed may be close to In:Ga:Zn=5:1:2.4<atomic ratio>.

[0360] Metal oxides formed by sputtering using the above target at a substrate temperature of 100°C to 130°C tend to have either an nc structure or a CAAC structure, or a mixed structure of these. On the other hand, metal oxides formed by sputtering at a substrate temperature of room temperature (RT) tend to have an nc crystal structure. Note that room temperature (RT) here includes the temperature when the substrate is not heated.

[0361] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wider energy gap than silicon in this manner, the off-state current of the transistor can be reduced.

[0362] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0363] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0364] (Embodiment 3) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described.

[0365] <Configuration example> 18A shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 attached to each other with a sealant 712. A pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided over the first substrate 701 in a region sealed by the first substrate 701, the second substrate 705, and the sealant 712. The pixel portion 702 is provided with a plurality of display elements.

[0366] An FPC terminal portion 708 to which an FPC 716 (Flexible printed circuit) is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Various signals and the like are supplied to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716 via the FPC terminal portion 708 and signal lines 710.

[0367] There may be a plurality of gate driver circuits 706. The gate driver circuits 706 and the source driver circuits 704 may each be formed separately on a semiconductor substrate or the like and may be in the form of a packaged IC chip. The IC chip can be mounted on the first substrate 701 or the FPC 716.

[0368] The transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 can be the transistors that are the semiconductor device of one embodiment of the present invention.

[0369] Examples of the display element provided in the pixel unit 702 include a liquid crystal element and a light-emitting element. Examples of the liquid crystal element include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element. Examples of the light-emitting element include a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), and a semiconductor laser. Examples of the light-emitting element include a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, and a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type can also be used.

[0370] A display device 700A shown in FIG. 18B is an example of a display device in which a flexible resin layer 743 is applied instead of the first substrate 701 and which can be used as a flexible display.

[0371] In the display device 700A, the pixel section 702 is not rectangular, but has arc-shaped corners. As shown in region P1 in FIG. 18B, the pixel section 702 and the resin layer 743 have cutouts formed by cutting out parts of the pixel section 702 and the resin layer 743. A pair of gate driver circuit sections 706 are provided on both sides of the pixel section 702. The gate driver circuit sections 706 are provided at the corners of the pixel section 702 along the arc-shaped contour.

[0372] The resin layer 743 has a protruding shape at a portion where the FPC terminal portion 708 is provided. A portion of the resin layer 743 including the FPC terminal portion 708 can be folded back to the rear side in an area P2 in Fig. 18B. By folding back a portion of the resin layer 743, the display device 700A can be mounted on an electronic device with the FPC 716 disposed so as to overlap the rear side of the pixel portion 702, thereby enabling space saving of the electronic device.

[0373] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as, for example, a source driver circuit. In this case, the source driver circuit unit 704 in the display device 700A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, and the like.

[0374] 18C is a display device that can be suitably used in electronic devices having a large screen, such as television devices, monitor devices, personal computers (including notebook and desktop computers), tablet terminals, and digital signage.

[0375] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuit units 722.

[0376] The multiple source driver ICs 721 are each attached to an FPC 723. One terminal of each of the multiple FPCs 723 is connected to the first substrate 701, and the other terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel portion 702 and mounted on the electronic device, thereby enabling space saving of the electronic device.

[0377] On the other hand, the gate driver circuit portion 722 is formed on the first substrate 701. This makes it possible to realize an electronic device with a narrow frame.

[0378] With this configuration, a large-sized, high-resolution display device can be realized. For example, the present invention can be applied to display devices with a diagonal screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more. In addition, a display device with an extremely high resolution such as 4K2K or 8K4K can be realized.

[0379] <Cross-section example> A configuration using liquid crystal elements as display elements and a configuration using EL elements will be described below with reference to Figs. 19 to 22. Figs. 19 to 21 are cross-sectional views taken along dashed line QR in Fig. 18A. Fig. 22 is a cross-sectional view taken along dashed line ST in display device 700A shown in Fig. 18B. Figs. 19 and 20 show configurations using liquid crystal elements as display elements, and Figs. 21 and 22 show configurations using EL elements.

[0380] [Description of common parts of the display device] 19 to 22 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The lead wiring portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. FIG. 20 illustrates a case where the capacitor 790 is not included.

[0381] The transistors described in Embodiment 2 can be used as the transistors 750 and 752.

[0382] The transistor used in this embodiment has an oxide semiconductor film that is highly purified and in which formation of oxygen vacancies is suppressed. The off-state current of the transistor can be reduced. Thus, the retention time of an electric signal such as an image signal can be increased, and the writing interval of the image signal can be set to be long. Thus, the frequency of a refresh operation can be reduced, which leads to an effect of reducing power consumption.

[0383] The transistor used in this embodiment mode can achieve high-speed driving because it has a relatively high field-effect mobility. For example, by using such a transistor capable of high-speed driving in a display device, a transistor in a pixel portion and a transistor used in a driver circuit portion can be formed over the same substrate. That is, a configuration in which a driver circuit formed using a silicon wafer or the like is not used is also possible, and the number of components in the display device can be reduced. Furthermore, by using a transistor capable of high-speed driving in the pixel portion, a high-quality image can be provided.

[0384] The capacitor 790 shown in FIG. 19, FIG. 21, and FIG. 22 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide as the semiconductor layer. The upper electrode has a low resistance like the source and drain regions of the transistor 750. In addition, a part of an insulating film functioning as the first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. In addition, a wiring obtained by processing the same film as the source and drain electrodes of the transistor is connected to the upper electrode.

[0385] A planarization insulating film 770 is provided over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0386] The transistor 750 in the pixel portion 702 and the transistor 752 in the source driver circuit portion 704 may have different structures. For example, a top-gate transistor may be used for one of them and a bottom-gate transistor may be used for the other. Note that, like the source driver circuit portion 704, the gate driver circuit portion 706 may also use a transistor having the same structure as the transistor 750 or a transistor having a different structure.

[0387] The signal line 710 is formed of the same conductive film as the source and drain electrodes of the transistors 750 and 752. In this case, it is preferable to use a low-resistance material such as a material containing copper, because signal delays caused by wiring resistance are small and display on a large screen is possible.

[0388] The FPC terminal portion 708 has a wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716. The wiring 760 is electrically connected to a terminal of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752.

[0389] A flexible substrate such as a glass substrate or a plastic substrate can be used as the first substrate 701 and the second substrate 705. When a flexible substrate is used as the first substrate 701, an insulating layer having a barrier property against water and hydrogen is preferably provided between the first substrate 701 and the transistor 750 or the like.

[0390] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and an insulating film 734 in contact with these are provided.

[0391] [Example of the configuration of a display device using a liquid crystal element] A display device 700 shown in FIG. 19 includes a liquid crystal element 775 and a spacer 778. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is formed over a planarization insulating film 770 and functions as a pixel electrode.

[0392] A material that transmits or reflects visible light can be used for the conductive layer 772. As a light-transmitting material, for example, an oxide material containing indium, zinc, tin, or the like can be used. As a reflective material, for example, a material containing aluminum, silver, or the like can be used.

[0393] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich a liquid crystal element.

[0394] 20 shows an example of a display device 700 using a horizontal electric field (e.g., FFS mode) liquid crystal element 775. A conductive layer 774 functioning as a common electrode is provided over a conductive layer 772 with an insulating layer 773 interposed therebetween. The alignment state of a liquid crystal layer 776 can be controlled by an electric field generated between the conductive layer 772 and the conductive layer 774.

[0395] 20, a storage capacitor can be formed using a stacked structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0396] 19 and 20, an alignment film may be provided in contact with the liquid crystal layer 776. In addition, optical members (optical substrates) such as a polarizing member, a phase difference member, and an anti-reflection member, and light sources such as a backlight and a sidelight may be provided as appropriate.

[0397] Thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used for the liquid crystal layer 776. In addition, when the in-plane switching mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may be used.

[0398] The liquid crystal element modes that can be used include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode.

[0399] A scattering type liquid crystal using a polymer dispersed type liquid crystal or a polymer network type liquid crystal can be used for the liquid crystal layer 776. In this case, a configuration for performing black and white display without providing the colored film 736, or a configuration for performing color display using the colored film 736 can be used.

[0400] A time-division display method (also called a field sequential driving method) that performs color display based on a time-sequential additive color mixing method may be applied as a driving method for the liquid crystal element. In this case, the color film 736 may not be provided. When the time-division display method is used, there is an advantage that the aperture ratio of the pixel can be improved and the resolution can be increased because there is no need to provide sub-pixels that exhibit the respective colors of R (red), G (green), and B (blue).

[0401] [Display device using light-emitting element] 21 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes a light-emitting material such as an organic compound or an inorganic compound.

[0402] As the light-emitting material, a fluorescent material, a phosphorescent material, a thermally activated delayed fluorescence (TADF) material, an inorganic compound (such as a quantum dot material), or the like can be used.

[0403] 21, an insulating film 730 that covers part of a conductive layer 772 is provided over a planarization insulating film 770. Here, the light-emitting element 782 is a top-emission light-emitting element that has a light-transmitting conductive film 788. Note that the light-emitting element 782 may have a bottom-emission structure in which light is emitted to the conductive layer 772 side or a dual-emission structure in which light is emitted to both the conductive layer 772 side and the conductive film 788 side.

[0404] The colored film 736 is provided at a position overlapping with the light-emitting element 782, and the light-shielding film 738 is provided at a position overlapping with the insulating film 730, in the lead-out wiring portion 711, and in the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, when the EL layer 786 is formed by coloring, the colored film 736 may not be provided.

[0405] A configuration of a display device that can be suitably applied to a flexible display is shown in Fig. 22. Fig. 22 is a cross-sectional view of the display device 700A shown in Fig. 18B taken along dashed line ST.

[0406] 22 has a stacked structure of a supporting substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 instead of the first substrate 701 shown in FIG. 21. A transistor 750, a capacitor 790, and the like are provided over the insulating layer 744 provided over the resin layer 743.

[0407] The support substrate 745 is a substrate that contains an organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer that contains an organic resin such as polyimide or acrylic. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is preferably thinner than the support substrate 745.

[0408] A display device 700A shown in Fig. 22 has a protective layer 740 instead of the second substrate 705 shown in Fig. 21. The protective layer 740 is bonded to a sealing film 732. A glass substrate, a resin film, or the like can be used as the protective layer 740. In addition, an optical member such as a polarizing plate or a scattering plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are laminated may be used as the protective layer 740.

[0409] An EL layer 786 included in the light-emitting element 782 is provided in an island shape over the insulating film 730 and the conductive layer 772. By creating the EL layer 786 so that each subpixel emits a different light color, color display can be achieved without using the colored film 736. A protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 is preferably an inorganic insulating film. A stacked structure including at least one inorganic insulating film and at least one organic insulating film is more preferably used.

[0410] FIG. 22 shows a bendable region P2. In the region P2, in addition to the support substrate 745 and the adhesive layer 742, there is a portion where no inorganic insulating film such as the insulating layer 744 is provided. In the region P2, a resin layer 746 is provided to cover the wiring 760. By providing as little inorganic insulating film as possible in the bendable region P2 and by using a configuration in which only a conductive layer containing a metal or alloy and a layer containing an organic material are laminated, it is possible to prevent cracks from occurring when the display device 700A is bent. Furthermore, by not providing the support substrate 745 in the region P2, a part of the display device 700A can be bent with an extremely small radius of curvature.

[0411] [Example of configuration in which an input device is provided on a display device] An input device may be provided in the display device 700 or the display device 700A shown in Figures 19 to 22. As the input device, for example, a touch sensor or the like can be given.

[0412] For example, various types of sensors can be used, such as a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, a pressure sensitive type, etc. Alternatively, two or more of these types may be used in combination.

[0413] The touch panel may have a configuration such as an in-cell type touch panel in which an input device is formed between a pair of substrates, a so-called on-cell type touch panel in which an input device is formed on the display device 700, or a so-called out-cell type touch panel in which an input device is attached to the display device 700.

[0414] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0415] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0416] (Embodiment 4) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0417] 23A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 does not necessarily have to be provided.

[0418] The transistor of one embodiment of the present invention can be applied to the transistors included in the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention can also be applied to the protection circuit 506.

[0419] The pixel section 502 has a plurality of pixel circuits 501 arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each pixel circuit 501 has a circuit for driving a display element.

[0420] The driver circuit unit 504 has driver circuits such as a gate driver 504a that outputs scanning signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may have at least a shift register. The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b may also be configured using a shift register.

[0421] The terminal portion 507 refers to a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0422] The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring. The protection circuit 506 shown in Fig. 23A is connected to various wirings, such as gate lines GL_1 to GL_X that are wirings between the gate driver 504a and the pixel circuit 501, or data lines DL_1 to DL_Y that are wirings between the source driver 504b and the pixel circuit 501. Note that in Fig. 23A, the protection circuit 506 is hatched to distinguish it from the pixel circuit 501.

[0423] The gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel unit 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (e.g., a drive circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) may be mounted on the substrate on which the pixel unit 502 is provided by COG or TAB (Tape Automated Bonding).

[0424] 23B and 23C show an example of a pixel circuit configuration that can be applied to the pixel circuit 501. In FIG.

[0425] The pixel circuits 501 shown in FIG. 23A can have the configurations shown in FIGS. 23B and 23C, for example.

[0426] 23B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL, and the like.

[0427] The potential of one of a pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the multiple pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

[0428] 23C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0429] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. A current flowing through the light emitting element 572 is controlled in accordance with a potential applied to the gate of the transistor 554, thereby controlling the light emission luminance of the light emitting element 572.

[0430] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0431] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0432] (Embodiment 5) A pixel circuit including a memory for correcting a gray scale displayed in a pixel and a display device including the pixel circuit will be described below. The transistors described in the second embodiment can be used as the transistors used in the pixel circuits described below.

[0433] <Circuit configuration> 24A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0434] The transistor M1 has a gate connected to the wiring G1, one of a source and a drain connected to the wiring S1, and the other connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of a source and a drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401.

[0435] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but typically, a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS (Micro Electro Mechanical Systems) element can be used.

[0436] The node connecting the transistor M1 and the capacitor C1 is referred to as a node N1, and the node connecting the transistor M2 and the circuit 401 is referred to as a node N2.

[0437] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. Also, the potential of the node N2 can be maintained by turning off the transistor M2. Also, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed according to the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0438] Here, the transistor including an oxide semiconductor, as described in Embodiment 2, can be used as one or both of the transistors M1 and M2. Therefore, the potentials of the nodes N1 and N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period during which the potentials of the nodes are held is short (specifically, when the frame frequency is 30 Hz or higher), a transistor including a semiconductor such as silicon may be used.

[0439] <Driving method example> Next, an example of an operation method of the pixel circuit 400 will be described with reference to Fig. 24B. Fig. 24B is a timing chart relating to the operation of the pixel circuit 400. Note that, for ease of explanation, the influence of various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, threshold voltages of transistors, and the like will not be taken into consideration here.

[0440] 24B, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0441] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ref is supplied to the line S2, and the first data potential V w supplies.

[0442] The node N1 is connected to a potential V ref A first data potential V w Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0443] [Period T2] In the next period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. data A predetermined constant potential is applied to the wiring S2, or the wiring S2 may be in a floating state.

[0444] A second data potential V data At this time, the second data potential V data In response to the change in potential, the potential of the node N2 changes by a potential dV. That is, a potential obtained by adding the first data potential Vw and the potential dV is input to the circuit 401. Note that although the potential dV is shown to be a positive value in FIG. 24B, it may be a negative value. That is, the potential of the second data potential V data is the potential V ref It may be lower.

[0445] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V data The potential becomes close to

[0446] In this manner, the pixel circuit 400 can combine two types of data signals to generate a potential to be supplied to the circuit 401 including a display element, and therefore, gray scale correction can be performed within the pixel circuit 400.

[0447] The pixel circuit 400 can generate a potential that exceeds the maximum potential that can be supplied by a source driver connected to the wirings S1 and S2. For example, when a light-emitting element is used, a high dynamic range (HDR) display or the like can be performed. When a liquid crystal element is used, overdrive driving or the like can be realized.

[0448] <Application Examples> [Example using liquid crystal element] The pixel circuit 400LC shown in Fig. 24C includes a circuit 401LC. The circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0449] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitance C2, and the other electrode connected to the potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0450] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted.

[0451] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, and therefore can, for example, realize high-speed display by overdrive driving, apply a liquid crystal material with a high driving voltage, etc. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is possible to correct the gradation according to the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0452] [Example using light-emitting element] The pixel circuit 400EL shown in Fig. 24D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0453] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, a source and a drain connected to a wiring to which a potential VH is applied, and the other connected to one electrode of the light-emitting element EL. comThe light-emitting element EL has the other electrode connected to a wiring that is supplied with a potential V L Connect with the wiring given.

[0454] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if not required.

[0455] In this embodiment, the anode side of the light-emitting element EL is connected to the transistor M3, but the cathode side of the light-emitting element EL may be connected to the transistor M3. H and potential V L The value of can be changed appropriately.

[0456] In the pixel circuit 400EL, a large current can be passed through the light-emitting element EL by applying a high potential to the gate of the transistor M3, and thus, for example, HDR display can be realized. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0457] Note that the circuits are not limited to those illustrated in FIGS. 24C and 24D, and may be configured to include additional transistors, capacitors, and the like.

[0458] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0459] (Embodiment 6) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0460] A display module 6000 shown in FIG. 25A has a display device 6006 connected by an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0461] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0462] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately according to the size of the display device 6006.

[0463] The display device 6006 may have a function as a touch panel.

[0464] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0465] The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

[0466] FIG. 25B is a cross-sectional schematic diagram of a display module 6000 with an optical touch sensor.

[0467] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. Also, in an area surrounded by an upper cover 6001 and a lower cover 6002, a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) are provided.

[0468] The display device 6006 is provided so as to overlap a printed circuit board 6010 and a battery 6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guiding portion 6017a and a light guiding portion 6017b.

[0469] Light 6018 emitted from the light-emitting unit 6015 passes through the light-guiding unit 6017a, the upper part of the display device 6006, and the light-guiding unit 6017b to reach the light-receiving unit 6016. When the light 6018 is blocked by a detection object such as a finger or a stylus, a touch operation can be detected.

[0470] A plurality of light emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving units 6016 are provided at positions facing the light emitting units 6015. This makes it possible to obtain information on the position where a touch operation is performed.

[0471] The light emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light receiving unit 6016 may be a photoelectric element that receives the light emitted by the light emitting unit 6015 and converts it into an electric signal. Preferably, a photodiode that can receive infrared light may be used.

[0472] The light guiding portion 6017a and the light guiding portion 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, and it is possible to prevent external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, if a resin that absorbs visible light and transmits infrared light is used, it is possible to more effectively prevent the touch sensor from malfunctioning.

[0473] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0474] (Embodiment 7) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0475] Electronic device 6500 shown in FIG. 26A is a portable information terminal that can be used as a smartphone.

[0476] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0477] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0478] FIG. 26B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0479] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0480] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0481] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on a printed circuit board 6517.

[0482] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. In addition, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0483] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0484] (Embodiment 8) In this embodiment, electronic devices including a display device manufactured according to one embodiment of the present invention will be described.

[0485] The electronic devices exemplified below each have a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices have high resolution. In addition, the electronic devices can have both high resolution and a large screen.

[0486] The display portion of the electronic device according to one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0487] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0488] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a house or building, or the interior or exterior of an automobile or the like.

[0489] FIG. 27A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0490] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, a shutter button 8004, etc. In addition, a detachable lens 8006 is attached to the camera 8000.

[0491] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0492] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0493] The housing 8001 has a mount having electrodes, and can be connected to a strobe device or the like in addition to the finder 8100 .

[0494] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0495] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0496] The button 8103 has a function such as a power button.

[0497] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a viewfinder 8100. Note that the camera 8000 may have a built-in viewfinder.

[0498] FIG. 27B is a diagram showing the external appearance of the head mounted display 8200.

[0499] The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 includes a built-in battery 8206.

[0500] A cable 8205 supplies power from a battery 8206 to a main body 8203. The main body 8203 includes a wireless receiver or the like and can display received video information on a display portion 8204. The main body 8203 also includes a camera and can use information on the movements of the user's eyeballs and eyelids as an input means.

[0501] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes capable of detecting a current flowing with the movement of the user's eyeball at positions that come into contact with the user. The wearing unit 8201 may also have a function of monitoring the user's pulse rate by the current flowing through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 according to the movement of the user's head.

[0502] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0503] 27C, 27D, and 27E are diagrams showing the external appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0504] A user can view the display on the display unit 8302 through the lens 8305. Note that it is preferable to arrange the display unit 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing another image displayed in a different area of ​​the display unit 8302 through the lens 8305, it is possible to perform three-dimensional display using parallax. Note that the present invention is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided, with one display unit being provided for each eye of the user.

[0505] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition, so that a user cannot see pixels even when the image is enlarged using a lens 8305 as in FIG. 27E, and a more realistic image can be displayed.

[0506] The electronic device shown in Figures 28A to 28G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0507] The electronic device shown in Fig. 28A to Fig. 28G has various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing a program or data recorded on a recording medium, etc. The functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have multiple display units. In addition, the electronic device may have a camera or the like to capture still images and videos and store them on a recording medium (external or built-in to the camera), a function of displaying the captured images on the display unit, etc.

[0508] Details of the electronic device shown in FIGS. 28A to 28G will be described below.

[0509] 28A is a perspective view showing a television device 9100. The television device 9100 can incorporate a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

[0510] FIG. 28B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on a plurality of surfaces. FIG. 28B shows an example in which three icons 9050 are displayed. Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mails, SNS, and phone calls, titles of e-mails and SNS, sender names, date and time, time, remaining battery level, and antenna reception strength. Alternatively, icons 9050 and the like may be displayed at the position where the information 9051 is displayed.

[0511] 28C is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.

[0512] FIG. 28D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch. The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0513] 28E, 28F, and 28G are perspective views showing a foldable mobile information terminal 9201. FIG. 28E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 28G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 28F is a perspective view of the mobile information terminal 9201 in a state in the middle of changing from one of FIG. 28E and FIG. 28G to the other. The mobile information terminal 9201 has excellent portability in a folded state, and has excellent viewability of the display due to a seamless wide display area in an unfolded state. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0514] 29A shows an example of a television device. A television device 7100 has a display unit 7500 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0515] 29A can be operated using an operation switch provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch panel may be applied to the display unit 7500, and the television set 7100 may be operated by touching the touch panel. The remote control 7111 may have a display unit in addition to operation buttons.

[0516] The television device 7100 may also include a television broadcast receiver and a communication device for network connection.

[0517] 29B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display unit 7500 is incorporated in the housing 7211.

[0518] 29C and 29D show an example of digital signage.

[0519] 29C includes a housing 7301, a display unit 7500, and a speaker 7303. The digital signage 7300 may further include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0520] 29(D) shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0521] The larger the display unit 7500, the more information can be provided at one time, and the larger the display area, the more easily it catches people's attention, which has the effect of increasing the effectiveness of advertising, for example.

[0522] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows the display unit 7500 to be used not only for advertising purposes, but also for providing information desired by the user, such as route information, traffic information, and commercial facility guide information.

[0523] 29C and 29D, it is preferable that the digital signage 7300 or the digital signage 7400 can wirelessly communicate with an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, or the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0524] A game using the information terminal 7311 as an operation means (controller) can also be executed on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to simultaneously participate in and enjoy the game.

[0525] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS. 29A to 29D.

[0526] Although the electronic device in this embodiment has a display portion, one embodiment of the present invention can also be applied to an electronic device that does not have a display portion.

[0527] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification. EXAMPLES

[0528] In this example, the composition of a metal oxide film that can be used in a semiconductor device according to one embodiment of the present invention was evaluated.

[0529] In this example, the compositions of metal oxide films prepared by different methods were evaluated by X-ray photoelectron spectroscopy (XPS). Samples (A1 to A5, B1, and B2) in which a metal oxide film having a thickness of 100 nm was formed on a glass substrate were used for the evaluation.

[0530] <Sample preparation> In the samples A1 to A5, the metal oxide films were formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=5:1:3 [atomic ratio]), and in the samples B1 and B2, the metal oxide films were formed by sputtering using an In-Zn oxide target (In:Zn=2:3 [atomic ratio]).

[0531] The deposition conditions for the metal oxide films of Samples A1 to A5 and Samples B1 and B2 are shown in Table 1. In Table 1, the target composition is indicated as Target, the substrate temperature during deposition of the metal oxide films is indicated as Tsub, the oxygen flow ratio is indicated as O2 / (Ar+O2), the pressure is indicated as Pressure, and the power supply power is indicated as Power.

[0532] [Table 1]

[0533] Sample A1 had a substrate temperature of room temperature (hereinafter also referred to as RT) during the formation of the metal oxide film. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow ratio was set to 10%. The pressure during film formation was 0.6 Pa, and the power supply power was 2.5 kW.

[0534] Sample A2 had a substrate temperature of room temperature (RT) during the formation of the metal oxide film. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow ratio was set to 50%. The pressure during film formation was 0.6 Pa, and the power supply power was 2.5 kW.

[0535] Sample A3 had a substrate temperature of room temperature (RT) during the formation of the metal oxide film. Oxygen gas (oxygen flow ratio of 100%) was used as the film-forming gas. The pressure during film formation was 0.6 Pa, and the power supply power was 2.5 kW.

[0536] Sample A4 had a substrate temperature of 130 °C during the formation of the metal oxide film. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow ratio was set to 10%. The pressure during film formation was 0.6 Pa, and the power supply power was 2.5 kW.

[0537] Sample A5 had a substrate temperature of 130 °C during the formation of the metal oxide film. Oxygen gas (oxygen flow ratio of 100%) was used as the film-forming gas. The pressure during film formation was 0.6 Pa, and the power supply power was 2.5 kW.

[0538] Sample B1 had a substrate temperature of room temperature (RT) during the formation of the metal oxide film. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow ratio was set to 2%. The pressure during film formation was 0.6 Pa, and the power supply power was 2.5 kW.

[0539] Sample B2 had a substrate temperature of room temperature (RT) during the formation of the metal oxide film. Oxygen gas (oxygen flow ratio of 100%) was used as the film-forming gas. The pressure during film formation was 0.6 Pa, and the power supply power was 2.5 kW.

[0540] <X-ray Photoelectron Spectroscopy Analysis> Next, X-ray photoelectron spectroscopy (XPS) analysis was carried out on Samples A1 to A5, B1 and B2.

[0541] For the XPS analysis, monochromatic Mg Kα radiation (λ=1253.6 eV) was used as the X-ray source. The detection area was 8 mm square or less, and the take-off angle was 45°. The detection depth was thought to be about 4 nm to 5 nm.

[0542] The atomic ratios of indium (In), gallium (Ga), zinc (Zn), and oxygen (O) for each sample obtained by XPS analysis are shown in Table 2. In Table 2, samples A1 to A5 show values ​​normalized with the atomic ratio of indium set to 5.00. Samples B1 and B2 show values ​​normalized with the atomic ratio of indium set to 2.00.

[0543] [Table 2]

[0544] As shown in Table 2, it was confirmed that the atomic ratio of zinc in the metal oxide film was smaller than that of the target. In this example, the atomic ratio of zinc contained in the target was about 81% or more and 94% or less. It was also confirmed that the atomic ratio of gallium in the metal oxide film tended to be smaller than that of the target. However, in the quantification of gallium, the waveform-separated In4d peak was removed, so it is possible that the quantification error was large. Therefore, the gallium ratio shown in Table 2 may be lower than the actual gallium content.

[0545] The configuration shown in this embodiment can be used in appropriate combination with other embodiments and mode of implementation. EXAMPLES

[0546] In this example, the crystallinity of a composition of a metal oxide film that can be used in a semiconductor device according to one embodiment of the present invention was evaluated.

[0547] In this example, X-ray diffraction (XRD) analysis was performed on metal oxide films with different fabrication methods to evaluate their crystallinity. For the evaluation, samples (Samples C1 to C3, D1 to D3, E1 to E3) were used in which metal oxide films with a thickness of 100 nm were formed on glass substrates.

[0548] <Sample Fabrication> Samples C1 to C3 were formed by sputtering a metal oxide film using an In-Ga-Zn oxide target (In:Ga:Zn = 5:1:3 [atomic ratio]). Samples D1 to D3 were formed by sputtering a metal oxide film using an In-Zn oxide target (In:Zn = 2:3 [atomic ratio]). Samples E1 to E3 were formed by sputtering a metal oxide film using an In-Zn oxide target (In:Zn = 4:1 [atomic ratio]).

[0549] The film formation conditions of the metal oxide films of Samples C1 to C3, D1 to D3, and E1 to E3 are shown in Table 3. In Table 3, the composition of the target is denoted as Target, the substrate temperature during film formation of the metal oxide film is denoted as Tsub, the oxygen flow ratio is denoted as O2 / (Ar + O2), the pressure is denoted as Pressure, and the power supply power is denoted as Power.

[0550]

Table 3

[0551] <X-ray Diffraction Analysis> Next, X-ray diffraction (XRD) analysis was performed on Samples C1 to C3, D1 to D3, and E1 to E3.

[0552] For the XRD analysis, the θ-2θ scan method, which is a type of out-of-plane method, was used. The θ-2θ scan method is a method in which the X-ray incidence angle is changed and the angle of the detector installed opposite the X-ray source is set to the same as the incidence angle to measure the X-ray diffraction intensity. The θ-2θ scan method is sometimes called the powder method. For the XRD analysis, Cu Kα rays (λ=0.15418 nm) were used as the X-ray source, the scanning range was 2θ=15 deg to 50 deg, the step width was 0.01 deg, and the scanning speed was 6.0 deg / min.

[0553] The results of the XRD analysis are shown in Figure 30. In Figure 30, the horizontal axis indicates the diffraction angle 2θ, and the vertical axis indicates the intensity of the diffracted X-rays. In Figure 30, 2θ=31 deg is indicated by a dashed line as an auxiliary line.

[0554] As shown in Fig. 30, a peak was observed near 2θ=31 deg in all samples, confirming that they had crystallinity. Note that, because the peak intensities observed in samples D1 to D3 were high, the scale of the vertical axis in Fig. 30 was made different from that of the other samples. Note that the broad peak near 2θ=24 deg is a peak caused by the glass substrate.

[0555] The configuration shown in this embodiment can be used in appropriate combination with other embodiments and mode of implementation. EXAMPLES

[0556] In this example, transistors (samples F, G, and H) were fabricated and their drain current-gate voltage characteristics (ID-VG characteristics) were evaluated. Note that transistors corresponding to the transistor 100 shown in FIG. 8 and the transistor 100A shown in FIG. 9 were fabricated. In this example, samples (F, G, and H) having different configurations of the semiconductor layer 108 were fabricated.

[0557] <Sample preparation>

[0558] First, a tungsten film with a thickness of about 100 nm was formed on a glass substrate by sputtering, and then processed to obtain a first gate electrode. Next, a first silicon nitride film with a thickness of about 240 nm, a second silicon nitride film with a thickness of about 60 nm, and a silicon oxynitride film with a thickness of about 3 nm were laminated by plasma CVD to form a first gate insulating layer.

[0559] The first silicon nitride film was formed with silane gas, nitrogen gas, and ammonia gas flow rates of 290 sccm, 2000 sccm, and 2000 sccm, respectively, pressure of 200 Pa, film formation power of 3000 W, and substrate temperature of 350°C.

[0560] The second silicon nitride film was formed with silane gas, nitrogen gas, and ammonia gas flow rates of 200 sccm, 2000 sccm, and 100 sccm, respectively, pressure of 100 Pa, film formation power of 2000 W, and substrate temperature of 350°C.

[0561] The silicon oxynitride film was formed with the flow rates of silane gas and nitrous oxide gas set to 20 sccm and 3000 sccm, respectively, the pressure set to 40 Pa, the film formation power set to 3000 W, and the substrate temperature set to 350°C.

[0562] Next, a first metal oxide film having a thickness of 30 nm was formed on the first gate insulating layer, and the film was processed to obtain a semiconductor layer. Three samples (F, G, and H) were fabricated under different film formation conditions for the first metal oxide film. In sample F, the first metal oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=5:1:3 [atomic ratio]). In sample G, the first metal oxide film was formed by sputtering using an In-Zn oxide target (In:Zn=2:3 [atomic ratio]). In sample H, the first metal oxide film was formed by sputtering using an In-Zn oxide target (In:Zn=4:1 [atomic ratio]).

[0563] The deposition conditions for the first metal oxide film of Samples F, G, and H are shown in Table 4. In Table 4, the target composition is indicated as Target, the substrate temperature during deposition of the first metal oxide film is indicated as Tsub, the oxygen flow ratio is indicated as O2 / (Ar+O2), the pressure is indicated as Pressure, and the power supply power is indicated as Power.

[0564] [Table 4]

[0565] After the semiconductor layer was formed, the substrate was subjected to a heat treatment in a nitrogen gas atmosphere at 350°C for 1 hour, and then to a heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas at 350°C for 1 hour. The mixed atmosphere of nitrogen gas and oxygen gas had a nitrogen gas:oxygen gas ratio of 4:1 (volume ratio).

[0566] Subsequently, as a second gate insulating layer, a first silicon oxynitride film having a thickness of about 5 nm, a second silicon oxynitride film having a thickness of about 140 nm, and a third silicon oxynitride film having a thickness of about 5 nm were each formed by a plasma CVD method.

[0567] The first silicon oxynitride film was formed with the flow rates of silane gas and nitrous oxide gas set to 24 sccm and 18000 sccm, respectively, the pressure set to 200 Pa, the film formation power set to 130 W, and the substrate temperature set to 350°C.

[0568] The second silicon oxynitride film was formed with the flow rates of silane gas and nitrous oxide gas set to 200 sccm and 4000 sccm, respectively, the pressure set to 300 Pa, the film formation power set to 750 W, and the substrate temperature set to 350°C.

[0569] The third silicon oxynitride film was formed with the flow rates of silane gas and nitrous oxide gas set to 20 sccm and 3000 sccm, respectively, the pressure set to 40 Pa, the film formation power set to 500 W, and the substrate temperature set to 350°C.

[0570] Next, a second metal oxide film having a thickness of 20 nm was formed on the second gate insulating layer by sputtering. The second metal oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The substrate temperature during film formation was 100°C. Oxygen gas (oxygen flow rate ratio 100%) was used as the film formation gas. The power supply was 2.5 kW and the pressure was 0.6 Pa.

[0571] Thereafter, a heat treatment was performed at 350° C. for 1 hour in a nitrogen-containing atmosphere.

[0572] Subsequently, a molybdenum film having a thickness of about 100 nm was formed as a conductive film on the second metal oxide film by a sputtering method.

[0573] Subsequently, a resist pattern was formed on the conductive film.

[0574] Next, the conductive film was etched using the resist pattern as a mask to obtain a conductive layer. The etching was performed by dry etching using SF6 gas as the etching gas.

[0575] The second metal oxide film was then etched by wet etching to obtain a metal oxide layer.

[0576] Next, an impurity element was added using the conductive layer as a mask. Boron was used as the impurity element, and a plasma ion doping device was used for the addition process. B2H6 gas was used as the gas for supplying boron.

[0577] Next, a silicon oxynitride film was formed by plasma CVD to a thickness of about 300 nm as a protective insulating layer covering the transistor.

[0578] The protective insulating layer was formed with silane gas and nitrogen gas flow rates of 290 sccm and 4000 sccm, respectively, pressure of 133 Pa, film-forming power of 1000 W, and substrate temperature of 350°C.

[0579] Subsequently, openings were made by etching a part of the protective insulating layer and the second gate insulating layer, and after forming a molybdenum film by sputtering, it was processed to obtain source and drain electrodes. Thereafter, an acrylic film with a thickness of about 1.5 μm was formed as a planarization layer, and heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 250°C, and 1 hour.

[0580] Through the above steps, samples F, G, and H each having a transistor formed on a glass substrate were obtained.

[0581] <ID-VG Characteristic Evaluation> Subsequently, the ID-VG characteristics of the transistors fabricated above were measured.

[0582] For the measurement of the ID-VG characteristics of the transistors, the voltage applied to the gate electrode (hereinafter also referred to as the gate voltage (VG)) was applied in steps of 0.25 V from -15 V to +20 V. Also, the voltage applied to the source electrode (hereinafter also referred to as the source voltage (VS)) was set to 0 V (comm), and the voltage applied to the drain electrode (hereinafter also referred to as the drain voltage (VD)) was set to 0.1 V and 10 V.

[0583] The ID-VG characteristics of samples F, G, and H are shown in FIG. 31. In FIG. 31, the samples (Sample) and the conditions of the semiconductor layer 108 are shown in the horizontal direction. The ID-VG characteristics of conditions with different transistor structures are shown in the vertical direction. The transistors corresponding to the transistor 100 shown in FIG. 8 are shown in the upper row, and the transistors corresponding to the transistor 100A shown in FIG. 9 are shown in the lower row. Also, transistors with a channel length of 50 μm and a channel width of 50 μm are shown. In the ID-VG characteristics of FIG. 31, the gate voltage (VG) is shown on the horizontal axis, the drain current (ID) is shown on the left vertical axis, and the field-effect mobility (μFE) is shown on the right vertical axis. Note that the ID-VG characteristics of one transistor were measured for each sample.

[0584] The field effect mobility (μFE) of samples F, G, and H is shown in Fig. 32. In Fig. 32, the horizontal axis represents the conditions of the sample and the semiconductor layer 108, and the vertical axis represents the field effect mobility (μFE). In Fig. 32, the transistor 100 shown in Fig. 8 is labeled Single, and the transistor 100A shown in Fig. 9 is labeled S-channel. The field effect mobility (μFE) indicates the maximum value up to VG=10 V for a transistor with a channel length of 50 μm and a channel width of 50 μm.

[0585] As shown in Figures 31 and 32, it was confirmed that all the samples exhibited good electrical characteristics. It was also confirmed that the higher the indium content, the higher the field effect mobility (μFE).

[0586] The configuration shown in this embodiment can be used in appropriate combination with other embodiments and mode of implementation. EXAMPLES

[0587] In this example, a transistor corresponding to the transistor 100C_a shown in FIG. 12D was fabricated, and its drain current-gate voltage characteristics (ID-VG characteristics) and reliability were evaluated. In this example, samples (J and K) with different configurations of the semiconductor layer 108 were fabricated. In addition, the insulating layer 110 functioning as a gate insulating layer had a single-layer structure.

[0588] <Sample preparation 1> The methods for preparing samples J and K will be described.

[0589] First, a titanium film having a thickness of 30 nm and a copper film having a thickness of 100 nm were formed in this order on a glass substrate by a sputtering method, and then processed to obtain a first gate electrode (bottom gate).

[0590] Next, as a first gate insulating layer, a first silicon nitride film having a thickness of 50 nm, a second silicon nitride film having a thickness of 150 nm, a third silicon nitride film having a thickness of 100 nm, and a first silicon oxynitride film having a thickness of 3 nm were formed in this order.

[0591] The first silicon nitride film and the third silicon nitride film were formed by PECVD using a mixed gas of silane gas with a flow rate of 200 sccm, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm. The pressure during film formation was 100 Pa, the film formation power was 2000 W, and the substrate temperature was 350°C.

[0592] The second silicon nitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 290 sccm, nitrogen gas at a flow rate of 2000 sccm, and ammonia gas at a flow rate of 2000 sccm. The pressure during film formation was 200 Pa, the film formation power was 3000 W, and the substrate temperature was 350°C.

[0593] The first silicon oxynitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 20 sccm and dinitrogen monoxide gas at a flow rate of 3000 sccm under a pressure of 40 Pa, a power of 3000 W, and a substrate temperature of 350° C.

[0594] Next, a first metal oxide film was formed on the first silicon oxynitride film. Here, two samples (samples J and K) were prepared by changing the deposition conditions of the first metal oxide film. Sample K is one embodiment of the present invention, and sample J is a comparative example.

[0595] The first metal oxide film of sample J was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the source power was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 30%. The thickness of the first metal oxide film was 25 nm.

[0596] The first metal oxide film of the sample K had a laminated structure of a first oxide film and a second oxide film on the first oxide film. The first oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power source was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow ratio was 30%. The second oxide film was formed by a sputtering method using an In-Zn oxide target (In:Zn=4:1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power source was 3.0 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow ratio was 5%. The thickness of the first oxide film was 20 nm, and the thickness of the second oxide film was 5 nm.

[0597] Next, the first metal oxide film was processed into islands to form a first metal oxide layer.

[0598] Next, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven was used for the heat treatment.

[0599] Next, a second silicon oxynitride film having a thickness of 140 nm was formed as a second gate insulating layer. The second silicon oxynitride film is a film that is resistant to the generation of nitrogen oxides (NO X The deposition conditions were such that the emission of fluorine was high (X is greater than 0 and less than or equal to 2). The second silicon oxynitride film was deposited by the PECVD method using a mixed gas of silane gas with a flow rate of 200 sccm and nitrous oxide gas with a flow rate of 8000 sccm. The deposition pressure was 250 Pa, the deposition power was 2000 W, and the substrate temperature was 240°C.

[0600] It is preferable that the second silicon oxynitride film in contact with the first metal oxide layer releases less nitrogen oxide due to the application of heat. Examples of nitrogen oxide include NO2 and NO. The nitrogen oxide contained in the second silicon oxynitride film forms a level in the second silicon oxynitride film, etc. The level is located within the energy gap of the first metal oxide layer. Therefore, when the nitrogen oxide diffuses to the interface between the second silicon oxynitride film and the first metal oxide layer, the level may trap electrons on the second silicon oxynitride film side. As a result, the trapped electrons remain near the interface between the second silicon oxynitride film and the first metal oxide layer, and the threshold voltage of the transistor shifts in the positive direction.

[0601] In this example, an insulating film that releases a lot of nitrogen oxide was used as the second silicon oxynitride film, and the influence of the composition of the first metal oxide layer on the characteristics of the transistor was confirmed under conditions of a large amount of nitrogen oxide.

[0602] In order to evaluate the second silicon oxynitride film itself, a sample (sample L) was prepared in addition to samples J and K. Details of sample L will be described later.

[0603] Subsequently, a heat treatment was carried out for 1 hour at 370° C. in a nitrogen atmosphere using an oven.

[0604] Next, a second metal oxide film having a thickness of 20 nm was formed on the second silicon oxynitride film. The second metal oxide film was formed by a sputtering method using an In-Zn oxide target (In:Zn=2:3 [atomic ratio]). The pressure during film formation was 0.3 Pa, the source power was 4.5 kW, and the substrate temperature was room temperature. Oxygen gas (oxygen flow rate ratio 100%) was used as the film formation gas.

[0605] Next, a heat treatment was carried out for 1 hour at 370° C. in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate=4:1) using an oven device.

[0606] Subsequently, a copper film having a thickness of 100 nm and a third metal oxide film having a thickness of 30 nm were formed in this order on the second metal oxide film. The copper film and the third metal oxide film were formed by a sputtering method. The copper film was formed by a sputtering method using a Cu target. The third metal oxide film was formed by a sputtering method using an In-Zn oxide target (In:Zn=2:3 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power supply power was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 30%.

[0607] Next, a resist mask was formed on the third metal oxide film, and the second metal oxide film, the copper film, and the third metal oxide film were processed to form a second metal oxide layer, a copper layer, and a third metal oxide layer by wet etching.

[0608] Next, cleaning was performed. For cleaning, an aqueous solution of 85 weight % phosphoric acid diluted 500 times was used. The etchant temperature during etching was room temperature, and the processing time was 15 seconds.

[0609] Next, the second silicon oxynitride film was etched using the resist mask described above as a mask to form a second gate insulating layer. In addition, when forming the second gate insulating layer, the first silicon oxynitride film in the area not overlapping with the resist mask was removed to expose a part of the third silicon nitride film. Dry etching was used for processing. After this, the resist mask was removed.

[0610] Subsequently, a fourth silicon nitride film having a thickness of 100 nm and a third silicon oxynitride film having a thickness of 300 nm were formed in this order as protective layers covering the transistor.

[0611] The fourth silicon nitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm, nitrogen gas at a flow rate of 5000 sccm, and ammonia gas at a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350°C.

[0612] The third silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 290 sccm and dinitrogen monoxide gas with a flow rate of 4000 sccm. The pressure during film formation was 133 Pa, the film formation power was 1000 W, and the substrate temperature was 350 °C.

[0613] Subsequently, a part of the protective layer covering the transistor was opened, and a molybdenum film with a thickness of 100 nm was formed by sputtering. Then, it was processed to obtain source and drain electrodes. Thereafter, an acrylic resin film with a thickness of about 1.5 μm was formed as a planarization layer, and heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 250 °C, and 1 hour.

[0614] Through the above steps, samples J and K each having a transistor formed on a glass substrate were obtained.

[0615] <Fabrication of Samples 2> The method for fabricating sample L will be described.

[0616] A silicon oxynitride film with a thickness of 100 nm was formed on a glass substrate. The silicon oxynitride film was formed under the same film formation conditions as the second silicon oxynitride film used as the second gate insulating layer of samples J and K.

[0617] <TDS Analysis> Subsequently, the desorbed gas from sample L was evaluated using thermal desorption spectrometry (TDS). In the TDS analysis, the substrate temperature was raised from about 50 °C to about 520 °C at a heating rate of 30 °C / min at the substrate temperature.

[0618] The TDS analysis results of sample L are shown in Fig. 33. In Fig. 33, the TDS analysis results for a mass-to-charge ratio of 30 (M / z = 30) are shown on the left side, and the TDS analysis results for a mass-to-charge ratio of 32 (M / z = 32) are shown on the right side. The gas with a mass-to-charge ratio of 30 (M / z = 30) is mainly nitric oxide molecules. The gas with a mass-to-charge ratio of 32 (M / z = 32) is mainly oxygen molecules. Also, in Fig. 33, the horizontal axis represents the substrate temperature (Tsub), and the vertical axis represents the detection intensity (Intensity) for a mass-to-charge ratio of 30 (M / z = 30) or the detection intensity (Intensity) for a mass-to-charge ratio of 32 (M / z = 32).

[0619] As shown in Fig. 33, it was found that sample L releases oxygen and nitrogen oxides when heated. Therefore, it is considered that the second silicon oxynitride film used as the second gate insulating layer of the transistors (samples J and K) releases oxygen and also releases nitrogen oxides when heated.

[0620] <ID-VG characteristic evaluation> Subsequently, the ID-VG characteristics of the transistors (samples J and K) were measured.

[0621] For the measurement of the ID-VG characteristics of the transistors, the voltage applied to the gate electrode (hereinafter also referred to as the gate voltage (VG)) was applied in steps of 0.25 V from -15 V to +20 V. Also, the voltage applied to the source electrode (VS) was set to 0 V (comm), and the voltages applied to the drain electrode (VD) were set to 0.1 V and 5.1 V.

[0622] The ID-VG characteristics of sample J are shown in FIG. 34. The ID-VG characteristics of sample K are shown in FIG. 35. In FIG. 34 and FIG. 35, the conditions of the sample and the semiconductor layer 108 are shown. In FIG. 34 and FIG. 35, the conditions of the channel length and the channel width of the transistor are different in the vertical direction, and three types of transistors are shown, the channel length is 2 μm and the channel width is 3 μm, the channel length is 3 μm and the channel width is 3 μm, and the channel length is 6 μm and the channel width is 3 μm. In FIG. 34 and FIG. 35, the horizontal axis indicates the gate voltage (VG), the left vertical axis indicates the drain current (ID), and the right vertical axis indicates the saturation mobility (μFE) at VG=15V. The ID-VG characteristics of 20 transistors were measured for each sample.

[0623] Figures 34 and 35 respectively show the average value (ave) and 3σ of the threshold voltage (Vth) and saturation mobility (μFE) for each transistor size. σ indicates the standard deviation. Figures 34 and 35 also show the difference (2△L) between the design channel length and the effective channel length. The effective channel length was obtained by TLM (Transmission Line Model) analysis.

[0624] <Reliability evaluation> Next, the reliability of the transistors (samples J and K) was evaluated. In this example, a PBTS (Positive Bias Temperature Stress) test was performed in which a positive potential was applied to the gate with respect to the source potential and the drain potential, and the transistors were held at high temperature.

[0625] In the PBTS test, the substrate on which the transistor is formed was kept at 60°C, and a voltage of 0.1 V was applied to the drain of the transistor and 20 V to the gate, and this condition was maintained for one hour. The test was conducted in a dark environment. For the PBTS test, a transistor with a channel length of 2 μm and a channel width of 3 μm was used, and the variation in threshold voltage (ΔVth) before and after the gate bias stress test was evaluated.

[0626] The variation (ΔVth) in threshold voltage of samples J and K is shown in Fig. 36. In Fig. 36, the horizontal axis indicates the conditions of the sample and the semiconductor layer 108, and the vertical axis indicates the variation (ΔVth) in threshold voltage in the PBTS test.

[0627] 34, it was confirmed that the field-effect mobility (μFE) of Sample K, which is one embodiment of the present invention, was higher than that of Comparative Example Sample J. It is believed that Sample K exhibited high field-effect mobility (μFE) because a metal oxide film having the composition described in Embodiment 1 was used for a channel formation region.

[0628] As shown in FIG. 36, it was confirmed that, compared with sample J, sample K had a smaller variation in threshold voltage (ΔVth) in the PBTS test.

[0629] In Samples J and K, an insulating film that releases a lot of nitrogen oxide is used for the second silicon oxynitride film, so that the threshold voltage of the transistor is likely to shift in the positive direction due to the levels caused by nitrogen oxide. However, in Sample K, which is one embodiment of the present invention, a metal oxide film having the composition shown in Embodiment 1 is used for the second oxide layer in contact with the second silicon oxynitride film, which is considered to suppress trapping of electrons in the levels caused by nitrogen oxide, and thus the shift in the threshold voltage in the PBTS test is small.

[0630] As described above, it was confirmed that Sample K, which is one embodiment of the present invention, is a transistor which has both excellent electrical characteristics and high reliability.

[0631] The configuration shown in this embodiment can be used in appropriate combination with other embodiments and mode of implementation. EXAMPLES

[0632] In this example, a transistor corresponding to the transistor 100C_a shown in FIG. 12D was fabricated, and its drain current-gate voltage characteristics (ID-VG characteristics) and reliability were evaluated. In this example, samples (samples L and M1 to M4) with different configurations of the semiconductor layer 108 were fabricated. In addition, the insulating layer 110 functioning as a gate insulating layer had a single-layer structure.

[0633] In this embodiment, three types of transistors were fabricated: a transistor in which the conductive layer 106 (bottom gate electrode) is electrically connected to the conductive layer 112 (top gate electrode), a transistor in which the conductive layer 106 (bottom gate electrode) is electrically connected to the conductive layer 120a or the conductive layer 120b (source electrode), and a transistor that does not have a conductive layer 106 (bottom gate electrode).

[0634] <Sample preparation> The method for producing the samples L and M1 to M4 will be described.

[0635] First, a tungsten film having a thickness of 100 nm was formed on a glass substrate by sputtering, and then processed to obtain a first gate electrode (bottom gate).

[0636] Next, as a first gate insulating layer, a first silicon nitride film having a thickness of 50 nm, a second silicon nitride film having a thickness of 150 nm, a third silicon nitride film having a thickness of 100 nm, and a first silicon oxynitride film having a thickness of 3 nm were formed in this order. Since the description of Example 4 can be referred to for the formation of the first silicon nitride film to the third silicon nitride film and the first silicon oxynitride film, detailed description thereof will be omitted.

[0637] Next, a first metal oxide film was formed over the first silicon oxynitride film. Five samples (samples L and M1 to M4) were fabricated in which the first metal oxide film had different configurations. Samples M1 to M4 are embodiments of the present invention, and sample L is a comparative example.

[0638] The first metal oxide film of sample L was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the source power was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 30%. The thickness of the first metal oxide film was 25 nm.

[0639] The first metal oxide films of the samples M1 to M4 each had a stacked structure of a first oxide film and a second oxide film on the first oxide film. The first oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power source was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow ratio was 30%. The second oxide film was formed by a sputtering method using an In-Zn oxide target (In:Zn=4:1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power source was 3.0 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow ratio was 5%.

[0640] In sample M1, the first oxide film was 22 nm thick, and the second oxide film was 3 nm thick. In sample M2, the first oxide film was 20 nm thick, and the second oxide film was 5 nm thick. In sample M3, the first oxide film was 15 nm thick, and the second oxide film was 10 nm thick. In sample M4, the first oxide film was 10 nm thick, and the second oxide film was 15 nm thick.

[0641] Next, the first metal oxide film was processed into islands to form a first metal oxide layer.

[0642] Next, a heat treatment was performed for 2 hours at 370° C. in a clean dry air (CDA) atmosphere using an oven.

[0643] Next, a second silicon oxynitride film having a thickness of 140 nm was formed as a second gate insulating layer. The second silicon oxynitride film is a film that is resistant to the generation of nitrogen oxides (NO X The deposition conditions were such that there was a large amount of emission of .alpha., .alpha., .beta., .beta.=0 or more and .beta.=2 or less). Regarding the deposition of the second silicon oxynitride film, the description in Example 4 can be referred to, and therefore a detailed description thereof will be omitted.

[0644] In this example, an insulating film that releases a lot of nitrogen oxide was used as the second silicon oxynitride film, and the influence of the configuration of the first metal oxide layer on the characteristics of the transistor was confirmed under conditions where the amount of nitrogen oxide was large.

[0645] Subsequently, a heat treatment was carried out for 1 hour at 370° C. in a nitrogen atmosphere using an oven.

[0646] Subsequently, a second metal oxide film having a thickness of 20 nm was formed on the second silicon oxynitride film. Since the description of Example 4 can be referred to for the formation of the second metal oxide film, a detailed description thereof will be omitted.

[0647] Next, a heat treatment was carried out for 1 hour at 370° C. in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate=4:1) using an oven device.

[0648] Next, a copper film having a thickness of 100 nm and a third metal oxide film having a thickness of 30 nm were formed in this order on the second metal oxide film. The copper film and the third metal oxide film were formed by a sputtering method. The copper film and the third metal oxide film were formed by the same method as in Example 4, and therefore detailed description thereof will be omitted.

[0649] Next, a resist mask was formed on the third metal oxide film, and the second metal oxide film, the copper film, and the third metal oxide film were processed to form a second metal oxide layer, a copper layer, and a third metal oxide layer by wet etching.

[0650] Next, the second silicon oxynitride film was etched using the resist mask described above as a mask to form a second gate insulating layer. In addition, when forming the second gate insulating layer, the first silicon oxynitride film in the area not overlapping with the resist mask was removed to expose a part of the third silicon nitride film. Dry etching was used for processing. After this, the resist mask was removed.

[0651] Next, cleaning was performed. For cleaning, an aqueous solution of 85 weight % phosphoric acid diluted 500 times was used. The etchant temperature during etching was room temperature, and the processing time was 15 seconds.

[0652] Subsequently, as a protective layer covering the transistor, a fourth silicon nitride film having a thickness of 20 nm, a fifth silicon nitride film having a thickness of 80 nm, and a third silicon oxynitride film having a thickness of 300 nm were formed in this order.

[0653] The fourth silicon nitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm and nitrogen gas at a flow rate of 5000 sccm under a pressure of 200 Pa, a deposition power of 2000 W, and a substrate temperature of 350°C.

[0654] The fifth silicon nitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm, nitrogen gas at a flow rate of 5000 sccm, and ammonia gas at a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350°C.

[0655] The third silicon oxynitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 290 sccm and dinitrogen monoxide gas at a flow rate of 4000 sccm under a pressure of 133 Pa, a power of 1000 W, and a substrate temperature of 350° C.

[0656] Subsequently, a part of the protective layer covering the transistor was opened, and a molybdenum film with a thickness of 100 nm was formed by sputtering. After that, it was processed to obtain source and drain electrodes. Then, an acrylic resin film with a thickness of about 1.5 μm was formed as a planarization layer, and heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 250 °C, and 1 hour.

[0657] Through the above processes, samples L, M1 to M4, each having a transistor formed on a glass substrate, were obtained.

[0658] <ID-VG Characteristic Evaluation> Subsequently, the ID-VG characteristics of the transistors (samples L, M1 to M4) were measured.

[0659] For the measurement of the ID-VG characteristics of the transistors, the voltage applied to the gate electrode (hereinafter also referred to as the gate voltage (VG)) was applied in steps of 0.25 V from -15 V to +20 V. Also, the voltage applied to the source electrode (VS) was set to 0 V (comm), and the voltages applied to the drain electrode (VD) were set to 0.1 V and 5.1 V.

[0660] The ID-VG characteristics of samples L, M1 to M4 are shown in FIGS. 37 to 51. FIGS. 37 to 41 show the ID-VG characteristics of a transistor in which the conductive layer 106 (bottom gate electrode) is electrically connected to the conductive layer 112 (top gate electrode). FIGS. 42 to 46 show the ID-VG characteristics of a transistor in which the conductive layer 106 (bottom gate electrode) is electrically connected to the conductive layer 120a or the conductive layer 120b (source electrode). FIGS. 47 to 51 show the ID-VG characteristics of a transistor without the conductive layer 106 (bottom gate electrode).

[0661] 37 to 51 show the conditions of the sample and the semiconductor layer 108. Also, the conditions of the channel length and channel width of the transistor are different in the vertical direction, and three types of transistors are shown, a channel length of 2 μm and a channel width of 50 μm, a channel length of 3 μm and a channel width of 50 μm, and a channel length of 6 μm and a channel width of 50 μm. Also, in each of FIGS. 37 to 51, the horizontal axis shows the gate voltage (VG), the left vertical axis shows the drain current (ID), and the right vertical axis shows the saturation mobility (μFE) at VG=15 V. Note that the ID-VG characteristics of 20 transistors were measured for each sample.

[0662] 37 to 51 respectively show the average value (ave) and 3σ of the threshold voltage (Vth) and saturation mobility (μFE) for each transistor size, where σ represents the standard deviation.

[0663] <Reliability evaluation> Next, the reliability of the transistors (samples L, M1 to M4) was evaluated. In this example, a PBTS (Positive Bias Temperature Stress) test was performed in which a positive potential was applied to the gate relative to the source potential and drain potential and the transistors were held at high temperature, and an NBTIS (Negative Bias Temperature Illumination Stress) test was performed in which a negative potential was applied to the gate in a light irradiation environment and the transistors were held at high temperature.

[0664] In the PBTS test, the substrate on which the transistor is formed is kept at 60°C, a voltage of 0.1 V is applied to the drain of the transistor, and a voltage of 20 V is applied to the gate, and this condition is maintained for one hour. The test was performed in a dark environment.

[0665] In the NBTIS test, the substrate on which the transistor is formed is kept at 60°C, a voltage of 10 V is applied to the drain of the transistor, and a voltage of -20 V is applied to the gate, and this condition is maintained for one hour. The test was performed in a light irradiation environment (irradiating light of about 3400 lux with a white LED).

[0666] In the reliability test, a transistor with a channel length of 2 μm and a channel width of 3 μm was used to evaluate the variation in threshold voltage (ΔVth) before and after the gate bias stress test. Note that the transistor used had a conductive layer 106 (bottom gate electrode) electrically connected to the conductive layer 120a or the conductive layer 120b (source electrode).

[0667] The variation (ΔVth) of the threshold voltage of samples L and M1 to M4 is shown in Fig. 52. In Fig. 52, the horizontal axis indicates the sample and the semiconductor layer 108, and the vertical axis indicates the variation (ΔVth) of the threshold voltage in the PBTS test and the variation (ΔVth) of the threshold voltage in the NBTIS test. Fig. 52 also shows the threshold voltage (initial Vth) of the transistor before the reliability test is performed.

[0668] 37 to 51, the field-effect mobility (μFE) of each of Samples M1 to M4 according to one embodiment of the present invention was confirmed to be higher than that of Comparative Example Sample L. It is believed that the high field-effect mobility (μFE) was exhibited by each of Samples M1 to M4 due to the use of a metal oxide film having the composition described in Embodiment 1 for a channel formation region.

[0669] 52, it was confirmed that the variation in threshold voltage (ΔVth) in the PBTS test was small for samples M1 to M4 compared to sample L which is a comparative example. It was also confirmed that the variation in threshold voltage (ΔVth) in the PBTS test was particularly small when the thickness of the In-Zn oxide was 5 nm or more. It is considered that the samples M1 to M4 which are one embodiment of the present invention use a metal oxide film having the composition shown in Embodiment 1 for the second oxide layer in contact with the second silicon oxynitride film, thereby suppressing the trapping of electrons at the level due to nitrogen oxide, and thus reducing the variation in threshold voltage in the PBTS test.

[0670] As described above, it was confirmed that the samples M1 to M4 which are embodiments of the present invention are transistors which have both excellent electrical characteristics and high reliability.

[0671] The configuration shown in this embodiment can be used in appropriate combination with other embodiments and mode of implementation. EXAMPLES

[0672] In this example, the crystallinity and the band gap of a metal oxide film that can be used in a semiconductor device according to one embodiment of the present invention were evaluated.

[0673] In this example, X-ray diffraction (XRD) analysis was performed on metal oxide films fabricated by different methods to evaluate their crystallinity. Similarly, band gaps were evaluated on metal oxide films fabricated by different methods. For the evaluation, samples (samples P1 to P8, Q1 to Q8) in which a metal oxide film having a thickness of 100 nm was formed on a glass substrate were used.

[0674] <Sample preparation> In the samples P1 to P8, the metal oxide films were formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=10:1:3 [atomic ratio]), and in the samples Q1 to Q8, the metal oxide films were formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=10:1:6 [atomic ratio]).

[0675] For samples P1 and Q1, the substrate temperature during deposition of the metal oxide film was room temperature (RT), and argon gas (oxygen flow rate ratio=0%) was used as the deposition gas.

[0676] For samples P2 and Q2, the substrate temperature during deposition of the metal oxide film was set to room temperature (RT), and a mixed gas of oxygen gas and argon gas was used as the deposition gas, with the oxygen flow rate ratio set to 10%.

[0677] For samples P3 and Q3, the substrate temperature during deposition of the metal oxide film was set to room temperature (RT), and a mixed gas of oxygen gas and argon gas was used as the deposition gas, with the oxygen flow rate ratio set to 33%.

[0678] For samples P4 and Q4, the substrate temperature during the formation of the metal oxide film was set to room temperature (RT). Oxygen gas (oxygen flow ratio = 100%) was used as the film-forming gas.

[0679] For samples P5 and Q5, the substrate temperature during the formation of the metal oxide film was set to 300 °C. Argon gas (oxygen flow ratio = 0%) was used as the film-forming gas.

[0680] For samples P6 and Q6, the substrate temperature during the formation of the metal oxide film was set to 300 °C. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow ratio was set to 10%.

[0681] For samples P7 and Q7, the substrate temperature during the formation of the metal oxide film was set to 300 °C. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow ratio was set to 33%.

[0682] For samples P8 and Q8, the substrate temperature during the formation of the metal oxide film was set to 300 °C. Oxygen gas (oxygen flow ratio = 100%) was used as the film-forming gas.

[0683] For all samples, the pressure during the formation of the metal oxide film was set to 0.4 Pa, and the power supply power was set to 200 W (DC).

[0684] <X-ray Diffraction Analysis> Next, X-ray diffraction (XRD) analysis of samples P1 to P8 and Q1 to Q8 was performed.

[0685] For the XRD analysis, the θ-2θ scan method was used. In the XRD analysis, Cu Kα rays (λ = 0.15418 nm) were used as the X-ray source, the scanning range was set to 2θ = 15 deg to 50 deg, the step width was set to 0.01 deg, and the scanning speed was set to 6.0 deg / min.

[0686] The XRD analysis results of samples P1 to P8 are shown in FIG. 53. The XRD analysis results of samples Q1 to Q8 are shown in FIG. 54. In FIG. 53 and FIG. 54, the substrate temperature (Tsub) during the formation of the metal oxide film is shown in the horizontal direction, and the oxygen flow ratio (O2) during the formation of the metal oxide film is shown in the vertical direction. In FIG. 53 and FIG. 54, the horizontal axis indicates the diffraction angle 2θ, and the vertical axis indicates the intensity of the diffracted X-rays. The scale of the vertical axis is different for each sample. In FIG. 53 and FIG. 54, 2θ=31 deg is shown by a dashed line as an auxiliary line.

[0687] As shown in Figures 53 and 54, a peak was observed near 2θ=31 deg in all samples, confirming that they had crystallinity. The broad peak near 2θ=24 deg is a peak caused by the glass substrate.

[0688] <Band gap evaluation> Next, the transmittance and reflectance of the samples P1 to P3 and Q1 to Q3 were measured, and the band gap (Eg) was calculated. The transmittance and reflectance were measured using a spectrophotometer.

[0689] The band gaps (Eg) of the samples P1 to P3 and Q1 to Q3 are shown in Fig. 55. In Fig. 55, the horizontal axis represents the oxygen flow rate ratio during the formation of the metal oxide film, and the vertical axis represents the band gap (Eg).

[0690] As shown in FIG. 55, it was confirmed that the band gap (Eg) of all the samples was about 2.5 eV.

[0691] The configuration shown in this embodiment can be used in appropriate combination with other embodiments and mode of implementation. EXAMPLES

[0692] In this example, the carrier concentration and mobility of a metal oxide film that can be used in a semiconductor device according to one embodiment of the present invention were evaluated.

[0693] In this example, Hall effect measurements were performed on metal oxide films fabricated by different methods, and the carrier concentration and mobility were evaluated. For the evaluation, samples (samples R1 to R12, S1 to S12) in which a metal oxide film with a thickness of 40 nm was formed on a glass substrate were used.

[0694] <Sample preparation> In the samples R1 to R12, the metal oxide films were formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=10:1:3 [atomic ratio]). In the samples S1 to S12, the metal oxide films were formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=10:1:6 [atomic ratio]).

[0695] For each of the samples R1 to R4 and S1 to S4, the substrate temperature during deposition of the metal oxide film was set to room temperature (RT), and argon gas (oxygen flow rate ratio=0%) was used as the deposition gas.

[0696] For each of Samples R5 to R8 and S5 to S8, the substrate temperature during deposition of the metal oxide film was set to room temperature (RT). A mixed gas of oxygen gas and argon gas was used as the deposition gas, and the oxygen flow rate ratio was set to 10%.

[0697] For each of Samples R9 to R12 and S9 to S12, the substrate temperature during deposition of the metal oxide film was set to room temperature (RT). A mixed gas of oxygen gas and argon gas was used as the deposition gas, and the oxygen flow rate ratio was set to 33%.

[0698] For all samples, the pressure during deposition of the metal oxide film was 0.4 Pa and the power source was 200 W (DC).

[0699] Next, a heat treatment was carried out using an oven.

[0700] Samples R1, R5, R9, S1, S5, and S9 were subjected to a heat treatment at 350° C. for 1 hour in a nitrogen gas atmosphere.

[0701] Samples R2, R6, R10, S2, S6, and S10 were heat-treated at 350°C for 1 hour in a nitrogen gas atmosphere, and then heat-treated at 350°C for 1 hour in an atmosphere of a mixed gas of nitrogen gas and oxygen gas (nitrogen gas flow rate: oxygen gas flow rate = 4:1).

[0702] Samples R3, R7, R11, S3, S7, and S11 were heat-treated at 450°C for 1 hour in a nitrogen gas atmosphere.

[0703] Samples R4, R8, R12, S4, S8, and S12 were heat-treated at 450°C for 1 hour in a nitrogen gas atmosphere, and then heat-treated at 450°C for 1 hour in an atmosphere of a mixed gas of nitrogen gas and oxygen gas (nitrogen gas flow rate: oxygen gas flow rate = 4:1).

[0704] <Hall effect measurement> Next, the Hall effect of samples R1 to R12 and S1 to S12 was measured.

[0705] The Hall effect measurement is a method of measuring electrical properties such as carrier density, mobility, and resistivity by utilizing the Hall effect in which an electromotive force appears in a direction perpendicular to both the current and the magnetic field by applying a magnetic field perpendicular to the direction of the current flowing through an object. In this example, the Hall effect measurement was performed at room temperature using the Van der Pauw method. For the Hall effect measurement, ResiTest manufactured by Toyo Technica Co., Ltd. was used.

[0706] The carrier concentrations of samples R1 to R12 are shown in Fig. 56A. The Hall mobilities of samples R1 to R12 are shown in Fig. 56B. The carrier concentrations of samples S1 to S12 are shown in Fig. 57A. The Hall mobilities of samples S1 to S12 are shown in Fig. 57B. In Figs. 56A and 57A, the horizontal axis represents the oxygen flow rate ratio during the formation of the metal oxide film, and the vertical axis represents the carrier density. In Figs. 56B and 57B, the horizontal axis represents the oxygen flow rate ratio during the formation of the metal oxide film, and the vertical axis represents the Hall mobility.

[0707] As shown in FIG. 56B and FIG. 57B, the Hall mobility of the sample of this example is 20 cm 2 / Vs or more.

[0708] The configuration shown in this embodiment can be used in appropriate combination with other embodiments and mode of implementation. [Explanation of symbols]

[0709] L1: Line, L2: Line, L3: Line, L4: Line, L5: Line, L6: Line, L7: Line, L8: Line, L9: Line, L10: Line, L11: Line, L12: Line, 10: Transistor, 10A: Transistor, 10B: Transistor, 10C: Transistor, 11: Range, 13: Range, 15: Range, 17: Range, 100: Transistor, 100_a: Transistor, 100_b: Transistor, 100A: Transistor, 100A_a: Transistor, 100A_b: Transistor, 100B: Transistor, 100B_a: Transistor, 100C: Transistor, 100C_a: Transistor, 100C_ b: transistor, 102: substrate, 103: insulating layer, 103a: insulating film, 103b: insulating film, 103c: insulating film, 103d: insulating film, 106: conductive layer, 108: semiconductor layer, 108a: semiconductor layer, 108b: semiconductor layer, 108f: metal oxide film, 108n: low resistance region, 110: insulating layer, 110a: insulating film, 110b: insulating film, 110c: insulating film, 112: conductive layer, 112f: conductive film, 114: metal oxide layer, 114f: metal oxide film, 116: insulating layer, 118: insulating layer, 120a: conductive layer, 120b: conductive layer, 140: impurity element, 141a: opening, 141b: opening, 142: opening

Claims

1. a semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, and a third conductive layer; the semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order on the first insulating layer; the semiconductor layer comprises indium, zinc, and oxygen; the semiconductor layer has a composition within a range connecting a first coordinate (1:0:0), a second coordinate (2:0:3), a third coordinate (14:4:21), a fourth coordinate (7:2:2), a fifth coordinate (14:7:1), a sixth coordinate (2:1:0), and the first coordinate, in this order, with straight lines in a ternary diagram showing the atomic ratios of indium, an element M, and zinc; The element M is at least one of gallium, aluminum, yttrium, and tin, the third insulating layer is in contact with an upper surface and a side surface of the first conductive layer and an upper surface of the second insulating layer; the second insulating layer is in contact with an upper surface and a side surface of the semiconductor layer; the second conductive layer is in contact with an upper surface of the semiconductor layer; the third conductive layer is in contact with an upper surface of the semiconductor layer; the second conductive layer contacts an upper surface of the third insulating layer; the third conductive layer contacts an upper surface of the third insulating layer; the second insulating layer contains oxygen; The third insulating layer includes nitrogen.

2. a semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a metal oxide layer, a third insulating layer, a second conductive layer, and a third conductive layer; the semiconductor layer, the second insulating layer, the metal oxide layer, and the first conductive layer are stacked in this order on the first insulating layer; the semiconductor layer comprises indium, zinc, and oxygen; the semiconductor layer has a composition within a range connecting a first coordinate (1:0:0), a second coordinate (2:0:3), a third coordinate (14:4:21), a fourth coordinate (7:2:2), a fifth coordinate (14:7:1), a sixth coordinate (2:1:0), and the first coordinate, in this order, with straight lines in a ternary diagram showing the atomic ratios of indium, an element M, and zinc; The element M is at least one of gallium, aluminum, yttrium, and tin, the third insulating layer is in contact with an upper surface and a side surface of the first conductive layer and an upper surface of the second insulating layer; the second insulating layer is in contact with an upper surface and a side surface of the semiconductor layer; the second conductive layer is in contact with an upper surface of the semiconductor layer; the third conductive layer is in contact with an upper surface of the semiconductor layer; the second conductive layer contacts an upper surface of the third insulating layer; the third conductive layer contacts an upper surface of the third insulating layer; the second insulating layer contains oxygen; The third insulating layer includes nitrogen.

3. In claim 1 or 2, the semiconductor layer has a region that does not overlap with the first conductive layer, The region comprises at least one of phosphorus, boron, magnesium, aluminum, and silicon.

4. In claim 3, The second insulating layer is in contact with the region of the semiconductor device.

5. In any one of claims 1 to 3, the second insulating layer includes silicon oxide; The third insulating layer comprises silicon nitride.

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