High-frequency amplifier

Abstract

To provide a stable high-frequency amplifier.SOLUTION: A high-frequency amplifier 1 comprises: an asymmetric Doherty amplifier 50 that has a carrier amplifier 54, and a peak amplifier 64 that starts an amplification operation in the case where an output of the carrier amplifier reaches a saturation region and has a saturation output that is different from the carrier amplifier; a driver amplifier 40 that drives the asymmetric Doherty amplifier; a branch circuit 51; and a phase adjustment circuit 61. An electric length from an input terminal of the driver amplifier to an output terminal of the carrier amplifier via the driver amplifier, the branch circuit, an input path on the carrier amplifier side, a path on the carrier amplifier side, and the carrier amplifier is set so that a phase difference between a signal input to the input terminal of the driver amplifier without passing the carrier amplifier and a signal that is fed back to the input terminal of the driver amplifier from the output terminal of the carrier amplifier becomes a negative feedback region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to high frequency amplifiers.

[0002] This application claims priority to Japanese Application No. 2020-002882, filed on January 10, 2020, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0003] In recent years, mobile communication systems such as mobile phones are becoming wider in bandwidth. For this reason, it is desirable for power amplifiers used in base station devices of the systems to have high power efficiency in wide frequency bands. As a power amplifier for achieving this high power efficiency, a Doherty amplifier having a carrier amplifier (also called a main amplifier) ​​and a peak amplifier is known. For example, Patent Document 1 discloses the structure of a Doherty amplifier (Doherty type amplifier). Note that a Doherty amplifier is usually connected to the rear stage of a driver amplifier. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2005 / 093948 Summary of the Invention

[0005] a first substrate carrying the carrier amplifier and the peak amplifier; and a second substrate carrying the driver amplifier, the branch circuit, and the phase adjustment circuit, wherein when the second substrate is stacked on the first substrate, an input terminal of the driver amplifier and an input terminal of the carrier amplifier are positioned to project onto each other, and an electrical length from the input terminal of the driver amplifier to the output terminal of the carrier amplifier is set to have a phase of (2n+1)×π, where n is an integer greater than or equal to 0. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a schematic diagram of a high-frequency amplifier according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a block diagram illustrating the high-frequency amplifier of FIG. [Diagram 3] FIG. 2 is a plan view of the upper part of FIG. [Figure 4] FIG. 2 is a plan view of the lower part of FIG. [Diagram 5] FIG. 2 is a circuit diagram of the driver amplifier shown in FIG. [Figure 6] FIG. 6 is a diagram for explaining the upper part corresponding to the circuit diagram of FIG. 5. [Figure 7] FIG. 2 is a circuit diagram of the Doherty amplifier shown in FIG. [Figure 8] The lower part corresponds to the circuit diagram of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Problems to be Solved by the Disclosure

[0007] Incidentally, when mounting a driver amplifier and a Doherty amplifier on a printed circuit board, if the driver amplifier, carrier amplifier, and peak amplifier are mounted on the same plane, a large-sized printed circuit board is required, making it difficult to miniaturize the amplifier. In this case, it is possible to mount the driver amplifier and the Doherty amplifier three-dimensionally. However, if the amplifier is configured in a two-story structure, for example, with the driver amplifier on the upper level and the carrier amplifier and peak amplifier on the lower level, the driver amplifier and the carrier amplifier may be close to each other in the vertical direction. This can cause the driver amplifier to become unstable.

[0008] The present disclosure has been made in consideration of the above-mentioned circumstances, and has an object to provide a stable high-frequency amplifier.

[0009] According to the present disclosure, a stable high-frequency amplifier can be provided. [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0010] a first substrate carrying the carrier amplifier and the peak amplifier; and a second substrate carrying the driver amplifier, the first substrate carrying the driver amplifier, the first branch circuit, and the second substrate carrying the phase adjustment circuit, wherein when the second substrate is stacked on the first substrate, an input terminal of the driver amplifier and an input terminal of the carrier amplifier are positioned to project onto each other, and an electrical length from the input terminal of the driver amplifier to the output terminal of the carrier amplifier is set to have a phase of (2n+1)×π, where n is an integer equal to or greater than 0.

[0011] For this reason, even if signal feedback (part of the output signal is returned from the output of the carrier amplifier to the input of the driver amplifier) ​​is applied, the driver amplifier will be in a range where instability does not occur (negative feedback area), and will not enter the positive feedback area. Therefore, the amplifier can be stabilized even if a two-story structure is adopted. (2) In one aspect of the high-frequency amplifier of the present disclosure, the phase difference between the high-frequency signal at the output terminal of the carrier amplifier and the high-frequency signal at the output terminal of the peak amplifier is in the range of π / 2 to 3π / 2.

[0012] Since the phase difference between the output signals of the carrier amplifier and the peak amplifier is in the range of π / 2 to 3π / 2, it is possible to minimize electromagnetic waves emitted to the outside from the carrier amplifier and the peak amplifier. (3) In one aspect of the high-frequency amplifier of the present disclosure, a grounded metal layer is disposed between the first substrate and the second substrate.

[0013] The grounded metal layer can block electromagnetic waves, so the first substrate is less susceptible to the effects of electromagnetic waves generated on the second substrate side, and the second substrate is less susceptible to the effects of electromagnetic waves generated on the first substrate side. (4) In one aspect of the high-frequency amplifier of the present disclosure, the first substrate has a planar shape that is projected onto the second substrate.

[0014] This allows the high-frequency amplifier to be miniaturized. (5) In one aspect of the high-frequency amplifier of the present disclosure, the peak amplifier is configured to have a greater saturated output than the carrier amplifier.

[0015] In a peak amplifier, the amount of phase shift required to obtain optimum matching is greater than in a carrier amplifier. [Details of the embodiment of the present disclosure] Specific examples of the high-frequency amplifier according to the present disclosure will be described below with reference to the accompanying drawings, in which: Fig. 1 is a cross-sectional view showing a schematic diagram of a high-frequency amplifier according to one embodiment of the present disclosure.

[0016] The high-frequency amplifier 1 is mounted in a communication device such as a base station device of a mobile communication system, and is used, for example, to amplify a transmission signal. The high-frequency amplifier 1 has a base member La4. The base member La4 is a metal (eg, copper) plate that serves both as a heat sink and an external terminal, and is disposed on the printed circuit board 100 of the communication device.

[0017] A lower stage 10, an upper stage 20, and a lid member 25 are mounted on a base member La4. The lower stage 10 corresponds to the first substrate of the present disclosure, and the upper stage 20 corresponds to the second substrate of the present disclosure.

[0018] The lower stage 10 is sandwiched between the base member La4 and the upper stage 20. The lower stage 10 is composed of a first dielectric layer 11 (e.g., 0.25 to 0.35 mm thick), a third wiring layer La3 (e.g., 18 to 35 μm thick), and a second dielectric layer 12 (e.g., 0.8 to 1.0 mm thick). The first dielectric layer 11 is provided on the base member La4 (e.g., 0.25 mm thick), and the third wiring layer La3 has a high-frequency line pattern formed thereon with the base member La4 forming the GND plane as a reference voltage, and active components such as a carrier amplifier 54 and a peak amplifier 64, as well as an inductor L and a capacitor C mounted thereon.

[0019] The carrier amplifier 54 and the peak amplifier 64 each have a surface 54a, 64a on which a predetermined circuit is formed, and a back surface 54b, 64b located opposite the surface 54a, 64a on which, for example, no circuit is formed. The carrier amplifier 54 and the peak amplifier 64 are embedded in the first dielectric layer 11, and are mounted on the third wiring layer La3 with the surfaces 54a, 64a both facing upward. The back surfaces 54b, 64b are both arranged facing downward so as to contact the base member La4, and are fixed to the base member La4 coated with sintered silver paste or sintered copper paste.

[0020] The upper stage 20 is laminated on the lower stage 10. The upper stage 20 is composed of a third dielectric layer 23 (e.g., 0.25 to 0.35 mm thick), a first wiring layer La1 (e.g., 18 to 35 μm thick), and a fourth dielectric layer 24 (e.g., 0.25 to 0.35 mm thick). Between the third dielectric layer 23 and the lower stage 10 (second dielectric layer 12), a second wiring layer La2 is disposed. The second wiring layer La2 (e.g., 35 μm thick) is, for example, a copper solid surface, and serves as a GND surface for the first wiring layer La1 and as a shield against electromagnetic waves generated between the upper stage 20 and the lower stage 10. The second wiring layer La2 corresponds to the grounded metal layer of the present disclosure.

[0021] A high-frequency line pattern is formed on the first wiring layer La1, and active components such as a driver amplifier 40, an inductor L, and a capacitor C are mounted on the first wiring layer La1.

[0022] The driver amplifier 40 has a surface 40a on which a predetermined circuit is formed, and a back surface 40b located opposite the surface 40a on which, for example, no circuit is formed. The driver amplifier 40 is embedded in the fourth dielectric layer 24, and is mounted on the first wiring layer La1 with the surface 40a facing the lower stage 10. The back surface 40b is disposed facing upward so as to be spaced apart from the lower stage 10.

[0023] The upper stage 20 is covered with a metal lid member 25. Since the driver amplifier 40 is mounted by flip chip (face down), from the viewpoint of thermal management, the back surface 40b of the driver amplifier 40 is arranged facing upward so as to contact the heat dissipation portion (0th wiring layer La0) of the lid member 25. The heat dissipation portion (0th wiring layer La0) is formed of a thin metal thin film layer for signal wiring, like the other wiring layers. The heat dissipation portion (0th wiring layer La0) is in contact with the nearby GND vias (e.g., φ300 μm) (heat dissipation vias 15d, 15c, 15b, 15a). For this reason, a heat dissipation path (hereinafter referred to as a first heat dissipation path) is formed from the driver amplifier 40 to the base member La4.

[0024] The electrical path between the first wiring layer La1 of the upper stage 20 and the third wiring layer La3 of the lower stage 10 is secured by using signal vias 14b and 14a. The electrical path between the first wiring layer La1 and the second wiring layer La2 is secured by using signal via 17a. The electrical paths between the first wiring layer La1 and the base member La4 are secured by using signal vias 13c, 13b, and 13a. The electrical path between the third wiring layer La3 and the base member La4 is secured by using signal via 16a.

[0025] In this way, the upper stage 20 is stacked on the lower stage 10, and the driver amplifier 40, carrier amplifier 54 and peak amplifier 64 are mounted three-dimensionally, thereby achieving miniaturization of the high-frequency amplifier 1, with the module size being 6 mm square at its outermost end and 2.2 mm thick.

[0026] Furthermore, no wire bond connection is required in this high-frequency amplifier 1. Therefore, it is possible to carry out the manufacturing process on a large panel, for example, about 500 mm square, and from this panel, for example, 6,000 pieces of 6 mm square can be obtained, achieving a significant reduction in costs due to reduced processing costs and material costs.

[0027] Here, when the upper stage 20 described in FIG. 3 is superimposed on the lower stage 10 described in FIG. 4, the input terminal of the driver amplifier 40 and the input terminal of the carrier amplifier 54 face each other in the vertical direction, and the distance between the input terminal of the driver amplifier 40 and the input terminal of the carrier amplifier 54 is, for example, 1 mm or less in the vertical direction, which may be significantly shorter than when the driver amplifier 40 and the carrier amplifier 54 are arranged on the same plane. In such a physical arrangement, if the phase difference between the two input signals is in the range of ±π / 2, interference occurs between the two input signals, causing the operation of the driver amplifier 40 to become unstable. In more detail, the output signal of the driver amplifier 40 is fed back to the input, and the driver amplifier 40 may oscillate.

[0028] Therefore, in the high-frequency amplifier 1, the electrical length from the input terminal of the driver amplifier 40 to the output terminal of the carrier amplifier 54, that is, the electrical length taking into account the wiring length and the chip components, or the delay time for the input signal of wavelength λ to propagate from the input terminal of the driver amplifier 40 to the output terminal of the carrier amplifier 54, including the chip components along the way, is converted into the phase of the input signal of wavelength λ, and set to be (2n+1)×π between the terminals, where n is an integer equal to or greater than 0.

[0029] To achieve this, the path from the drain output of the driver amplifier 40 to the branch circuit 51 is made to make a large detour from the center to the right half of the upper stage 20, as shown by curved pattern 49 in FIG. 3, and the path from the output of the branch circuit 51 to the via 52a is deliberately made curved rather than straight, as shown by curved pattern 52 in FIG. 3.

[0030] In this way, the electrical length from the input terminal of the driver amplifier 40 to the output terminal of the carrier amplifier 54 is set to have a phase of (2n+1)×π. Therefore, even when signal feedback, that is, feedback that returns a part of the output signal from the output of the carrier amplifier 54 to the input of the driver amplifier 40, is applied, the driver amplifier 40 is in a range where instability does not occur, in other words, in a negative feedback region, and does not enter 2nπ, that is, a positive feedback region where instability occurs. Therefore, the amplifier 1 can be stabilized even if a two-story structure is adopted.

[0031] Furthermore, in a typical Doherty amplifier, the phase difference between the carrier amplifier and the peak amplifier is set to π / 2, but in the high-frequency amplifier 1, this phase difference is purposely set to π. In other words, the phase difference between the RF signal at the output terminal of the carrier amplifier 54 and the RF signal at the output terminal of the peak amplifier 64 is set in the range from π / 2 to 3π / 2.

[0032] As a result, the electromagnetic waves emitted from the carrier amplifier 54 and the electromagnetic waves emitted from the peak amplifier 64 cancel each other out in close proximity, so that the electromagnetic waves emitted to the outside of the high-frequency amplifier 1 can be kept small.

[0033] The phase of the carrier amplifier 54 and the phase of the peak amplifier 64 are synchronized at the output terminal RFout by the phase adjustment circuit 61 described in FIG. 3, the input matching circuits 53, 63 described in FIGS. 7 and 8, the output matching circuits 55, 65, and the transmission line TRL1 (the 90° transmission line 56a described in FIG. 4).

[0034] Fig. 2 is a block diagram for explaining the high-frequency amplifier of Fig. 1. Fig. 3 is a plan view of the upper part of Fig. 1, and Fig. 4 is a plan view of the lower part of Fig. 1.

[0035] The high-frequency amplifier 1 includes a driver amplifier 40 and a Doherty amplifier 50 provided in the subsequent stage of the driver amplifier 40, and is configured to be capable of amplifying signals in a frequency band of, for example, 5 GHz to 6 GHz.

[0036] The driver amplifier 40 amplifies an RF (Radio Frequency) signal defined by a wavelength λ input to an input terminal RFin to a degree that enables the Doherty amplifier 50 to amplify the signal to a predetermined transmission power.

[0037] The Doherty amplifier 50 includes a branching circuit 51, a phase adjustment circuit 61, a carrier amplifier 54, a peak amplifier 64, and Doherty networks 56, 66, and further amplifies the RF signal amplified by the driver amplifier 40 and outputs it from an output terminal RFout.

[0038] The driver amplifier 40, the carrier amplifier 54, and the peak amplifier 64 are amplifiers that use, for example, a GaN-HEMT (High Electron Mobility Transistor) as an amplifying element. The driver amplifier 40, the carrier amplifier 54, and the peak amplifier 64 each have a gate pad provided on one side of a rectangle, and a drain pad provided on the side opposite to the gate pad.

[0039] The driver amplifier 40, the carrier amplifier 54, and the peak amplifier 64 have source pads on both sides of the gate pad. However, the driver amplifier 40 has two source pads connected to the GND formed on the upper stage 20. On the other hand, the carrier amplifier 54 and the peak amplifier 64 have source pads connected to the base member La4 via the back surfaces 54b and 64b described in FIG. 1. This ensures the GND and forms a heat dissipation path from the carrier amplifier 54 and the peak amplifier 64 to the base member La4 (hereinafter, this will be referred to as a second heat dissipation path).

[0040] The second heat dissipation path is considered to have a superior heat dissipation property compared to the first heat dissipation path. In the second heat dissipation path, the source pads of the carrier amplifier 54 and the peak amplifier 64 are connected to the base member La4 via the rear surfaces 54b and 64b. The base member La4 is a plate made of metal (e.g., copper) and has a superior heat dissipation property. On the other hand, in the first heat dissipation path, the source pad of the driver amplifier 40 is connected to the heat dissipation part (the 0th wiring layer La0) via the rear surface 40b, and is connected to the base member La4 via a nearby GND via. The 0th wiring layer La0 is a metal thin film for signal wiring, and therefore is inferior in terms of heat dissipation efficiency to the base member La4, which is a plate made of metal (e.g., copper). As a result, since this heat dissipation part (the 0th wiring layer La0) determines the rate of heat conduction, the second heat dissipation path is considered to have a superior heat dissipation property compared to the first heat dissipation path.

[0041] With regard to the first heat dissipation path, it is believed that the heat dissipation efficiency of the first heat dissipation path can be improved by increasing the diameter of the heat dissipation vias 15a, 15b, 15c, and 15d, or by providing an additional heat dissipation via in parallel to the current heat dissipation path (first heat dissipation path) in the heat dissipation path connecting the heat dissipation section (0th wiring layer La0) and the base member La4.

[0042] The upper stage 20 shown in FIG. 3 and the lower stage 10 shown in FIG. 4 have substantially similar planar shapes, and both are formed, for example, with a 6 mm square.

[0043] As shown in FIG. 1, an RF signal input to an input terminal RFin (signal via 13a) via a signal wiring 101a provided on a printed circuit board 100 of a communication device passes through the base member La4 described in FIG. 1 and the lower stage 10, passes through the signal vias 13a, 13b, and 13c shown in FIG. 1, and is input to the lower left corner of the upper stage 20 as viewed in FIG. 3 without being connected to anywhere in the lower stage 10. The driver amplifier 40 is mounted near the lower left of the upper stage 20, and the RF signal amplified by the driver amplifier 40 makes a large turn as shown by a curved pattern 49 in FIG. 3. In detail, after heading toward the upper side of the upper stage 20 as viewed in FIG. 3, it turns right and proceeds left along this upper side, turns again right and heads toward the lower side of the upper stage 20, and reaches a branch circuit 51 provided in the same upper stage 20 as the driver amplifier 40.

[0044] The branch circuit 51 is, for example, a Wilkinson type distributor, and divides the RF signal amplified by the driver amplifier 40 equally into an input path on the peak amplifier side and an input path on the carrier amplifier side.

[0045] One of the RF signals distributed by the branch circuit 51 (input path on the carrier amplifier side) passes through a predetermined curved pattern 52 and travels from a via 52a formed near the bottom side of the upper stage 20 as viewed in Fig. 3 to the lower stage 10. This passes through a path similar to the signal path passing through the signal vias 14a and 14b shown in Fig. 1. In contrast, the other of the RF signals distributed by the branch circuit 51 (input path on the peak amplifier side) reaches a phase adjustment circuit 61 provided in the upper stage 20 in the same manner as the driver amplifier 40.

[0046] The phase adjustment circuit 61 delays the phase of the input signal to the peak amplifier 64 by a predetermined distributed constant. For example, it delays by 90°. The RF signal that has passed through the phase adjustment circuit 61 travels from a via 61a formed near the bottom side of the upper stage 20 as viewed in FIG. 3 toward the lower stage 10. This also passes through a path similar to the signal path that passes through the signal vias 14a and 14b shown in FIG.

[0047] In the present embodiment, an example has been described in which the phase adjustment circuit 61 is arranged between the branch circuit 51 and the peak amplifier 64, rather than between the branch circuit 51 and the carrier amplifier 54. However, the present disclosure is not limited to this example. For example, it is also possible to arrange the phase adjustment circuit between the branch circuit 51 and the carrier amplifier 54, rather than between the branch circuit 51 and the peak amplifier 64, to delay the phase of the input signal to the carrier amplifier 54.

[0048] The Doherty amplifier 50 of this embodiment is an asymmetric Doherty amplifier, and the peak amplifier 64 and the carrier amplifier 54 each show a different maximum output intensity for an input RF signal. For example, the peak amplifier 64 has a saturation output (size) about twice as large as that of the carrier amplifier 54, and the peak amplifier 64 starts amplifying when the output of the carrier amplifier 54 reaches a saturation region. Specifically, the carrier amplifier 54 operates in class AB or class B. The peak amplifier 64 operates in class C. When the instantaneous power is small, the carrier amplifier 54 operates and the peak amplifier 64 does not operate, thereby improving power efficiency. When the instantaneous power is large, both the carrier amplifier 54 and the peak amplifier 64 operate, so that the saturated power can be increased while maintaining high power efficiency.

[0049] As an example, the output of the driver amplifier 40, the carrier amplifier 54, and the peak amplifier 64 will be described below. The driver amplifier 40 has an output of 10 W, the carrier amplifier 54 has an output of 15 W, and the peak amplifier 64 has an output of 30 W. Here, the 10 W output refers primarily to the size of the FET, and does not mean that 10 W is always output, but rather that the FET has a size sufficient for 10 W output.

[0050] The RF signal amplified by the carrier amplifier 54 reaches a Doherty network 56 on the carrier amplifier side provided in the lower stage 10. This Doherty network 56 is provided with a 90° transmission line (also called a λ / 4 line) 56a. Therefore, the RF signal amplified by the carrier amplifier 54 is output via the 90° transmission line 56a from an output terminal RFout provided in the upper right corner of the lower stage 10 as viewed in FIG. 4 after being combined with an output signal from a peak amplifier 64 (described later).

[0051] On the other hand, the RF signal amplified by the peak amplifier 64 reaches a Doherty network 66 on the peak amplifier side provided in the lower stage 10, where it is combined with the output signal of the carrier amplifier 54 and is output from the output terminal RFout via a signal path passing through the signal via 16a shown in Fig. 1. The signal output from the output terminal RFout propagates from the high-frequency amplifier 1 to the outside via a signal wiring 101b provided on a printed circuit board 100 of the communication device as shown in Fig. 1. Note that the Doherty network 56 on the carrier amplifier side and the Doherty network 66 on the peak amplifier side correspond to the Doherty network of the present disclosure.

[0052] Fig. 5 is a driver amplifier circuit diagram of Fig. 1, and Fig. 6 is a diagram explaining the upper part corresponding to the circuit diagram of Fig. 5. Fig. 7 is a Doherty amplifier circuit diagram of Fig. 1, and Fig. 8 is a diagram explaining the lower part corresponding to the circuit diagram of Fig. 7.

[0053] 5 is input to the gate of the driver amplifier 40 via an input matching circuit 30 (a total of five components: inductor L1 and capacitors C1 to C4). A gate bias is supplied from a power supply Vg via an inductor L2. Capacitor C5 is a bypass capacitor for the power supply Vg, and resistor R1 is an adjustment resistor.

[0054] The drain output of the driver amplifier 40 is provided to a branch circuit 51 via an output matching circuit 41 (inductors L4, L5, and capacitors C7 to C9). A drain bias is supplied from a power supply Vd via an inductor L3. A capacitor C6 is a bypass capacitor for the power supply Vd.

[0055] Next, as shown in FIG. 7, in the branch circuit 51, the RF signal from the driver amplifier 40 is equally divided into a matching circuit including L11 and C24 and a matching circuit including C23, L12, and C29.

[0056] The RF signal, the phase of which has been adjusted by the matching circuit formed by L11 and C24, reaches the lower stage 10 via the curved pattern 52 and via 52a described with reference to FIG.

[0057] The RF signal that reaches the lower stage 10 is input to the gate of the carrier amplifier 54 via an input matching circuit 53 (capacitors C31, C11 to 14). A gate bias is supplied from a power supply Vg via an inductor L6. A capacitor C15 is a bypass capacitor for the power supply Vg, and a resistor R4 is an adjustment resistor.

[0058] The drain output of the carrier amplifier 54 is provided to a Doherty network 56 on the carrier amplifier side via a DC blocking capacitor C26. A drain bias is supplied from a power supply Vd via an inductor L9. A capacitor C21 is a bypass capacitor for the power supply Vd.

[0059] The Doherty network 56 on the carrier amplifier side is composed of an output matching circuit 55 composed of a transmission line TRL2 and a capacitor C25, and a transmission line TRL1 (including the 90° transmission line 56a described in Figure 4) for combining the output of the carrier amplifier 54 and the output of the peak amplifier 64.

[0060] On the other hand, the RF signal that has been equally divided by the branch circuit 51 and has its phase adjusted by the matching circuit consisting of C23, L12, and C29 has its phase further adjusted by the phase adjustment circuit 61 (inductors L15, L16, capacitor C32), reaches the lower stage 10 through the via 61a, and heads toward the peak amplifier 64.

[0061] The RF signal that reaches the lower stage 10 is input to the gate of the peak amplifier 64 via an input matching circuit 63 (inductor L7, capacitors C16 to C19). A gate bias is supplied from a power supply Vg via an inductor L8. Capacitor C20 is a bypass capacitor for the power supply Vg, and resistor R5 is an adjustment resistor.

[0062] The drain output of the peak amplifier 64 is provided to the Doherty network 66 on the peak amplifier side via a DC blocking capacitor C28. The drain bias is supplied from the power supply Vd via an inductor L10. The capacitor C22 is a bypass capacitor for the power supply Vd.

[0063] The Doherty network 66 on the peak amplifier side is configured with a two-stage configuration of a capacitor C27 and a capacitor C10, an output matching circuit 65 configured with a transmission line TRL3, and a transmission line TRL4.

[0064] Comparing the above-mentioned amplifier outputs, it is believed that the current consumption or power consumption, and the resulting heat generation, increase in the order of the driver amplifier 40, the carrier amplifier 54, and the peaking amplifier 64. In the high-frequency amplifier 1 of this embodiment, the peaking amplifier 64 and the carrier amplifier 54, which generate more heat, are connected to the second heat dissipation path with better heat dissipation efficiency, and the driver amplifier 40, which generates less heat, is connected to the first heat dissipation path. With this configuration, the high-frequency amplifier 1 can provide a small high-frequency amplifier with good heat dissipation properties.

[0065] In the high-frequency amplifier 1, the peak amplifier 64 and the carrier amplifier 54 are connected to the second heat dissipation path, and the driver amplifier 40 is connected to the first heat dissipation path. Therefore, as shown in FIG. 1, an RF signal input to the input terminal RFin (signal via 13a) passes through the lower stage 10 from the base member La4, passes through the signal vias 13a, 13b, and 13c shown in FIG. 1, and is input to the lower left corner of the upper stage 20 as viewed in FIG. 3 without being connected to anywhere in the lower stage 10. In addition, the RF signal distributed by the branch circuit 51 is input to the peak amplifier 64 and the carrier amplifier 54 provided in the lower stage 10, and passes through a path similar to the signal path passing through the signal vias 14a and 14b shown in FIG. 1. By passing through these signal paths, the high-frequency amplifier 1 can provide a small-sized high-frequency amplifier with good heat dissipation.

[0066] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0067] 1...high frequency amplifier, 10...lower stage, 11...first dielectric layer, 12...second dielectric layer, 13a, 13b, 13c, 14a, 14b, 16a, 17a...signal via, 15a, 15b, 15c, 15d...heat dissipation via, 20...upper stage, 23...third dielectric layer, 24...fourth dielectric layer, 25...cover, 30...input matching circuit, 40...driver amplifier, 40a...front surface, 40b...rear surface, 41...output matching circuit, 49...curved pattern, 50...Doherty amplifier, 51...branch circuit, 52...curved pattern, 52a...via, 53...input matching circuit, 54...carrier amplifier, 54a...front surface, 54b...rear surface, 55...output matching circuit, 56, 66...Doherty amplifier network, 56a...90° transmission line, 61...phase adjustment circuit, 61a...via, 63...input matching circuit, 64...peak amplifier, 64a...front surface, 64b...back surface, 65...output matching circuit, 100...printed circuit board, 101a, 101b...wiring on the printed circuit board, La0...0th wiring layer (heat dissipation section), La1...1st wiring layer, La2...2nd wiring layer, La3...3rd wiring layer, La4...base member, RFin...input terminal, RFout...output terminal, L, L1 to L12, L15, L16...inductors, C, C1 to C29, C31, C32...capacitors, R1, R3 to R5...resistors, TRL1 to TRL4...transmission lines, Vd, Vg...power supplies.

Claims

1. an asymmetric Doherty amplifier including a carrier amplifier and a peak amplifier having a saturated output different from that of the carrier amplifier, the peak amplifier starting an amplifying operation when the output of the carrier amplifier reaches a saturated region, and amplifying an input high-frequency signal having a wavelength λ; a driver amplifier that drives the asymmetric Doherty amplifier; a branching circuit that branches the high-frequency signal amplified by the driver amplifier into an input path on the peak amplifier side and an input path on the carrier amplifier side; a phase adjustment circuit provided in either one of the path on the peak amplifier side or the path on the carrier amplifier side, delaying either a phase of an input signal to the peak amplifier or a phase of an input signal to the carrier amplifier; a first substrate on which the carrier amplifier and the peak amplifier are mounted; a second substrate on which the driver amplifier, the branch circuit, and the phase adjustment circuit are mounted; The second substrate and the first substrate are stacked one on top of the other, a signal input to the input terminal of the driver amplifier via the branch circuit, the input path on the carrier amplifier side, the path on the carrier amplifier side, and the carrier amplifier to the output terminal of the carrier amplifier, the signal input to the input terminal of the driver amplifier without passing through the carrier amplifier and the signal fed back from the output terminal of the carrier amplifier to the input terminal of the driver amplifier are set to be in a negative feedback region.

2. 2. The high-frequency amplifier according to claim 1, wherein at least a portion of the driver amplifier, an input matching circuit of the driver amplifier, and an output matching circuit of the driver amplifier, and at least a portion of the carrier amplifier, an input matching circuit of the carrier amplifier, and an output matching circuit of the carrier amplifier are positioned to project onto each other.

3. 2. The high-frequency amplifier according to claim 1, wherein at least a portion of the driver amplifier and at least a portion of the carrier amplifier are positioned to project onto each other.

4. 4. The high-frequency amplifier according to claim 1, wherein the electrical length is set to have a phase of (2n+1)×π, where n is an integer equal to or greater than 0.

5. 5. The high-frequency amplifier according to claim 1, wherein a phase difference between the high-frequency signal at the output terminal of the carrier amplifier and the high-frequency signal at the output terminal of the peak amplifier is in a range from π / 2 to 3π / 2.

6. 6. The high-frequency amplifier according to claim 1, further comprising a grounded metal layer disposed between the first substrate and the second substrate.

7. The high-frequency amplifier according to claim 1 , wherein the first substrate has a planar shape projected onto the second substrate.

8. 8. The high-frequency amplifier according to claim 1, wherein the peak amplifier is configured to have a saturated output greater than a saturated output of the carrier amplifier.

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