Chip-based service processing method and device, storage medium and electronic equipment

Abstract

To disclose a chip-based service processing method and device, a storage medium, and electronic equipment.SOLUTION: A chip comprises at least two subsystems conforming to a first function security level. A service processing method of the chip comprises the steps of: determining a first service conforming to a second function security level, which is higher in rank than the first function security level; determining first to-be-operated data corresponding to the first service; computing, by each of the at least two sub systems, the first to-be-operated data, to obtain first computation results corresponding to the at least two subsystems, respectively; determining a matching relationship between the first computation results corresponding to the at least two subsystems, respectively; and processing the first service based on the matching relationship.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to functional safety technology, and in particular to a chip-based business processing method, device, storage medium, and electronic device. [Background technology]

[0002] Functional safety is generally about avoiding unacceptable risks caused by functional failures of a system. In the field of driving, there are multiple tasks with functional safety levels. Currently, tasks with high functional safety levels generally need to be realized by dedicated chips, but the dedicated chips have poor performance and cannot support tasks with high functional safety levels and relatively complex tasks. Summary of the Invention [Problem to be solved by the invention]

[0003] The present disclosure provides a chip-based business processing method, device, storage medium and electronic device to support business with a high functional safety level by hardware with a low functional safety level, and thus utilize the large computing power of the hardware with a low functional safety level to support business with a high functional safety level and relatively complex business. [Means for solving the problem]

[0004] According to one aspect of an embodiment of the present disclosure, there is provided a chip-based business processing method, the chip including at least two subsystems conforming to a first functional safety level, the chip-based business processing method comprising: determining a first operation conforming to a second functional safety level, the second functional safety level being ranked higher than the first functional safety level; determining first computation target data corresponding to the first task; a step of computing the first computation target data by the at least two subsystems, respectively, to obtain first computation results corresponding to the at least two subsystems; determining a matching relationship between the first calculation results corresponding to the at least two subsystems; and processing the first task based on the matching relationship.

[0005] According to another aspect of an embodiment of the present disclosure, there is provided a chip-based business processing device, the chip including at least two subsystems conforming to a first functional safety level, the chip-based business processing device comprising: a first determination module for determining a first operation conforming to a second functional safety level, the second functional safety level being ranked higher than the first functional safety level; a second determination module for determining first computation target data corresponding to the first task determined by the first determination module; a first calculation module for calculating the first calculation target data determined by the second determination module, respectively, by the at least two subsystems, to obtain first calculation results corresponding to the at least two subsystems; a third determination module for determining a matching relationship between the first calculation results obtained by the first calculation module and corresponding to the at least two subsystems respectively; and a first processing module for processing the first business determined by the first determination module based on the matching relationship determined by the third determination module.

[0006] According to yet another aspect of an embodiment of the present disclosure, there is provided a computer-readable storage medium having a computer program stored therein, the computer program being used to execute a business processing method based on the above-mentioned chip.

[0007] According to yet another aspect of an embodiment of the present disclosure, there is provided an electronic device, the electronic device comprising: A processor; a memory for storing instructions executable by the processor; The processor is used to read and execute the executable instructions from the memory to realize the business processing method based on the above chip.

[0008] According to yet another aspect of an embodiment of the present disclosure, a computer program product is provided, the computer program product comprising instructions, when executed by a processor, for performing the business processing method based on the above chip. Effect of the Invention

[0009] According to the chip-based task processing method, device, storage medium, electronic device, and program product provided in the above embodiments of the present disclosure, for a first task conforming to a second functional safety level, at least two subsystems in the chip can calculate first computation target data corresponding to the first task, respectively, to obtain first computation results corresponding to the at least two subsystems. Based on the matching relationship between the first computation results corresponding to the at least two subsystems, respectively, an appropriate processing method can be adopted to process the first task. For example, when the matching relationship is used to characterize that each of the first computation results among the N first computation results has a relatively high degree of agreement, the appropriate processing method can be adopted to ensure the normal completion of the first task. When the matching relationship is used to characterize that each of the first computation results among the N first computation results does not have a relatively high degree of agreement, the appropriate processing method can be adopted to ensure the safety of the vehicle to which the chip belongs. Note that one safety requirement may be divided into two redundant safety requirements. For example, ASIL-D may be divided into ASIL-B(D) and ASIL-B(D). For example, ASIL-D may be divided into ASIL-C(D) and ASIL-A(D). In the embodiment of the present disclosure, at least two subsystems in the chip are compliant with a low functional safety level, and the chip is also compliant with a low functional safety level, for example, ASIL-B, but the at least two subsystems in the chip can be backed up by each other to achieve redundancy, so that the chip can support a task with a high functional safety level, for example, ASIL-D task. That is, the embodiment of the present disclosure can support a task with a high functional safety level by hardware with a low functional safety level, and thus can utilize the large computing power of the hardware with a low functional safety level to support a task with a high functional safety level and relatively complex task. [Brief description of the drawings]

[0010] [Figure 1]1 is a flowchart of a chip-based transaction processing method provided in some exemplary embodiments of the present disclosure. [Diagram 2] 1 is a flowchart of a method for computing first computation target data by at least two subsystems provided in some exemplary embodiments of the present disclosure; [Diagram 3] 11 is a flowchart of a chip-based transaction processing method provided in some further exemplary embodiments of the present disclosure. [Figure 4] 11 is a flowchart of a method for computing second target data by a second processor in a target subsystem provided in some exemplary embodiments of the present disclosure; [Diagram 5] 1 is a flowchart of a method for determining a matching relationship between first calculation results corresponding to at least two subsystems, respectively, provided in some exemplary embodiments of the present disclosure. [Figure 6A] 1A-1D are structural schematic diagrams of a chip in accordance with some exemplary embodiments of the present disclosure. [Figure 6B] 13A-13C are structural schematic diagrams of a chip according to some other exemplary embodiments of the present disclosure. [Figure 6C] 13A-13C are structural schematic diagrams of a chip according to some other exemplary embodiments of the present disclosure. [Figure 7] FIG. 2 is a structural schematic diagram of a business processing device based on the chip provided in some exemplary embodiments of the present disclosure. [Figure 8] FIG. 2 is a structural schematic diagram of a first computing module in some exemplary embodiments of the present disclosure. [Figure 9] FIG. 2 is a structural schematic diagram of a business processing device based on a chip provided in some other exemplary embodiments of the present disclosure. [Figure 10] FIG. 2 is a structural schematic diagram of a second computing module in some exemplary embodiments of the present disclosure. [Figure 11] FIG. 13 is a structural schematic diagram of a third determination module in some exemplary embodiments of the present disclosure. [Figure 12]1 is a structural schematic diagram of an electronic device provided in some exemplary embodiments of the present disclosure. [Figure 13] 1 is a structural schematic diagram of a chip provided in some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In order to interpret the present disclosure, exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. Obviously, the described embodiments are only some embodiments of the present disclosure, not all embodiments, and the present disclosure is not limited to the exemplary embodiments.

[0012] It should be noted that, unless otherwise specified, the relative arrangements of parts and steps, formulas and numerical values ​​described in these embodiments do not limit the scope of the present disclosure.

[0013] [Application Summary] In the field of driving, there are multiple functional safety level works. For example, ISO 26262, the functional safety standard for automobiles, determines the relevant definition for Automotive Safety Integration Level (ASIL), and relates to Quality Management (QM), five kinds of functional safety levels, namely ASIL-A, ASIL-B, ASIL-C and ASIL-D, where the rank of QM is lower than ASIL-A, the rank of ASIL-A is lower than ASIL-B, the rank of ASIL-B is lower than ASIL-C, and the rank of ASIL-C is lower than ASIL-D.

[0014] Currently, tasks with high functional safety levels generally need to be realized by dedicated chips, but the performance of the dedicated chips is poor and they cannot support tasks with high functional safety levels and relatively complex tasks. For example, tasks with a functional safety level of ASIL-D (which may be called ASIL-D tasks) need to be realized by dedicated chips, but due to the poor performance of the dedicated chips, they can usually only support simple ASIL-D tasks, but cannot support relatively complex ASIL-D tasks, making it difficult to meet actual needs.

[0015] [Example System] In order to facilitate understanding of the following chip-based business processing method, here we first introduce the chip related to the embodiment of the present disclosure.

[0016] Optionally, the chip according to the embodiment of the present disclosure may be a chip specialized for supporting the intelligent drive function, and may be called an intelligent drive dedicated chip. The intelligent drive function may include three parts, namely, a detection function, a planning function, and a control function. The detection function can be used to detect the environment around the vehicle, for example, to detect roads, static objects, dynamic objects, etc. The static objects may include, for example, buildings, traffic sign lights, etc. The dynamic objects may include, for example, obstacles such as pedestrians, riders, and other vehicles. The planning function can be used to plan according to the task requirements of the intelligent drive, for example, to plan whether to brake, turn, slow down, etc., or to plan an optimal driving route. The control function can be used to control the execution mechanism in the vehicle to realize the vehicle's braking, turning, slowing down, etc.

[0017] Optionally, the chip according to the embodiment of the present disclosure may include at least two subsystems conforming to a first functional safety level. The first functional safety level may be a functional safety level with a relatively low rank. For example, the first functional safety level may be ASIL-B. Also, for example, the first functional safety level may be QM. The at least two subsystems may be represented as N subsystems, where N may be an integer equal to or greater than 2. Conforming the N subsystems to the first functional safety level may be understood as the N subsystems being developed in accordance with the first functional safety level. All of the N subsystems may be subsystems for performing data calculations to assist in the realization of business processing.

[0018] The subsystems described in this disclosure may be referred to as hardware units and include at least corresponding hardware capable of implementing functional safety level functions, such as a processor, memory, peripheral modules, etc. In one example, N may be 2, and each subsystem among the N subsystems may include a processor, memory, peripheral modules, etc. The processor may be, for example, a Central Processing Unit (CPU). The memory may be, for example, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR) or a Static Random Access Memory (SRAM).

[0019] In some embodiments, the chip may further include a controller, which may be a small chip or device with processing capabilities, such as a microcontroller unit (MCU). In other examples, the MCU may be a controller installed outside the chip, and the embodiments of the present disclosure do not limit the positional relationship between the chip and the controller, and the following embodiments will be illustratively described using an example in which the chip includes the controller.

[0020] When processing a task with a high functional safety level, the first processors in the at least two hardware units can operate on first calculation target data corresponding to the task with the high level, and obtain first calculation results corresponding to the at least two hardware units, respectively. The controller can match the first calculation results corresponding to the at least two hardware units, and process the task with a high functional safety level based on the matching relationship.

[0021] In some examples, after the first processors in the at least two hardware units obtain first arithmetic results respectively corresponding to the at least two hardware units, they can respectively write the first arithmetic results to the DDR of each hardware unit, trigger an interrupt, and notify the MCU to read the first arithmetic results from the DDR of each hardware unit. After the MCU reads the first arithmetic results from the DDR of each hardware unit, it matches the first arithmetic results respectively corresponding to each hardware unit, and processes the first task according to the matching relationship.

[0022] In some other examples, the first processors in the at least two hardware units may write the first arithmetic results to the SRAM after obtaining the first arithmetic results corresponding to the at least two hardware units, respectively, trigger an interrupt, and notify the MCU to read the first arithmetic results corresponding to each hardware unit from the SRAM. After the MCU reads the first arithmetic results corresponding to each hardware unit from the SRAM, it matches the first arithmetic results corresponding to each hardware unit, and processes the first task according to the matching relationship.

[0023] [Exemplary Method] 1 is a flowchart of a chip-based transaction processing method provided in some exemplary embodiments of the present disclosure. The method shown in FIG. 1 may include steps 110, 120, 130, 140, and 150, and the method may be performed by a chip.

[0024] In step 110, a first operation is determined that complies with a second functional safety level, where the second functional safety level is ranked higher than the first functional safety level.

[0025] Optionally, the second functional safety level may be a functional safety level with a relatively higher rank than the first functional safety level. For example, the second functional safety level may be ASIL-C. Also, for example, the second functional safety level may be ASIL-D.

[0026] In the field of driving, there are a plurality of tasks related to the control of the running state of a vehicle. The plurality of tasks may be a plurality of tasks to be executed while the vehicle is running. The control of the running state of a vehicle may include, but is not limited to, controlling the running path, speed, acceleration, etc. of the vehicle, and controlling whether the vehicle brakes or not, whether the vehicle turns or not, etc. The first task conforming to the second functional safety level may be a task having very strict safety requirements among the plurality of tasks related to the control of the running state of the vehicle. If the second functional safety level is ASIL-C, the first task conforming to the second functional safety level may be called an ASIL-C task. If the second functional safety level is ASIL-D, the first task conforming to the second functional safety level may be called an ASIL-D task. In one example, the ASIL-D task may be an Automatic Emergency Braking (AEB) task.

[0027] In some examples, the first task may be referred to as a first task, and the functional safety level ranking of this first task is higher than the functional safety level ranking of at least two subsystems (i.e., at least two hardware units) in the chip.

[0028] In some embodiments, the hardware units for processing each task can be pre-configured based on the functional safety level of each task. For a task with a relatively high functional safety level (e.g., the first task), at least two hardware units may be pre-configured to perform this task, thereby ensuring that the hardware units with a lower functional safety level can support the tasks with a higher functional safety level and relatively more complex tasks.

[0029] For example, two hardware units, a hardware unit 10 and a hardware unit 20, may be pre-allocated for a first task, and when the first task is executed, a first processor 11 in the hardware unit 10 and a first processor 21 in the hardware unit 20 can respectively calculate first calculation target data corresponding to the first task. By having these two hardware units back up each other, the chip can be made to support operations with a high level of functional safety. The embodiment of the present disclosure does not limit the number of hardware units pre-allocated for the first task, and the number of hardware units executing the first task is related to the functional safety level of the first task.

[0030] In step 120, a first computation target data corresponding to a first task is determined.

[0031] Optionally, the first computation target data corresponding to the first task may be data that is required to participate in a computation to support the first task. In some examples, the first computation target data corresponding to the first task may be determined by a first processor in at least two hardware units pre-configured for the first task.

[0032] In general, the vehicle to which the chip belongs may be equipped with sensor devices including, but not limited to, a camera, a radar, a positioning sensor, etc. As an example, the camera may be a monocular camera or a binocular camera, the radar may be a laser radar or a millimeter wave radar, and the positioning sensor may be a positioning sensor based on the Global Navigation Satellite System (GNSS) or based on the Global Positioning System (GPS). The first computation target data corresponding to the first task may be data collected by at least some sensors in the sensor device. Or, the first computation target data corresponding to the first task is data obtained after performing a certain data processing on the data collected by at least some sensors in the sensor device.

[0033] In one example, the first task is an AEB task, and at least two hardware units are arranged in advance for the AEB task. A first processor included in each of the at least two hardware units may receive image data collected by a camera and point cloud data collected by a radar. That is, the first calculation target data corresponding to the first task may include image data collected by a camera and point cloud data collected by a radar. Alternatively, a first processor included in each of the at least two hardware units may receive image data collected by a camera and point cloud data collected by a radar, and fuse the image data collected by the camera and the point cloud data collected by the radar to obtain fusion data. That is, the first calculation target data corresponding to the first task may include fusion data.

[0034] In step 130, the first calculation target data is calculated by at least two subsystems, respectively, to obtain first calculation results corresponding to the at least two subsystems, respectively.

[0035] Alternatively, the at least two subsystems may be represented as N subsystems. Each of the N subsystems may have M sets of code data arranged therein. N and M may be integers equal to or greater than 2. Each set of code data of the M sets of code data may correspond to one task of the second functional safety level, and each set of code data is used to characterize an arithmetic logic of the task corresponding to the set of code data. The arithmetic logic may be understood as a data calculation method that needs to be performed to support the realization of a task process, and the arithmetic logic may involve multiple arithmetic types, including but not limited to tensor calculation, vector calculation, etc. As an example, the tensor calculation may include a convolution calculation. The vector calculation may include a point-to-point elementwise calculation. In general, the arithmetic logic may be realized by an algorithm.

[0036] Optionally, for each of the N subsystems, the subsystem may determine code data for characterizing a computation logic corresponding to a first task from the M sets of code data arranged therein, and for convenience of explanation, the determined code data may be hereinafter referred to as the first code data. The subsystem executes the first code data to compute the first computation target data according to the computation logic corresponding to the first task, and obtains a first computation result corresponding to the subsystem. In this manner, N first computation results can be obtained that correspond one-to-one to the N subsystems.

[0037] In one example, the first task is an AEB task, and the calculation logic corresponding to the AEB task may be to calculate the distance between the vehicle to which the chip belongs and the vehicle ahead based on the first calculation target data, determine a magnitude relationship between this distance and a preset safety distance, and set this magnitude relationship as the first calculation result. Or, the calculation logic corresponding to the AEB task may be to calculate the distance between the vehicle to which the chip belongs and the vehicle ahead based on the first calculation target data, calculate a target speed of the vehicle to which the chip belongs (i.e., an adjusted speed of the vehicle to which the chip belongs) based on this distance and the preset safety distance, and set the target speed as the first calculation result.

[0038] In step 140, a matching relationship between the first calculation results corresponding to the at least two subsystems is determined.

[0039] In some embodiments, after at least two hardware units respectively calculate first calculation target data and obtain first calculation results respectively corresponding to the at least two hardware units, the first calculation results are respectively written to corresponding memories (e.g., DDR or SRAM), an interrupt is triggered, and a controller (e.g., MCU) is notified to respectively read the first calculation results respectively corresponding to the at least two hardware units from the memory, and the controller further determines a matching relationship of the first calculation results respectively corresponding to the at least two hardware units, and appropriately processes the first task based on the matching relationship.

[0040] Optionally, the N first operation results, which correspond one-to-one to the N subsystems, may be compared two by two to obtain a matching relationship, which may be used to characterize whether each of the N first operation results has a relatively high degree of agreement.

[0041] In step 150, a first transaction is processed based on the matching relationship.

[0042] Optionally, the first task may be processed in a processing manner adapted to the matching relationship.

[0043] When the matching relationship is used to characterize that each first calculation result among the N first calculation results has a relatively high consistency, a first type of processing method may be adopted to process the first task, where the first type of processing method may be a processing method that can ensure the successful completion of the first task.

[0044] For example, when the MCU determines that the first calculation results respectively corresponding to at least two hardware units have a relatively high consistency, the MCU can control the actuator to perform a corresponding operation to ensure successful completion of the first task.

[0045] When the matching relationship is used to characterize that each of the first calculation results among the N first calculation results does not have a relatively high degree of consistency, a second type of processing method may be adopted to process the first business, where the second type of processing method may be different from the first type of processing method, and the second type of processing method may be a processing method that can ensure the safety of the vehicle to which the chip belongs.

[0046] For example, when the MCU determines that the first calculation results respectively corresponding to at least two hardware units do not have a relatively high consistency, the MCU may control an actuator to perform a preset operation to ensure the safety of vehicle operation.

[0047] In an embodiment of the present disclosure, for a first task conforming to a second functional safety level, at least two subsystems in the chip calculate first computation target data corresponding to the first task, respectively, to obtain first computation results corresponding to the at least two subsystems. Based on a matching relationship between the first computation results corresponding to the at least two subsystems, an appropriate processing method can be adopted to process the first task. For example, when the matching relationship is used to characterize that each of the first computation results among the N first computation results has a relatively high degree of agreement, the first type of processing method can be adopted to ensure the normal completion of the first task. When the matching relationship is used to characterize that each of the first computation results among the N first computation results does not have a relatively high degree of agreement, the second type of processing method can be adopted to ensure the safety of the vehicle to which the chip belongs. Note that one safety requirement may be divided into two redundant safety requirements. For example, ASIL-D may be divided into ASIL-B(D) and ASIL-B(D). Also, for example, ASIL-D may be divided into ASIL-C(D) and ASIL-A(D). In an embodiment of the present disclosure, at least two subsystems in a chip are compliant with a low functional safety level, and the chip is also compliant with a low functional safety level, for example, compliant with ASIL-B, but the at least two subsystems in the chip can be backed up by each other to achieve redundancy, so that the chip can support a task with a high functional safety level, for example, ASIL-D task. That is, the embodiment of the present disclosure can support a task with a high functional safety level by hardware with a low functional safety level, and thus can utilize the large computing power of the hardware with a low functional safety level to support a task with a high functional safety level and relatively complex task.

[0048] 2 is a flowchart of a method for calculating a first calculation target data by at least two subsystems provided in some exemplary embodiments of the present disclosure. The method shown in FIG. 2 may include step 210 and step 220.

[0049] Optionally, in the method shown in FIG. 2, each subsystem of the at least two subsystems may include a first processor and a memory, and the memory may include a dedicated memory space corresponding to the first processor.

[0050] Optionally, the first processor may be a central processing unit. The memory may be a double data rate synchronous dynamic random memory. The memory may have a portion of space reserved specifically for the first processor, and in the process of performing data calculations to assist in the realization of business processing, this portion of space may only allow the first processor to access and store (i.e., write data and read data), and this portion of space may be a dedicated memory space corresponding to the first processor. The size of the dedicated memory space corresponding to the first processor may be arranged according to actual needs, and the present disclosure is not limited thereto.

[0051] In step 210, the first computation target data is stored in a dedicated storage space corresponding to each of the at least two subsystems.

[0052] Optionally, each of the at least two subsystems may further include a peripheral module or the like.

[0053] Optionally, for each subsystem of the at least two subsystems, the subsystem may obtain data collected by at least some sensors in the sensor device through the peripheral module, and based on this, the first processor may determine first computation target data and write the first computation target data into a dedicated memory space corresponding to the subsystem. The dedicated memory space corresponding to the subsystem may be a dedicated memory space corresponding to the first processor in the subsystem.

[0054] In step 220, a first processor of each of the at least two subsystems performs an operation on a first operation target data in a corresponding dedicated memory space, where any one of the first processors accesses and stores data in the corresponding dedicated memory space during the operation.

[0055] Selectively, for each subsystem of the at least two subsystems, a first processor in the subsystem may calculate first calculation target data in a dedicated memory space corresponding to the subsystem, and during the calculation, necessary data may be read from the dedicated memory space corresponding to the subsystem, and the data obtained by the calculation and required to be stored may be written to the dedicated memory space corresponding to the subsystem.

[0056] Since the first processors in different subsystems each calculate the first calculation target data in a corresponding dedicated memory space, and access and store data in the corresponding dedicated memory space during the calculation, it can be considered that the basic data (i.e., the first calculation target data) used in the calculation process of the different subsystems is independent of each other, and the memory spaces used are also independent of each other. In this way, the operating processes of the different subsystems are also independent of each other and do not affect each other, so that it is possible to ensure that at least two subsystems in the chip realize redundancy as backups for each other, and the chip can support operations with a high level of functional safety.

[0057] 3 is a flowchart of a chip-based transaction processing method provided in another exemplary embodiment of the present disclosure. The method shown in FIG. 3 may include steps 310, 320, 330, 340, and 350.

[0058] Optionally, in the method shown in FIG. 3, each subsystem among at least some of the at least two subsystems may include a second processor.

[0059] Optionally, each of at least some of the at least two subsystems may include at least one second processor. Like the first processor, the second processor may be a central processing unit.

[0060] In step 310, a second operation that complies with the first functional safety level is determined.

[0061] Optionally, the first functional safety level may be a relatively low-ranked functional safety level, for example, the first functional safety level may be ASIL-B.

[0062] In the field of driving, there are a number of tasks related to vehicle driving state control. The second task conforming to the first functional safety level may be a task that has less stringent safety requirements among the multiple tasks related to vehicle driving state control. For example, the second task may be a driving route planning task.

[0063] In some examples, the second task may be referred to as a second task, and the functional safety level ranking of this second task is the same as the functional safety level ranking of at least two subsystems (i.e., at least two hardware units) in the chip.

[0064] In some embodiments, a processor (eg, the second processor) may be pre-deployed for the second task because the functional safety level of the second task is relatively low.

[0065] In step 320, second computation target data corresponding to a second transaction is determined.

[0066] Alternatively, the second computation target data corresponding to the second task may be data that is required to participate in the computation to support the second task. The second computation target data corresponding to the second task may be data collected by at least some sensors in the sensor device. Alternatively, the second computation target data corresponding to the second task is data obtained after performing a certain data processing on the data collected by at least some sensors in the sensor device.

[0067] In some examples, a second processor may determine second computed data corresponding to the second task, e.g., the second processor may receive data related to the second task collected by at least some sensors in the sensor device.

[0068] In step 330, a second processor in the target subsystem calculates second target data and obtains a second calculation result, where the target subsystem is one of the subsystems including the second processor.

[0069] Optionally, the number of subsystems including the second processor among the at least two subsystems may be one or more, and which subsystem including the second processor is to be designated as the target subsystem for supporting the processing of the second task may be pre-arranged or may be determined by a software scheduling algorithm.

[0070] Optionally, second code data may be arranged in the target subsystem, and the second code data may be used to characterize an arithmetic logic corresponding to the second task (for ease of explanation, hereinafter referred to as a first arithmetic logic). In this way, the target subsystem can execute the second code data to operate the second operation target data according to the first arithmetic logic, and obtain a second operation result.

[0071] In one example, the second task is a driving route planning task, and the computational logic corresponding to the driving route planning task (i.e., the first computational logic) may detect the environment around the vehicle to which the chip belongs based on the second computation target data, obtain the environmental detection results, predict the future positions and actions of obstacles, etc. based on the environmental detection results, plan a driving route for the vehicle to which the chip belongs based on the predicted future positions and actions of the obstacles, and use this driving route as the second computation result.

[0072] In some examples, the second processor may process a second task based on the second computation result after determining the second computation result. For example, the second processor may trigger an interrupt after determining the second computation result, read the second computation result from a memory (e.g., DDR), and notify the first processor to process the second task. For example, the second processor may further check the second computation result after determining the second computation result, obtain a check result, and process the second task based on the check result.

[0073] In step 340, the second calculation result is checked to obtain a check result.

[0074] Optionally, by executing step 310, in addition to determining the second task conforming to the first functional safety level, a third task conforming to the first functional safety level may be determined. The third task may be a task related to the second task. For example, the second task may be a travel route planning task, and the third task may be a task for determining whether or not a collision risk exists on a travel route obtained based on the travel route planning task. In response to this, third calculation target data corresponding to the third task may be calculated to obtain a third calculation result.

[0075] In some examples, a check result corresponding to the second operation result may be inferred based on a check result obtained by checking the third operation result.

[0076] When the third calculation result is used to characterize the occurrence of a collision on the driving path, it is determined that the check on the second calculation result does not pass, and a check result can be obtained to characterize that the check on the second calculation result does not pass.

[0077] When the third calculation result is used to characterize that no collision occurs on the driving path, it is determined that the check on the second calculation result passes, and a check result can be obtained to characterize that the check on the second calculation result passes.

[0078] In step 350, a second transaction is processed based on the check result.

[0079] In some optional embodiments of the present disclosure, step 350 may include, in response to the check result characterizing that the check on the second operation result is passed, executing a business operation corresponding to the second operation, and, in response to the check result characterizing that the check on the second operation result is not passed, performing another operation on the second operation target data by a second processor in the target subsystem to obtain a third operation result, and processing the second operation based on the third operation result.

[0080] Optionally, in addition to the second code data for characterizing the first arithmetic logic, the target subsystem may also be arranged with third code data for characterizing another arithmetic logic (hereinafter, for ease of explanation, may be referred to as the second arithmetic logic) different from the first arithmetic logic corresponding to the second task. The second arithmetic logic characterized by the third code data may be more conservative (e.g., more advantageous for ensuring driving safety) than the first arithmetic logic characterized by the second code data. In one example, both the second arithmetic logic and the first arithmetic logic may be realized by an algorithm, and the algorithm for realizing the second arithmetic logic may be more complicated than the algorithm for realizing the first arithmetic logic.

[0081] If the check result is characterized in that the check on the second calculation result is passed, it can be determined that the reasonableness and reliability of the second calculation result meets the requirements. Then, a business operation corresponding to the second business can be executed. For example, the second business may be a driving route planning business, and the business operation corresponding to the second business may be to control the vehicle to which the chip belongs to drive according to the driving route obtained based on the driving route planning business.

[0082] If the check result is characterized in that the check on the second operation result is not passed, it can be determined that the rationality and reliability of the second operation result does not meet the requirements. Then, the target subsystem can execute the third code data to operate the second operation target data according to the second operation logic to obtain a third operation result. The second task can be processed based on the third operation result.

[0083] In one example, the second task is a travel route planning task, the second calculation result is a travel route L1, and the third calculation result is a travel route L2. Compared with the calculation logic for obtaining the travel route L1, the calculation logic for obtaining the travel route L2 is more conservative, so the travel route L2 may be considered to have a relatively high level of security. Then, the vehicle to which the chip belongs can be controlled to travel according to the travel route L2.

[0084] In this way, the second task can be processed by adopting an appropriate processing method with reference to the check result of the second calculation result, which is advantageous in ensuring the processing effect for the task with a low functional safety level. For example, by using a safer driving route, the driving safety of the vehicle to which the chip belongs can be ensured.

[0085] In some embodiments, after the third calculation result is obtained, the third calculation result can be checked, and the second task can be processed based on the checking result of the third calculation result.

[0086] In the embodiment of the present disclosure, for a second task conforming to a first functional safety level, a second processor in a target subsystem in the chip can calculate second computation target data corresponding to the second task, obtain a second computation result, and adopt an appropriate processing manner to process the second task based on a check result of the second computation result. For example, if the check result meets the requirements, a task operation corresponding to the second task can be executed to complete the second task. The second task is a task with a low functional safety level, and thus, by adopting the embodiment of the present disclosure, the chip can support tasks with a low functional safety level. That is, in the embodiment of the present disclosure, the chip can support tasks with a high functional safety level as well as tasks with a low functional safety level, and has a relatively wide application range and can better meet actual needs.

[0087] 4 is a flowchart of a method for computing second target data by a second processor in a target subsystem provided in some exemplary embodiments of the present disclosure. The method shown in FIG. 4 may include step 410 and step 420.

[0088] Optionally, in the method shown in FIG. 4, each subsystem of the at least two subsystems may include a memory, and the memory may include a general purpose storage space.

[0089] As explained above, the memory may include a dedicated memory space corresponding to the first processor, and the remaining memory space in the memory may be general purpose memory space.

[0090] In step 410, the second computation target data is stored in a target storage space, where the target storage space includes at least a portion of a general-purpose storage space corresponding to at least two subsystems respectively.

[0091] Alternatively, the target subsystem may obtain data collected by at least some sensors in the sensor device through the peripheral module, and the second processor may determine second calculation target data based on the data and write the second calculation target data to the target memory space. The target memory space may include all general-purpose memory spaces corresponding to the at least two subsystems. Or, the target memory space may include a part of the general-purpose memory space corresponding to the at least two subsystems. For ease of understanding, the following description will be given taking as an example a case where the target memory space includes all general-purpose memory spaces corresponding to the at least two subsystems.

[0092] Optionally, the second processor may write the second target data according to an address interleaving policy, which belongs to a dual channel memory technology and may involve two sets of memories, and data access and storage may be alternated between the two sets of memories, and when one set of memories accesses or stores data, the other set of memories is prepared for the next data access or storage, thereby improving the bandwidth and throughput rate of access and storage.

[0093] In one example, the at least two subsystems are two subsystems, and the general-purpose memory space in one of the subsystems is represented by general-purpose memory space K1, and the general-purpose memory space in the other subsystem is represented by general-purpose memory space K2. In this case, first, 128 bytes of data in the second calculation target data are written to the general-purpose memory space K1, and then another 128 bytes of data in the second calculation target data are written to the general-purpose memory space K2, and then, after writing yet another 128 bytes of data in the second calculation target data to the general-purpose memory space K1, yet another 128 bytes of data in the second calculation target data is written to the general-purpose memory space K2. The subsequent steps can be inferred accordingly, and no further explanation will be given here.

[0094] In step 420, a second processor in the target subsystem performs an operation on a second operation target data in the target memory space, where the second processor in the target subsystem accesses and stores data in the target memory space during the operation according to an address interleaving policy.

[0095] Optionally, the second processor in the target subsystem may operate on the second data to be operated on in the target storage space, and during the operation, the required data may be read from the target storage space, and the data obtained by the operation and required to be stored may be written to the target storage space. In the process of accessing and storing data in the target storage space, an address interleaving policy may be adopted, and specifically, the relevant description of the method for writing the second data to be operated on may be referred to above, and no further description will be given here.

[0096] In an embodiment of the present disclosure, a second processor in the target subsystem may calculate a second calculation target data in the target memory space, and during the calculation, access and store data in the target memory space according to an address interleaving policy, thereby effectively using general-purpose memory spaces in different subsystems, which is advantageous for improving the bandwidth of data access and storage, and can meet the performance requirements of operations with low functional safety levels.

[0097] 5 is a flowchart of a method for determining a matching relationship between first calculation results corresponding to at least two subsystems provided in some exemplary embodiments of the present disclosure. The method shown in FIG. 5 may include step 510, step 520, and step 530.

[0098] Optionally, in the method shown in FIG. 5, the first operation result corresponding to each subsystem of the at least two subsystems may include sub-operation results respectively corresponding to the at least two sub-operation steps.

[0099] As described above, the first task may be a task that has very strict safety requirements among a plurality of tasks related to vehicle driving state control. For example, the first task may be an AEB task, and the calculation logic corresponding to the AEB task may be to calculate the distance between the vehicle to which the chip belongs and the vehicle ahead based on the first calculation target data, determine the magnitude relationship between this distance and a preset safety distance, and set this magnitude relationship as the first calculation result. In this case, calculating the distance between the vehicle to which the chip belongs and the vehicle ahead may be regarded as one sub-calculation step (for convenience of explanation, hereinafter, may be referred to as the first sub-calculation step), and this distance may be a sub-calculation result corresponding to the first sub-calculation step. Also, determining the magnitude relationship between this distance and the preset safety distance may be regarded as another sub-calculation step (for convenience of explanation, hereinafter, may be referred to as the second sub-calculation step), and this magnitude relationship may be a sub-calculation result corresponding to the second sub-calculation step.

[0100] In step 510, a set consisting of first operation results respectively corresponding to at least two subsystems is partitioned to obtain subsets respectively corresponding to at least two sub-operation steps, where each subset corresponding to any one of the sub-operation steps includes at least two sub-operation results.

[0101] For example, when partitioning a set of first operation results respectively corresponding to at least two subsystems, the MCU may partition the first operation results respectively corresponding to the at least two subsystems according to at least two sub-operation steps to obtain sub-operation results respectively corresponding to the at least two sub-operation steps, where the sub-operation results corresponding to each sub-operation step may constitute a subset corresponding to the sub-operation step.

[0102] Alternatively, the at least two subsystems may be two subsystems, and the first operation result corresponding to one of the subsystems may be represented by operation result 1, and the first operation result corresponding to the other subsystem may be represented by operation result 2. The operation result 1 may include a sub-operation result A1 corresponding to the first sub-operation stage and a sub-operation result A2 corresponding to the second sub-operation stage. The operation result 2 may include a sub-operation result B1 corresponding to the first sub-operation stage and a sub-operation result B2 corresponding to the second sub-operation stage. Then, a set consisting of the operation result 1 and the operation result 2 may include the sub-operation result A1, the sub-operation result A2, the sub-operation result B1, and the sub-operation result B2. By dividing this set, a subset corresponding to the first sub-operation stage and a subset corresponding to the second sub-operation stage can be obtained. The subset corresponding to the first sub-operation stage may include the sub-operation result A1 and the sub-operation result B1. The subset corresponding to the second sub-operation stage may include the sub-operation result A2 and the sub-operation result B2.

[0103] In step 520, for each sub-operation step of the at least two sub-operation steps, a matching degree between each sub-operation result in the subset corresponding to this sub-operation step is determined.

[0104] Exemplarily, for each sub-operation stage among the at least two sub-operation stages, the MCU may determine a similarity between each sub-operation result among the at least two sub-operation results corresponding to this sub-operation stage, where the similarity between each sub-operation result among the at least two sub-operation results corresponding to this sub-operation stage is a matching degree between each sub-operation result in a subset corresponding to the sub-operation stage.

[0105] Alternatively, in the first sub-operation step, a similarity algorithm may be used to determine the similarity between the sub-operation result A1 and the sub-operation result B1, and the determined similarity may be taken as the matching degree between the sub-operation result A1 and the sub-operation result B1. In the second sub-operation step, a similarity algorithm may be used to determine the similarity between the sub-operation result A2 and the sub-operation result B2, and the determined similarity may be taken as the matching degree between the sub-operation result A2 and the sub-operation result B2.

[0106] In step 530, a matching relationship is determined based on the matching degrees respectively corresponding to the at least two sub-calculation steps.

[0107] Alternatively, if the matching degrees (e.g., similarity degrees) corresponding to the first sub-operation step and the second sub-operation step are both greater than a preset matching degree, the matching relationship may be used to characterize that the operation result 1 and the operation result 2 satisfy the preset matching condition, that is, the operation result 1 and the operation result 2 have a relatively high degree of agreement. For example, the preset matching degrees may be 80%, 85%, 90%, etc., and are not listed here one by one.

[0108] Alternatively, when the matching degree corresponding to at least one of the first sub-operation stage and the second sub-operation stage is lower than a predetermined matching degree, the matching relationship may be used to characterize that the operation result 1 and the operation result 2 do not satisfy the predetermined matching condition, i.e., the operation result 1 and the operation result 2 do not have a relatively high degree of consistency.

[0109] The number of sub-operation stages is not limited to two, and may be, for example, three, four, or more than four, and is not listed here. If the matching degrees corresponding to all the sub-operation stages are all greater than the preset matching degree, the matching relationship may be used to characterize that the first operation results corresponding to the at least two subsystems respectively satisfy the preset matching condition, otherwise, the matching relationship may be used to characterize that the first operation results corresponding to the at least two subsystems respectively do not satisfy the preset matching condition.

[0110] In an embodiment of the present disclosure, in the process of determining a matching relationship, not only may the sub-operation results obtained at the final stage be referred to, but also the sub-operation results obtained at an intermediate stage may be referred to. In this way, the data used to determine the matching relationship is richer and more diverse, which is advantageous for ensuring the rationality and reliability of the determined matching relationship.

[0111] In some embodiments, in the process of determining the matching relationship, only the sub-operation result obtained in the final stage may be used as a reference.

[0112] In some optional examples, step 150 may include a step of executing a business operation corresponding to a first business in response to the matching relationship characterizing that the first calculation results corresponding to the at least two subsystems, respectively, satisfy a predetermined matching condition, and a step of executing a predetermined security protection operation in response to the matching relationship characterizing that the first calculation results corresponding to the at least two subsystems, respectively, do not satisfy the predetermined matching condition.

[0113] Alternatively, when the matching relationship is used to characterize that the first calculation results respectively corresponding to the at least two subsystems satisfy a preset matching condition, the MCU may execute a task operation corresponding to the first task. That is, when the MCU determines that the first calculation results respectively corresponding to the at least two hardware units satisfy the preset matching condition, it indicates that the first calculation results have a relatively high degree of consistency, and then the MCU may control the corresponding actuator to execute a task operation corresponding to the first task. For example, the first task may be an AEB task, and the task operation corresponding to the first task may be an emergency brake.

[0114] Alternatively, when the matching relationship is used to characterize that the first calculation results respectively corresponding to the at least two subsystems do not meet the preset matching condition, the task operation corresponding to the first task may not be executed, and the preset safety protection operation may be executed. The preset safety protection operation may include, but is not limited to, suggesting that a person controls the vehicle, pull over to a road, etc. That is, when the MCU determines that the first calculation results respectively corresponding to the at least two hardware units do not meet the preset matching condition, it is indicated that the first calculation results do not have a relatively high degree of consistency, and then the MCU can control the actuator to execute a preset safety protection operation, such as a person controls the vehicle or pull over to a road, to ensure the driving safety of the vehicle.

[0115] In an embodiment of the present disclosure, by referring to the matching relationship, it is possible to rationally determine whether or not there is an abnormality in the business that needs to be processed, and based on the determination result, an appropriate processing method can be adopted to process the first business, thereby supporting business with a high level of functional safety while ensuring the safety of the vehicle to which the chip belongs.

[0116] In some alternative examples, as shown in FIG. 6A, the chip may include two subsystems that meet the functional safety level of ASIL-B. The subsystem on the left side of the two subsystems may be called the first subsystem, and the subsystem on the right side of the two subsystems may be called the second subsystem. The first subsystem may include CPU A, CPU C, Periph A, and DDR A. The second subsystem may include CPU B, CPU D, Periph B, and DDR B. Each of CPU A and CPU B may be a first processor. Each of CPU C and CPU D may be a second processor. Each of Periph A and Periph B may be a peripheral module. Each of DDR A and DDR B may be a memory.

[0117] For any one ASIL-D task, CPU A and CPU B can respectively calculate the calculation target data corresponding to the ASIL-D task (e.g., the above-mentioned first calculation target data) according to the calculation logic corresponding to the ASIL-D task. If the calculation results corresponding to CPU A and CPU B (e.g., the above-mentioned first calculation result) have a relatively high consistency, the task operation corresponding to the ASIL-D task can be executed.

[0118] For any one of the ASIL-B tasks, the CPU C or CPU D can calculate the calculation target data corresponding to the ASIL-B task (e.g., the second calculation target data described above) according to the calculation logic corresponding to the ASIL-B task. The CPU C or CPU D obtains the calculation result (e.g., the second calculation result described above) and executes the task operation corresponding to the ASIL-B task based on the calculation result.

[0119] In some examples, the chip may further include a controller (e.g., an MCU).

[0120] For any one ASIL-D task, as shown in FIG. 6B, taking the controller as an example of an MCU, CPU A can write corresponding arithmetic result to DDR A, trigger an interrupt, and notify the MCU to read corresponding arithmetic result from DDR A. CPU B can write corresponding arithmetic result to DDR B, trigger an interrupt, and notify the MCU to read corresponding arithmetic result from DDR B. After reading the arithmetic results corresponding to CPU A and CPU B from DDR A and DDR B respectively, the MCU further determines the matching relationship between the arithmetic results corresponding to CPU A and CPU B. If the MCU determines that the arithmetic results corresponding to CPU A and CPU B respectively (such as the first arithmetic result in the above) have a relatively high consistency, it can execute a task operation corresponding to this ASIL-D task.

[0121] As shown in FIG. 6B, taking the controller as an example of an MCU, CPU A can write corresponding arithmetic results to SRAM, trigger an interrupt, and notify the MCU to read corresponding arithmetic results from SRAM. CPU B can write corresponding arithmetic results to SRAM, trigger an interrupt, and notify the MCU to read corresponding arithmetic results from SRAM. After respectively reading the arithmetic results corresponding to CPU A and CPU B from SRAM, the MCU further determines the matching relationship between the arithmetic results corresponding to CPU A and CPU B. If the MCU determines that the arithmetic results corresponding to CPU A and CPU B respectively (such as the first arithmetic result in the above) have a relatively high consistency, it can execute the task operation corresponding to this ASIL-D task.

[0122] For any one of the ASIL-B tasks, CPU C or CPU D writes the corresponding calculation result to memory (e.g., DDR A or DDR B), triggers an interrupt, and notifies CPU A and CPU B to read the calculation result obtained by CPU C or CPU D from memory (e.g., the second calculation result in the above).

[0123] Alternatively, DDR A may include a dedicated memory space Q1 and a general-purpose memory space K1. DDR B may include a dedicated memory space Q2 and a general-purpose memory space K2. In the process of performing data calculations to support the realization of business processing, CPU A can access and store data only in the dedicated memory space Q1. In the process of performing data calculations to support the realization of business processing, CPU B can access and store data only in the dedicated memory space Q2. In the process of performing data calculations to support the realization of business processing, CPU C can not only access and store data in the general-purpose memory space K1, but also access and store data in the general-purpose memory space K2. In the process of performing data calculations to support the realization of business processing, CPU D can not only access and store data in the general-purpose memory space K1, but also access and store data in the general-purpose memory space K2.

[0124] In some alternative examples, as shown in FIG. 6C, a chip may include a first set of processors, a second set of processors, a third set of processors, a first set of memory, a second set of memory, and a bus module. The first set of processors may be used to support ASIL-B operations. The first set of processors may include at least one processor. The second set of processors and the third set of processors may cooperate with each other to support ASIL-D operations. The second set of processors and the third set of processors may each include at least one processor. The first set of memory and the second set of memory may each include at least one memory.

[0125] As an example, the first set of processors may include two CPUs, such as CPU C or CPU D in FIG. 6A. The second set of processors may include a single CPU, such as CPU A in FIG. 6A. The third set of processors may include a single CPU, such as CPU B in FIG. 6A. The first set of memories may include one or more DDRs, such as DDR A in FIG. 6A. The second set of memories may include one or more DDRs, such as DDR B in FIG. 6A.

[0126] Alternatively, both the first set of memories and the second set of memories may include a dedicated storage space and a general purpose storage space. The address range of the general purpose storage space in the first set of memories may be represented by address range A, and the address range of the dedicated storage space in the first set of memories may be represented by address range B. The address range of the general purpose storage space in the second set of memories may be represented by address range A, and the address range of the dedicated storage space in the second set of memories may be represented by address range C.

[0127] For ASIL-B tasks, the first set of processors can access and store data in address range A in the first set of memories and address range A in the second set of memories through the bus module, and thus the first set of processors can obtain all bus bandwidth resources and all storage resources, which is advantageous for realizing high performance computing.

[0128] For ASIL-D tasks, the second set of processors can access and store data in address range B through the first part of the bus module, and the third set of processors can access and store data in address range C through the second part of the bus module; in this way, the second set of processors can obtain some bus bandwidth resources and some storage resources, and the third set of processors can also obtain some bus bandwidth resources and some storage resources; the bus bandwidth resources obtained by the second set of processors and the bus bandwidth resources obtained by the third set of processors may come from different hardware paths, and the storage resources obtained by the second set of processors and the storage resources obtained by the third set of processors may come from different storage devices, which is advantageous for the second set of processors and the third set of processors to realize redundancy as backups for each other.

[0129] In some examples, the chip may further include an MCU (not shown in FIG. 6C ), which can read the operation results determined by the second set of processors and the third set of processors from the memory (for example, the MCU can read the operation results determined by the second set of processors and the third set of processors from Address range B and Address range C, respectively), and the MCU can match the operation results determined by the second set of processors and the third set of processors, obtain a matching relationship, and further perform corresponding processing for ASIL-D tasks based on the matching relationship.

[0130] As described above, by adopting the embodiments of the present disclosure, the requirements of ASIL-D tasks can be met by two independent ASIL-B hardware, so that the larger computing power of the ASIL-B hardware can be utilized to support relatively complex ASIL-D tasks and better meet the performance requirements of ASIL-B tasks.

[0131] [Example Device] FIG. 7 is a structural schematic diagram of a business processing device based on a chip provided in some exemplary embodiments of the present disclosure. The chip may include at least two subsystems that comply with a first functional safety level. The device shown in FIG. 7 may include: a first determination module 710 for determining a first task that complies with a second functional safety level, where the rank of the second functional safety level is higher than the rank of the first functional safety level; a second determination module 720 for determining first computation target data corresponding to the first task determined by the first determination module 710; a first computation module 730 for computing the first computation target data determined by the second determination module 720 by at least two subsystems respectively to obtain first computation results respectively corresponding to the at least two subsystems; a third determination module 740 for determining a matching relationship between the first computation results respectively corresponding to the at least two subsystems obtained by the first computation module 730; and a first processing module 750 for processing the first task determined by the first determination module 710 based on the matching relationship determined by the third determination module 740.

[0132] In some optional examples, the first processing module 750 includes a first processing sub-module for executing a business operation corresponding to a first business in response to the matching relationship determined by the third determination module 740 characterizing that the first calculation results corresponding to the at least two subsystems, respectively, satisfy a predetermined matching condition, or a second processing sub-module for executing a predetermined security protection operation in response to the matching relationship determined by the third determination module 740 characterizing that the first calculation results corresponding to the at least two subsystems, respectively, do not satisfy the predetermined matching condition.

[0133] In some alternative examples, each subsystem of the at least two subsystems includes a first processor and a memory, the memory including a dedicated storage space corresponding to the first processor.

[0134] As shown in FIG. 8, the first calculation module 730 includes a first memory submodule 810 for storing the first calculation target data determined by the second determination module 720 in a dedicated memory space corresponding to each subsystem among the at least two subsystems, and a first calculation submodule 820 for calculating the first calculation target data stored in the corresponding dedicated memory space by the first memory submodule 810 by each first processor of the at least two subsystems, wherein any one of the first processors accesses and stores data in the corresponding dedicated memory space during calculation.

[0135] In some alternative examples, each subsystem among at least some of the at least two subsystems includes a second processor.

[0136] As shown in FIG. 9, the apparatus provided in the embodiment of the present disclosure includes a fourth determination module 910 for determining a second task conforming to a first functional safety level, a fifth determination module 920 for determining second calculation target data corresponding to the second task determined by the fourth determination module 910, a second calculation module 930 for calculating the second calculation target data determined by the fifth determination module 920 by a second processor in a target subsystem to obtain a second calculation result, where the target subsystem is one of the subsystems including the second processor, the second calculation module 930 being one of the subsystems including the second processor, a check module 940 for checking the second calculation result obtained by the second calculation module 930 to obtain a check result, and a second processing module 950 for processing the second task based on the check result obtained by the check module 940.

[0137] In some alternative examples, each subsystem of the at least two subsystems includes a memory, the memory including a general purpose storage space.

[0138] As shown in FIG. 10, the second calculation module 930 includes a second storage submodule 1010 for storing the second calculation target data determined by the fifth determination module 920 in a target memory space, where the target memory space includes a general-purpose memory space corresponding to at least two subsystems respectively, and a second calculation submodule 1020 for calculating the second calculation target data stored in the target memory space by the second storage submodule 1010 by a second processor in the target subsystem, where the second processor in the target subsystem accesses and stores data in the target memory space according to an address interleaving policy during calculation.

[0139] In some optional examples, the second processing module 950 includes a third processing sub-module for executing a business operation corresponding to the second business in response to the check result obtained by the check module 940 characterizing that the check on the second calculation result is passed, or a fourth processing sub-module for performing another calculation on the second calculation target data by a second processor in the target subsystem in response to the check result obtained by the check module 940 characterizing that the check on the second calculation result is not passed, and processing the second business based on the third calculation result.

[0140] In some alternative examples, the first operation result corresponding to each subsystem of the at least two subsystems includes sub-operation results respectively corresponding to at least two sub-operation steps.

[0141] As shown in FIG. 11, the third determination module 740 includes a partitioning submodule 1110 for partitioning a set consisting of first calculation results corresponding to at least two subsystems obtained by the first calculation module 730, and obtaining subsets corresponding to at least two sub-calculation stages, where the subset corresponding to any one of the sub-calculation stages includes at least two sub-calculation results; a first determination submodule 1120 for determining, for each sub-calculation stage among the at least two sub-calculation stages, a matching degree between each sub-calculation result in the subset corresponding to this sub-calculation stage; and a second determination submodule 1130 for determining a matching relationship based on the matching degree corresponding to the at least two sub-calculation stages determined by the first determination submodule 1120.

[0142] In the device of the present disclosure, each of the selective embodiments, selective embodiments, and selective examples disclosed above can be flexibly selected and combined as necessary to achieve corresponding functions and effects, and will not be recited one by one in the present disclosure.

[0143] [Examples of electronic devices] FIG. 12 is a block diagram of an electronic device provided in some embodiments of the disclosure, where the electronic device 1200 includes one or more processors 1210 and memory 1220.

[0144] The processor 1210 may be a central processing unit (CPU) or other type of processing unit having data processing and / or instruction execution capabilities, and may control other components in the electronic device 1200 to perform desired functions.

[0145] The memory 1220 may include one or more computer program products, which may include various types of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or high-speed cache memory (cache). The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. The computer-readable storage media may store one or more computer program instructions, which the processor 1210 may execute to realize the methods of the embodiments of the present disclosure described above and / or other desired functions.

[0146] In one example, the electronic device 1200 may further include input devices 1230 and output devices 1240, where these components are interconnected by a bus system and / or other type of connection mechanism (not shown).

[0147] The input device 1230 may further include, for example, a keyboard, a mouse, various sensors, a touch screen, and the like.

[0148] The output device 1240 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network, and a remote output device connected thereto.

[0149] Of course, for simplicity, Fig. 12 shows only some of the components related to the present disclosure in the electronic device 1200, and omits components such as buses, input / output interfaces, etc. In addition, the electronic device 1200 may further include any other suitable components according to specific application situations.

[0150] FIG. 13 is a structural schematic diagram of a chip provided in some of the embodiments of the present disclosure. As shown in FIG. 13, the chip 1300 includes at least two hardware units 1310 that comply with a first functional safety level and a controller 1320.

[0151] At least two hardware units 1310 are used to determine a first task conforming to a second functional safety level and first computation target data corresponding to the first task, respectively, where the rank of the second functional safety level is higher than the rank of the first functional safety level.

[0152] The at least two hardware units 1310 are used to respectively operate on first operation target data and obtain first operation results respectively corresponding to the at least two hardware units 1310 .

[0153] The controller 1320 is used for determining a matching relationship between the first arithmetic results respectively corresponding to the at least two hardware units 1310, and processing a first task based on the matching relationship.

[0154] For example, the controller 1320 executes a task operation corresponding to a first task in response to the matching relationship characterizing that the first calculation results corresponding to the at least two hardware units 1310, respectively, satisfy a predetermined matching condition, or the controller 1320 executes a predetermined safety protection operation in response to the matching relationship characterizing that the first calculation results corresponding to the at least two hardware units 1310, respectively, do not satisfy the predetermined matching condition.

[0155] 13, each hardware unit 1310 of the at least two hardware units 1310 includes a first processor 1311 and a memory 1312, and the memory 1312 includes a dedicated storage space corresponding to the first processor 1311. The first processor 1311 is used to store first computation target data in the dedicated storage space and compute the first computation target data in the dedicated storage space corresponding to the first processor 1311, where the first processor 1311 accesses and stores data to the corresponding dedicated storage space during computation.

[0156] In some examples, among the at least two hardware units 1310, some hardware units may include a second processor 1313, while other hardware units may not include a second processor 1313, and each hardware unit 1310 among the at least two hardware units 1310 may both include a second processor 1313, and embodiments of the present disclosure are not limited in this regard.

[0157] As shown in FIG. 13, the at least one hardware unit 1310 includes a second processor 1313 .

[0158] The second processor 1313 is used to determine a second task conforming to the first functional safety level and second calculation target data corresponding to the second task, calculate the second calculation target data, obtain a second calculation result, and process the second task based on the second calculation result.

[0159] In some examples, after the second processor 1313 determines the second operation result, it can write the second operation result to the memory 1312, trigger an interrupt, notify the first processor 1311 to read the second operation result from the memory 1312, and process the second task.

[0160] In some examples, processing the second task based on the second operation result may include checking the second operation result, obtaining a check result, and processing the second task based on the check result.

[0161] Exemplarily, in response to the check result characterizing that the check on the second operation result is passed, a task operation corresponding to the second task is executed; or, in response to the check result characterizing that the check on the second operation result is not passed, a second processor calculates the second operation target data according to a second operation logic to obtain a third operation result, and processes the second task based on the third operation result.

[0162] In some examples, the memory 1312 in each hardware unit 1310 includes a general-purpose memory space.

[0163] The second processor 1313 is used to store the second computation target data in a target memory space, where the target memory space includes at least a portion of a general-purpose memory space corresponding to the at least two hardware units 1310 respectively.

[0164] The second processor 1313 is used to calculate second target data in the target memory space according to the first calculation logic, where the second processor 1313 accesses and stores data in the target memory space according to an address interleaving policy during the calculation.

[0165] In some examples, the first operation result corresponding to each hardware unit 1310 of the at least two hardware units 1310 includes sub-operation results respectively corresponding to at least two sub-operation stages.

[0166] The controller 1320 is used to classify the first operation results corresponding to the at least two hardware units 1310 respectively according to at least two sub-operation steps, obtain sub-operation results corresponding to the at least two sub-operation steps respectively, determine, for each sub-operation step among the at least two sub-operation steps, a similarity between each sub-operation result among the at least two sub-operation results corresponding to this sub-operation step, and determine a matching relationship based on the similarities corresponding to the at least two sub-operation steps respectively.

[0167] [Exemplary Computer Program Products and Computer-Readable Storage Media] In addition to the methods and apparatus described above, embodiments of the present disclosure may also be a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the method steps of the various embodiments of the present disclosure described in the "Exemplary Methods" section above of this specification.

[0168] The computer program product may be written with program code for carrying out operations of the disclosed embodiments in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and traditional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's device, as separate software packages, partly on the user's computing device and partly on a remote computing device, or entirely on a remote computing device or server.

[0169] Furthermore, an embodiment of the present disclosure may be a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform steps in the methods of the various embodiments of the present disclosure described in the "Exemplary Methods" section above of this specification.

[0170] The computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of readable storage media (a non-exhaustive list) include an electrical connection having one or more conductors, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical memory device, a magnetic memory device, or any suitable combination of the above.

[0171] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, the advantages, advantages, effects, etc. mentioned in the present disclosure are not limited but merely illustrative, and these advantages, advantages, effects, etc. are not necessarily possessed by each embodiment of the present disclosure. In addition, the specific details disclosed above are not limited but merely serve to serve as examples and to facilitate understanding, and the above details do not necessarily limit the present disclosure to be realized by the above specific details.

[0172] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and its equivalent technology, the present disclosure is also intended to include these modifications and variations.

Claims

1. A method of chip-based transaction processing carried out by a chip, comprising: The chip includes at least two hardware units that comply with a first functional safety level, and a business processing method based on the chip includes: determining a first task conforming to a second functional safety level, the second functional safety level being ranked higher than the first functional safety level; determining first computation target data corresponding to the first task; a step of computing the first operation target data by the at least two hardware units, respectively, to obtain first operation results corresponding to the at least two hardware units; determining a matching relationship between the first operation results corresponding to the at least two hardware units; and processing the first task based on the matching relationship.

2. The step of processing the first task based on the matching relationship includes: executing a task operation corresponding to the first task in response to the matching relationship characterizing that the first operation results respectively corresponding to the at least two hardware units satisfy a predetermined matching condition; 2. The chip-based business processing method of claim 1, further comprising: executing a predetermined security protection operation in response to the matching relationship characterizing that the first operation results respectively corresponding to the at least two hardware units do not satisfy a predetermined matching condition.

3. Each hardware unit of the at least two hardware units includes a first processor and a memory, the memory including a dedicated storage space corresponding to the first processor; The step of computing the first computation target data by the at least two hardware units, storing the first computation target data in the dedicated memory space corresponding to each hardware unit of the at least two hardware units; 2. The chip-based business processing method of claim 1, further comprising: a step of calculating the first calculation target data in the corresponding dedicated memory space by the first processor of each of the at least two hardware units, wherein any one of the first processors accesses and stores data in the corresponding dedicated memory space during calculation.

4. At least one of the hardware units includes a second processor; The chip-based transaction method includes: determining a second task that complies with the first functional safety level; determining second computation target data corresponding to the second task; a step of calculating the second calculation target data by the second processor to obtain a second calculation result; The chip-based business processing method according to claim 1 , further comprising: processing the second task based on the second calculation result.

5. Each hardware unit of the at least two hardware units includes a memory, the memory including a general purpose storage space; The step of computing the second computation target data by the second processor includes: storing the second computation target data in a target storage space, the target storage space including at least a portion of the general-purpose storage space corresponding to each of the at least two hardware units; 5. The chip-based business processing method of claim 4, further comprising: a step of computing the second computation target data in the target memory space according to a first computation logic by the second processor, wherein the second processor accesses and stores data in the target memory space according to an address interleaving policy during the computation.

6. The step of processing the second task based on the second calculation result includes: checking the second calculation result to obtain a check result; in response to the check result characterizing the check on the second operation result as passing, performing a task operation corresponding to the second task; 5. The chip-based business processing method of claim 4, further comprising: in response to the check result characterizing that the check on the second calculation result does not pass, the second processor calculates the second calculation target data according to a second calculation logic to obtain a third calculation result, and processes the second task based on the third calculation result.

7. the first operation result corresponding to each hardware unit of the at least two hardware units includes sub-operation results respectively corresponding to at least two sub-operation steps; determining a matching relationship between the first operation results corresponding to the at least two hardware units, partitioning the first operation result corresponding to the at least two hardware units according to the at least two sub-operation steps to obtain the sub-operation results corresponding to the at least two sub-operation steps; determining, for each sub-operation step of the at least two sub-operation steps, a degree of similarity between each of the sub-operation results of the at least two sub-operation results corresponding to the sub-operation step; and determining the matching relationship based on the similarity degrees respectively corresponding to the at least two sub-operation steps.

8. a controller and at least two hardware units conforming to a first functional safety level; The at least two hardware units are respectively used to determine a first task conforming to a second functional safety level and a first computation target data corresponding to the first task, and the rank of the second functional safety level is higher than the rank of the first functional safety level; the at least two hardware units are used to operate the first operation target data, respectively, and obtain first operation results corresponding to the at least two hardware units, respectively; The controller is used to determine a matching relationship between the first arithmetic results respectively corresponding to the at least two hardware units, and process the first task based on the matching relationship.

9. The controller: In response to the matching relationship characterizing that the first operation results respectively corresponding to the at least two hardware units satisfy a predetermined matching condition, performing a task operation corresponding to the first task; Or, 9. The chip of claim 8, wherein the matching relationship is used to execute a predetermined security operation in response to characterizing that the first operation results corresponding to the at least two hardware units respectively do not satisfy a predetermined matching condition.

10. Each hardware unit of the at least two hardware units includes a first processor and a memory, the memory including a dedicated storage space corresponding to the first processor, and the first processor: storing the first computation target data in the dedicated memory space; The chip of claim 8, used to calculate the first calculation target data in the dedicated memory space corresponding to the first processor, the first processor accessing and storing data in the corresponding dedicated memory space during calculation.

11. At least one of the hardware units includes a second processor, the second processor comprising: determining a second task conforming to the first functional safety level and second computation target data corresponding to the second task; Calculating the second calculation target data to obtain a second calculation result; The chip according to claim 8 , which is used to process the second task based on the second calculation result.

12. Each hardware unit of the at least two hardware units includes a memory, the memory includes a general purpose storage space, and the second processor: storing the second operation target data in a target storage space; used to operate on the second operation target data in the target storage space according to a first operation logic; 12. The chip of claim 11, wherein the target memory space includes at least a portion of the general-purpose memory space corresponding to each of the at least two hardware units, and the second processor accesses and stores data in the target memory space during operations according to an address interleaving policy.

13. The first operation result corresponding to each hardware unit of the at least two hardware units includes sub-operation results respectively corresponding to at least two sub-operation steps, and the controller: Partitioning the first operation result corresponding to the at least two hardware units according to the at least two sub-operation steps, and obtaining the sub-operation results corresponding to the at least two sub-operation steps, respectively; determining, for each sub-operation step of the at least two sub-operation steps, a similarity between each of the sub-operation results of the at least two sub-operation results corresponding to the sub-operation step; The chip according to claim 8 , further comprising: a processor for executing the at least one sub-operation step; a processor for executing the at least one sub-operation step;

14. A computer-readable storage medium storing a computer program used for executing a business processing method based on the chip according to any one of claims 1 to 7.

15. A processor; a memory for storing instructions executable by the processor; An electronic device, wherein the processor is used to read and execute the executable instructions from the memory to realize a business processing method based on the chip according to claim 1 .

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