Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device which can suppress degradation of conduction.SOLUTION: A silicon carbide semiconductor device includes: a first-conductivity silicon carbide semiconductor substrate 1; a first-conductivity first semiconductor layer 2; a second-conductivity second semiconductor layer 3; a first-conductivity first semiconductor region 7; a trench 18; a gate insulative film 9; a gate electrode 10; a first electrode 13; and a second electrode 14. In the first semiconductor layer 2, there is provided a plurality of ion injection layers 16 in parallel to a front surface of the silicon carbide semiconductor substrate 1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to silicon carbide semiconductor devices and methods of manufacturing silicon carbide semiconductor devices. [Background technology]

[0002] Patent Document 1 describes a technique for suppressing the expansion of stacking faults and reducing surge voltage in a trench MOSFET made of silicon carbide semiconductor. More specifically, an SLR region, which is a region in which the minority carrier lifetime is partially shortened, is provided in a part of the drift region of the trench MOSFET. The SLR region is doped with nitrogen, which is an n-type impurity, and vanadium to reduce the carrier lifetime. Patent Document 2 also describes a similar technique. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-094415 [Patent Document 2] JP 2020-004779 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the use of vanadium as a transition metal dopant is not commonly used in semiconductor manufacturing processes, and there are issues regarding the risk of metal contamination of the gate oxidation furnace when SiC epitaxial substrates containing vanadium, a metal impurity other than a dopant, are used in the gate oxidation process, as well as increased implementation costs.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can more simply suppress degradation due to electrical conduction. [Means for solving the problem]

[0006] A silicon carbide semiconductor device according to one aspect of the disclosure is as follows. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of a first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A trench is provided that penetrates the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. A gate electrode is provided inside the trench via a gate insulating film. A first electrode is provided on surfaces of the second semiconductor layer and the first semiconductor region. A second electrode is provided on a rear surface of the silicon carbide semiconductor substrate. A plurality of ion-implanted layers are provided in the first semiconductor layer parallel to the front surface of the silicon carbide semiconductor substrate. Effect of the Invention

[0007] Advantageous Effects of Invention According to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to an aspect of the present disclosure, there is an effect that degradation due to electrical conduction can be suppressed. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to an embodiment; [Diagram 2] 1 is a graph showing the results of simulating the ion implantation profiles of N, Al, and P ions into SiC. [Diagram 3] 3 is a graph showing the calculation results of the net concentration due to the difference between the implantation concentrations of N,Al and P,Al when co-doping is performed using the data of FIG. 2. [Figure 4] 1A to 1C are cross-sectional views (part 1) illustrating schematic diagrams of a silicon carbide semiconductor device according to an embodiment during manufacture. [Diagram 5] 5A to 5C are cross-sectional views (part 2) illustrating schematic diagrams of a silicon carbide semiconductor device according to the embodiment during manufacture. [Figure 6]5A to 5C are cross-sectional views (part 3) illustrating schematic configurations of the silicon carbide semiconductor device according to the embodiment during manufacture. [Figure 7] 4 is a cross-sectional view (part 4) illustrating a schematic diagram of a silicon carbide semiconductor device according to the embodiment during manufacture. FIG. [Figure 8] 5 is a cross-sectional view (part 5) illustrating a schematic diagram of a silicon carbide semiconductor device according to the embodiment during manufacture. FIG. [Figure 9] 6 is a cross-sectional view illustrating a silicon carbide semiconductor device according to the embodiment during its manufacture (part 6). FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] <Overview of the embodiment of the present disclosure> (1) A silicon carbide semiconductor device according to one aspect of the present disclosure is as follows. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of a first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A trench is provided penetrating the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. A gate electrode is provided inside the trench via a gate insulating film. A first electrode is provided on surfaces of the second semiconductor layer and the first semiconductor region. A second electrode is provided on a rear surface of the silicon carbide semiconductor substrate. A plurality of ion-implanted layers are provided in the first semiconductor layer parallel to the front surface of the silicon carbide semiconductor substrate.

[0010] According to the above disclosure, a plurality of ion implantation layers are formed in the drift layer (first semiconductor layer of the first conductivity type), +The drift layer is disposed parallel to the front surface of the starting substrate (a silicon carbide semiconductor substrate of the first conductivity type). This allows the lifetime of the drift layer to be shortened. This prevents the expansion of stacking faults when a large current flows through the body diode, and suppresses degradation in electrical conduction. Furthermore, shortening the lifetime of the drift layer reduces reverse recovery loss during switching, which in turn reduces switching loss.

[0011] (2) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (1), the ion-implanted layer may be a layer co-implanted with aluminum and nitrogen, aluminum and phosphorus, boron and nitrogen, boron and phosphorus, gallium and nitrogen, or gallium and phosphorus.

[0012] (3) Furthermore, in the silicon carbide semiconductor device according to the present disclosure described above in (1), the ion-implanted layer may be a layer into which aluminum and phosphorus are co-implanted.

[0013] According to the above disclosure, by co-doping Al and P, it is possible to flatten the net concentration profile of the implanted region with fewer implantation steps than by co-doping Al and N.

[0014] (4) In the silicon carbide semiconductor device according to the present disclosure, in any one of (1) to (3) described above, the ion-implanted layer may have a maximum and a minimum of a net concentration profile that are equal to or lower than an impurity concentration of the first semiconductor layer.

[0015] According to the above disclosure, the influence on Ron (on-resistance) and BV (breakdown voltage) can be reduced.

[0016] (5) Furthermore, in the silicon carbide semiconductor device according to the present disclosure described above in (1), the ion-implanted layer may be a layer implanted with ions of oxygen or a rare gas element.

[0017] According to the above disclosure, ion implantation of O (oxygen) and rare gas elements forms crystal defects that act as lifetime killers in the drift layer 2, shortening the lifetime of the drift layer 2, thereby suppressing the expansion of stacking faults when a large current is passed through the body diode, thereby suppressing current degradation. Furthermore, O (oxygen) has a pinning effect on crystal dislocations, and can suppress the expansion of stacking faults.

[0018] (6) Furthermore, in the silicon carbide semiconductor device according to this disclosure, in any one of (1) to (5) described above, the first semiconductor layer may have a total thickness of 10 μm or more, and the ion-implanted layer may have a thickness of 0.1 μm or more and 1 μm or less.

[0019] (7) A method for manufacturing a silicon carbide semiconductor device according to one aspect of the present disclosure is as follows. First, a first step is performed in which a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is formed on a front surface of a silicon carbide semiconductor substrate of a first conductivity type by repeating epitaxial growth and ion implantation. The first semiconductor layer includes a plurality of ion-implanted layers parallel to the front surface of the silicon carbide semiconductor substrate. Next, a second step is performed in which a second semiconductor layer of a second conductivity type is formed on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a third step is performed in which a first semiconductor region of a first conductivity type is selectively formed on a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a fourth step is performed in which a trench is formed that penetrates the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. Next, a fifth step is performed in which a gate electrode is formed inside the trench via a gate insulating film. Next, a sixth step is performed in which a first electrode is formed on surfaces of the second semiconductor layer and the first semiconductor region. Next, a seventh step is performed in which a second electrode is formed on the back surface of the silicon carbide semiconductor substrate.

[0020] <Foundational knowledge of this disclosure> First, the problems with conventional semiconductor devices will be described. Silicon carbide (SiC) is expected to be a next-generation semiconductor material to replace silicon (Si). A semiconductor element using silicon carbide as a semiconductor material (hereinafter referred to as a silicon carbide semiconductor device) has various advantages, such as the ability to reduce the resistance of the element in the on-state to one-hundredth of that of a conventional semiconductor element using silicon as a semiconductor material, and the ability to be used in higher temperature environments (200°C or higher). This is due to the characteristics of the material itself, that is, the band gap of silicon carbide is about three times larger than that of silicon, and the dielectric breakdown field strength is nearly one order of magnitude larger than that of silicon.

[0021] Silicon carbide semiconductor devices that have been commercially available to date include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) having a planar gate structure or a trench gate structure.

[0022] In conventional trench MOSFETs, the n-type drift layer is often formed as a single layer by epitaxial growth using nitrogen doping. This means that the lifetime is long, and when a large current flows through the body diode of a trench MOSFET, stacking faults may expand, causing degradation of electrical conductivity. Furthermore, reverse recovery loss during switching is large. This reverse recovery loss is one of the causes of switching loss in MOSFETs, and it can be said that switching loss can be reduced if reverse recovery loss can be reduced.

[0023] For this reason, in conventional trench MOSFETs, in order to pass a large current through the body diode, it is necessary to improve resistance to current degradation, and to reduce the amount of charge stored in the drift layer in order to reduce reverse recovery loss during switching.

[0024] Preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. In the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In addition, it is preferable that the description of the same or equivalent includes within 5% in consideration of variations in manufacturing.

[0025] (Details of the embodiment) A semiconductor device according to an embodiment that solves the above-mentioned problems will be described below. The semiconductor device according to the present disclosure is configured using a wide band gap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated (manufactured) using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a trench MOSFET 50 as an example. FIG. 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the embodiment. FIG. 1 shows only an active region of the trench MOSFET 50 through which a main current flows.

[0026] As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment has n + A drift layer (first semiconductor layer of first conductivity type) 2 is deposited on a first main surface (front surface), for example a (0001) surface (Si surface), of a starting substrate (silicon carbide semiconductor substrate of first conductivity type) 1.

[0027] n + The starting substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The drift layer 2 is + The starting substrate 1 is doped with a lower impurity concentration, for example, nitrogen. - The drift layer 2 is an n-type silicon carbide epitaxial layer. - The drift layer 2 may be called an n-type silicon carbide epitaxial layer. +A current diffusion layer 6 may be formed on the surface opposite to the starting mold substrate 1. The current diffusion layer 6 is + The impurity concentration is lower than that of the starting substrate 1 and higher than that of the drift layer 2. For example, the high concentration n - The current diffusion layer 6 may be called a carrier diffusion layer, a JFET layer, or a second drift layer. + The starting substrate 1, drift layer 2, current diffusion layer 6, and p-type base layer 3 (described later) are combined to form a silicon carbide semiconductor substrate.

[0028] 1, the drift layer 2 is composed of three layers. That is, the drift layer 2 includes, from the bottom, a first SiC layer 2a, a second SiC layer 2b, and a third SiC layer 2c. As described above, the first to third SiC layers 2a to 2c are made of low-concentration n - The first ion-implanted layer 16a is an n-type silicon carbide epitaxial layer on the surface side (upper side) of the first SiC layer 2a. + The third SiC layer 2c is formed on the surface of the first p-type starting substrate 1. Similarly, a second ion implantation layer 16b is formed on the surface side (upper side) of the second SiC layer 2b. In the following description, the first and second ion implantation layers 16a, 16b are collectively referred to as ion implantation layer 16. The ion implantation layers 16 may all be formed inside the drift layer 2 as shown in FIG. 1, or some of them may be exposed on the surface of the drift layer 2 (provided on the surface side of the third SiC layer 2c). In FIG. 1, no ion implantation layer is provided after the formation of the third SiC layer 2c because the first p-type ion implantation layer 16b is formed by ion implantation. + Type region 4 and 2p + This is because it is expected that crystal defects will diffuse into third SiC layer 2c from type region 5. If the effect of reducing the carrier lifetime is not sufficient, a third ion-implanted layer may be provided on the surface of third SiC layer 2c.

[0029] The ion implantation layer 16 is, for example, a layer in which a p-type dopant and an n-type dopant are co-implanted (co-doped). In this case, the combination of the p-type dopant and the n-type dopant is, for example, aluminum (Al) and nitrogen (N), Al and phosphorus (P), boron (B) and N, B and P, gallium (Ga) and N, or Ga and P. The ion implantation layer 16 preferably has a thickness of 0.1 μm or more and 1 μm or less. If the ion implantation layer 16 is shallower than this, the ion implantation layer 16 will disappear due to hydrogen etching during the subsequent epitaxial growth, and if it is deeper than this, an apparatus capable of performing ion implantation processing at a higher acceleration energy will be required, which will increase the cost of implantation.

[0030] In addition, in the ion implantation layer 16, in order to reduce the influence on the breakdown voltage and on-resistance, it is preferable that the p-type dopant (Al, B, Ga) and the n-type dopant (N, P) concentrations are approximately equal. Since the ion implantation layer 16 is provided in the drift layer 2, - It is preferable that the n-type dopant is implanted in the ion-implanted layer in a larger amount than the p-type dopant, and the net carrier concentration (compensation concentration) obtained by subtracting the concentration of the p-type dopant from the concentration of the n-type dopant is approximately equal to the carrier concentration in the remaining regions of the first to third SiC layers 2a to 2c that are not ion-implanted. More preferably, when the activation rate of each ion after activation annealing is clear, it is preferable to adjust the ion implantation concentration of each of the n-type dopant and the p-type dopant so that the net carrier concentrations of the n-type and the p-type are the same, taking the activation rate into consideration.

[0031] Furthermore, the total thickness of the drift layer 2 is preferably 10 μm or more. This allows a MOSFET with a breakdown voltage of 1.2 kV or more to be realized. For example, when two ion-implanted layers 16 are provided as shown in FIG. 1, the thicknesses of the first SiC layer 2a and the second SiC layer 2b are preferably 5 μm or more. This is because the diffusion length of the lifetime killer introduced by the ion-implanted layer 16 is estimated to be 4 μm or more, as described later. However, when the total thickness of the drift layer 2 is 20 μm or more, the thicknesses of the respective SiC layers constituting the drift layer 2 are preferably 10 μm or more. This is because performing four SiC epitaxial growths with a SiC layer thickness of 5 μm would result in an increase in manufacturing costs.

[0032] As described later, ion implantation layer 16 is formed in drift layer 2 by dividing the number of epitaxial film formations of drift layer 2 into multiple stages, ion implanting n-type dopants and p-type dopants into drift layer 2 before forming the next stage of epitaxial film, and then repeating the process of forming the next stage of epitaxial film.

[0033] In this way, by repeating the epitaxial deposition of the drift layer 2, the crystal defects that are generated during ion implantation and become lifetime killers are diffused as indicated by the arrow T in FIG. 1, thereby shortening the lifetime of the drift layer 2. The diffusion length of the crystal defects that become lifetime killers is estimated to be 4 μm or more. From this point of view, it is considered that the epitaxial film thickness per layer is preferably about 5 to 10 μm in order to sufficiently diffuse the lifetime killers in the depth direction of the epitaxial film. This diffusion of crystal defects occurs, for example, by heating during the crystal growth of the second SiC layer 2b after the first ion implantation layer 16a is formed in the first SiC layer 2a.

[0034] In the embodiment, the lifetime of the drift layer 2 is reduced, so that the expansion of stacking faults when a large current flows through the body diode is suppressed, current degradation can be suppressed, and switching loss can be reduced.

[0035] Fig. 2 is a graph showing the results of simulating the ion implantation profile of N, Al, and P ions into SiC. In Fig. 2, the horizontal axis shows the implantation depth of N, Al, and P ions in μm, and the vertical axis shows the implantation concentration in atoms / cm. 3 Figure 2 shows the results of implantation of N, Al, and P ions with a maximum acceleration energy of 700 keV and an implantation concentration of N, Al, and P ions of 3×10 16 atoms / cm 3 This is the result of a simulation performed under implantation conditions consisting of multiple stages of acceleration energy and dose, resulting in a box profile.

[0036] FIG. 3 is a graph showing the calculation results of the net concentration due to the difference in the implantation concentrations of N,Al and P,Al when co-doping is performed using the data in FIG. 2. In FIG. 3, the horizontal axis shows the implantation depth of N, Al, and P ions in μm. The vertical axis shows the net concentration in atoms / cm. 3 The net concentration is the difference between the n-type dopant and the p-type dopant, and Figure 3 shows two cases: N-Al (the value obtained by subtracting the Al concentration from the N concentration) and P-Al (the value obtained by subtracting the Al concentration from the P concentration).

[0037] Here, if the maximum and minimum of the net concentration profile of the ion implantation layer 16 are set to be equal to or lower than the impurity concentration of the drift layer 2, the effect on Ron (on-resistance) and BV (breakdown voltage) can be reduced. According to Fig. 3, the fluctuation of the net concentration is smaller when co-doping Al and P than when co-doping Al and N. Therefore, the net concentration profile of the implantation region can be flattened with fewer implantation steps when co-doping Al and P than when co-doping Al and N.

[0038] The ion-implanted layer 16 may be a layer implanted with ions of O (oxygen) or a rare gas element. The rare gas element may be, for example, neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe). In this case, the ion-implanted layer 16 preferably has a thickness of 0.1 μm or more and 1 μm or less. If the ion-implanted layer 16 is shallower than this, it will be lost by hydrogen etching during the subsequent epitaxial growth, and if it is deeper than this, an apparatus capable of performing ion implantation processing at a higher acceleration energy will be required, increasing the cost of implantation.

[0039] In addition, the implantation concentration of O (oxygen) or rare gas elements is 1×10, which can be implanted at room temperature (RT) without destroying the crystal structure of SiC. 16 cm -3 More than 2×10 17 cm -3 The implantation depth is arbitrary, but may be shallower for the purpose of utilizing diffusion.

[0040] Even in this case, the epitaxial film formation of the drift layer 2 is divided into multiple stages, and before the next stage of epitaxial film formation, O (oxygen) or a rare gas element is ion-implanted into the drift layer 2, and then the next stage of epitaxial film formation is repeated to form the drift layer 2.

[0041] Ion implantation of O (oxygen) and rare gas elements forms crystal defects in the drift layer 2, which act as lifetime killers. These crystal defects diffuse as indicated by arrow T in Figure 1, shortening the lifetime of the drift layer 2. Because the lifetime of the drift layer 2 is shortened, the expansion of stacking faults when a large current flows through the body diode is suppressed, current degradation can be suppressed, and switching losses can be reduced. Furthermore, O (oxygen) has a pinning effect on crystal dislocations, and can suppress the expansion of stacking faults.

[0042] The ion implantation layers for introducing the above-mentioned life-time killers utilize the common n-type dopants, p-type dopants, oxygen, and rare gases used in the manufacturing process of silicon carbide semiconductors, and have the advantage of being easy to introduce at normal cost.

[0043] n + A back electrode (second electrode) 14 is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor base) of the mold starting substrate 1. The back electrode constitutes a drain electrode. A drain electrode pad (second electrode) is provided on the surface of the back electrode.

[0044] A trench gate structure is formed on the first main surface side (p-type base layer 3 side) of the silicon carbide semiconductor substrate. + n from the surface on the first main surface side of the mold starting substrate 1 + The gate electrode 10 penetrates the p-type source region 7 and the p-type base layer 3 to reach the current spreading layer 6. A gate insulating film 9 is formed on the bottom and side walls of the trench 18 along the inner wall of the trench 18, and a gate electrode 10 is formed inside the gate insulating film 9 in the trench 18. The gate electrode 10 is insulated from the drift layer 2, the current spreading layer 6 and the p-type base layer 3 by the gate insulating film 9. A part of the gate electrode 10 may protrude from above the trench 18 (the source electrode pad 15 side) towards the source electrode pad 15.

[0045] The drift layer 2 and the current diffusion layer 6 are provided with a first p + Type region 4 and 2p + A mold region 5 is selectively provided. + The type region 4 reaches a position deeper on the drain side than the bottom of the trench 18. + The lower end (drain side end) of the mold region 4 is located closer to the drain side than the bottom of the trench 18. + The mold region 4 is provided between the trenches 18. As shown in FIG. + The type region 4 is a p ++ The p-type contact region 8 is in contact with the p ++It is also possible for the first p-type contact region 8 not to be in contact with the first p-type contact region 8. + The p-type region 4 is provided in a surface layer of the current spreading layer 6 and is in contact with the p-type base layer 3 .

[0046] 2nd p. + The lower end of the mold region 5 is located closer to the drain side than the bottom of the trench 18. + The mold region 5 is formed at a position facing the bottom of the trench 18 in the depth direction z. + The width of the mold region 5 is wider than the width of the trench 18. The bottom of the trench 18 is the second p + The p-type region 5 may extend between the p-type base layer 3 and the second p + The second p + It is not necessary for the first p to be in contact with the mold region 5. + Type region 4 and 2p + The mold region 5 is doped with, for example, aluminum (Al).

[0047] 1st p. + A part of the mold region 4 is extended to the trench 18 side to form a second p + In this case, the first p + A part of the mold region 4 is the first p + Type region 4 and 2p + The current diffusion layers 6 may be arranged alternately in a direction (hereinafter, referred to as a second direction) y perpendicular to the direction (hereinafter, referred to as a first direction) x in which the first and second mold regions 5 are arranged. + Part of type region 4 and 2p + It is sufficient that a part of the mold region 5 is connected at least at one or more places. + Holes generated when avalanche breakdown occurs at the junction between the mold region 5 and the drift layer 2 can be efficiently evacuated to the ohmic electrode 13, reducing the burden on the gate insulating film 9 and improving reliability.

[0048] A p-type base layer (a second semiconductor layer of a second conductivity type) 3 is provided on the first main surface side of the base body of the drift layer 2. The impurity concentration of the p-type base layer 3 is, for example, 1p + The impurity concentration of the p-type base layer 3 may be lower than that of the n-type region 4. This makes it possible to prevent a decrease in breakdown voltage due to punch-through by suppressing the spread of the depletion layer in the p-type base layer 3 even if the concentration is reduced to lower the threshold voltage. + A p-type source region (a first semiconductor region of a first conductivity type) 7 and ++ A contact region 8 is selectively provided. + Type source region 7 and p ++ The mold contact regions 8 abut each other.

[0049] Although FIG. 1 illustrates only two trench MOS structures, more trench MOS gate (insulated gate made of metal-oxide-semiconductor) structures may be arranged in parallel.

[0050] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 10 embedded in the trench 18. The ohmic electrode (first electrode) 13 is connected to the n-type ohmic electrode 10 via a contact hole opened in the interlayer insulating film 11. + Type source region 7 and p ++ The ohmic electrode 13 is in contact with the type contact region 8. The ohmic electrode 13 is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. On the ohmic electrode 13, a source electrode pad 15 is provided.

[0051] In addition, a barrier metal (not shown) for preventing, for example, diffusion of metal atoms from the ohmic electrode 13 to the gate electrode 10 is provided between the ohmic electrode 13 and the interlayer insulating film 11 and the source electrode pad 15. The barrier metal is formed by depositing a Ti film and a TiN film in this order.

[0052] (Method of Manufacturing Silicon Carbide Semiconductor Device According to an Embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Figures 4 to 9 are cross-sectional views that typically show states during the manufacturing process of a silicon carbide semiconductor device according to an embodiment.

[0053] First, n-type silicon carbide + A starting substrate 1 is prepared, and n + A first SiC layer 2a is epitaxially formed on the starting substrate 1. The state up to this point is shown in FIG. 4. Next, a p-type dopant, an n-type dopant, O (oxygen), or a rare gas element is ion-implanted into the first SiC layer 2a to form a first ion-implanted layer 16a. The state up to this point is shown in FIG. 5.

[0054] Next, the second SiC layer 2b is epitaxially formed on the first SiC layer 2a. The state up to this point is shown in FIG. 6. Next, a p-type dopant, an n-type dopant, O (oxygen), or a rare gas element is ion-implanted into the second SiC layer 2b to form a second ion-implanted layer 16b. The state up to this point is shown in FIG. 7.

[0055] Next, a third SiC layer 2c is epitaxially formed on the second SiC layer 2b. The state up to this point is shown in FIG. 8. The first, second and third SiC layers 2a, 2b and 2c are combined to form the drift layer 2, and the first and second ion implantation layers 16a and 16b are combined to form the ion implantation layer 16. As a result, the ion implantation layer 16 is formed in the drift layer 2.

[0056] Here, an example in which two ion-implanted layers 16 are formed is shown, but three or more layers can also be formed in the same manner by repeating epitaxial film formation and ion implantation.

[0057] Next, a current diffusion layer 6 having a thickness of about 0.7 μm is epitaxially grown on the silicon substrate 1 by, for example, 1 to 3×10 17 / cm 3 Next, p-type impurities, for example, aluminum atoms, are implanted by ion implantation to form a first p-type impurity layer having a depth of about 0.6 μm in the drift layer 2 and the current diffusion layer 6. +Type area 4, 2nd p + The mold region 5 is, for example, 1 to 5 × 10 18 / cm 3 The state up to this point is shown in FIG.

[0058] Next, a p-type base layer 3 having a thickness of about 0.5 μm is epitaxially grown on the surface of the current diffusion layer 6. 17 / cm 3 Next, a resist mask (not shown) having desired openings is formed on the surface of the p-type base layer 3 by photolithography. Then, an n-type ion implantation process is performed to form a n-type ion implantation region having a thickness of about 0.5 μm. + The mold source layer 7 is, for example, 1 to 3 × 10 19 / cm 3 The impurity concentration is .

[0059] Next, an ion implantation mask having a predetermined opening is formed, and n + A p-type impurity such as aluminum is ion-implanted into a part of the p-type source layer 7 and a part of the p-type base layer 3. ++ The contact region 8 is, for example, 1 to 3 × 10 20 / cm 3 The impurity concentration is .

[0060] Next, a heat treatment is performed in an inert gas atmosphere at about 1750° C. to activate the impurity regions formed by ion implantation. Note that each ion implantation region may be activated collectively by a single heat treatment, or activation may be performed by performing a heat treatment each time an ion implantation is performed.

[0061] Next, n + A trench forming mask having a predetermined opening is formed on the surface of the source region 7 by photolithography, for example, an oxide film. + The second p-type source region 7 and the p-type base layer 3 are penetrated. + A trench 18 is formed so as to reach the mold region 5. Next, the trench forming mask is removed.

[0062] After forming the trench 18, isotropic etching may be performed to remove damage to the trench 18, and sacrificial oxidation may be performed to round the corners of the bottom of the trench 18 and the opening of the trench 18. Only one of isotropic etching and sacrificial oxidation may be performed. Also, sacrificial oxidation may be performed after isotropic etching. This makes it possible to present a clean surface of the silicon carbide, and by rounding the corners, electric field concentration at the bottom and opening of the trench 18 can be suppressed.

[0063] Next, n + Type source region 7 and p ++ A gate insulating film 9 is formed along the surface of the contact region 8 and the bottom and sidewalls of the trench 18. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1300° C. in a gas atmosphere containing oxygen. Alternatively, this gate insulating film 9 may be formed by a method of deposition by a chemical reaction such as high temperature oxidation (High Temperature Oxide: HTO).

[0064] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 18. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 18 to form the gate electrode 10.

[0065] Next, an insulating film is formed on the surface of the gate electrode 10. For example, an oxidation process is performed in an oxygen atmosphere at 1000° C. to form a thermal oxide film. Next, the surface is protected with a protective film. For example, the protective film is formed using a resist for photolithography. Next, the insulating film formed on the back surface, the gate electrode, and the gate insulating film are all removed by dry etching. Next, the protective film formed on the surface is removed in an ashing and stripping process. For example, stripping is performed by ashing in oxygen plasma and SPM cleaning (sulfuric acid-hydrogen peroxide mixture cleaning: piranha cleaning).

[0066] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, forming an interlayer insulating film 11. Next, the interlayer insulating film 11 and the gate insulating film 10 are patterned by photolithography. + Type source region 7 and p ++ A contact hole is formed to expose the n-type contact region 8. Next, a conductive film, for example, nickel, which becomes the ohmic electrode 13 is formed in the contact hole and on the interlayer insulating film 11 by, for example, a sputtering method. Next, a heat treatment at about 1000° C. is performed to selectively react the conductive film with silicon carbide, and then the unreacted conductive film is selectively removed to leave the ohmic electrode 13 only in the contact hole, and the n-type contact region 8 is formed. + Type source region 7 and p ++ The contact region 8 is brought into contact with an ohmic electrode 13 .

[0067] Next, a Ti film is formed on the surfaces of the ohmic electrode 13 and the interlayer insulating film 11, and then a TiN film is formed on the surface of the Ti film to form a barrier metal. Next, a metal film to become the source electrode pad 15 is formed on the ohmic electrode 13 and the interlayer insulating film 11 on the front surface of the silicon carbide semiconductor substrate by, for example, a sputtering method. For example, an Al-Si film is formed by a DC magnetron sputtering film forming device. The sputtering conditions are Ar gas, gas pressure of 0.3 Pa, wafer heating temperature of 430° C., DC sputtering power of 12 kW, and film formation time is adjusted so that the film thickness is 3 to 7 μm.

[0068] The thickness of the electrode pad on the interlayer insulating film 11 may be, for example, 5.5 μm. The electrode pad may be made of, for example, aluminum containing 1% silicon (Al-Si). Next, the metal film is selectively removed to form the source electrode pad 15.

[0069] Next, n + After the front surface of the mold starting substrate 1 is covered with a protective film (not shown) for protection, + The starting substrate 1 is polished from the back side to form a n +The starting mold substrate 1 may be thinned to the product thickness.

[0070] Next, n + On the second main surface of the starting substrate 1, a conductive film that will become the drain electrode 14, for example, a molybdenum film and a nickel film, are successively formed by, for example, a sputtering method. Then, a heat treatment such as laser annealing is performed to form an n + The drain electrode 14 is formed by reacting the mold starting substrate 1 with a conductive film to form an ohmic junction.

[0071] Next, for example, titanium, nickel and gold are deposited in this order as a drain electrode pad on the surface of the drain electrode 14. In this manner, the silicon carbide semiconductor device shown in FIG.

[0072] As described above, according to the embodiment, a plurality of ion implantation layers are formed in the drift layer. + The body diode is provided parallel to the front surface of the starting substrate. This shortens the lifetime of the drift layer. This prevents the expansion of stacking faults when a large current flows through the body diode, and suppresses degradation due to current flow. Furthermore, switching loss can be reduced.

[0073] In the above embodiment according to Figs. 1 to 9, the drift layer 2 is formed in a three-layer structure, but the film thickness and the number of layers can be changed depending on the desired element withstand voltage. Table 1 summarizes typical design examples according to withstand voltage classes. Design example 1 and design example 2 are cases where the drift layer 2 is formed in a two-layer structure, and are suitable for withstand voltages of 1.2 kV and 2.0 kV. Design example 3 is a case where the drift layer shown in the embodiment of Fig. 1 etc. is formed in a three-layer structure, and is a design example for a 3.3 kV class. Design example 4 is a case where the drift layer is formed in a six-layer structure, and illustrates a design for a 6.5 kV class with a higher withstand voltage.

[0074] In Table 1, 5 μm and 10 μm are used as the thickness of each SiC layer constituting the drift layer. However, the thickness of each SiC layer is not limited to this, and can be selected to minimize the number of times the SiC layer is grown, taking into consideration the required thickness of the drift layer and the diffusion length of the crystal defects introduced in the ion implantation layer described above.

[0075] [Table 1]

[0076] The present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present disclosure. For example, in the above-described embodiments, + The impurity concentration of a normal n-type drift region that does not have a super junction (SJ) structure with the starting n-type substrate may be higher than the impurity concentration of the n-type region of the parallel pn layer. The present disclosure also applies when the conductivity types (n-type, p-type) are reversed. [Industrial Applicability]

[0077] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present disclosure are useful for power semiconductor devices having an SJ structure used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0078] 1n + Starting substrate 2. Drift layer 2a 1st SiC layer 2b 2nd SiC layer 2c 3rd SiC layer 3 p-type base layer 4 1st p. + type area 5 2nd p. + type area 6 Current spreading layer 7 n + Type Source Area 8 p ++ Mold Contact Area 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 13 Ohmic electrode 14 Back electrode 15 Source electrode pad 16 Ion implantation layer 16a First ion implantation layer 16b Second ion implantation layer 18 Trench 50 Trench MOSFET

Claims

1. a first conductivity type silicon carbide semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having a lower impurity concentration than the silicon carbide semiconductor substrate; a second semiconductor layer of a second conductivity type provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a trench penetrating the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer; a gate electrode provided inside the trench via a gate insulating film; a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region; A second electrode provided on a back surface of the silicon carbide semiconductor substrate; Equipped with a first semiconductor layer having a first ion-implanted layer formed in parallel with a front surface of the silicon carbide semiconductor substrate;

2. 2. The silicon carbide semiconductor device according to claim 1, wherein the ion-implanted layer is a layer in which aluminum and nitrogen, aluminum and phosphorus, boron and nitrogen, boron and phosphorus, gallium and nitrogen, or gallium and phosphorus are co-implanted.

3. 2. The silicon carbide semiconductor device according to claim 1, wherein the ion-implanted layer is a layer into which aluminum and phosphorus are co-implanted.

4. 4. The silicon carbide semiconductor device according to claim 3, wherein the ion implantation layer has a maximum and a minimum of a net concentration profile equal to or lower than an impurity concentration of the first semiconductor layer.

5. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the ion-implanted layer is a layer implanted with ions of oxygen or a rare gas element.

6. The total thickness of the first semiconductor layer is 10 μm or more, 2 . The silicon carbide semiconductor device according to claim 1 , wherein the ion-implanted layer has a thickness of not less than 0.1 μm and not more than 1 μm.

7. a first step of forming a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate by repeating epitaxial growth and ion implantation on a front surface of the silicon carbide semiconductor substrate, the first semiconductor layer including a plurality of ion implantation layers parallel to the front surface of the silicon carbide semiconductor substrate; a second step of forming a second semiconductor layer of a second conductivity type on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a third step of selectively forming a first semiconductor region of a first conductivity type in a surface layer of the second semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a fourth step of forming a trench penetrating the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer; a fifth step of forming a gate electrode inside the trench via a gate insulating film; a sixth step of forming a first electrode on surfaces of the second semiconductor layer and the first semiconductor region; a seventh step of forming a second electrode on a back surface of the silicon carbide semiconductor substrate; A method for manufacturing a silicon carbide semiconductor device comprising the steps of:

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