Gate drive device

Abstract

To appropriately control gate drive ability when a semiconductor switching element is turned off for suppressing switching loss and surge voltage.SOLUTION: A Vce detection circuit 120 detects rise of inter-electrode voltage Vce between a positive electrode and a negative electrode when a semiconductor switching element 10a is turned off. A drive circuit 150 is configured to control timing of decreasing gate drive ability from first drive ability to second drive ability by using a detection result by the Vce detection circuit 120 during turn-off operation of the semiconductor switching element 10a.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a gate driver for a semiconductor switching element. [Background technology]

[0002] As one aspect of a gate drive device that drives and controls a gate-driven semiconductor switching element, a configuration in which a gate drive current is switched between two stages during a turn-off operation is described in WO 2022 / 050032 (Patent Document 1).

[0003] In the gate driver of Patent Document 1, the gate is discharged with a first gate drive current from the start of turn-off, and when a delay time Td has elapsed from the start of turn-off, the sink capability of the gate is switched so that the gate is discharged with a second gate drive current smaller than the first gate drive current. Furthermore, it is described that the delay time Td is adjusted using a surge voltage detected as a peak value of the drain voltage at each turn-off.

[0004] In addition, JP 2021-93676 A (Patent Document 2) describes the configuration of a semiconductor device for gate driving that is capable of detecting voltage abnormalities (unsaturated state) when a semiconductor switching element is on while ensuring insulation. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2022 / 050032 [Patent Document 2] Patent Publication No. 2021-93676 Summary of the Invention [Problem to be solved by the invention]

[0006] However, according to the gate driver of Patent Document 1, there is a concern that adjustment using surge voltages at multiple turn-offs is required until an appropriate switching timing of the sink capability corresponding to the element variation of the threshold voltage of the semiconductor switching element is obtained. Therefore, there is a concern that the surge voltage will be excessive because the initial value before the delay time adjustment is too short. On the other hand, if the initial value of the delay time is set on the safe side so that the surge voltage is small, there is a concern that switching loss will be large until the adjustment to the appropriate delay time is completed.

[0007] The present disclosure has been made to solve such problems, and an object of the present disclosure is to provide a gate drive device that can appropriately control the gate drive capability when a semiconductor switching element is turned off in order to suppress switching loss and surge voltage. [Means for solving the problem]

[0008] In one aspect of the present disclosure, there is provided a gate drive device for a semiconductor switching element. The gate drive device includes a voltage detection circuit and a drive circuit that drives a gate of the semiconductor switching element. The voltage detection circuit detects a rise in an inter-electrode voltage between a positive electrode and a negative electrode when the semiconductor switching element is turned off. The drive circuit is configured to control the timing of reducing the gate drive capability from a first drive capability to a second drive capability in a turn-off operation of the semiconductor switching element, using a detection result by the voltage detection circuit. Effect of the Invention

[0009] According to the present disclosure, by using the detection result of the rise in the inter-electrode voltage when a semiconductor switching element is turned off to control the timing of reducing the gate drive capability from a first drive capability to a second drive capability, it is possible to appropriately control the gate drive capability at the time of turn-off in order to suppress switching loss and surge voltage. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating a configuration of a gate driving device according to a comparative example. [Diagram 2] FIG. 11 is a conceptual waveform diagram showing a turn-off operation of the gate drive device according to the comparative example. [Diagram 3] FIG. 13 is a conceptual waveform diagram showing a turn-off operation when the sink capability is constant. [Figure 4] 1 is a block diagram illustrating a configuration of a gate driving device according to a first embodiment. [Diagram 5] 4 is a conceptual waveform diagram showing a turn-off operation of the gate driving device according to the first embodiment. FIG. [Figure 6] FIG. 11 is a conceptual circuit diagram illustrating the configuration of a gate driving device according to a second embodiment. [Figure 7] FIG. 11 is a first conceptual diagram illustrating the operation of the gate driving device according to the second embodiment. [Figure 8] FIG. 11 is a second conceptual diagram illustrating the operation of the gate driving device according to the second embodiment. [Figure 9] FIG. 11 is a conceptual circuit diagram illustrating the configuration of a gate driving device according to a third embodiment. [Figure 10] FIG. 11 is a first conceptual diagram illustrating the operation of the gate driving device according to the third embodiment. [Figure 11] FIG. 11 is a second conceptual diagram illustrating the operation of the gate driving device according to the third embodiment. [Figure 12] FIG. 11 is a conceptual circuit diagram illustrating the configuration of a gate driving device according to a fourth embodiment. [Figure 13] FIG. 11 is a conceptual waveform diagram showing a turn-off operation of the gate driver according to the fourth embodiment. [Figure 14] FIG. 13 is a conceptual circuit diagram illustrating the configuration of a gate driving device according to a fifth embodiment. [Figure 15] FIG. 13 is a conceptual waveform diagram showing a normal turn-on operation of the gate driver according to the fifth embodiment. [Figure 16] FIG. 13 is a conceptual waveform diagram showing a turn-on operation in which a desaturated state occurs in the gate drive device according to the fifth embodiment. [Figure 17] FIG. 13 is a conceptual circuit diagram illustrating the configuration of a gate driving device according to a sixth embodiment. [Figure 18] FIG. 13 is a conceptual waveform diagram showing a normal turn-on operation of the gate driver according to the sixth embodiment. [Figure 19] FIG. 13 is a conceptual waveform diagram showing a turn-on operation in which a desaturated state occurs in the gate drive device according to the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference characters, and their description will not be repeated in principle.

[0012] Embodiment 1 (Configuration and operation of comparative example) First, a comparative example will be described to explain the problems with Patent Document 1 in detail.

[0013] 1 is a block diagram illustrating a configuration of a gate driving device 100# according to a comparative example. The gate driving device 100# has a function of switching the sink capability (gate driving capability) of a gate, similar to that described in Patent Document 1.

[0014] 1, the gate driver 100# has a function of a driver IC (Integrated Circuit) for the semiconductor switching element 10a. The semiconductor switching element 10a is typically configured as an IGBT (Insulated Gate Bipolar Transistor) and has a negative electrode (emitter: E) connected to a low potential side node 22, a positive electrode (collector: C) connected to a high potential side node 23, and a gate (control electrode: G) that receives an output voltage VOUT of the gate driver 100#. The semiconductor switching element 10a may be configured as another gate drive type semiconductor switching element such as a MOS (Metal Oxide Semiconductor)-FET (Field Effect Transistor).

[0015] In this embodiment, the low potential side node 22 is connected to GND (ground potential), and the potential of the high potential side node 23 changes depending on whether the semiconductor switching element 10a is turned on or off, but the connection destination of the low potential side node 22 and the high potential side node 23 is arbitrary.

[0016] The gate driver 100 # includes a signal input terminal 101 , a reference potential terminal 102 , an output terminal 103 , a driver circuit 150 , and a delay circuit 190 .

[0017] A control signal VIN for the semiconductor switching element 10a is input to the signal input terminal 101. The control signal VIN is a binary signal that is set to a high level (hereinafter referred to as "H level") during the on-period of the semiconductor switching element 10a, and is set to a low level (hereinafter referred to as "L level") during the on-period of the semiconductor switching element 10a.

[0018] The reference potential terminal 102 is electrically connected to the negative electrode of the semiconductor switching element 10a. The output terminal 103 is electrically connected to the gate (control electrode) of the semiconductor switching element 10a. Therefore, the voltage of the gate with respect to the negative electrode of the semiconductor switching element 10a, that is, the gate-emitter voltage (hereinafter also simply referred to as "gate voltage") Vge, is controlled by the output voltage VOUT of the gate driver 100#.

[0019] The gate driver 100# turns on the semiconductor switching element 10a by setting the output voltage VOUT to a positive voltage Vcc during the H level period of the control signal VIN, and turns off the semiconductor switching element 10a by setting the output voltage VOUT to a reference potential (0 (V)) during the L level period of the control signal VIN.

[0020] The gate driver 100# generates a gate current via the output terminal 103, thereby changing the gate voltage Vge through the output voltage VOUT, thereby turning on or off the semiconductor switching element 10a. The delay circuit 190 outputs a signal obtained by adding a delay time Td to the control signal VIN.

[0021] The drive circuit 150 has sink circuits 151 and 152 for switching the sink capability (gate drive capability) when turning off the semiconductor switching element 10a. The sink circuits 151 and 152 are connected in parallel to the output terminal 103, and the on / off of the sink circuits 151 and 152 is controlled individually. The sink circuits 151 and 152 can be configured, for example, by transistors connected in parallel between the output terminal 103 and the reference potential terminal 102.

[0022] FIG. 2 shows a conceptual operational waveform diagram when semiconductor switching element 10a is turned off by gate driving device 100# according to the comparative example.

[0023] As shown in FIG. 2, when the control signal VIN changes from H level to L level at time t0, a turn-off operation is started. Before time t0, the output voltage VOUT of the gate driver 100# is set to a positive voltage Vcc higher than the threshold voltage Vthg of the semiconductor switching element 10a, and the semiconductor switching element 10a is in an ON state. In the ON state, a collector-emitter current is generated from the positive electrode to the negative electrode, and the voltage VHV of the high potential side node 23, i.e., the collector-emitter voltage Vce, which is the "interelectrode voltage" between the positive electrode and the negative electrode of the semiconductor switching element 10a, is the reference potential (0:GND). In each of the following waveform diagrams, the 0 (V) of the output voltage VOUT and the collector-emitter voltage Vce (voltage VHV) corresponds to the potential of the reference potential terminal 102 (i.e., the potential of the negative electrode of the semiconductor switching element 10a).

[0024] During the on-period of the semiconductor switching element 10a, the sink circuits 151 and 152 are turned off, while they are turned on at the time t0 when the turn-off operation starts. Each of the sink circuits 151 and 152 generates a gate current for discharging the gate of the semiconductor switching element 10a through the output terminal 103.

[0025] The sink circuit 151 is turned on during the off-period of the semiconductor switching element 10a, that is, during the L-level period of the control signal VIN. On the other hand, the sink circuit 152 is turned off at the time t2 when the output signal of the delay circuit 190 changes from the H level to the L level. The time t2 is the timing at which the delay time Td by the delay circuit 190 has elapsed from the turn-off start time t0. As a result, the sink capacity for discharging by the drive circuit 150 is set to the gate current I1 by both the sink circuits 151 and 152 between the times t0 and t2, while after the time t2, it is reduced to the gate current I2 (I2 < I1) by only the sink circuit 151.

[0026] When the turn-off is started, the output voltage VOUT decreases from the positive voltage Vcc in response to the discharge by the sink circuits 151 and 152. Since the decrease rate of the output voltage VOUT depends on the gate current, the decrease rate of the output voltage VOUT between the times t0 and t2 is larger than that after the time t2. That is, in the gate drive device 100♯, the sink capacity, that is, the decrease rate of the output voltage VOUT, is switched at the time t2 defined by the delay time Td.

[0027] Thereafter, when the control signal VIN changes to the H level, the sink circuit 151 is turned off and the sink capacity becomes zero. The drive circuit 150 generates a gate current in the direction of charging the output terminal 103 and the gate of the semiconductor switching element 10a during the H-level period of the control signal VIN.

[0028] FIG. 3 shows a conceptual waveform diagram during the turn-off operation when the sink capacity is constant.

[0029] 3, at time t0, when the control signal VIN changes from H level to L level, a turn-off operation is initiated, as in Fig. 2. In the turn-off operation of Fig. 3, the drive circuit 150 discharges the output terminal 103 and the gate of the semiconductor switching element 10a with a constant sink capability (gate current), so that the output voltage VOUT drops from the positive voltage Vcc during the on-period to 0 (V) at a constant rate.

[0030] The semiconductor switching element 10a is turned off as the gate voltage Vge drops from the positive voltage Vcc in response to the output voltage VOUT. Specifically, when the gate voltage Vge drops below the threshold voltage Vthg, the collector-emitter voltage Vce starts to rise. After that, after the output voltage VOUT (gate voltage Vge) drops to 0 (V), the semiconductor switching element 10a is completely turned off, the collector-emitter current is cut off, and the collector-emitter voltage Vce reaches a steady value.

[0031] The rate of increase of the collector-emitter voltage Vce during the turn-off operation depends on the rate of decrease of the output voltage VOUT. If the rate of decrease of the output voltage VOUT is large, the rate of increase of the collector-emitter voltage Vce also becomes large, and the surge voltage Vs, which is the maximum value of the collector-emitter voltage Vce generated during turn-off, also becomes high. If the surge voltage becomes excessive, it may exceed the withstand voltage of the load to which the semiconductor switching element 10a is connected, and may damage the load.

[0032] On the other hand, if the rate at which the output voltage VOUT falls is small, the rate at which the collector-emitter voltage Vce rises also falls, resulting in a lower surge voltage Vs. On the other hand, the turn-off operation becomes gentler, so the time it takes to complete the turn-off operation becomes longer, resulting in higher switching losses. Thus, it is known that there is a trade-off between the suppression of switching losses and surge voltages depending on the rate at which the output voltage VOUT falls.

[0033] 2 again, in gate driver 100#, immediately after the start of turn-off from time t0 to t2, the gate current is increased to increase the rate at which the output voltage VOUT falls, thereby increasing switching loss. Meanwhile, the gate current is decreased during the turn-off operation (time t2) to decrease the rate at which the output voltage VOUT falls, thereby suppressing surge voltage Vs. Providing such a gate current (sink capability) switching function makes it possible to suppress both switching loss and surge voltage.

[0034] On the other hand, there is element variation in the threshold voltage Vthg of the semiconductor switching element 10a. Illustrated in Fig. 2 are waveforms HVa, HVb, and HVc of the collector-emitter voltage Vce when Vthg=Va, Vb, and Vc.

[0035] When Vthg=Vb, the collector-emitter voltage Vce rises from time t1b. For example, the waveform HVb when Vthg=Vb is the waveform of the collector-emitter voltage Vce when the threshold voltage of the semiconductor switching element 10a is at the median value of the specifications, and the surge voltage and switching loss are balanced and suppressed by switching the sink capability at time t2 when the delay time Td has elapsed from the start of turn-off (time t0).

[0036] On the other hand, when the threshold voltage of the semiconductor switching element 10a is within the standard but higher than the above-mentioned specification median, Vthg=Va (Va>Vb) is satisfied, and the collector-emitter voltage Vce rises from time t1a, which is earlier than time t1b, as shown in the waveform HVa. On the other hand, since the timing of switching the sink capability does not change at time t2, the timing of switching the sink capability is delayed with respect to the rise of the collector-emitter voltage Vce in the waveform HVa compared to the waveform HVb. As a result, the surge voltage in the waveform HVa is larger than that in the waveform HVb.

[0037] On the other hand, when the threshold voltage of the semiconductor switching element 10a is within the standard but lower than the median value of the above specifications, Vthg = Vc (Vc < Vb), and as shown in the waveform HVc, the collector-emitter voltage Vce rises from a time t1c later than the time t1b. Therefore, in the waveform HVc, compared with the waveform HVb, contrary to the waveform HVa, the timing for switching the sink capacity becomes earlier with respect to the rise of the collector-emitter voltage Vce. As a result, in the waveform HVc, while the surge voltage is smaller than that in the waveform HVb, there is a concern that the switching loss may increase.

[0038] Patent Document 1 describes that the delay time Td is sequentially adjusted so that the surge voltage falls within a predetermined voltage range in correspondence with the actual value of the surge voltage for each turn-off, but until the delay time Td is set to an appropriate value, there is a problem that the surge voltage or the switching loss increases.

[0039] Also, when the threshold voltage changes due to the temperature rise of the semiconductor switching element, although the appropriate delay time changes, there is a concern that the switching loss or the surge voltage may increase before the delay time is adjusted based on the actual value of the surge voltage.

[0040] (Configuration and operation of Embodiment 1) Therefore, in the present embodiment, based on the detection of the rise of the collector-emitter voltage Vce, the timing of the decrease in the sink capacity (gate drive capacity) during the turn-off operation is controlled.

[0041] FIG. 4 is a block diagram for explaining the configuration of the gate drive device 100A according to Embodiment 1.

[0042] 4, the gate driving device 100A includes a signal input terminal 101, a reference potential terminal 102, an output terminal 103, and a driving circuit 150 similar to those of the gate driving device 100# according to the comparative example, as well as a voltage detection terminal 104, a Vce detection circuit 120, and a delay circuit 140. The signal input terminal 101, the reference potential terminal 102, the output terminal 103, and the driving circuit 150 are configured similarly to those of the comparative example (FIG. 1). Therefore, the driving circuit 150 is configured such that the sink capability can be switched between two stages by the sink circuits 151 and 152.

[0043] The voltage detection terminal 104 is connected to the positive electrode (collector) of the semiconductor switching element 10a, and receives a voltage VHV (hereinafter also referred to as an input voltage VHV) equivalent to the collector-emitter voltage Vce.

[0044] The Vce detection circuit 120 is configured to detect the rising edge of the collector-emitter voltage Vce based on the input voltage VHV. For example, when the input voltage VHV (collector-emitter voltage Vce) becomes higher than a predetermined determination voltage Vr, the Vce detection circuit 120 changes the Vce rising edge detection signal VHd from L level to H level. The Vce detection circuit 120 corresponds to one embodiment of the "voltage detection circuit", and the determination voltage Vr corresponds to one embodiment of the "first determination voltage".

[0045] The delay circuit 140 generates an output signal VHdly by adding a delay time Tdh to the detection signal VHd from the Vce detection circuit 120. A control signal VIN and the output signal VHdly of the delay circuit 140 are input to the drive circuit 150. The delay circuit 140 can be configured, for example, by a plurality (an even number) of inverters (NOT gates) connected in series. The delay time Tdh corresponds to one embodiment of the "first delay time."

[0046] FIG. 5 shows a conceptual operational waveform diagram when the semiconductor switching element 10a is turned off by the gate driving device 100A according to the first embodiment.

[0047] As shown in Fig. 5, similarly to Fig. 2, at time t0, when the control signal VIN changes from H level to L level, a turn-off operation is initiated. In response to this, the sink circuits 151 and 152 are turned on, and the output terminal 103 and the gate of the semiconductor switching element 10a are discharged by the gate current I1 (sink capability) from both the sink circuits 151 and 152. As a result, the output voltage VOUT decreases at the same rate as the decrease rate from time t0 to t2 in Fig. 2 in order to suppress switching loss.

[0048] At time t1, when the gate voltage Vge drops to the threshold voltage Vthg in response to the drop in the output voltage VOUT, the collector-emitter voltage Vce starts to rise. Then, at time t3, the collector-emitter voltage Vce rises to the determination voltage Vr of the Vce detection circuit 120. This causes the detection signal VHd to change from the L level to the H level.

[0049] At time t4, when the delay time Tdh by the delay circuit 140 has elapsed from time t3, the output signal VHdly of the delay circuit 140 changes from the L level to the H level, and in response, the sink circuit 152 is turned off. On the other hand, the sink circuit 151 is maintained on while the control signal VIN is at the L level.

[0050] As a result, after time t4, the gate current (sink capability) is reduced to I2, similarly to after time t2 in Fig. 2. This reduces the rate at which the output voltage VOUT (gate-emitter voltage Vce) decreases in order to reduce the surge voltage. The delay time Tdh by the delay circuit 140 can be preset to correspond to the time difference between times t1b and t2 in the waveform HVb in Fig. 2.

[0051] As a result, according to the gate drive device of the first embodiment, the sink capability (gate drive capability) of the drive circuit 150 can be switched by online control according to the actual rising timing of the collector-emitter voltage Vce. As a result, even if the threshold voltage varies due to the element variation or element temperature change of the semiconductor switching element 10a, the sink capability (gate drive capability) of the drive circuit 150 can be switched at an appropriate timing (e.g., corresponding to the waveform HVb in FIG. 2) for suppressing the surge voltage and switching loss in a balanced manner. This makes it possible to eliminate the influence of manufacturing variations in the semiconductor switching elements and stably suppress the surge voltage and switching loss at the time of turn-off.

[0052] Embodiment 2 In the second embodiment, a description will be given of a preferred configuration example of the Vce detection circuit 120. In the present embodiment, a circuit configuration that takes into consideration ensuring insulation so that the Vce detection circuit 120 and the drive circuit 150 are mounted on the same IC will be exemplified.

[0053] 6 is a conceptual circuit diagram illustrating the configuration of a gate driving device 100B according to embodiment 2. The gate driving device 100B corresponds to a specific internal configuration of the Vce detection circuit 120 in the gate driving device 100A (FIG. 4). That is, the operation of the gate driving device 100B when it is turned off is similar to the turn-off operation of the gate driving device 100A (FIG. 4).

[0054] As shown in FIG. 6, the Vce detection circuit 120 includes a current source 121, current mirror circuits 122 and 125, a voltage division circuit 126 including resistor elements R1 and R2, and a voltage comparator .

[0055] The current mirror circuit 125 has P-type transistors T1, T2, and T4 and an N-type transistor T3. Typically, the transistors T1, T2, and T4 are PMOS transistors, and the transistor T3 is an NMOS transistor. The transistor T1 is connected between the voltage detection terminal 104 and a node N4, and the transistor T2 is connected between the voltage detection terminal 104 and a node N3. Thus, the P-type transistors T1 and T2 have their sources connected to the positive electrode of the semiconductor switching element 10a through the voltage detection terminal 104.

[0056] The transistor T3 is connected between the node N4 and the node N5. The transistor T4 is connected between the node N3 and the node N1. The gates of the transistors T1 and T2 are connected to the node N3 which is the connection node of the transistors T2 and T4. The gate of the transistor T4 is connected to the node N4 which is the connection node of the transistors T1 and T3.

[0057] The current mirror circuit 122 has transistors Q1 and Q2. The transistors Q1 and Q2 are, for example, configured by npn-type bipolar transistors. The current source 121 outputs a constant current Ia to a node N6 connected to the gate of the transistor T3. The transistor Q1 is electrically connected between the node N6 and the reference potential terminal 102, and the transistor Q2 is electrically connected between the node N5 and the reference potential terminal 102. The bases (control electrodes) of the transistors Q1 and Q2 are connected to the node N5.

[0058] Thus, the current mirror circuit 125 corresponds to an embodiment of the "first current mirror circuit" and constitutes a "current supply circuit" that generates an "output current" for the voltage divider circuit 126. The node N5 is also connected to the current source 121 via the current mirror circuit 122, and the current mirror circuit 122 corresponds to an embodiment of the "second current mirror circuit." The transistors T1 to T4 correspond to the "first transistor" to the "fourth transistor," respectively.

[0059] The voltage comparator 130 outputs a detection signal VHd according to a comparison result between the voltage V+ at the positive input terminal and the voltage V- at the negative input terminal. The detection signal VHd is set to an H level when V+>V-, and is set to an L level when V+≦V-.

[0060] Since the positive input terminal of the voltage comparator 130 is connected to the node N2, the voltage V+ corresponds to the voltage VN2 of the node N2. Meanwhile, a voltage source 135 that outputs a determination voltage Vt, which is a DC voltage, is electrically connected between the negative input terminal of the voltage comparator 130 and the reference potential terminal 102 (the negative electrode of the semiconductor switching element 10a).

[0061] In the Vce detection circuit 120, the transistors T3 and T4 are connected between the high-voltage circuit HVC formed by the transistors T1 and T2, and the low-voltage circuit LVC between the nodes N1 and N5 and the reference potential terminal 102. Therefore, the transistors T3 and T4, to which the differential voltage of the high-voltage circuit HVC and the low-voltage circuit LVC is applied between the collector and emitter, are respectively formed of high-voltage PMOS transistors and NMOS transistors having a withstand voltage capable of applying the voltage of the positive electrode (collector) of the semiconductor switching element 10a. By forming the gate driver 100B using high-voltage PMOS transistors and NMOS transistors using HVIC (High Voltage Integrated Circuit) technology (PN junction isolation technology), the Vce detection circuit 120 can be fabricated in the same IC as the driver circuit 150.

[0062] A current Ia (constant current) from the current source 121 is transmitted to P-type transistors T1 and T2 constituting a current mirror via a current mirror circuit 122. A current Ib flowing through the transistors T2 and T4 varies according to an input voltage VHV of the voltage detection terminal 104 (i.e., a collector-emitter voltage Vce of the semiconductor switching element 10a), with the current Ia (constant current) from the current source 121 as an upper limit. The current Ib corresponds to an “output current” supplied to the voltage divider circuit 126.

[0063] The resistive elements R1 and R2 constituting the voltage dividing circuit 126 are connected in series with the current mirror circuit 125 (transistors T2, T4) between the voltage detection terminal 104 and the reference potential terminal 102. The resistive elements R1 and R2 are connected in series via the node N2 between the node N1 to which the current Ib is supplied from the current mirror circuit 125 and the reference potential terminal 102. Hereinafter, the resistance values ​​of the resistive elements R1 and R2 will also be represented as R1 and R2.

[0064] 7 and 8 are conceptual diagrams for explaining the operation of the gate driver 100B.

[0065] FIG. 7 shows the characteristics of the current Ib versus the collector-emitter voltage Vce.

[0066] 2 and 7, the collector-emitter voltage Vce (input voltage VHV) becomes the source voltage of the transistors T1 and T2, so in a region where Vce is lower than the threshold voltage Vpmos of the transistors T1 and T2, the current Ib does not occur (Ib=0). When Vce becomes higher than the threshold voltage Vpmos, the current Ib occurs. The current Ib increases as Vce increases, but is saturated at the current Ia (constant current) from the current source 121.

[0067] FIG. 8 shows a characteristic diagram of the input voltage to the voltage comparator 130 versus the collector-emitter voltage Vce.

[0068] 2 and 8, a voltage VN1 is generated at node N1, which is represented by the product of current Ib and the resistance value (R1+R2) described in FIG. 7. A voltage VN2 is generated at node N2, which is obtained by dividing voltage VN1 by R1 / (R1+R2). Voltage VN2 corresponds to the input voltage on the positive side of voltage comparator 130. It is understood that voltage VN2 is proportional to current Ib.

[0069] In the region where Vce≦Vpmos, VN1=VN2=0, and when Vce>Vpmos, voltages VN1 and VN2 are generated in response to the generation of current Ib. As Vce increases, voltages VN1 and VN2 increase in proportion to current Ib, but saturate in response to current Ia from current source 121. Voltage VN1 saturates at voltage V0, which is the product of current Ia and resistance value (R1+R2) (V0=Ia·(R1+R2)), and voltage VN2 saturates at the voltage, which is the product of current Ia and resistance value R2.

[0070] 7 and 8, when the collector-emitter voltage Vce is the decision voltage Vr shown in Fig. 5, the voltages VN1 and VN2 are expressed as VN1=V1r=Ir·(R1+R2) and VN2=V2r=Ir·R2) using the current Ib=Ir (Fig. 7). That is, the current Ib is generated so as to rise to a saturation value (Ia) as the collector-emitter voltage Vce rises in a voltage region including the decision voltage Vr.

[0071] Therefore, by designing the determination voltage Vt (voltage source 135) input to the negative side of the voltage comparator 130 so that V2r=Vt, the voltage comparator 130 can set the detection signal VHd to the L level when Vce≦Vr, while setting the detection signal VHd to the H level when Vce>Vr. The determination voltage Vr corresponds to one embodiment of a "first determination voltage," and the determination voltage Vt corresponds to one embodiment of a "second determination voltage."

[0072] According to the gate driving device of the second embodiment, the rising edge of the collector-emitter voltage Vce during a turn-off operation is detected based on the output voltage of the voltage divider circuit 126 that uses the output current (Ib) of the current mirror circuit that generates a current according to the collector-emitter voltage Vce, and a turn-off operation similar to that of the first embodiment can be performed.

[0073] This allows the resistance value of the voltage divider circuit to be smaller than in a configuration in which the rising edge of Vce is detected by simple resistive voltage division of the collector-emitter voltage Vce. As a result, the rate of change of the input voltage (+ side) of the voltage comparator 130 in response to the change in Vce increases, making it possible to improve the detection accuracy of Vce=Vt (time t3) in FIG. 5.

[0074] 6, the resistor elements R1 and R2 and the current source 121 are not external components but are internal elements of the IC. Therefore, through the pairing of R1 and R2, the pairing of transistors T1 and T2 (current mirror), and the pairing of transistors Q1 and Q2 (current mirror circuit 122), it is possible to improve the accuracy of the voltage VN2=V2r at the node N2 for detecting Vce>Vr.

[0075] Embodiment 3 FIG. 9 is a conceptual circuit diagram illustrating the configuration of a gate driving device 100C according to the third embodiment.

[0076] 9, the gate driver 100C is different from the gate driver 100B (FIG. 6) in the configuration of the Vce detection circuit 120. Specifically, the connection destination of the gates of the P-type transistors T1 and T2 that configure a current mirror is changed from the node N3 to the node N4, and a resistive element R3 is further provided.

[0077] The resistor R3 is connected between the node N4 and a node N7 corresponding to the drain of the transistor T3 configured as a high-voltage NMOS transistor. The gate of the transistor T4 configured as a high-voltage PMOS transistor is connected to the node N7. The node N7 corresponds to the connection node of the resistor R3 and the transistor T3. The node N4 corresponds to the connection node of the transistor T1 and the resistor R3 in FIG. 9.

[0078] The configuration of other parts of the gate driver 100C, including the Vce detection circuit 120, is similar to that of FIG. 6 (gate driver 100B), and therefore detailed description will not be repeated.

[0079] 6 described in the second embodiment, a voltage difference equivalent to the gate-source voltage of the transistor T2 occurs between the input voltage VHV and the voltage of the node N3 in the Vce detection circuit 120. This causes a similar voltage difference to occur between the node N1 and the input voltage VHV (collector-emitter voltage Vce).

[0080] 9, the gates of the transistors T1 and T2 are connected to the node N4, so that in response to the generation of the current Ia, a current flows through the nodes N4 and N5 and a current flows through the nodes N3 and N1. As a result, the on-resistance (resistance between the drain and source) of the transistor T2 becomes sufficiently low, and the voltage of the node N3 becomes equal to the input voltage VHV (collector-emitter voltage Vce).

[0081] Furthermore, the current causes a voltage drop across resistor R3, ensuring the gate-source voltage of transistor T4 (P type), thereby lowering the on-resistance of transistor T4. As a result, the voltage of node N1, like node N3, becomes equal to input voltage VHV (collector-emitter voltage Vce).

[0082] 10 and 11 are conceptual diagrams for explaining the operation of the gate driver 100C.

[0083] FIG. 10 shows the characteristics of the current Ib versus the collector-emitter voltage Vce, similar to FIG.

[0084] 10, in the gate driver 100C (FIG. 9), when the collector-emitter voltage Vce (input voltage VHV) is generated (Vce>0), the current Ib flowing through the node N1 changes according to the input voltage VHV (collector-emitter voltage Vce of the semiconductor switching element 10a) of the voltage detection terminal 104, with the current Ia from the current source 121 as an upper limit. It can be seen that in the third embodiment as well, the current Ib is generated so as to rise to a saturation value (Ia) in response to the rise in the collector-emitter voltage Vce in a voltage region including the determination voltage Vr.

[0085] 7 (Embodiment 2), if the collector-emitter voltage Vce does not exceed the threshold voltage Vpmos of the transistors T1 and T2, the current Ib does not flow in the node N1. For this reason, there is a concern that a detection error will occur in the timing when the collector-emitter voltage Vce reaches the determination voltage Vt if the current value Ir at Vce=Vr becomes different from the expected value due to a change in Vpmos caused by element variations or the like.

[0086] In contrast to this, in FIG. 10 (third embodiment), the current value Ir of the current Ib corresponding to Vce=Vr is not affected by variations in the threshold voltages Vpmos of the transistors T1 and T2.

[0087] FIG. 11 shows a characteristic diagram of the input voltage to the voltage comparator 130 versus the collector-emitter voltage Vce, similar to FIG.

[0088] The voltages VN1 and VN2 are represented by the product of the current Ib and the resistance value (R1+R2) or the resistance value R1, and therefore change according to the collector-emitter voltage Vce, similar to the current Ib. By generating the input voltage (voltage VN2) of the voltage comparator 130 using the current Ib having the characteristics of FIG. 10, it becomes possible to accurately detect the timing at which the collector-emitter voltage Vce reaches the determination voltage Vr, without being affected by the threshold voltage Vpmos of the transistors T1 and T2.

[0089] Thus, in the gate drive device according to Embodiment 3, compared with the gate drive device according to Embodiment 2, the influence of element variations can be suppressed, and the detection accuracy of the rise of the collector-emitter voltage Vce (Vce ≥ Vr) can be improved.

[0090] Embodiment 4. FIG. 12 is a conceptual circuit diagram for explaining the configuration of a gate drive device 100D according to Embodiment 4.

[0091] As shown in FIG. 12, the gate drive device 100D is different in that, in addition to the configuration of the gate drive device 100C (FIG. 9), it further includes a voltage comparator 131 and an N-type transistor 123 for constituting a "current supply stop circuit".

[0092] The voltage comparator 131 outputs a signal according to the comparison result between the output voltage VOUT of the drive circuit 150 and the determination voltage Vt2 from the voltage source 136. The output signal of the voltage comparator 131 is set to the H level when VOUT < Vt2, while it is set to the L level when VOUT ≥ Vt2.

[0093] The transistor 123 is connected in parallel with the current mirror circuit 122 (transistor Q1) between the node N6 and the reference potential terminal 102. In Embodiment 4, the output signal of the voltage comparator 131 is input to the gate of the transistor 123 as a current stop signal Vcut. Since the configuration of other parts of the gate drive device 100D is the same as that of FIG. 9 (gate drive device 100C), detailed description will not be repeated.

[0094] The Vce detection circuit 120 needs to operate when the collector-emitter voltage Vce rises after the turn-off starts. On the other hand, after the rise of Vce is completed (during the off period after the turn-off operation of the semiconductor switching element 10a is completed), it does not need to operate. Therefore, the determination voltage Vt2 input to the voltage comparator 131 can be set to a positive voltage near 0, which is lower than the threshold voltage of the semiconductor switching element 10a, in order to detect the completion of the turn-off operation of the semiconductor switching element 10a. The determination voltage Vt2 corresponds to an embodiment of the "third determination voltage".

[0095] Therefore, the current stop signal Vcut is set to the L level during the on period (VIN = H level) of the semiconductor switching element 10a in which the output voltage VOUT is set to the positive voltage Vcc. Further, after the turn-off starts, it is maintained at the L level until the turn-off operation is completed. Further, the current stop signal Vcut changes to the H level after the turn-off operation is completed and is maintained at the H level during the off period of the next semiconductor switching element 10a (until the next turn-on).

[0096] FIG. 13 is a conceptual waveform diagram during the turn-off operation of the gate drive device according to the fourth embodiment.

[0097] The waveforms of the control signal VIN, the sink circuits 151, 152, the output voltage VOUT, and the input voltage VHV (collector-emitter voltage Vce) in FIG. 13 are the same as those in FIG. 5. In FIG. 13, in addition to the above, the waveform of the current stop signal Vcut is further shown.

[0098] As shown in FIG. 13, the current stop signal Vcut is at the L level at the time t0 when the turn-off operation starts, but changes from the L level to the H level at the time t5 when VOUT < Vt2 after the output voltage VOUT decreases after the turn-off operation starts.

[0099] After time t5, when the control signal VIN changes from L level to H level to turn on the semiconductor switching element 10a, the output voltage VOUT rises toward the positive voltage Vcc, and the current stop signal Vcut returns to L level. During the ON period of the semiconductor switching element 10a, the current stop signal Vcut is maintained at L level.

[0100] During an L level period of the current stop signal Vcut, the current Ia from the current source 121 passes through the transistor Q1 and is input to the current mirror circuit 125 (transistor T2) via the current mirror circuit 122. As a result, a current Ib is generated in response to an increase in the collector-emitter voltage Vce, causing the Vce detection circuit 120 to perform a detection operation.

[0101] On the other hand, during the H level period of the current stop signal Vcut, the current Ia from the current source 121 bypasses the current mirror circuit 122 and flows through the turned-on transistor 132, and is not transmitted to the current mirror circuit 125. As a result, even if the collector-emitter voltage Vce occurs, the current mirror circuit 125 cannot generate the current Ib at the node N1. This causes the detection operation by the Vce detection circuit 120 to stop.

[0102] During the off period in which the control signal VIN is maintained at the L level after the completion of the turn-off operation of the semiconductor switching element 10a, the collector-emitter voltage Vce is generated, and therefore when the current Ia is supplied to the current mirror circuit 125, the current Ib is continuously generated to the voltage divider circuit 126. On the other hand, timing detection for switching the sink capability at the time of turn-off is not necessary during the off period after the completion of the turn-off operation of the semiconductor switching element 10a.

[0103] Therefore, after the turn-off operation of the semiconductor switching element 10a is completed, the transistor 132 is turned on to form a current path that bypasses the current mirror circuit 122 (transistor Q1) for the current Ia (constant current) of the current source 121, thereby making the current Ib in the Vce detection circuit 120 equal to 0. That is, the transistor 132 corresponds to one embodiment of the "fifth transistor", and by not supplying the current Ia to the current mirror circuit 125 during the on period of the transistor 123, the generation of the current Ib in the Vce detection circuit 120 can be stopped.

[0104] The current Ia is generated in a low-voltage circuit using a power supply voltage of several (V) to several tens (V). On the other hand, the current Ib is generated by a high voltage (e.g., several hundred (V)) of the main circuit that is turned on and off by the semiconductor switching element 10a. Therefore, the power consumption by the current Ib is greater than the power consumption by the current Ia, so that the supply of the current Ia is stopped after the turn-off operation is completed, and the detection operation by the Vce detection circuit 120 is stopped, thereby reducing the power consumption.

[0105] When the semiconductor switching element 10a is turned on after time t5, the output voltage VOUT rises and becomes VOUT>Vt2, and the supply of the current Ia to the Vce detection circuit 120 begins. However, since Vce=0 during the on-period of the semiconductor switching element 10a, the current Ib does not occur. By supplying the current Ia, the detection operation of the Vce detection circuit 120 is resumed, and it becomes possible to prepare for the start of the turn-off operation (time t0) at which the control signal VIN changes from H level to L level.

[0106] Thus, according to the gate driving device of embodiment 4, in addition to the effects of the gate driving device of embodiment 3, it is possible to reduce power consumption when the operation of the Vce detection circuit 120 is not required (the off period after the semiconductor switching element 10a has been turned off).

[0107] In the example of Fig. 12, a voltage comparator 131 and an N-type transistor 123 for configuring a "current supply stopping circuit" are additionally arranged in the gate driving device 100C (Fig. 9) according to embodiment 3, but it is also possible to arrange a "current supply stopping circuit" in the gate driving device 100B (Fig. 6) according to embodiment 2. In this case, by connecting a transistor 123, the gate of which receives a current stop signal Vcut, in parallel with the transistor Q1 in the configuration shown in the figure, it is possible to combine embodiments 2 and 4.

[0108] Embodiment 5. In the fifth embodiment, a configuration example will be described in which the Vce detection circuit 120 is also utilized during the turn-on operation of the semiconductor switching element 10a. Specifically, the Vce detection circuit 120 is used to detect the occurrence of a non-saturated state during the turn-on operation, as described in Patent Document 2.

[0109] As described in Patent Document 2, it is known that in a semiconductor switching element, when an overcurrent occurs, an unsaturated state occurs, and even though the element is in the on state, a voltage abnormality occurs in which the voltage between the positive electrode and the negative electrode rises. For this reason, in order to avoid a continuous overcurrent state in the semiconductor switching element, it is effective to detect the above-mentioned voltage abnormality (unsaturated state).

[0110] FIG. 14 is a conceptual circuit diagram for explaining the configuration of a gate driving device according to the fifth embodiment.

[0111] As shown in FIG. 14, the gate driver 100E differs from the configuration of the gate driver 100D (FIG. 12) in that it further includes an AND gate 129 for ensuring operation of the Vce detection circuit 120 during a turn-on operation, a protection circuit 180 that operates when an unsaturated state occurs, and that the Vce detection circuit 120 further includes a voltage comparator 132 for detecting the unsaturated state.

[0112] The AND gate 129 inputs the result of an AND operation between the output signal of the voltage comparator 131 similar to that of FIG. 12 and the inverted signal of the control signal VIN as the current stop signal Vcut to the gate of the transistor 132 similar to that of FIG. 12. As a result, the current stop signal Vcut is reliably set to the L level during the H level period of the control signal VIN (the ON period of the semiconductor switching element 10a). Also, during the L level period of the control signal VIN, during the period of VOUT≧Vt2, that is, until the turn-off is completed, the output signal of the voltage comparator 131 is at the L level, so the current stop signal Vcut is set to the L level. Thereafter, when the turn-off is completed and the output signal of the voltage comparator 131 becomes the H level, the current stop signal Vcut is set to the H level.

[0113] The voltage comparator 132 generates a detection signal VFd according to the result of comparison between the voltage VN2 at the node N2 of the Vce detection circuit 120 and a determination voltage Vt3 from a voltage source 137. When VN2≦Vt3, the detection signal VFd is set to an L level, and when VN2>Vt3, the detection signal VFd is set to an H level.

[0114] The determination voltage Vt3 is set corresponding to the determination voltage Vrdst with respect to Vce in order to detect that the collector-emitter voltage Vce has not decreased due to the occurrence of a desaturated state at the time of turn-on. For example, in the Vce-VN2 characteristic of FIG. 11, the determination voltage Vt3 can be set corresponding to the value of the voltage VN2 when Vce=Vrdst. Therefore, the voltage comparator 132 operates to set the detection signal VFd to the L level when Vce≦Vrdst, and to set the detection signal VFd to the H level when Vce>Vrdst. The determination voltage Vrdst corresponds to one embodiment of the "fourth determination voltage".

[0115] The protection circuit 180 includes a delay circuit 181 , a NAND gate 182 , and an AND gate 183 .

[0116] The delay circuit 181 outputs a delayed signal S1 obtained by adding a delay time Tdp to the control signal VIN. The NAND gate 182 outputs a signal S2 according to the result of a NAND operation between the detection signal VFd output by the voltage comparator 132 and the delayed signal S1. The delay circuit 181, like the delay circuit 140, can be configured by a plurality (an even number) of inverters (NOT gates) connected in series.

[0117] The AND gate 183 outputs a control signal S3 to be input to the drive circuit 150 according to the result of an AND operation between the control signal VIN that has not passed through the delay circuit 181 and the signal S2. The drive circuit 150 generates an output voltage VOUT during turn-on, that is, during the H-level period of the control signal VIN, according to the control signal S3.

[0118] During the period from the start of turn-on when the control signal VIN changes from L level to H level until the delay time Tdp (delay circuit 181) has elapsed, the delay signal S1 is at L level, so the signal S2 from the NAND gate 182 is fixed at H level. Therefore, the control signal S3 has the same signal level as the control signal VIN regardless of the level of the detection signal VFd.

[0119] After the delay time Tdp from the start of turn-on has elapsed, the signal S2 is set to H level if the detection signal VFd is at L level. On the other hand, the signal S2 is set to H level if the detection signal VFd is at H level. In this case, even if the control signal VIN is set to H level, the control signal S3 is set to L level. In other cases, the control signal S3 is set to H level.

[0120] When the control signal S3 is set to the L level during a turn-on operation, the drive circuit 150 detects that a "protection signal" has been generated and turns on the sink circuits 151, 152 to change the output voltage VOUT to 0 (V). The configuration of other parts of the gate drive device 100E is similar to that of FIG. 12 (gate drive device 100D), and therefore detailed description will not be repeated.

[0121] FIG. 15 is a conceptual waveform diagram showing a normal turn-on operation of the gate driver according to the fifth embodiment.

[0122] As shown in FIG. 15, at time t0, when the control signal VIN changes from H level to L level and the turn-off operation is initiated, the output voltage VOUT, the input voltage VHV, and the current stop signal Vcut exhibit waveforms similar to those in FIG. 13.

[0123] At time t6, the control signal VIN changes from L level to H level to start the turn-on operation. In response to this, the drive circuit 150 charges the output terminal 103 and the gate of the semiconductor switching element 10a to increase the output voltage VOUT to a positive voltage Vcc higher than the threshold voltage Vthg. In addition, the current stop signal Vcut changes from H level to L level to start the detection operation by the Vce detection circuit 120.

[0124] At time t7, when the output voltage VOUT, i.e., the gate voltage Vge of the semiconductor switching element 10a, becomes higher than the threshold voltage Vthg, a current starts to flow between the collector and the emitter, and the input voltage VHV (collector-emitter voltage Vce) starts to drop. If the turn-on operation is completed normally, the input voltage VHV (collector-emitter voltage Vce) becomes approximately 0 (V). Therefore, at time t8, which is the delay time Tdp (delay circuit 181) after time t6 (start of the turn-on operation) has elapsed, the control signal S3 from the protection circuit 180 is at H level, so that the drive circuit 150 maintains the output voltage VOUT at the positive voltage Vcc.

[0125] In contrast to this, FIG. 16 shows a conceptual waveform diagram of a turn-on operation when a desaturated state occurs.

[0126] In FIG. 16 as well, the operation at turn-off, that is, the waveforms from time t0 to t6, are the same as in FIG.

[0127] In FIG. 16, after the turn-on operation starts at time t6, the input voltage VHV starts to decrease from time t7. However, in the semiconductor switching element 10a, an unsaturated state occurs due to an excessive collector-emitter current (overcurrent state), and therefore a voltage abnormality occurs in which the input voltage VHV (collector-emitter voltage Vce) does not decrease as in FIG. 15 (normal state).

[0128] Due to such a voltage abnormality, Vce>Vrdst, and therefore VN2>Vt3 in the voltage comparator 132, and therefore the detection signal VFd is set to the H level. In response to this, at time t8 when the delay time Tdp (delay circuit 181) has elapsed since time t6 (start of the turn-on operation), the control signal S3 (FIG. 14) from the protection circuit 180 changes to the L level.

[0129] In response to this, the drive circuit 150 reduces the output voltage VOUT to 0 (V), thereby turning off the semiconductor switching element 10a. This makes it possible to realize a protection function that automatically turns off the semiconductor switching element 10a in response to detection of an unsaturated state at the time of turn-on.

[0130] In addition, in FIG. 14, a configuration has been described in which the gate driving device 100D (FIG. 12) according to embodiment 4 further includes a voltage comparator 132 and a protection circuit 180 for a protection function by detecting a desaturated state. However, it is also possible to combine each of embodiments 1 to 3 with embodiment 4 by configuring each of the gate driving devices 100A to 100C according to embodiments 1 to 3 to further include a similar voltage comparator 132 and protection circuit 180.

[0131] Thus, according to the gate driving device of embodiment 5, in addition to the effects achieved by embodiments 1 to 4, it is possible to realize a protection function against overcurrent during turn-on operation by sharing the Vce detection circuit used during turn-off operation.

[0132] Embodiment 6 FIG. 17 is a conceptual circuit diagram illustrating the configuration of a gate driving device 100F according to the sixth embodiment.

[0133] 17, gate driver 100F differs from gate driver 100E (FIG. 14) in that it omits the arrangement of voltage comparator 132. In the sixth embodiment, a configuration is shown in which a common voltage can be used as a determination voltage Vr for detecting the rise of collector-emitter voltage Vce during a turn-off operation and a determination voltage Vrdst for detecting a desaturated state during a turn-on operation.

[0134] In the gate driver 100F, a detection signal VHd output from the voltage comparator 130 is input to the protection circuit 180. Since the voltage source 135 outputs the determination voltage Vt=Vt3, it is understood that the detection signal VHd during the turn-on operation is the same signal as the detection signal VFd output from the voltage comparator 132 in FIG.

[0135] The configuration of other parts of the gate driver 100F is similar to that of FIG. 14 (gate driver 100E), and therefore detailed description will not be repeated.

[0136] FIG. 18 is a conceptual waveform diagram showing a normal turn-on operation of the gate driver according to the sixth embodiment.

[0137] The waveform diagram in FIG. 18 is similar to the waveform diagram in FIG. 16, except that the determination voltage Vr used during the turn-off operation and the determination voltage Vrdst used during the turn-on operation are unified.

[0138] FIG. 19 is a conceptual waveform diagram showing a turn-on operation in which a desaturated state occurs in the gate driver according to the sixth embodiment.

[0139] The waveform diagram in FIG. 19 is similar to the waveform diagram in FIG. 17, except that the determination voltage Vr used during the turn-off operation and the determination voltage Vrdst used during the turn-on operation are unified.

[0140] In this way, when the decision voltage Vr used during the turn-off operation and the decision voltage Vrdst used during the turn-on operation can be made common, the arrangement of voltage comparator 132 in FIG. 14 can be omitted, so that the voltage comparator 130 used during the turn-off operation can be shared, thereby realizing a protection function against overcurrent in response to the detection of an unsaturated state during the turn-on operation.

[0141] However, in cases where the characteristics of the semiconductor switching element 10a require a relatively high threshold voltage Vrdst for detecting a desaturated state (for example, Vrdst=50 (V)), there is a concern that Vr=Vsdst may delay detection of the rise of Vce during turn-off operation. Therefore, in such cases, it is preferable to apply the configuration of the fifth embodiment (FIG. 14) in which both the voltage comparator 130 (threshold voltage Vr) and the voltage comparator 132 (threshold voltage Vrdst) are provided.

[0142] In addition, in FIG. 17, a configuration has been described in which the gate driving device 100D (FIG. 12) of embodiment 4 shares the voltage comparator 130 (Vr=Vrdst2) and further includes a protection circuit 180 for protecting against an unsaturated state. However, it is also possible to combine each of embodiments 1 to 3 with embodiment 6 by configuring each of the gate driving devices 100A to 100C of embodiments 1 to 3 such that Vr=Vrdst2 in the voltage comparator 130 and further includes a protection circuit 180.

[0143] Thus, according to the gate driving device of embodiment 6, in addition to the effects of embodiments 1 to 4, it is possible to realize a protection function against overcurrent during turn-on operation while reducing the number of additional circuit elements.

[0144] In this embodiment, examples of circuit configurations of the Vce detection circuit 120 that generate an output current (current Ib) to the voltage divider circuit 126 are illustrated in FIG. 6 (embodiment 2) and FIG. 9 (embodiment 3). However, as long as the Vce-Ib characteristics shown in FIG. 7 and FIG. 10 are realized, any circuit configuration can be applied to the "current supply circuit" that supplies the current Ib.

[0145] In addition, in the present embodiment, an example has been described in which the gate driving devices 100A to 100F are mounted on the same IC using HVIC technology, and the driving circuit 150 and peripheral circuits such as the Vce detection circuit 120 are mounted on the same IC. However, it is also possible to arrange the Vce detection circuit 120 as an external circuit of the driving circuit 150 configured as a driving IC.

[0146] Regarding the multiple embodiments described above, we would like to confirm that it is intended from the beginning of the application that the configurations described in each embodiment may be appropriately combined, including combinations not mentioned in the specification, to the extent that no inconsistencies or contradictions arise.

[0147] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0148] 10a semiconductor switching element, 22 low potential side node, 23 high potential side node, 100♯, 100A to 100F gate driver, 101 signal input terminal, 102 reference potential terminal, 103 output terminal, 104 voltage detection terminal, 120 Vce detection circuit, 121 current source, 122, 125 current mirror circuit, 123, 132, Q1, Q2, T1 to T4 transistor, 126 voltage divider circuit, 130 to 132 voltage comparator, 135 to 137 voltage source, 140, 181, 190 delay circuit, 150 drive circuit, 151, 152 sink circuit, 180 protection circuit, HVC high voltage circuit, I1, I2 gate current, IC drive, Ia, Ib current, Ir current value, LVC low voltage circuit, S1 delay signal, S2 signal, S3 Control signal (protection signal), VIN control signal (semiconductor switching element), Td, Tdh, Tdp delay time, VFd, VHd detection signal, VHV input voltage (voltage detection terminal), VHdly output signal, VOUT output voltage, Vcc positive voltage, Vce collector-emitter voltage, Vcut current stop signal, Vge gate voltage, Vpmos, Vthg threshold voltage, Vr, Vrdst, Vt, Vt2, Vt3 judgment voltage, Vs surge voltage.

Claims

1. A gate driver for a semiconductor switching element, a voltage detection circuit that detects a rise in an inter-electrode voltage between the positive electrode and the negative electrode when the semiconductor switching element is turned off; a drive circuit for driving a gate of the semiconductor switching element, a gate driver configured to control the timing of reducing the gate drive capability from a first drive capability to a second drive capability using a detection result by the voltage detection circuit during a turn-off operation of the semiconductor switching element;

2. the voltage detection circuit detects a rise in the inter-electrode voltage when the inter-electrode voltage becomes higher than a predetermined first determination voltage after the start of a turn-off operation of the semiconductor switching element; 2. The gate drive device according to claim 1, wherein the drive circuit sets the gate drive capability to the first drive capability at the start of the turn-off operation, and reduces the gate drive capability from the first drive capability to the second drive capability at a timing when a predetermined first delay time has elapsed after the voltage detection circuit detects a rise in the inter-electrode voltage.

3. The voltage detection circuit a current supply circuit and a voltage divider circuit connected in series between the positive electrode and the negative electrode; a voltage comparator that outputs a detection signal of a rise in the inter-electrode voltage when the output voltage of the voltage divider circuit is higher than a second determination voltage; the current supply circuit is configured so that an output current increases up to a saturation value as the inter-electrode voltage increases in a voltage region including the first determination voltage; the voltage divider circuit is configured to generate the output voltage proportional to the output current of the current supply circuit; 3. The gate drive device according to claim 2, wherein the second determination voltage is set in accordance with the output voltage generated by the voltage divider circuit in response to the output current when the inter-electrode voltage is the first determination voltage.

4. The current supply circuit includes: a first current mirror circuit connected between the positive electrode and the voltage divider circuit; the first current mirror circuit generates the output current according to a current at a node connected via a current source that outputs a constant current and a second current mirror circuit; 4. The gate driver of claim 3, wherein the first current mirror circuit includes first and second P-type transistors having sources electrically connected to the positive electrode and gates interconnected.

5. The first current mirror circuit comprises: an N-type third transistor connected between the first transistor and the second current mirror circuit so that the current supplied from the current supply circuit flows through it; a fourth P-type transistor connected between the second transistor and the voltage divider circuit, the gates of the first transistor and the second transistor are connected to a connection node of the second transistor and the fourth transistor; 5. The gate driver according to claim 4, wherein the gate of said fourth transistor is connected to a connection node between said first transistor and said third transistor.

6. The first current mirror circuit comprises: an N-type third transistor connected between the first transistor and the second current mirror circuit so that the current supplied from the current supply circuit flows through it; a resistive element connected between the first transistor and the third transistor; a fourth P-type transistor connected between the second transistor and the voltage divider circuit, the gates of the first transistor and the second transistor are connected to a connection node between the first transistor and the resistance element; 5. The gate driver according to claim 4, wherein the gate of said fourth transistor is connected to a connection node between said resistance element and said third transistor.

7. 5. The gate driver according to claim 4, further comprising a current supply stopping circuit for stopping current supply from the current source to the first current mirror circuit via the second current mirror circuit during a period from when the semiconductor switching element has been turned off until when the semiconductor switching element is next turned on.

8. a current supply stopping circuit for stopping the supply of current from the current source to the first current mirror circuit via the second current mirror circuit during the period from when the semiconductor switching element has been turned off until when the semiconductor switching element is turned on next; The current supply stopping circuit a fifth transistor connected in parallel with the second current mirror circuit to form a path for the constant current from the current source bypassing the second current mirror circuit; 7. The gate driver according to claim 5, wherein the fifth transistor is turned on during a period in which the output voltage of the drive circuit is lower than a third determination voltage that is lower than a threshold voltage of the semiconductor switching element.

9. the voltage detection circuit is further configured to detect a non-saturated state of the semiconductor switching element based on the inter-electrode voltage when the semiconductor switching element is turned on; 2. The gate driver according to claim 1, wherein the drive circuit drives the gate so as to turn off the semiconductor switching element when the unsaturated state is detected by the voltage detection circuit during the turn-on operation of the semiconductor switching element.

10. the voltage detection circuit further detects the unsaturated state of the semiconductor switching element when the inter-electrode voltage does not decrease below a predetermined fourth determination voltage after the start of the turn-on operation of the semiconductor switching element; The gate driver a protection circuit that generates a protection signal when the desaturation state is detected by the voltage detection circuit at a timing when a predetermined second delay time has elapsed since the start of the turn-off operation; 8. The gate driver according to claim 2, wherein the drive circuit drives the gate so as to turn off the semiconductor switching element when the protection signal is generated by the protection circuit.

11. 11. The gate driver according to claim 10, wherein the first determination voltage and the fourth determination voltage are common.

12. A gate drive device as claimed in claim 1, wherein the voltage detection circuit and the drive circuit are mounted on the same integrated circuit.

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