Communication circuit and integrated circuit

Abstract

To reduce the number of man hours to be changed in the change of a frequency of a signal handled by a communication circuit without changing a crystal oscillator.SOLUTION: An integrated circuit having a communication circuit comprises: a transmission circuit 10 that transmits a sinusoidal signal corresponding to one or 0 of transmission digital data; a reception circuit 20 that outputs reception digital data in which an input wave signal received corresponds to one or 0; a first memory 31 that stores a frequency setting value of the sinusoidal signal; and a second memory 32 that stores a frequency determination value of the input wave signal. The transmission circuit sets a frequency of the sinusoidal signal in accordance with the frequency setting value stored in the first memory. The reception circuit changes a transmission frequency of the signal by determining the frequency of the input wave signal in accordance with the frequency determination value stored in the second memory.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to communication circuits and integrated circuits. [Background technology]

[0002] 2. Description of the Related Art There is known a communication IC that is configured to oscillate a sine wave signal corresponding to a 1 or 0 signal of digital data provided from a microcomputer and outputs this sine wave signal from a signal output terminal (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-150306 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional communication circuits, the frequency of the signals handled by the communication circuits depends on the oscillation frequency of the crystal unit connected to the communication circuits, and therefore it is difficult to change the frequency of the signals handled by the communication circuits without replacing the crystal unit.

[0005] The present disclosure provides a communication circuit and an integrated circuit that can reduce the number of steps required to change the frequency of a signal handled by the communication circuit. [Means for solving the problem]

[0006] The first aspect is a transmission circuit for transmitting a sine wave signal corresponding to 1 or 0 of the transmitted digital data; a receiving circuit that outputs received digital data corresponding to a received input wave signal being 1 or 0; A first memory that stores a frequency setting value of the sine wave signal, The transmission circuit is a communication circuit that sets the frequency of the sine wave signal according to the frequency setting value stored in the first memory.

[0007] A second aspect is the communication circuit of the first aspect, The transmission circuit includes: a generator circuit for generating a sine wave setting code that varies according to the frequency setting value stored in the first memory; An output circuit may be included which converts the sine wave setting code into the sine wave signal and outputs the sine wave signal.

[0008] A third aspect is the communication circuit of the second aspect, The generation circuit may set an output period of each code value of the sine wave setting code in accordance with the transmission digital data and the frequency setting value stored in the first memory.

[0009] A fourth aspect is a communication circuit according to any one of the first to third aspects, A second memory for storing a frequency judgment value of the input wave signal is further provided. The receiving circuit may determine a frequency of the input wave signal according to the frequency decision value stored in the second memory.

[0010] A fifth aspect is the communication circuit of the fourth aspect, The receiving circuit may set the received digital data to 0 or 1 depending on the result of determining the frequency of the input wave signal.

[0011] A sixth aspect is the communication circuit of the fifth aspect, The receiving circuit may set the received digital data to one of 0 and 1 if the frequency of the input wave signal is within a frequency range determined by the frequency judgment value, and may set the received digital data to the other of 0 and 1 if the frequency of the input wave signal is not within the frequency range.

[0012] The seventh aspect is a transmission circuit for transmitting a sine wave signal corresponding to 1 or 0 of the transmitted digital data; a receiving circuit that outputs received digital data corresponding to a received input wave signal being 1 or 0; a memory for storing a frequency judgment value of the input wave signal; The receiving circuit is a communication circuit that determines the frequency of the input wave signal according to the frequency decision value stored in the memory.

[0013] The eighth aspect is An integrated circuit comprising: a communication circuit according to any one of the first to seventh aspects; and a data transmission / reception circuit that transmits the transmission digital data and receives the reception digital data.

[0014] The ninth aspect is A communication circuit according to any one of the first to sixth aspects, and a data transmission / reception circuit for transmitting the transmission digital data and receiving the reception digital data, The data transmission / reception circuit is an integrated circuit that provides the frequency setting value stored in the first memory to the communication circuit.

[0015] The tenth aspect is A communication circuit according to a seventh aspect, and a data transmission / reception circuit for transmitting the transmission digital data and receiving the reception digital data, The data transmission / reception circuit is an integrated circuit that provides the frequency decision value stored in the memory to the communication circuit. Effect of the Invention

[0016] The present disclosure can reduce the number of steps required to change the frequency of a signal handled by a communication circuit. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of an integrated circuit including a communication circuit according to an embodiment. [Diagram 2] 10 is a timing chart showing an example of a transmission operation. [Diagram 3] 10 is a timing chart showing an example of a receiving operation. [Figure 4]FIG. 2 is a diagram illustrating an example of the configuration of a generating circuit that generates a sine wave. [Diagram 5] FIG. 1 is a diagram illustrating an example of the configuration of an output circuit that outputs a sine wave. [Figure 6] 13 is a timing chart when the frequency of the sine wave signal is set to 500 kHz. [Figure 7] 13 is a timing chart when the frequency of the sine wave signal is set to 250 kHz. [Figure 8] FIG. 2 is a diagram illustrating an example of a configuration of an amplitude determination circuit. [Figure 9] FIG. 2 is a diagram illustrating an example of a configuration of a frequency determination circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0019] 1 is a diagram showing an example of a configuration of an integrated circuit including a communication circuit according to an embodiment. The integrated circuit 300 is a semiconductor integrated circuit that communicates with a communication partner circuit (not shown) (hereinafter, also referred to as a "communication partner circuit X"). The integrated circuit 300 includes a communication circuit 100 and a data transmission / reception circuit 200.

[0020] The communication circuit 100 is a communication interface circuit between a communication partner circuit X and a data transmitting / receiving circuit 200. The communication circuit 100 includes a transmitting circuit 10 and a receiving circuit 20. An example of the data transmitting / receiving circuit 200 is a microcomputer.

[0021] The transmission circuit 10 converts the transmission digital data TXD generated by the data transmission / reception circuit 200 into an analog sine wave signal SOUT and transmits the converted sine wave signal SOUT. The communication partner circuit X receives the sine wave signal SOUT transmitted from the transmission circuit 10.

[0022] The receiving circuit 20 receives an analog input wave signal AMPIN transmitted from the communication partner circuit X, and converts the received input wave signal AMPIN into received digital data RXD. The receiving circuit 20 outputs the converted received digital data RXD. The data transmitting / receiving circuit 200 receives the received digital data RXD output from the receiving circuit 20.

[0023] 2 is a timing chart showing an example of a transmission operation. The data transmitting / receiving circuit 200 transmits transmission digital data TXD consisting of signals of 0 and 1 according to the contents to be transmitted to the communication partner circuit X. The communication circuit 100 receives the transmission digital data TXD. The transmission circuit 10 in the communication circuit 100 transmits a sine wave signal SOUT corresponding to the signal of 1 or 0 of the transmission digital data TXD provided from the data transmitting / receiving circuit 200.

[0024] Fig. 2 shows an example of the transmission digital data TXD composed of a signal 0 whose low level is 0 volts and a signal 1 whose high level is 5 volts. Fig. 2 also illustrates a case where the transmission circuit 10 transmits a sine wave signal SOUT corresponding to the signal 0 of the transmission digital data TXD. However, the transmission circuit 10 may transmit a sine wave signal SOUT corresponding to the signal 1 of the transmission digital data TXD.

[0025] When the transmission digital data TXD is at a high level, the transmission circuit 10 holds the output of the sine wave signal SOUT at a phase of 0°. This causes a signal of a constant level to be output from the output terminal of the sine wave signal SOUT. When the transmission digital data TXD changes from a high level to a low level, the transmission circuit 10 starts outputting the sine wave signal SOUT from a phase of -90° after the transmission start delay time Tdon has elapsed. Note that the transmission circuit 10 may start outputting the sine wave signal SOUT from a phase of +90° after the transmission start delay time Tdon has elapsed.

[0026] When the transmission digital data TXD changes from low level to high level, the transmission circuit 10 forcibly holds the output of the sine wave signal SOUT at a phase of 0° after the transmission end delay time Tdoff has elapsed, regardless of the phase of the output of the sine wave signal SOUT. This stops the output of the sine wave signal SOUT.

[0027] In this manner, in the case of FIG. 2, the transmission circuit 10 transmits the sine wave signal SOUT during the period corresponding to the signal of 0 of the transmission digital data TXD.

[0028] 3 is a timing chart showing an example of a receiving operation. The communication partner circuit X transmits a sine wave signal (i.e., the input wave signal AMPIN received by the receiving circuit 20) according to the content to be transmitted to the data transmitting / receiving circuit 200, similar to the case where the transmitting circuit 10 transmits the sine wave signal SOUT. The receiving circuit 20 in the communication circuit 100 receives the input wave signal AMPIN. The receiving circuit 20 outputs received digital data RXD corresponding to the received input wave signal AMPIN being a signal of 1 or 0.

[0029] 3 illustrates a case where the receiving circuit 20 outputs received digital data RXD corresponding to an input wave signal AMPIN of 0. However, the receiving circuit 20 may output received digital data RXD corresponding to a received input wave signal AMPIN of 1.

[0030] When the receiving circuit 20 determines that the frequency of the received input wave signal AMPIN is within a predetermined normal range, it changes the receiving digital data RXD from high level to low level after the reception start delay time TDET1 has elapsed. The receiving circuit 20 maintains the receiving digital data RXD at low level during the period during which it determines that the frequency of the received input wave signal AMPIN is within the predetermined normal range. When the receiving circuit 20 determines that the frequency of the received input wave signal AMPIN is outside the predetermined normal range, it changes the receiving digital data RXD from low level to high level after the reception end delay time TDET2 has elapsed. Note that the case where it is determined that the frequency of the received input wave signal AMPIN is outside the predetermined normal range may include the case where it is determined that the input wave signal AMPIN is not detected.

[0031] In this manner, in the case of FIG. 3, the receiving circuit 20 outputs the received digital data RXD in which the signal is 0 during a period corresponding to the reception period of the input wave signal AMPIN whose frequency is within the normal range.

[0032] An example of a system in which such a communication method is used is a water heater system that has a function of communicating between a water heater main body and a remote control device via a communication line. The water heater system includes a water heater main body and at least one remote control device. The remote control device transmits, for example, a control signal (remote control signal) for remotely operating the water heater main body to the water heater main body via the communication line. The remote control device is installed, for example, in a kitchen or bathroom. The water heater main body transmits, for example, a control signal (remote control signal) for displaying setting information such as hot water temperature on the display of the remote control device to the remote control device via the communication line.

[0033] 1 is built into at least one of the remote control device and the water heater body, for example. In this case, the integrated circuit 300 is also called a water heater IC. The sine wave signal SOUT and the input wave signal AMPIN are transmitted on a communication line connecting the remote control device and the water heater body.

[0034] 1, the communication circuit 100 of this embodiment includes a memory circuit 30. The memory circuit 30 includes a first memory 31 that stores a frequency set value A of the sine wave signal SOUT, and a second memory 32 that stores a frequency judgment value B of the input wave signal AMPIN. The memory circuit 30 may include only one of the first memory 31 and the second memory 32. For example, the first memory 31 is a register that stores the frequency set value A, and the second memory 32 is a register that stores the frequency judgment value B.

[0035] The frequency set value A is a value for setting the frequency of the sine wave signal SOUT transmitted from the transmission circuit 10. The transmission circuit 10 sets the frequency of the sine wave signal SOUT in accordance with the frequency set value A stored in the first memory 31. As a result, by changing the frequency set value A stored in the first memory 31 to a different value, the transmission circuit 10 can change the setting of the frequency of the sine wave signal SOUT in accordance with the changed value. Therefore, the number of steps for changing the frequency of the signal handled by the communication circuit 100 (in this case, the sine wave signal SOUT) can be reduced.

[0036] The data transmitting / receiving circuit 200 provides the communication circuit 100 with the frequency set value A stored in the first memory 31. As a result, the frequency set value A provided to the communication circuit 100 by the data transmitting / receiving circuit 200 is changed to a different value, and the data transmitting / receiving circuit 200 can rewrite the frequency set value A stored in the first memory 31 to the changed value. The transmission circuit 10 changes the setting of the frequency of the sine wave signal SOUT in accordance with the rewritten value. This makes it possible to reduce the number of steps required to change the frequency of the signal (in this case, the sine wave signal SOUT) handled by the communication circuit 100.

[0037] The data transmitting / receiving circuit 200 transmits, for example, an address signal ADDR that specifies an address in the first memory 31, and a data signal DATA that indicates the frequency setting value A. As a result, the frequency setting value A provided from the data transmitting / receiving circuit 200 is stored in the first memory 31.

[0038] The frequency judgment value B is a value for judging the frequency of the input wave signal AMPIN received by the receiving circuit 20. The receiving circuit 20 judges the frequency of the input wave signal AMPIN according to the frequency judgment value B stored in the second memory 32. As a result, the receiving circuit 20 can change judgment conditions such as the judgment threshold value of the frequency of the input wave signal AMPIN according to the changed value by changing the frequency judgment value B stored in the second memory 32 to a different value. Therefore, the number of steps for changing the frequency of the signal handled by the communication circuit 100 (in this case, the input wave signal AMPIN) can be reduced.

[0039] The data transmitting / receiving circuit 200 provides the communication circuit 100 with the frequency judgment value B stored in the second memory 32. As a result, the frequency judgment value B provided to the communication circuit 100 from the data transmitting / receiving circuit 200 is changed to a different value, and the data transmitting / receiving circuit 200 can rewrite the frequency judgment value B stored in the second memory 32 to the changed value. The receiving circuit 20 changes the judgment conditions such as the judgment threshold value of the frequency of the input wave signal AMPIN according to the rewritten value. Therefore, the number of steps for changing the frequency of the signal handled by the communication circuit 100 (in this case, the input wave signal AMPIN) can be reduced.

[0040] The data transmitting / receiving circuit 200 transmits, for example, an address signal ADDR that specifies an address of the second memory 32 and a data signal DATA that indicates the frequency judgment value B. As a result, the frequency judgment value B provided from the data transmitting / receiving circuit 200 is stored in the second memory 32.

[0041] The transmission circuit 10 includes, for example, a generation circuit 11 that generates a sine wave signal SOUT, and an output circuit 12 that outputs the sine wave signal SOUT generated by the generation circuit 11. The generation circuit 11 sets the frequency of the sine wave signal SOUT according to a frequency set value A stored in a first memory 31. For example, when a frequency set value A for setting the frequency of the sine wave signal SOUT to 500 kHz is stored in the first memory 31, the output circuit 12 outputs a sine wave signal SOUT of 500 kHz. For example, when a frequency set value A for setting the frequency of the sine wave signal SOUT to 250 kHz is stored in the first memory 31, the output circuit 12 outputs a sine wave signal SOUT of 250 kHz.

[0042] The generation circuit 11 may generate a sine wave setting code that changes according to the frequency setting value A stored in the first memory 31. The output circuit 12 converts the sine wave setting code generated by the generation circuit 11 into a sine wave signal SOUT and outputs it. This makes it possible to reduce the number of steps required to change the frequency of the sine wave signal SOUT.

[0043] Fig. 4 is a diagram showing an example of the configuration of a generation circuit that generates a sine wave. Fig. 4 shows an example of a generation circuit 11 that generates a sine wave setting code that changes according to a frequency setting value A stored in a first memory 31. The generation circuit 11 shown in Fig. 4 is a pseudo sine wave generator that generates a DAC (Digital to Analog Converter) setting code, which is an example of a sine wave setting code.

[0044] The generation circuit 11 includes a counter 41, a table 42, and a selector 43. The counter 41 generates a select signal for setting a period for outputting each of the DAC code values ​​stored in the table 42 according to the transmission digital data TXD and the frequency setting value A stored in the first memory 31. The DAC code value is a code value of a DAC setting code. The table 42 is a memory for storing a plurality of DAC code values ​​for generating a sine wave signal SOUT, which is a pseudo sine wave. The selector 43 selects and outputs a DAC code value stored in the table 42 according to the select signal generated by the counter 41. In this way, a DAC setting code for outputting a sine wave signal SOUT, which is a pseudo sine wave, is generated.

[0045] Fig. 5 is a diagram showing an example of the configuration of an output circuit that outputs a sine wave. The output circuit 12 is a DAC that converts the digital DAC setting code generated by the generation circuit 11 into an analog sine wave signal SOUT and outputs it. Fig. 4 illustrates the case where the output circuit 12 is a 4-bit DAC. However, the number of bits may be a value other than 4 bits.

[0046] The output circuit 12 has resistor circuits 51, 52, 53, and 54 to which digital DAC setting codes are input, and a resistor circuit 50 that outputs an analog sine wave signal SOUT from an output terminal. The output circuit 12 outputs the sine wave signal SOUT by resistive voltage division by the resistor circuits 50, 51, 52, 53, and 54. R represents the resistance value of each resistor element, and 2R represents twice the resistance value of R.

[0047] The transmission circuit 10 has the configuration shown in FIGS. 4 and 5, and can transmit a sine wave signal SOUT that is a pseudo sine wave as shown in FIG. 6 or FIG.

[0048] Fig. 6 is a timing chart when the frequency of the sine wave signal SOUT is set to 500 kHz. Fig. 7 is a timing chart when the frequency of the sine wave signal SOUT is set to 250 kHz. In Fig. 6 or 7, the counter 41 (Fig. 4) counts the elapsed time since the logic of the transmission digital data TXD is inverted (in this example, the elapsed time since the logic is inverted from high level to low level) according to the clock signal CLK provided from the data transmission / reception circuit 200. The counter 41 switches and outputs the DAC setting code generated by the DAC code value stored in the table 42 according to a period determined according to the frequency setting value A.

[0049] Therefore, by changing the value of the frequency setting value A, the transmission circuit 10 can output a sine wave signal SOUT of a different frequency.

[0050] 1, the receiving circuit 20 may set the receiving digital data RXD to 0 or 1 depending on the result of determining the frequency of the received input wave signal AMPIN. The receiving circuit 20 has an amplitude determining circuit 21 that determines the amplitude of the received input wave signal AMPIN, and a frequency determining circuit 22 that determines the frequency of the received input wave signal AMPIN.

[0051] The amplitude determination circuit 21 determines whether the amplitude of the sinusoidal input wave signal AMPIN satisfies a predetermined amplitude standard. The amplitude determination circuit 21 converts the input wave signal AMPIN that satisfies the predetermined amplitude standard into a square wave amplitude output signal LATOUT having the same frequency as the input wave signal AMPIN.

[0052] The frequency determination circuit 22 determines whether or not the frequency of the input wave signal AMPIN (here, the frequency of the converted amplitude output signal LATOUT) is included in a frequency range R determined by the frequency determination value B. The frequency range R indicates a normal range of frequencies. When the frequency of the amplitude output signal LATOUT is included in the frequency range R, the frequency determination circuit 22 sets the received digital data RXD to one value of 0 or 1 (0 in the case of FIG. 3). On the other hand, when the frequency of the amplitude output signal LATOUT is not included in the frequency range R, the frequency determination circuit 22 sets the received digital data RXD to the other value of 0 or 1 (1 in the case of FIG. 3).

[0053] 8 is a diagram showing an example of the configuration of an amplitude judgment circuit. The amplitude judgment circuit 21 has a comparator 77 that compares the amplitude detection value of the input wave signal AMPIN with a threshold value VH, a comparator 78 that compares the amplitude detection value of the input wave signal AMPIN with a threshold value VL, and a latch circuit 79. The amplitude judgment circuit 21 has an amplitude detection circuit that detects the amplitude of the input wave signal AMPIN by dividing it using resistors 71 and 72, and a threshold generation circuit that generates threshold values ​​VH and VL by dividing the power supply voltage using resistors 73, 74, 75, and 76. The threshold value VH is higher than the threshold value VL.

[0054] The latch circuit 79 sets the level of the amplitude output signal LATOUT to a first logic level (e.g., high level) when the amplitude detection value of the input wave signal AMPIN is higher than the threshold VH. The latch circuit 79 sets the level of the amplitude output signal LATOUT to a second logic level (e.g., low level) when the amplitude detection value of the input wave signal AMPIN is lower than the threshold VL. The latch circuit 79 holds the level of the amplitude output signal LATOUT when the amplitude detection value of the input wave signal AMPIN is higher than the threshold VL and lower than the threshold VH.

[0055] With such a configuration, the amplitude determination circuit 21 can convert the sinusoidal input wave signal AMPIN into a square-wave amplitude output signal LATOUT (see FIG. 3) having the same frequency as the input wave signal AMPIN.

[0056] 9 is a diagram showing an example of the configuration of a frequency determination circuit. The frequency determination circuit 22 determines whether or not the frequency of the amplitude output signal LATOUT from the amplitude determination circuit 21 is included in the frequency range R. The upper and lower limits of the frequency range R are determined by the frequency determination value B stored in the second memory 32. When the frequency of the amplitude output signal LATOUT is within the frequency range R, the frequency determination circuit 22 sets the received digital data RXD to one level (for example, low level). On the other hand, when the frequency of the amplitude output signal LATOUT is outside the frequency range R, the frequency determination circuit 22 sets the received digital data RXD to the other level (for example, high level).

[0057] The frequency determination circuit 22 has a period measurement counter 81, a detection determination circuit 82, and an output latch circuit 83. The period measurement counter 81 constantly monitors the period (in other words, the frequency) of the amplitude output signal LATOUT. The detection determination circuit 82 validates the amplitude output signal LATOUT when the frequency of the amplitude output signal LATOUT is within the frequency range R, and invalidates the amplitude output signal LATOUT when the frequency of the amplitude output signal LATOUT is outside the frequency range R (when the frequency is abnormal).

[0058] When the period measurement counter 81 counts a predetermined number of edges from the first edge of the amplitude output signal LATOUT, the detection presence / absence determination circuit 82 switches the reception digital data RXD from high level to low level (see FIG. 3). On the other hand, when a frequency abnormality is detected in the amplitude output signal LATOUT a predetermined number of times or more within a predetermined time, the detection presence / absence determination circuit 82 switches the reception digital data RXD from low level to high level (see FIG. 3).

[0059] Therefore, the receiving circuit 20 can change the upper limit or lower limit of the frequency range R by changing the value of the frequency judgment value B.

[0060] As described above, the embodiment has been described, but the above embodiment is presented as an example, and the present invention is not limited to the above embodiment. The above embodiment can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0061] 10 Transmitting circuit 11 Generation circuit 12 Output circuit 20 Receiving circuit 21 Amplitude judgment circuit 22 Frequency determination circuit 30 Memory circuit 31 First Memory 32 Second Memory 41 Counter 42 Table 43 Selector 50,51,52,53,54 Resistor circuit 71, 72, 73, 74, 75, 76 Resistance 77,78 Comparator 79 Latch Circuit 81 Period Measurement Counter 82 Detection presence / absence determination circuit 83 Output latch circuit 100 Communication Circuit 200 Data transmission / reception circuit 300 Integrated Circuits

Claims

1. a transmission circuit for transmitting a sine wave signal corresponding to 1 or 0 of the transmitted digital data; a receiving circuit that outputs received digital data corresponding to a received input wave signal being 1 or 0; a first memory for storing a frequency setting value of the sine wave signal; The transmission circuit sets the frequency of the sine wave signal according to the frequency setting value stored in the first memory.

2. The transmission circuit includes: a generator circuit for generating a sine wave setting code that varies according to the frequency setting value stored in the first memory; 2. The communication circuit according to claim 1, further comprising: an output circuit that converts the sine wave setting code into the sine wave signal and outputs the sine wave signal.

3. The communication circuit according to claim 2 , wherein the generation circuit sets an output period of each code value of the sine wave setting code in accordance with the transmission digital data and the frequency setting value stored in the first memory.

4. a second memory for storing a frequency judgment value of the input wave signal; The communication circuit of claim 1 , wherein the receiving circuit determines a frequency of the input wave signal according to the frequency determination value stored in the second memory.

5. 5. The communication circuit according to claim 4, wherein the receiving circuit sets the received digital data to 0 or 1 depending on a result of determining the frequency of the input wave signal.

6. 6. The communication circuit of claim 5, wherein the receiving circuit sets the received digital data to one of 0 and 1 when the frequency of the input wave signal is within a frequency range determined by the frequency judgment value, and sets the received digital data to the other of 0 and 1 when the frequency of the input wave signal is not within the frequency range.

7. a transmission circuit for transmitting a sine wave signal corresponding to 1 or 0 of the transmitted digital data; a receiving circuit that outputs received digital data corresponding to a received input wave signal being 1 or 0; a memory for storing a frequency judgment value of the input wave signal; The receiving circuit determines a frequency of the input wave signal according to the frequency determination value stored in the memory.

8. 8. An integrated circuit comprising: the communication circuit according to claim 1; and a data transmission / reception circuit that transmits the transmission digital data and receives the reception digital data.

9. 7. A communication device comprising: the communication circuit according to claim 1; and a data transmission / reception circuit that transmits the transmission digital data and receives the reception digital data, The data transmission / reception circuit provides the frequency setting value stored in the first memory to the communication circuit.

10. A data transmission / reception circuit for transmitting the transmission digital data and receiving the reception digital data, comprising: the communication circuit according to claim 7; The data transmission / reception circuitry provides the frequency decision value stored in the memory to the communication circuitry.

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