Operation verification control device, operation verification control method, and operation verification control program

Abstract

To more efficiently and highly accurately detect presence of a defective portion in operation verification of a logic circuit.SOLUTION: An operation verification control device 40 includes: a counting unit 41 that counts the number according to the passage of time; an adding unit 42 that adds, to input data 401, numerical data 420 indicating the number counted by the counting unit 41 at a timing when the input data 401 is input to a target part 50 for operation verification, and adds, to output data 402, the numerical data 420 indicating the number counted by the counting unit 41 at a timing when the output data 402 is output from the target part 50 for operation verification; a selection unit 43 that selects, in the input data 401 and the output data 402, a combination of the input data 401 and the output data 402 in which the number indicated by the added numerical data 420 satisfies a predetermined selection condition 430; and an output unit 44 that outputs the selected input data 401 and the output data 402 to an analysis unit 60 that analyzes operation of the target part 50 for operation verification.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to an operation verification control device, an operation verification control method, and an operation verification control program. [Background technology]

[0002] As the integration density of semiconductors increases year by year, the content of operational verification of logic circuits using such semiconductors becomes more complicated and cumbersome, making it difficult to identify the location of operational malfunctions. Therefore, technology for more appropriately identifying the location of operational malfunctions in operational verification of logic circuits is desired.

[0003] In relation to the above-mentioned technology, Patent Document 1 discloses an inspection device for a semiconductor device including at least a scan-designed logic circuit and a memory. This inspection device inputs a scan-in signal to be applied to the scan-designed logic circuit, a memory test signal to be applied to the memory, and an external test mode control signal to the semiconductor device. This inspection device includes a scan determination means for comparing and determining the scan-in signal with a scan-out signal of the scan-designed logic circuit, a memory determination means for comparing and determining the memory test signal with an output signal of the memory, and a test mode control means for controlling the scan determination means and the memory determination means by a test mode control signal. This inspection device then extracts a memory determination signal and a scan determination signal separately from the output sides of the memory determination means and the scan determination means. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2003-218179 A Summary of the Invention [Problem to be solved by the invention]

[0005] In devices having logic circuits, aging tests and the like are usually performed to check whether there are any operational defects by operating the device for a long time. In such aging tests and the like, it is required to efficiently and accurately detect the presence of defective parts that become apparent when the operation verification test is performed for a long time. In other words, the challenge is to detect the presence of defective parts more efficiently and accurately in the operation verification of logic circuits. It cannot be said that the above-mentioned Patent Document 1 is yet sufficient to solve such a problem.

[0006] A primary object of the present invention is to more efficiently and accurately detect the presence of a defective portion in verifying the operation of a logic circuit. [Means for solving the problem]

[0007] An operational verification control device according to one embodiment of the present invention comprises a counting means for counting numbers according to the passage of time, an adding means for adding numerical data to the input data indicating the number counted by the counting means at the timing when the input data is input into a part that is a target of operational verification, and adding numerical data to the output data indicating the number counted by the counting means at the timing when the output data is output from the part that is a target of operational verification, a selecting means for selecting a combination of the input data and the output data such that the number indicated by the added numerical data satisfies a predetermined selection condition, and an output means for outputting the selected input data and output data to an analyzing means for analyzing the operation of the part that is a target of operational verification.

[0008] In another aspect of achieving the above-mentioned object, an operation verification control method according to one embodiment of the present invention counts numbers over time using an information processing device, adds numerical data to the input data indicating the number counted at the timing when input data is input into a part that is a target of operation verification, adds numerical data to the output data indicating the number counted at the timing when output data is output from the part that is a target of operation verification, selects a combination of the input data and the output data in which the number indicated by the added numerical data satisfies a predetermined selection condition, and outputs the selected input data and output data to an analysis means that analyzes the operation of the part that is a target of operation verification.

[0009] In addition, in a further aspect of achieving the above-mentioned object, an operation verification control program according to one embodiment of the present invention causes a computer to execute a counting process that counts numbers according to the passage of time; an addition process that adds numerical data indicating the number counted by the counting process to the input data at the timing when input data is input into a part that is a target of operation verification, and adds numerical data indicating the number counted by the counting process to the output data at the timing when output data is output from the part that is a target of operation verification; a selection process that selects a combination of the input data and the output data such that the number indicated by the added numerical data satisfies a predetermined selection condition, and an output process that outputs the selected input data and output data to an analysis means that analyzes the operation of the part that is a target of operation verification.

[0010] Furthermore, the present invention can also be realized by a computer-readable, non-volatile recording medium in which such an operation verification control program (computer program) is stored. Effect of the Invention

[0011] The present invention can detect the presence of a defective portion more efficiently and with higher accuracy in verifying the operation of a logic circuit. [Brief description of the drawings]

[0012] [Figure 1] 1 is a block diagram showing a configuration of an operation verification system 1 according to the present disclosure. [Diagram 2] 1 is a block diagram showing detailed configurations of an input unit 17 and an operation verification target circuit 20 of an operation verification control device 10 according to the present disclosure. [Diagram 3] This is a time chart showing an example of the count value of the timer 11 that the operation verification control device 10 according to the present disclosure adds to the input data to the operation verification target circuit 20 and the output data from the operation verification target circuit 20, and the values ​​of these data. [Figure 4A] 1 is a flowchart (1 / 2) showing the operation of the operation verification system 1 according to the present disclosure. [Figure 4B] 11 is a flowchart (2 / 2) showing the operation of the operation verification system 1 according to the present disclosure. [Diagram 5] 2 is a block diagram showing a configuration of an operation verification control device 40 according to the present disclosure. FIG. [Figure 6] 4 is a flowchart showing the operation of an operation verification control device 40 according to the present disclosure. [Figure 7] FIG. 9 is a block diagram showing a configuration of an information processing device 900 capable of realizing an operation verification control device according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0014] <First embodiment> 1 is a block diagram showing a configuration of an operation verification system 1 according to the present disclosure. The operation verification system 1 broadly includes an operation verification control device 10, an operation verification target circuit 20 (an example of a target part for operation verification), and a management terminal 30. The operation verification control device 10 is an information processing device such as a server that controls the execution of operation verification (including, for example, aging tests) of the operation verification target circuit 20, which is a logic circuit including semiconductors and the like. The operation verification control device 10 and the operation verification target circuit 20 operate in synchronization with each other using the same operation clock signal.

[0015] The management terminal 30 is an information processing device such as a personal computer, tablet terminal, or smartphone used by a user of the operation verification control device 10. The management terminal 30 accepts input operations by the user and inputs the information input by the user to the operation verification control device 10. The management terminal 30 displays the information output from the operation verification control device 10 on a display screen (not shown) provided therein.

[0016] The operation verification control device 10 includes a timer 11, an addition unit 12, a selection unit 13, an output unit 14, a measurement unit 15, a restart control unit 16, an input unit 17, a reception unit 18, a storage unit 19, an operation verification data generation unit 100, a first analysis unit 101, and a second analysis unit 102. The timer 11, the addition unit 12, the selection unit 13, the output unit 14, the measurement unit 15, the restart control unit 16, the input unit 17, and the reception unit 18 are examples of a counting means, an addition means, a selection means, an output means, a measurement means, a restart means, an input means, and a reception means, respectively.

[0017] The storage unit 19 is, for example, a storage device such as a RAM (Random Access Memory) 903 or a hard disk 904, which will be described later with reference to Fig. 7. At least a part of the storage unit 19 may be provided in one or more external devices capable of communicating with the operation verification control device 10. The storage unit 19 stores operation verification conditions 190, which will be described later.

[0018] In addition, the operation verification control device 10 of the present disclosure includes a first analysis unit 101 and a second analysis unit 102 described below, but the first analysis unit 101 (an example of an analysis means) and the second analysis unit 102 may be included in an external device communicatively connected to the operation verification control device 10.

[0019] The receiving unit 18 receives operation verification conditions 190 inputted via an input operation on the management terminal 30 by a user, and stores the received operation verification conditions 190 in the storage unit 19. The operation verification conditions 190 include, for example, parameters (representing an execution environment for operation verification) that control the execution of operation verification on the operation verification target circuit 20 by the operation verification control device 10. The receiving unit 18 may receive the operation verification conditions 190 from an external device (not shown) that can communicate with the operation verification control device 10.

[0020] The timer 11 has a function of counting a number according to the passage of time, and starts counting the passage of time, for example, when the operation verification control device 10 is started. The timer 11 may count the elapsed time expressed, for example, by year, month, day, hour, minute, and second (including millisecond to nanosecond granularity). The timer 11 may, for example, count up by one in synchronization with the operation clock of the operation verification control device 10 and output the value as the elapsed time.

[0021] The operation verification data generating unit 100 generates input data to be input to the operation verification target circuit 20 based on the operation verification conditions 190. The operation verification conditions 190 may include, for example, an algorithm for generating a pattern of input data for verifying the operation of the operation verification target circuit 20 as comprehensively as possible. For example, an existing technique used in an aging test or the like can be applied as the algorithm. The operation verification data generating unit 100 inputs the generated input data to the input unit 17.

[0022] 2 is a block diagram showing a detailed configuration of the input unit 17 and the operation verification target circuit 20 of the operation verification control device 10 according to the present disclosure. Hereinafter, the configurations of the input unit 17 and the operation verification target circuit 20 will be described with reference to FIG.

[0023] The input unit 17 includes a function a 171, a function b 172, and a function c 173, which are logic circuits each performing a predetermined logical operation. In the input unit 17, the functions a 171, b 172, and c 173 are connected in series. The input data input from the operation verification data generation unit 100 to the input unit 17 is input from the function a 171 to the operation verification target circuit 20 via logic circuits connected in series in the order of the functions c 173, b 172, and a 171. It is assumed that the input unit 17 has been previously confirmed to have no defects and to operate normally.

[0024] The operation verification target circuit 20 includes a function A21, a function B22, and a function C23, which are logic circuits each performing a predetermined logical operation. In the operation verification target circuit 20, the function A21, the function B22, and the function C23 are connected in series.

[0025] The input unit 17 and the circuit 20 to be verified are in a logically opposed relationship, and more specifically, the above-mentioned function A21 and function a171 are logically opposed, the function B22 and function b172 are logically opposed, and the function C23 and function c173 are logically opposed. In this disclosure, for example, a function that outputs a value y when a value x is input and a function that outputs a value x when a value y is input are referred to as being logically opposed to each other. More specifically, examples of logically opposed functions include a function that adds a value to an input value and a function that subtracts a value from an input value, or a function that multiplies an input value by a value and a function that divides the input value.

[0026] Function A21, function B22, and function C23 each include a first input and a first output, and a second input and a second output. When function A21, function B22, and function C23 output data input from the first input to the first output, they operate as function A21, function B22, and function C23, respectively. On the other hand, when function A21, function B22, and function C23 output data input from the second input to the second output, they operate as functions equivalent to function a171, function b172, and function c173, respectively. That is, in function A21, function B22, and function C23, the function of outputting data input from the first input to the first output and the function of outputting data input from the second input to the second output are in a logically opposed relationship with each other.

[0027] The circuit 20 to be verified for operation also includes selection circuits 24 and 25. The selection circuit 24 selects either the data output from the first output of the function A21 or the data output from the second output of the function B22, and inputs the selection result to the second input of the function A21. The selection circuit 25 selects either the data output from the first output of the function B22 or the data output from the second output of the function C23, and inputs the selection result to the second input of the function B22. The selection operation of the selection circuits 24 and 25 described above is determined by information included in the verification condition 190, which indicates the selection of one of a plurality of signal paths related to the processing of data in the circuit 20 to be verified for operation.

[0028] Here, function A21 outputs value y from the first output when value x is input to the first input, function B22 outputs value z from the first output when value y is input to the first input, and function C23 outputs value w from the first output when value z is input to the first input. In this case, function A21 outputs value x from the second output when value y is input to the second input, function B22 outputs value y from the second output when value z is input to the second input, and function C23 outputs value z from the second output when value w is input to the second input. Similarly, function a171 outputs value x when value y is input, function b172 outputs value y when value z is input, and function c173 outputs value z when value w is input.

[0029] When a value w is input to the input unit 17 as input data from the operation verification data generation unit 100, function c173 to which the value w is input outputs a value z to function b172, function b172 to which the value z is input outputs a value y to function a171, and function a171 to which the value y is input outputs a value x to a first input of function A21 in the operation verification target circuit 20. The input unit 17 outputs the data input to function c173 from the operation verification data generation unit 100, the data output from function c173, the data output from function b172, and the data output from function a171 to the addition unit 12 as input data for the operation verification target circuit 20.

[0030] In the above case, function A21, to which the value x is input from function a171 in input unit 17 to its first input, outputs the value y from its first output to the first input of function B22 and to the selection circuit 24. Function B22, to which the value y is input to its first input, outputs the value z from its first output to the first input of function C23 and to the selection circuit 25. Function C23, to which the value z is input to its first input, outputs the value w from its first output to the second analysis unit 102.

[0031] The second analysis unit 102, to which a value w is input from the first output of the function C23 in the circuit 20 to be verified, folds back the input value w and outputs it to the second input of the function C23, and the function C23, to which the value w is input to its second input, outputs the value z from its second output to the selection circuit 25. The selection circuit 25 selects either the value z input from the first output of the function B22 or the value z input from the second output of the function C23, and outputs the selected value z to the second input of the function B22. The function B22, to which the value z is input to its second input, outputs the value y from its second output to the selection circuit 24. The selection circuit 24 selects either the value y input from the first output of the function A21 or the value y input from the second output of the function B22, and outputs the selected value y to the second input of the function A21. The function A21, to which the value y is input to its second input, outputs the value x from its second output. The circuit 20 under operation verification outputs to the addition unit 12 as output data from the circuit 20 under operation verification the data output from the second output of function A21, the data output from the selection circuit 24, the data output from the selection circuit 25, the data input from the second analysis unit 102 to the second input of function C23, and the data input from the first output of function C23 to the second analysis unit 102.

[0032] The adding unit 12 adds the time counted by the timer 11 (the count value of the timer 11) as a timestamp to the input data for the operation verification target circuit 20, which is input from the input unit 17 as described above, and to the output data from the operation verification target circuit 20, which is input from the operation verification target circuit 20 as described above. The time counted by the timer 11 is an example of numerical data.

[0033] FIG. 3 is a time chart showing an example of the count value (timestamp) of the timer 11 that the addition unit 12 of the operation verification control device 10 according to the present disclosure adds to the input data to the operation verification target circuit 20 and the output data from the operation verification target circuit 20, and an example of the values ​​of these data.

[0034] In the example shown in FIG. 3, in the input unit 17 and the operation verification target circuit 20 illustrated in FIG. 2, the time required for each of the function A21, function B22, function C23, function a171, function b172, and function c173 to process and output the input data is set to one cycle of the operation clock. In addition, in the second analysis unit 102, the time required for the data input from the first output of the function C23 to be folded back to the second input of the function C23 and output is also set to one cycle of the operation clock. Note that the time required for each function to process and output the input data is not limited to one cycle of the operation clock, and may require, for example, two or more cycles. The timer 11 counts up its count value by one for each cycle of the operation clock, such as "0001", "0002", etc. In addition, according to the operation verification condition 190, the selection circuit 24 selects and outputs the first output of the function A21, and the selection circuit 25 selects and outputs the first output of the function B22.

[0035] 3, the count value of the timer 11 when data of the value w is input from the operation verification data generation unit 100 to the function c 173 of the input unit 17 is "0001". In this case, the addition unit 12 adds the count value "0001" of the timer 11 to the data of the value w input to the function c 173. Note that in this disclosure, data whose value is w and to which "0001" is added as the count value of the timer 11 will be described as w(0001), as shown in FIG.

[0036] The function c173 processes the data of the value w input as described above in the next cycle of the operating clock, and outputs data of the value z. At this time, the addition unit 12 adds the count value "0002" of the timer 11 to the data of the value z output from the function c173 (i.e., z(0002)).

[0037] The data of value z output from function c173 is then processed over time in the input unit 17 and the circuit 20 under operation verification. The adding unit 12 generates data y(0003), x(0004), y(0005), z(0006), w(0007), w(0008), and x(0006) by adding the count value of the timer 11 to the data processed over time as shown in FIG.

[0038] Furthermore, if the operation verification condition 190 is different from the above case and indicates that the selection circuit 24 selects and outputs the second output of function B22 and the selection circuit 25 selects and outputs the second output of function C23, the time chart for the output data from the operation verification target circuit 20 will be different from that in Figure 3.

[0039] The adding unit 12 outputs the input data to the operation verification target circuit 20 and the output data from the operation verification target circuit 20 to which the count value of the timer 11 has been added as described above, to the selecting unit 13 and the measuring unit 15 .

[0040] The selection unit 13 selects a combination of input data and output data for which the count value of the added timer 11 satisfies a selection condition included in the operation verification condition 190, with respect to the input data to the circuit 20 to be operationally verified and the output data from the circuit 20 to be operationally verified input from the addition unit 12.

[0041] 3, if the operation verification target circuit 20 operates normally, it is expected that the data w(0001) input to function c173, the data w(0007) output from the first output of function C23, and the data w(0008) input to the second input to function C23 will be equal in value. Therefore, in this case, the first analysis unit 101 only needs to confirm whether the data input to function c173 with the timer 11 count value of 0001, the data output from the first output of function C23 with the timer 11 count value of 0007, and the data input to the second input of function C23 with the timer 11 count value of 0008 are equal in value. In this case, the selection condition included in the operation verification condition 190 need only represent the selection of a combination of data input to function c173 having a timer 11 count value of 0001, data output from a first output of function C23 having a timer 11 count value of 0007, and data input to a second input of function C23 having a timer 11 count value of 0008.

[0042] Similarly, if the operation verification target circuit 20 operates normally, it is expected that the data z (0002) output from the function c173 and the data z (0006) output from the selection circuit 25 will be equal in value. Therefore, in this case, the selection condition included in the operation verification condition 190 need only represent the selection of a combination of the data output from the function c173 in which the count value of the timer 11 is 0002, and the data output from the selection circuit 25.

[0043] In this way, the selection conditions included in the operation verification conditions 190 represent the selection of a combination of data whose values ​​are equal, for example, input data to the operation verification target circuit 20 in which the count value of the timer 11 is 0001, and output data from the operation verification target circuit 20 in which the count values ​​of the timer 11 are 0007 and 0008.

[0044] The selection unit 13 outputs the data included in the input data to the operation verification target circuit 20 selected as described above and the output data from the operation verification target circuit 20 to the output unit 14. The selection unit 13 may include a buffer capable of holding the data input from the addition unit 12 so that the selection unit 13 can select and output data having different count values ​​of the timer 11 (i.e., data generated at different timings).

[0045] Furthermore, if the operation verification condition 190 indicates that the selection circuit 24 selects and outputs the second output of function B22 and that the selection circuit 25 selects and outputs the second output of function C23, unlike the case illustrated in Figure 3, the selection conditions included in the operation verification condition 190 also differ from the case illustrated in Figure 3.

[0046] The measurement unit 15 measures the number of data included in the input data to the operation verification target circuit 20 input from the addition unit 12 and the number of data included in the output data from the operation verification target circuit 20 during a predetermined period, for example, and outputs the measurement result to the output unit 14. The measurement unit 15 may measure the number of data for each of the data output from the selection circuit 24, the data output from the selection circuit 25, the data output from the first output of the function C23, the data input to the second input of the function C23, and the data output from the second output of the function A21. For example, if a certain data is lost due to the presence of a defective part in the operation verification target circuit 20, the relationship between the number of data included in the measured input data to the operation verification target circuit 20 and the number of data included in the output data from the operation verification target circuit 20 becomes invalid, so that the first analysis unit 101 detects the presence of a defective part in the operation verification target circuit 20. The measurement unit 15 also measures the above-mentioned number of data for multiple settings related to the selection circuits 24 and 25. As a result, the presence of a defect related to data loss is detected for a plurality of paths related to data processing in the circuit 20 under operation verification.

[0047] The output unit 14 outputs the data included in the input data to the selected circuit 20 for operation verification input from the selection unit 13 and the data included in the output data from the circuit 20 for operation verification to the first analysis unit 101. The output unit 14 also outputs the measurement results, input from the measurement unit 15, relating to the number of data items included in the input data to the circuit 20 for operation verification and the number of data items included in the output data from the circuit 20 for operation verification to the first analysis unit 101.

[0048] The first analysis unit 101 performs an analysis of defective points in the circuit 20 based on the information input from the output unit 14 as described above. The first analysis unit 101 detects the presence of a defective point in the circuit 20 when, for example, data that is expected to be equal and is included in the input data to the circuit 20 and the output data from the circuit 20 do not match in value. The first analysis unit 101 also detects the presence of a defective point in the circuit 20 when the relationship between the number of data items included in the input data to the circuit 20 and the number of data items included in the output data from the circuit 20 is incorrect.

[0049] The first analysis unit 101 outputs the results of the analysis of the defective portion in the operation verification target circuit 20 as described above to the reset control unit 16 and the management terminal 30.

[0050] The second analysis unit 102 detects the presence of a fault in the circuit 20 for operation verification with respect to the input data for the circuit 20 output from the function a171 in the input unit 17 and the output data output from the first output of the function C in the circuit 20 for operation verification. The second analysis unit 102 outputs the result of the analysis of the fault in the circuit 20 for operation verification as described above to the management terminal 30.

[0051] When the analysis result of the operation of the operation verification target circuit 20 by the first analysis unit 101 satisfies the restart condition included in the operation verification condition 190, the restart control unit 16 stops the operation verification data generation operation by the operation verification data generation unit 100. Then, the restart control unit 16 stops the operation of the input unit 17 and the operation verification target circuit 20. After that, in accordance with the operation verification condition 190, the restart control unit 16 changes parameters related to the generation condition of the operation verification data by the operation verification data generation unit 100, the verification path of the operation verification target circuit 20 changed by the settings of the selection circuits 24 and 25, the selection condition in the selection unit 13, and the restart condition in the restart control unit 16. Then, the restart control unit 16 restarts (resets) the operation verification data generation unit 100, the input unit 17, and the operation verification target circuit 20, which are in a paused state.

[0052] The restart condition included in the operation verification condition 190 indicates, for example, that the analysis result by the first analysis unit 101 indicates that the operation verification target circuit 20 has continued to operate normally for a predetermined period or a predetermined number of times. When the operation verification target circuit 20 has continued to operate normally for a predetermined period in a certain operation environment indicated by the operation verification condition 190, it is estimated that there is no defective part in that operation environment. Therefore, in this case, in order to perform the operation verification of the operation verification target circuit 20 more comprehensively, it is desirable to change the operation environment to another operation environment indicated by the operation verification condition 190 and perform the operation verification of the operation verification target circuit 20.

[0053] The restart condition included in the operation verification condition 190 indicates, for example, that the analysis result by the first analysis unit 101 indicates that an abnormal operation has occurred in the operation verification target circuit 20. For example, if the occurrence of the abnormal operation causes the operation verification target circuit 20 to enter a deadlock state, it becomes difficult to continue the operation verification of the operation verification target circuit 20. Therefore, in this case, in order to continue the operation verification of the operation verification target circuit 20, it is desirable to restart the operation verification target circuit 20 and resume the operation verification.

[0054] Furthermore, when the analysis result by the first analysis unit 101 satisfies a verification operation end condition included in the operation verification conditions 190, the restart control unit 16 stops the operations of the operation verification data generation unit 100, the input unit 17, and the operation verification target circuit 20, and ends the verification operation by the operation verification control device 10. The verification operation end condition indicates, for example, that the operation verification of the operation verification target circuit 20 has been completed for all operating environments included in the operation verification conditions 190.

[0055] The restart control unit 16 also completes the verification operation by the operation verification control device 10 when the reception unit 18 receives information input by a user through an input operation on the management terminal 30, instructing the operation verification control device 10 to complete the verification operation.

[0056] Furthermore, when the restart control unit 16 restarts the operation verification data generating unit 100, the input unit 17, and the operation verification target circuit 20, a predetermined period may be required until the operation of each of these components becomes stable. Therefore, during the predetermined period after the restart, there is a possibility that a pseudo faulty portion may be detected. Therefore, in order to prevent such a pseudo faulty portion from being detected, for example, the selection condition included in the operation verification condition 190 may indicate that the selection unit 13 starts selecting input data to the operation verification target circuit 20 and output data from the operation verification target circuit 20 after a predetermined period after the operation verification target circuit 20 is restarted.

[0057] Next, the operation (processing) of the operation verification system 1 according to the present disclosure will be described in detail with reference to the flowcharts of FIGS. 4A and 4B.

[0058] The operation verification control device 10 and the operation verification target circuit 20 are started (step S101). The timer 11 starts counting (step S102). The reception unit 18 receives the operation verification conditions 190 from the management terminal 30, and stores the received operation verification conditions 190 in the storage unit 19 (step S103).

[0059] The restart control unit 16 initializes or changes the conditions for generating operation verification data by the operation verification data generation unit 100, the verification path of the operation verification target circuit 20 (selection setting of the selected circuits 24 and 25), the selection conditions in the selection unit 13, and the restart conditions in the restart control unit 16 in accordance with the operation verification conditions 190 (step S104). The operation verification data generation unit 100 generates operation verification data in accordance with the generation conditions for operation verification data indicated by the operation verification conditions 190, and inputs the generated operation verification data to the input unit 17 (step S105). The input unit 17 inputs the operation verification data input from the operation verification data generation unit 100 to the operation verification target circuit 20 (step S106).

[0060] The adding unit 12 adds the count value of the timer 11 to input data to the operation verification target circuit 20, including the input to function c 173, the output from function c 173, the output from function b 172, and the output from function a 171, in the input unit 17, and inputs the input data to the selecting unit 13 and the measuring unit 15 (step S107). The adding unit 12 adds the count value of the timer 11 to output data from the operation verification target circuit 20, including the second output from function A 21, the output from the selecting circuit 24, the output from the selecting circuit 25, the first output from function C 23, and the second input to function C 23, in the operation verification target circuit 20, and inputs the output data to the selecting unit 13 and the measuring unit 15 (step S108).

[0061] The selection unit 13 selects input data to the operation verification target circuit 20 and output data from the operation verification target circuit 20, whose added count value satisfies the selection condition included in the set operation verification condition 190, and inputs the selected input data and output data to the first analysis unit 101 via the output unit 14 (step S109). The measurement unit 15 measures the number of pieces of input data to the operation verification target circuit 20 and output data from the operation verification target circuit 20, to which the count value has been added, and inputs the measurement result to the first analysis unit 101 via the output unit 14 (step S110).

[0062] The first analysis unit 101 analyzes the input data and output data selected by the selection unit 13 and input from the output unit 14, and the number of pieces of input data and output data measured by the measurement unit 15, and notifies the restart control unit 16 of the analysis result (step S111).

[0063] If the analysis result by the first analysis unit 101 satisfies the verification operation end condition included in the operation verification conditions 190 (Yes in step S113), the entire process ends. If the analysis result by the first analysis unit 101 does not satisfy the verification operation end condition included in the operation verification conditions 190 (No in step S113), the restart control unit 16 determines whether the analysis result notified from the first analysis unit 101 satisfies the restart condition included in the operation verification conditions 190 (step S114).

[0064] If the analysis result notified by the first analysis unit 101 does not satisfy the restart condition (No in step S115), the process returns to step S105. If the analysis result notified by the first analysis unit 101 satisfies the restart condition (Yes in step S115), the restart control unit 16 stops the generation of operation verification data by the operation verification data generation unit 100, stops the operation of the input unit 17 and the operation verification target circuit 20 (step S116), and the process returns to step S104.

[0065] The operation verification control device 10 according to the present disclosure can detect the presence of defective parts more efficiently and with high accuracy in the operation verification of a logic circuit. This is because the operation verification control device 10 adds a count value by a timer 11 to input data for an operation verification target circuit 20 and output data from the operation verification target circuit 20, selects a combination of input data and output data for which the count value satisfies a predetermined selection condition, and outputs the combination to a first analysis unit 101.

[0066] The effects achieved by the operation verification control device 10 according to the present disclosure will be described in detail below.

[0067] In devices having logic circuits, aging tests and the like are usually performed to check for operational defects by operating the device for a long period of time. In such aging tests and the like, it is required to efficiently and accurately detect the presence of defects that become apparent when the operation verification test is performed for a long period of time. In other words, the challenge is to detect the presence of defects more efficiently and accurately in the operation verification of logic circuits.

[0068] In response to such a problem, the operation verification control device 10 according to the present disclosure counts the number according to the passage of time. When input data is input to the operation verification target circuit 20, the operation verification control device 10 adds the count value by the timer 11 to the input data. When output data is output from the operation verification target circuit 20, the operation verification control device 10 adds the count value by the timer 11 to the output data. The operation verification control device 10 selects a combination of input data and output data for which the added count value satisfies a selection condition included in a predetermined operation verification condition 190. Then, the operation verification control device 10 outputs the selected input data and output data to a first analysis unit 101 that analyzes the operation of the operation verification target circuit 20. In general, in a logic circuit to be the target of operation verification, the input data and output data are often associated with each other, for example, by making the values ​​equal, using the timing at which each input data and output data was generated (the count value by the timer 11) as a key, as illustrated in FIG. 3. The operation verification control device 10 detects the presence of a defect in the operation verification target circuit 20 using the above-mentioned correspondence by adding a count value by the timer 11 to each piece of input data and output data. This allows the operation verification control device 10 to detect the presence of a defect more efficiently and accurately in the operation verification of a logic circuit.

[0069] Furthermore, the operation verification control device 10 according to the present disclosure measures the number of pieces of input data to the operation verification target circuit 20 and the number of pieces of output data from the operation verification target circuit 20, and outputs the measurement results to the first analysis unit 101. This allows the operation verification control device 10 to reliably detect defects such as data loss in the operation verification target circuit 20, and therefore allows the existence of defective parts to be detected more efficiently and accurately.

[0070] Furthermore, in the operation verification control device 10 according to the present disclosure, the selection condition used by the selector 13 selects a combination of input data and output data according to a selection condition corresponding to each of a plurality of signal paths in the operation verification target circuit 20 that has a function for selecting one of a plurality of signal paths for data. This enables the operation verification control device 10 to more efficiently and accurately detect the presence of defective points in the plurality of signal paths for data processing in the operation verification target circuit 20.

[0071] Furthermore, when the analysis result of the operation of the operation verification target circuit 20 by the first analysis unit 101 satisfies a restart condition included in the operation verification condition 190, the operation verification control device 10 according to the present disclosure stops the operation of the operation verification target circuit 20, changes the operation verification condition 190, and restarts the operation verification target circuit 20. The restart condition includes at least one of the analysis result by the first analysis unit 101 indicating that normal operation has continued for a predetermined period and the analysis result indicating the occurrence of abnormal operation of the operation verification target circuit 20. That is, the operation verification control device 10 automatically performs the operation verification of the operation verification target circuit 20 while changing the execution environment of the operation verification, and automatically restarts the operation verification target circuit 20 to continue the operation verification when abnormal operation occurs. In this way, the operation verification control device 10 can reduce the burden on the user in the operation verification work of the operation verification target circuit 20.

[0072] Furthermore, in the operation verification control device 10 according to the present disclosure, the selection condition used by the selector 13 indicates that selection of input data for the operation verification target circuit 20 and output data from the operation verification target circuit 20 is started a predetermined period of time after the operation verification target circuit 20 is restarted. This allows the operation verification control device 10 to avoid detecting a pseudo fault point during the predetermined period of time after the operation verification target circuit 20 is restarted, when it is assumed that a pseudo fault point is highly likely to be detected.

[0073] In addition, the operation verification control device 10 according to the present disclosure described above includes an input unit 17 having a function corresponding to the circuit 20 to be verified for operation, but the input unit 17 is not limited to having a function corresponding to the circuit 20 to be verified for operation.

[0074] <Second embodiment> FIG. 5 is a block diagram showing a configuration of an operation verification control device 40 according to the present disclosure.

[0075] The operation verification control device 40 according to the present disclosure includes a counting unit 41, an adding unit 42, a selecting unit 43, and an output unit 44. The counting unit 41, the adding unit 42, the selecting unit 43, and the output unit 44 are examples of a counting means, an adding means, a selecting means, and an output means, respectively.

[0076] The counter 41 counts the number according to the passage of time. The counter 41 operates in the same manner as the timer 11 of the operation verification control device 10, for example.

[0077] The adding unit 42 adds number data 420 indicating the number counted by the counting unit 41 at the timing when the input data 401 is input to the target part 50 for operation verification to the input data 401. The adding unit 42 adds number data 420 indicating the number counted by the counting unit 41 at the timing when the output data 402 is output from the target part 50 for operation verification to the output data 402. The target part 50 for operation verification is, for example, a circuit similar to the operation verification target circuit 20 in the operation verification system 1. The input data 401 and the output data 402 are, for example, data similar to the input data to the operation verification target circuit 20 in the operation verification system 1 and the output data from the operation verification target circuit 20. The adding unit 42 operates in the same manner as the adding unit 12 in the operation verification control device 10.

[0078] The selection unit 43 selects a combination of the input data 401 and the output data 402 in which the number indicated by the added number data 420 satisfies a predetermined selection condition 430. The selection condition 430 is, for example, the same as the selection condition included in the operation verification condition 190 of the operation verification control device 10. The selection unit 43 operates in the same manner as the selection unit 13 of the operation verification control device 10, for example.

[0079] The output unit 44 outputs the selected input data 401 and output data 402 to an analysis unit 60 that analyzes the operation of the target part 50 for operation verification. The analysis unit 60 is a component similar to, for example, the first analysis unit 101 in the operation verification control device 10. The output unit 44 operates in the same manner as, for example, the output unit 14 in the operation verification control device 10.

[0080] Next, the operation (processing) of the operation verification control device 40 according to the present disclosure will be described in detail with reference to the flowchart of FIG.

[0081] The counting unit 41 counts the number according to the passage of time (step S201). The adding unit 42 adds the number data 420 representing the number counted by the counting unit 41 to the input data 401 for the target part 50 of the operation verification and the output data 402 from the target part 50 of the operation verification (step S202). The selecting unit 43 selects a combination of the input data 401 and the output data 402 in which the number indicated by the added number data 420 satisfies the selection condition 430 (step S203). The output unit 44 outputs the selected input data 401 and output data 402 to the analyzing unit 60 (step S204), and the entire process ends.

[0082] The operation verification control device 40 according to the present disclosure can detect the presence of defective parts more efficiently and with high accuracy in the operation verification of a logic circuit because the operation verification control device 40 adds number data 420 counted by the counting unit 41 to input data 401 for a target part 50 for operation verification and output data 402 from the target part 50 for operation verification, selects a combination of the input data 401 and the output data 402 whose number indicated by the number data 420 satisfies a predetermined selection condition 430, and outputs the combination to the analysis unit 60.

[0083] <Hardware configuration example> In each of the above-mentioned embodiments, each unit in the operation verification control device shown in Fig. 1 and Fig. 5 can be realized by a dedicated HW (Hardware) (electronic circuit). In Fig. 1 and Fig. 5, at least the following components can be considered as functional (processing) units (software modules) of a software program including instructions executed by a processor. Timer 11 and counting unit 41, Addition parts 12 and 42, Selection units 13 and 43, Output units 14 and 44, Measuring unit 15, Restart control unit 16, Input section 17, Reception desk 18, A memory control function in the memory unit 19; ·First analysis section 101, ·Second analysis section 102.

[0084] However, the division of the various parts shown in these drawings is for the convenience of explanation, and various configurations may be assumed for implementation. An example of the hardware environment in this case will be described with reference to FIG.

[0085] Fig. 7 is a diagram for explaining an example of the configuration of an information processing device 900 (computer) capable of realizing the operation verification control device according to the present disclosure. That is, Fig. 7 shows the configuration of a computer (information processing device) capable of realizing the operation verification control device shown in Figs. 1 and 5, and shows a hardware environment capable of realizing each function in the above-mentioned embodiment. However, each unit in the above-mentioned operation verification control device may be provided in a distributed manner in multiple information processing devices 900, or at least some of the functions may be provided in a server or the like constituting a cloud computing environment.

[0086] The information processing device 900 shown in FIG. ·CPU(Central_Processing_Unit)901, ROM (Read_Only_Memory) 902, ·RAM(Random_Access_Memory)903, Hard disk (storage device) 904, A communication interface 905; Bus 906 (communication line), A reader / writer 908 capable of reading and writing data stored in a recording medium 907 such as a CD-ROM (Compact Disc Read Only Memory), · Input / output interfaces 909 such as monitors, speakers, keyboards, etc.

[0087] That is, the information processing device 900 having the above components is a general computer in which these components are connected via a bus 906. The information processing device 900 may have a plurality of CPUs 901, or may have a CPU 901 configured with a multi-core. The information processing device 900 may not have some of the above components.

[0088] The present invention, explained using the above-mentioned embodiment as an example, supplies a computer program capable of realizing the following functions to the information processing device 900 shown in Fig. 7. The functions are the above-mentioned configurations in the block configuration diagrams (Figs. 1 and 5) referred to in the explanation of the embodiment, or the functions of the flowcharts (Figs. 4A, 4B, and 6). The present invention is then achieved by reading the computer program into the CPU 901 of the hardware, interpreting it, and executing it. The computer program supplied to the device may be stored in a readable and writable volatile memory (RAM 903), or a non-volatile storage device such as a ROM 902 or a hard disk 904.

[0089] In the above case, the method of supplying the computer program to the hardware can be a currently common procedure, such as installing the program in the device via a recording medium 907 such as a CD-ROM, or downloading the program from an external source via a communication line such as the Internet. In such a case, the present invention can be considered to be configured by the code constituting the computer program, or the recording medium 907 on which the code is stored.

[0090] The present invention has been described above by taking the above-mentioned embodiment as an exemplary example. However, the present invention is not limited to the above-mentioned embodiment. That is, the present invention can be applied in various aspects that can be understood by a person skilled in the art within the scope of the present invention.

[0091] Note that some or all of the above-described embodiments can be described as follows: However, the present invention described by way of example in the above-described embodiments is not limited to the following.

[0092] (Appendix 1) A counting means for counting the number according to the passage of time; an adding means for adding, to the input data, numerical data indicating a number counted by the counting means at a timing when the input data is input to the part that is the subject of the operation verification, and adding, to the output data, numerical data indicating a number counted by the counting means at a timing when the output data is output from the part that is the subject of the operation verification; a selection means for selecting a combination of the input data and the output data in which a number indicated by added numeric data satisfies a predetermined selection condition; an output means for outputting the selected input data and the selected output data to an analysis means for analyzing the operation of the target portion of the operation verification; An operation verification control device comprising:

[0093] (Appendix 2) The apparatus further includes a receiving unit for receiving the selection conditions input from an external source. 2. An operational verification control device as described in appendix 1.

[0094] (Appendix 3) a measuring unit for measuring the number of pieces of the input data and the output data, The output means outputs the measurement result of the number of pieces of data to the analysis means. 3. The operation verification control device according to claim 1 or 2.

[0095] (Appendix 4) A plurality of signal paths for data in the target portion of the operation verification are prepared; the selection means selects a combination of the input data and the output data in accordance with the selection conditions corresponding to each of the plurality of prepared signal paths. 3. The operation verification control device according to claim 1 or 2.

[0096] (Appendix 5) and a restart control means for stopping the operation of the target part of the operational verification when the analysis result of the analysis means of the operation of the target part of the operational verification satisfies a restart condition, changing the operational verification conditions including the restart condition and the selection condition, and then restarting the target part of the operational verification. 3. The operation verification control device according to claim 1 or 2.

[0097] (Appendix 6) The restart condition includes at least one of the analysis result indicating that normal operation has continued for a predetermined period of time and the analysis result indicating that abnormal operation has occurred. 6. The operation verification control device according to claim 5.

[0098] (Appendix 7) the selection means starts selecting the input data and the output data after a predetermined period of time has elapsed since the part to be subjected to the operation verification is restarted. 6. The operation verification control device according to claim 5.

[0099] (Appendix 8) further comprising an input unit for inputting the input data to the part to be verified in which a plurality of logic functions are connected in series; the input means includes a plurality of opposing logic functions each of which functions in opposition to the plurality of logic functions and which are connected in series in a reverse order to the target part of the operation verification; the adding means adds the numerical data to the input data which is an output of each of the corresponding logic functions and to the output data which is an output of each of the corresponding logic functions; 3. The operation verification control device according to claim 1 or 2.

[0100] (Appendix 9) By the information processing device, Count the number over time, adding numerical data indicating a number counted at a timing when input data is input to a target portion for operation verification to the input data, and adding numerical data indicating a number counted at a timing when output data is output from the target portion for operation verification to the output data; selecting a combination of the input data and the output data in which a number indicated by added numeric data satisfies a predetermined selection condition; outputting the selected input data and output data to an analysis means for analyzing the operation of the target portion of the operation verification; Operation verification control method.

[0101] (Appendix 10) Accepting the selection conditions input from an external source; 10. The operation verification control method according to claim 9.

[0102] (Appendix 11) Counting the number of pieces of input data and the number of pieces of output data; outputting the measurement result of the number of pieces of data to the analysis means; 11. The operation verification control method according to claim 9 or 10.

[0103] (Appendix 12) A plurality of signal paths for data in the target portion of the operation verification are prepared; represents selecting a combination of the input data and the output data in accordance with the selection condition corresponding to each of the plurality of prepared signal paths, 11. The operation verification control method according to claim 9 or 10.

[0104] (Appendix 13) when the analysis result of the operation of the target part of the operation verification by the analysis means satisfies a restart condition, the operation of the target part of the operation verification is stopped, and the operation verification conditions including the restart condition and the selection condition are changed, and then the target part of the operation verification is restarted. 11. The operation verification control method according to claim 9 or 10.

[0105] (Appendix 14) The restart condition includes at least one of the analysis result indicating that normal operation has continued for a predetermined period of time and the analysis result indicating that abnormal operation has occurred. 14. The operation verification control method according to claim 13.

[0106] (Appendix 15) and starting the selection of the input data and the output data after a predetermined period of time has elapsed since the part to be subjected to the operation verification was restarted. 14. The operation verification control method according to claim 13.

[0107] (Appendix 16) inputting the input data into the part to be verified for operation, in which a plurality of logic functions are connected in series; a plurality of opposing logic functions connected in series in a reverse order to the target part of the operation verification, the opposing logic functions being in opposition to each other in the input of the input data; adding the numerical data to the input data, which is an output of each of the corresponding logic functions, and to the output data, which is an output of each of the corresponding logic functions; 11. The operation verification control method according to claim 9 or 10.

[0108] (Appendix 17) A counting process for counting the number of pieces over time; an addition process of adding, to the input data, numerical data indicating a number counted by the counting process at a timing when the input data is input to the part that is the target of the operation verification, and adding, to the output data, numerical data indicating a number counted by the counting process at a timing when the output data is output from the part that is the target of the operation verification; a selection process for selecting a combination of the input data and the output data in which a number indicated by added numeric data satisfies a predetermined selection condition; an output process of outputting the selected input data and the selected output data to an analysis means that analyzes the operation of the target part of the operation verification; An operation verification control program for causing a computer to execute the above.

[0109] (Appendix 18) causing the computer to further execute a reception process for receiving the selection conditions input from an external source; 18. The operation verification control program according to claim 17.

[0110] (Appendix 19) further causing the computer to execute a measurement process of measuring the number of pieces of the input data and the output data; The output process outputs the measurement result of the number of pieces of data to the analysis means. 19. An operation verification control program according to claim 17 or 18.

[0111] (Appendix 20) A plurality of signal paths for data in the target portion of the operation verification are prepared; the selection process selects a combination of the input data and the output data in accordance with the selection condition corresponding to each of the plurality of prepared signal paths. 19. An operation verification control program according to claim 17 or 18.

[0112] (Appendix 21) and causing the computer to execute a restart control process, in which, when an analysis result of the operation of the target part of the operation verification by the analysis means satisfies a restart condition, the operation of the target part of the operation verification is stopped, and the operation verification conditions including the restart condition and the selection condition are changed, and then the target part of the operation verification is restarted. 19. An operation verification control program according to claim 17 or 18.

[0113] (Appendix 22) The restart condition includes at least one of the analysis result indicating that normal operation has continued for a predetermined period of time and the analysis result indicating that abnormal operation has occurred. 22. The operation verification control program according to claim 21.

[0114] (Appendix 23) the selection process starts selection of the input data and the output data after a predetermined period of time has elapsed since the part to be subjected to the operation verification is restarted. 22. The operation verification control program according to claim 21.

[0115] (Appendix 24) further causing the computer to execute an input process for inputting the input data to the part to be verified in which a plurality of logic functions are connected in series; the input processing includes a plurality of opposing logic functions that are functionally opposing each of the plurality of logic functions and are connected in series in a reverse order to the target portion of the operation verification, The adding process adds the numerical data to the input data which is an output of each of the corresponding logic functions and the output data which is an output of each of the corresponding logic functions. 19. An operation verification control program according to claim 17 or 18. [Explanation of symbols]

[0116] 1 Operation verification system 10 Operation verification control device 11 Timer 12 Addition 13 Selection section 14 Output section 15 Measurement section 16 Restart control section 17 Input section 171 Function A 172 Function B 173 Function C 18 Reception Department 19 Memory section 190 Operation Verification Conditions 101 1st Analysis Department 102 2nd Analysis Department 20 Circuit to be verified 21 Function A 22 Function B 23 Function C 24 Selection circuit 25 Selection circuit 30 Management terminal 40 Operation verification control device 401 Input Data 402 Output Data 41 Counting Department 42 Addition 420 Number Data 43 Selection section 430 Selection Criteria 44 Output section 50 Parts subject to operational verification 60 Analysis Department 900 Information processing device 901 CPU 902 ROM 903 RAM 904 Hard disk (storage device) 905 Communication Interface 906 Bus 907 Recording media 908 Reader / Writer 909 Input / Output Interface

Claims

1. A counting means for counting the number according to the passage of time; an adding means for adding, to the input data, numerical data indicating a number counted by the counting means at a timing when the input data is input to the part that is the subject of the operation verification, and adding, to the output data, numerical data indicating a number counted by the counting means at a timing when the output data is output from the part that is the subject of the operation verification; a selection means for selecting a combination of the input data and the output data in which a number indicated by added numeric data satisfies a predetermined selection condition; an output means for outputting the selected input data and the selected output data to an analysis means for analyzing the operation of the target portion of the operation verification; An operation verification control device comprising:

2. The apparatus further includes a receiving unit for receiving the selection conditions input from an external source. The operation verification control device according to claim 1 .

3. a measuring unit for measuring the number of pieces of the input data and the output data, The output means outputs the measurement result of the number of pieces of data to the analysis means.

3. The operation verification control device according to claim 1 or 2.

4. A plurality of signal paths for data in the target portion of the operation verification are prepared; the selection means selects a combination of the input data and the output data in accordance with the selection conditions corresponding to each of the plurality of prepared signal paths.

3. The operation verification control device according to claim 1 or 2.

5. and a restart control means for stopping the operation of the target part of the operational verification when the analysis result of the analysis means of the operation of the target part of the operational verification satisfies a restart condition, changing the operational verification conditions including the restart condition and the selection condition, and then restarting the target part of the operational verification.

3. The operation verification control device according to claim 1 or 2.

6. The restart condition includes at least one of the analysis result indicating that normal operation has continued for a predetermined period of time and the analysis result indicating that abnormal operation has occurred. The operation verification control device according to claim 5 .

7. the selection means starts selecting the input data and the output data after a predetermined period of time has elapsed since the part to be subjected to the operation verification is restarted. The operation verification control device according to claim 5 .

8. further comprising an input unit for inputting the input data to the part to be verified in which a plurality of logic functions are connected in series; the input means includes a plurality of opposing logic functions each of which functions in opposition to the plurality of logic functions and which are connected in series in a reverse order to the target part of the operation verification; the adding means adds the numerical data to the input data which is an output of each of the corresponding logic functions and to the output data which is an output of each of the corresponding logic functions; 3. The operation verification control device according to claim 1 or 2.

9. By the information processing device, Count the number over time, adding numerical data indicating a number counted at a timing when input data is input to a target portion for operation verification to the input data, and adding numerical data indicating a number counted at a timing when output data is output from the target portion for operation verification to the output data; selecting a combination of the input data and the output data in which a number indicated by added numeric data satisfies a predetermined selection condition; outputting the selected input data and output data to an analysis means for analyzing the operation of the target portion of the operation verification; Operation verification control method.

10. A counting process for counting the number of pieces over time; an addition process of adding, to the input data, numerical data indicating a number counted by the counting process at a timing when the input data is input to the part that is the target of the operation verification, and adding, to the output data, numerical data indicating a number counted by the counting process at a timing when the output data is output from the part that is the target of the operation verification; a selection process for selecting a combination of the input data and the output data in which a number indicated by added numeric data satisfies a predetermined selection condition; an output process of outputting the selected input data and the selected output data to an analysis means that analyzes the operation of the target part of the operation verification; An operation verification control program for causing a computer to execute the above.

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