Substrate

Abstract

To provide a method for manufacturing a substrate which can suppress insulation breakdown of an insulating layer.SOLUTION: A substrate includes: a base plate 10; an insulating layer 20 arranged on one surface of the base plate 10; a metal layer 30 arranged on a surface opposite to the base plate 10 of the insulating layer 20; and a sealing resin layer 40 sealing the metal layer 30, wherein in a portion formed of the metal layer 30 coming in contact with the insulating layer 20 and the sealing resin layer 40, a height of a step between the metal layer 30 and the sealing resin layer 40 is 20% or less of a thickness of the insulating layer 20.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a substrate.

[0002] In the field of power modules and the like, there is a demand for substrates that efficiently dissipate heat generated by semiconductor elements. Substrates that mount semiconductor elements and have metal layers that contribute to dissipating heat from the mounted semiconductor elements, and insulating layers that hold the metal layers and prevent the metal layers from shorting out with each other, are used as such substrates.

[0003] Patent Document 1 describes a substrate having a structure in which a circuit pattern portion formed by processing a metal plate to provide a cutout portion is bonded to a base plate via a heat dissipation layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2022-123984 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above-mentioned substrate, the insulating properties of the insulating layer may deteriorate.

[0006] An example of an object of the present invention is to provide a substrate having an insulating layer with excellent insulating properties.

[0007] According to the present invention, there is provided a substrate as follows:

[0008] [1] A substrate including a base plate, an insulating layer disposed on one surface of the base plate, a metal layer disposed on a surface of the insulating layer opposite to the base plate, and a sealing resin layer sealing the metal layer, A substrate, wherein in a portion formed of the metal layer and the sealing resin layer in contact with the insulating layer, the height of a step between the metal layer and the sealing resin layer is 20% or less of the thickness of the insulating layer. [2] The base plate has a heat dissipation protrusion on a surface opposite to the one surface. The substrate according to [1]. [3] The metal layer is The surface is plated, The region facing the insulating layer does not have the plating. The substrate according to [1] or [2]. [4] The sealing resin layer contains an epoxy resin. A substrate according to any one of [1] to [3]. [5] When the thickness of the thickest portion of the insulating layer is T2(MAX) and the thickness of the thinnest portion of the insulating layer is T2(MIN), (T2(MAX)-T2(MIN)) / T2(MAX) is 0.2 or less. A substrate according to any one of [1] to [4]. [6] An area of ​​the side surface of the metal layer that is covered with the sealing resin layer is 98% or more of the entire side surface of the metal layer. A substrate according to any one of [1] to [5]. Effect of the Invention

[0009] According to the present invention, a substrate having an insulating layer with excellent insulating properties can be provided. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an overview of a substrate according to an embodiment of the present invention. [Diagram 2] 13A and 13B are diagrams showing modified examples of the substrate according to the embodiment. [Diagram 3] 1A to 1C are diagrams illustrating an outline of a method for manufacturing a substrate according to an embodiment of the present invention. [Figure 4] FIG. 1 is a diagram showing a first example of a circuit sealing step. [Diagram 5] FIG. 13 is a diagram showing a second example (side gate method) of a circuit sealing process. [Figure 6] FIG. 13 is a diagram showing a second example (pin gate method) of a circuit sealing process. [Figure 7] FIG. 1 is a diagram showing an outline of a grinding process. [Figure 8] 1A-1C show a method of preparing a metal layer secured to an adhesive tape. [Figure 9] FIG. 2 is a plan view of a grooved metal plate having grooves of a desired pattern and a predetermined depth. [Figure 10] 11 is a diagram showing the height T of a step between a metal layer and a sealing resin layer. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In all drawings, the same components are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. Note that the drawings are for explanatory purposes only. The shapes and dimensional ratios of the components in the drawings do not necessarily correspond to the actual products.

[0012] In this specification, the expression "a to b" in the explanation of a numerical range means from a to b, unless otherwise specified. For example, "1% by mass to 5% by mass" means "1% by mass to 5% by mass."

[0013] [Outline of the substrate 100] FIG. 1 is a diagram showing an example of a cross section of a substrate 100 according to the present embodiment. The substrate 100 includes a base substrate 10, an insulating layer 20, a metal layer 30, and a sealing resin layer 40. The insulating layer 20 is disposed on one surface of the base substrate 10. A metal layer 30 for mounting a semiconductor element is disposed on one surface of the insulating layer 20 opposite to the base substrate 10. The metal layer 30 is sealed by the sealing resin layer 40. The total thickness T0 of the substrate 100 is not particularly limited, but is preferably 0.7 mm or more and 7 mm or less, and more preferably 0.9 mm or more and 6 mm or less. Each component will be described in detail below.

[0014] <Base substrate 10> The base substrate 10 holds an insulating layer 20. In addition, as shown in FIG. 2, a heat dissipation member 11 such as a heat dissipation fin or a radiator may be attached to the surface of the base substrate 10 opposite to the insulating layer 20. The heat dissipation member 11 has, for example, a shape having a heat dissipation protrusion. In this case, the heat dissipation property of the substrate 100 is improved. The heat dissipation member 11 may be integrated with the base substrate 10.

[0015] The material constituting the base substrate 10 may be, for example, one or a combination of two or more selected from copper, a copper alloy, aluminum, and an aluminum alloy. Among these, it is preferable to include at least one of copper and aluminum from the viewpoint of strength.

[0016] The thickness T1 of the base substrate 10 is not particularly limited, but is preferably 30% or more and 70% or less of the total thickness T0.

[0017] The upper limit of the thickness T1 of the base substrate 10 is, for example, 5 mm or less, preferably 4 mm or less, and more preferably 3 mm or less. When the thickness T1 of the base substrate 10 is set to this value or less, the substrate 100 becomes thinner and the processability of the substrate 100 in the contour processing, cutting processing, and the like is improved.

[0018] The lower limit of the thickness T1 of the base substrate 10 is, for example, 0.3 mm or more, preferably 0.5 mm or more, and more preferably 0.8 mm or more. When the thickness T1 of the base substrate 10 is set to this value or more, the heat dissipation properties of the substrate 100 can be improved.

[0019] <Insulating layer 20> The material constituting the insulating layer 20 according to this embodiment is, for example, a thermosetting resin. The thermosetting resin may be one or a combination of two or more selected from the group consisting of epoxy resin, phenol resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, and polyurethane resin.

[0020] It is preferable to mix a filler containing particles having electrical insulation and high thermal conductivity into the insulating layer 20. As a constituent material of the particles of such a filler, for example, at least one of a metal oxide such as alumina and a nitride such as boron nitride can be used.

[0021] The thickness T2 of the insulating layer 20 is appropriately set depending on the purpose, but from the viewpoint of the strength of the substrate 100, the lower limit is preferably 30 μm or more, and more preferably 50 μm or more. Moreover, from the viewpoint of more effectively transferring heat from the semiconductor element to the base substrate 10, the upper limit is preferably 300 μm or less, and more preferably 200 μm or less.

[0022] Furthermore, it is preferable that the thickness T2 of the insulating layer 20 is uniform regardless of location. Specifically, when the thickness of the thickest portion of the insulating layer 20 is T2(MAX) and the thickness of the thinnest portion of the insulating layer 20 is T2(MIN), it is preferable that (T2(MAX)-T2(MIN)) / T2(MAX) is 0.2 or less.

[0023] Furthermore, the insulating layer 20 according to this embodiment preferably has a thermal conductivity of 3 W / (m·K) or more, more preferably 7 W / (m·K) or more, and even more preferably 12 W / (m·K) or more, thereby improving the heat dissipation properties of the substrate 100.

[0024] <Metal layer 30> For example, a semiconductor element is mounted on the metal layer 30. The metal layer 30 is made of a metal material having electrical conductivity. For example, one or a combination of two or more selected from copper, copper alloy, aluminum, and aluminum alloy can be used as the metal material constituting the metal layer 30. This makes the metal layer 30 have a relatively small resistance value. It is more preferable that the metal layer 30 is a copper-containing layer that contains copper. Note that the metal layer 30 may be at least partially covered with a coating layer. The coating layer is, for example, a protective layer that protects the metal layer 30, such as a plating layer, from the outside air, or an antiseptic. When the metal layer 30 is covered with a coating layer, deterioration such as oxidation of the metal layer 30 can be suppressed during the manufacturing process of the substrate 100 described later.

[0025] The lower limit of the thickness T3 of the metal layer 30 is, for example, 0.3 mm or more, preferably 0.5 mm or more, and more preferably 1.0 mm or more. The upper limit of the thickness T3 of the metal layer 30 is, for example, 3.0 mm or less, preferably 2.5 mm or less, and more preferably 2.0 mm or less. The method for manufacturing a substrate according to the present embodiment, which will be described later, can form a metal layer 30 having a thickness equal to or greater than the above lower limit. Furthermore, by making the thickness T3 of the metal layer 30 equal to or greater than the above lower limit, heat generation in the circuit pattern can be suppressed even in applications requiring high current. Furthermore, by making the thickness T3 of the metal layer 30 equal to or less than the above upper limit, the method for manufacturing a substrate according to the present embodiment can be easily applied.

[0026] In addition, in a portion formed of the metal layer 30 and the sealing resin layer 40 in contact with the insulating layer 20, the height T (see FIG. 10) of the step between the metal layer 30 and the sealing resin layer 40 is preferably 20% or less, more preferably 10% or less, and particularly preferably 5% or less of the thickness of the insulating layer 20. This makes the thickness of the insulating layer 20 uniform, and can suppress deterioration of the insulating properties of the insulating layer 20.

[0027] Moreover, the region of the side surface of the metal layer 30 that is covered by the sealing resin layer 40 is preferably 98% or more, more preferably 99% or more, and even more preferably 99.9% or more of the entire side surface of the metal layer 30. In other words, the height T3' of the region of the metal layer 30 that is covered by the sealing resin layer 40 is preferably 98% or more of the height T3 of the metal layer 30, more preferably 99% or more, and even more preferably 99.9% or more.

[0028] <Sealing resin layer 40> The sealing resin layer 40 seals the metal layer 30. In Fig. 1, the sealing resin layer 40 is formed so as not to cover the first surface 31 of the metal layer 30 opposite the insulating layer 20, but the sealing resin layer 40 may be formed so as to cover at least a part of the first surface 31.

[0029] The sealing resin layer 40 is formed, for example, from a cured body of a thermosetting resin. The thermosetting resin may be one or a combination of two or more selected from the group consisting of epoxy resin, phenol resin, polyimide resin, bismaleimide resin, urea resin, melamine resin, polyurethane resin, cyanate ester resin, silicone resin, oxetane resin (oxetane compound), (meth)acrylate resin, unsaturated polyester resin, diallyl phthalate resin, and benzoxazine resin.

[0030] More specific examples of the thermosetting resin include novolac-type phenolic resins such as phenol novolac resin, cresol novolac resin, bisphenol A-type novolac resin, and triazine skeleton-containing phenol novolac resin; phenolic resins such as unmodified resol phenolic resins, oil-modified resol phenolic resins modified with tung oil, linseed oil, walnut oil, etc., resol-type phenolic resins, aralkyl-type phenolic resins such as phenol aralkyl-type phenolic resins, and triphenylmethane-type phenolic resins; Bisphenol type epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, tetramethylbisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol E type epoxy resin, bisphenol M type epoxy resin, bisphenol P type epoxy resin, and bisphenol Z type epoxy resin; novolac type epoxy resins such as phenol novolac type epoxy resin and cresol novolac type epoxy resin; Epoxy resins such as biphenyl type epoxy resins, biphenyl aralkyl type epoxy resins, aryl alkylene type epoxy resins, naphthalene type epoxy resins, anthracene type epoxy resins, phenoxy type epoxy resins, dicyclopentadiene type epoxy resins, norbornene type epoxy resins, adamantane type epoxy resins, fluorene type epoxy resins, and trisphenylmethane type epoxy resins; One or a combination of two or more selected from the following can be used: resins having a triazine ring, such as urea resins and melamine resins; unsaturated polyester resins; maleimide resins, such as bismaleimide compounds; polyurethane resins; diallyl phthalate resins; silicone-based resins; benzoxazine resins; polyimide resins; polyamide-imide resins; and cyanate ester resins, such as benzocyclobutene resins, novolac-type cyanate resins, bisphenol A-type cyanate resins, bisphenol E-type cyanate resins, and tetramethylbisphenol F-type cyanate resins.

[0031] The sealing resin layer 40 may also contain a filler. Examples of materials constituting the filler include silica, alumina, kaolin, talc, clay, mica, rock wool, wollastonite, glass powder, glass flakes, glass beads, glass fiber, silicon carbide, silicon nitride, aluminum nitride, carbon black, graphite, titanium dioxide, calcium carbonate, calcium sulfate, barium carbonate, magnesium carbonate, magnesium sulfate, barium sulfate, cellulose, aramid, wood, and the like. One or a combination of two or more of these materials can be used.

[0032] Further, the lower limit value of the linear expansion coefficient of the encapsulation resin layer 40 is preferably 10 ppm / K or more, more preferably 11 ppm / K or more. Also, the upper limit value of the linear expansion coefficient of the encapsulation resin layer 40 is preferably 20 ppm / K or less, more preferably 19 ppm / K or less.

[0033] [Method for manufacturing substrate 100] Referring to FIG. 3, a method for manufacturing the substrate 100 according to the present embodiment will be described. FIG. 3 is a process cross-sectional view showing the manufacturing process of the substrate 100.

[0034] <S10: Circuit encapsulation step> As shown in FIG. 3, in the circuit encapsulation step S10, the encapsulation circuit layer 50 is formed by encapsulating the metal layer 30 with the encapsulation resin layer 40. As a method for forming the encapsulation circuit layer 50, a compression molding method, a transfer molding method, or an injection molding method can be used. Details of the method for molding the encapsulation circuit layer 50 will be described later.

[0035] <S20: Insulating layer formation step> In the insulating layer forming step S20, the sealing circuit layer 50 is pressed against the insulating material arranged on the base substrate 10 and the insulating material is heated, so that the insulating material is cured to form the insulating layer 20, and the sealing circuit layer 50 is fixed to the insulating layer 20. The insulating layer forming step S20 is performed, for example, by arranging the insulating material on the base substrate 10, and then heating the sealing circuit layer 50 under predetermined heating conditions while pressing the sealing circuit layer 50 against the insulating material (insulating layer 20) with a predetermined pressure. The lower limit of the predetermined pressure is preferably 8 MPa or more, and more preferably 10 MPa or more. The upper limit of the predetermined pressure is preferably 15 MPa or less, and more preferably 12 MPa or less. The lower limit of the predetermined heating temperature is preferably 160° C. or more, and more preferably 180° C. or more. The upper limit of the predetermined heating temperature is preferably 210° C. or less, and more preferably 190° C. or less. The lower limit of the predetermined heating time is preferably 100 seconds or more, and more preferably 120 seconds or more. The upper limit of the above-mentioned predetermined heating time is preferably 150 seconds or less, and more preferably 140 seconds or less.

[0036] In addition, in the insulating layer forming step S20, when the sealing circuit layer 50 is pressed against the insulating material and heated, the insulating material is preferably in a B-stage state. The B-stage state is, for example, a state in which the reaction rate calculated from the measurement results of a DSC (differential scanning calorimeter) is more than 0% and is not more than 60%.

[0037] As described above, according to the method for manufacturing a substrate according to the present embodiment, the insulating layer 20 is formed while pressing the surface of the sealing circuit layer 50 formed by the metal layer 30 and the sealing resin layer 40 against the insulating material, so that the pressure applied from the metal layer 30 to the insulating material and the pressure applied from the sealing resin layer 40 to the insulating material become uniform. This makes it possible to suppress the metal layer 30 from biting into the insulating material (insulating layer 20). This reduces the step between the metal layer 30 and the sealing resin layer 40 at the portion of the metal layer 30 that contacts the insulating layer 20. As a result, it is possible to suppress a decrease in the insulation property of the insulating layer 20.

[0038] Next, a specific example of the circuit sealing step S10 will be described. FIG. 4 is a diagram showing a first example of the circuit sealing step S10. The first example is a step by compression molding. First, a metal layer 30 fixed to an adhesive tape 2 is prepared (S11). The adhesive tape 2 includes, for example, an adhesive layer that adheres and holds the metal layer 30, and a base layer for holding the adhesive layer. Next, a sealing material 60 is arranged so as to face a first surface 31, which is the surface of the metal layer 30 held by the adhesive tape 2 opposite to the adhesive tape 2, and the sealing material 60 is pressed toward the metal layer 30 and heated to form a sealing resin layer 40 (S12). For example, as shown in FIG. 4, the sealing material 60 is placed in a mold 70 and heated under a predetermined heating condition while being pressed toward the metal layer 30 with a predetermined pressure, thereby forming the sealing resin layer 40. In addition, the sealing material 60 is preferably plate-shaped. Thereafter, the adhesive tape 2 is removed to obtain a sealing circuit layer 50 (S13). The lower limit of the above-mentioned predetermined pressure is preferably 5 MPa or more, and more preferably 6 MPa or more. The upper limit of the above-mentioned predetermined pressure is preferably 10 MPa or less, and more preferably 9 MPa or less. The lower limit of the above-mentioned predetermined heating temperature is preferably 150°C or more, and more preferably 170°C or more. The upper limit of the above-mentioned predetermined heating temperature is preferably 200°C or less, and more preferably 190°C or less. The lower limit of the above-mentioned predetermined heating time is preferably 90 seconds or more, and more preferably 100 seconds or more. The upper limit of the above-mentioned predetermined heating time is preferably 120 seconds or less, and more preferably 110 seconds or less.

[0039] Next, FIGS. 5 and 6 are diagrams showing a second example of the circuit sealing step S10. The second example is a process by injection molding. In the second example, first, a metal layer 30 fixed to an adhesive tape 2 is prepared (S11). Since S11 is the same as in the first example, the description in FIGS. 5 and 6 is omitted. Next, the adhesive tape 2 and the metal layer 30 are placed in a mold 70 of an injection molding machine (S22). The mold 70 includes an upper mold 71 and a lower mold 72, and the adhesive tape 2 and the metal layer 30 are sandwiched between the upper mold 71 and the lower mold 72. Next, a sealing material 60 that has been heated and melted is injected into the mold 70 and then reacted and solidified to form a sealing circuit layer 50 (S23).

[0040] The example shown in FIG. 5 is a side gate type in which the cylinder 73 for injecting the sealing material 60 is located on the side of the area where the adhesive tape 2 and the metal layer 30 are arranged. In contrast, the example shown in FIG. 6 is a pin gate type in which the cylinder 73 is located on the upper surface of the area where the adhesive tape 2 and the metal layer 30 are arranged. In the case of the side gate type, since the outlet of the cylinder 73 is on the side of the sealing circuit layer 50, it is superior in that burrs of the sealing resin layer 40 on the upper surface of the sealing circuit layer 50 (i.e., the surface facing the insulating layer 20) are less likely to occur. On the other hand, in the case of the pin gate type, since the outlet of the cylinder 73 is on the upper surface of the sealing circuit layer 50, the injection pressure of the sealing material 60 is less likely to be applied to the side of the metal layer 30. Furthermore, since there are multiple cylinders 73, the difference in pressure on each side of the metal layer 30 is suppressed. As a result, in the case of the pin gate type, the occurrence of misalignment of the metal layer 30 is less likely to occur.

[0041] The above-mentioned method for forming the sealing circuit layer 50 is merely an example, and the method is not limited thereto.

[0042] Next, a modified example of the method for manufacturing the substrate 100 according to the present embodiment will be described. The modified example of the method for manufacturing the substrate 100 according to the present embodiment includes a grinding step S15 for grinding one surface of the encapsulating circuit layer 50 as shown in FIG. 7 between the circuit encapsulating step S10 and the insulating layer forming step S20.

[0043] For example, when the sealing circuit layer 50 is formed by the method shown in FIG. 4, the first surface 31 of the metal layer 30 opposite to the surface adhered to the adhesive tape 2 may be covered with the sealing resin layer 40. In the grinding step S15, the sealing resin layer 40 covering the metal layer 30 can be removed. In addition, the surface ground in the grinding step S15 is more flattened with burrs removed. Therefore, by pressing this surface against the insulating material in the insulating layer forming step S20, it is possible to prevent the burrs from entering the insulating material and the metal layer 30 from biting into the insulating material, and the deterioration of the insulating properties of the insulating layer 20 can be further suppressed.

[0044] Furthermore, when the metal layer 30 is covered with plating as a protective layer, the plating on the surface pressed against the insulating material may be removed in the grinding step S15. In this way, the heat dissipation property of the metal layer 30 can be improved while suppressing deterioration of the metal layer 30.

[0045] Next, a method for preparing the metal layer 30 fixed to the adhesive tape 2 in the specific example of the circuit sealing step S10 shown in FIG. 4 will be described. FIG. 8 is a process cross-sectional view showing an example of a method for preparing the metal layer 30 fixed to the adhesive tape 2. First, one surface (lower surface in the figure) of the metal plate 4 is covered with a masking tape 3 (S1). The masking tape 3 is not particularly limited as long as it is resistant to the etching in the next step (S2). Next, the other surface (upper surface in the figure) of the metal plate 4 that is not covered with the masking tape 3 is etched to obtain a grooved metal plate 4 in which grooves 5 of a desired pattern are formed to a predetermined depth. FIG. 9 is a plan view of the grooved metal plate 4 in which grooves 5 of a desired pattern are formed to a predetermined depth.

[0046] Next, the surface of the grooved metal plate 4 on which the grooves 5 are formed is covered with adhesive tape 2, and the masking tape 3 is removed (S3).

[0047] Next, the grooved metal plate 4 covered with the adhesive tape 2 is turned over so that the adhesive tape 2 side is facing down to adjust its orientation (S4), and further, the top surface of the grooved metal plate 4 (i.e., the surface opposite the adhesive tape 2) is etched to remove and open the top surfaces of the grooves 5, thereby forming the metal layer 30 (S5). As a result, the metal layer 30 fixed to the adhesive tape 2 is obtained.

[0048] The adhesive tape 2 may be any type of resin tape as long as it can adequately cover the surface of the metal plate 4 and can be adequately peeled off during the manufacturing process of the substrate 100. As the resin tape, a polyimide resin tape is preferable, and more specifically, a two-layer film member having an adhesive layer on one side of a polyimide layer serving as a base material is preferable. The thickness of the polyimide layer serving as a base material may be, for example, about 25 μm. As the adhesive layer, for example, an acrylic resin, an epoxy resin, or a silicone resin may be used.

[0049] Although the embodiments of the present invention have been described above with reference to the drawings, these are merely examples of the present invention, and various configurations other than those described above can also be adopted. [Explanation of symbols]

[0050] 100 Substrates 10 Base Board 20 Insulating layer 30 metal layer 31 Page 1 40 Sealing resin layer 50 Sealing circuit layer 60 Encapsulation material 70 Mold 71 Upper mold 72 Lower mold 73 Cylinder 2 Adhesive tape 3. Masking tape 4 metal plate 5 grooves

Claims

1. A substrate including a base plate, an insulating layer disposed on one surface of the base plate, a metal layer disposed on a surface of the insulating layer opposite to the base plate, and a sealing resin layer sealing the metal layer, A substrate, wherein in a portion formed of the metal layer and the sealing resin layer in contact with the insulating layer, the height of a step between the metal layer and the sealing resin layer is 20% or less of the thickness of the insulating layer.

2. The base plate has a heat dissipation protrusion on a surface opposite to the one surface. The substrate of claim 1 .

3. The metal layer is The surface is plated, The region facing the insulating layer does not have the plating. The substrate according to claim 1 or 2.

4. The sealing resin layer contains an epoxy resin. The substrate according to claim 1 or 2.

5. When the thickness of the thickest portion of the insulating layer is T2(MAX) and the thickness of the thinnest portion of the insulating layer is T2(MIN), (T2(MAX)-T2(MIN)) / T2(MAX) is 0.2 or less. The substrate according to claim 1 or 2.

6. an area of ​​the side surface of the metal layer that is covered with the sealing resin layer is 98% or more of the entire side surface of the metal layer; The substrate according to claim 1 or 2.

Images