Semiconductor device, method of manufacturing semiconductor device, and power conversion device

Abstract

To provide a semiconductor device that can prevent dielectric breakdown of an insulating film facing a gate electrode in the vicinity of a boundary between an active region and an inactive region.SOLUTION: A second trench TR2 is provided in an inactive region RI, is in contact with an active region RA, and has a second sidewall SW2 having a longitudinal portion SW2a and a lateral portion SW2b, and a second bottom BT2. A second bottom diffusion layer 17 of a second conductivity type is provided at least in a part of the second bottom BT2. A second sidewall diffusion layer 16b of the second conductivity type is provided at least on one of the longitudinal portion SW2a and the lateral portion SW2b. A gate electrode 18 includes a gate buried portion 18b buried in each of a plurality of first trenches TR1 and a gate wiring portion 18w extending from the gate buried portion 18b into the second trench TR2. The second bottom diffusion layer 17 is disposed at least in a portion of the second bottom BT2 on which the gate wiring portion 18w is disposed in a plan view.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Power semiconductor devices (more simply called power devices) are used as switching elements for controlling the power supply to loads such as motors. There are many demands on power devices, such as miniaturization, weight reduction, and low loss. Low loss is one of the biggest demands, and it also contributes to consideration for the global environment by reducing energy consumption. Furthermore, there is a demand to achieve the above demands at the lowest possible cost.

[0003] As the above-mentioned semiconductor device, one having an insulated gate, such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), is widely used. In particular, a method of reducing loss by increasing channel density by making the insulated gate a vertical trench gate is also widely used. In recent years, it has been proposed to apply wide band gap semiconductors such as silicon carbide (SiC) to improve the performance of semiconductor devices. Trench type MOSFETs to which SiC can be applied as a semiconductor material are disclosed in, for example, Patent Documents 1 to 3. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2017 / 138215 [Patent Document 2] JP 2015-126086 A [Patent Document 3] JP 2010-147222 A Summary of the Invention [Problem to be solved by the invention]

[0005] When switching the trench gate switching element as described above, the breakdown of the gate insulating film formed of an oxide film or the field insulating film directly under the gate pad may become a problem. In particular, when SiC is used as the semiconductor material, a higher breakdown voltage and higher speed operation are expected compared to the case of Si, but due to these factors, it is difficult to ensure the reliability of the insulating film. Specifically, in a switching element that requires a high breakdown voltage, the electric field strength applied to the insulating film is also high. In addition, in high-speed operation, dV / dt also becomes high, and an increase in voltage occurs due to the displacement current.

[0006] In particular, the gate electrode of a trench-gate switching element has a portion embedded in a trench formed in an active region and a portion extending from the portion to an inactive region (in other words, a region outside the active region). If the gate electrode faces the drift layer through a gate insulating film at the bottom or sidewall of the trench near the boundary between these portions, the gate electrode is easily affected by the potential of the drift layer. As a result, the above-mentioned insulating film breakdown is likely to occur. In order to prevent this, it is conceivable to form an impurity diffusion layer of a conductivity type opposite to that of the drift layer at the bottom and sidewall of the trench, but a trench structure provided with a diffusion layer that takes such consideration into account has not been sufficiently studied so far.

[0007] The present disclosure has been made to solve the above-mentioned problems, and one of its objectives is to provide a semiconductor device that can prevent dielectric breakdown of an insulating film facing a gate electrode near the boundary between an active region and an inactive region. [Means for solving the problem]

[0008] One aspect of the present disclosure is a semiconductor device having, in a plan view, an active region, and an inactive region including a breakdown voltage region and a gate wiring region in contact with the active region. The semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, a first electrode provided on the first main surface of the semiconductor substrate, a second electrode provided on the second main surface of the semiconductor substrate, an insulating film provided on the first main surface of the semiconductor substrate, and a gate electrode provided on the first main surface via the insulating film.

[0009] The semiconductor substrate includes a drift layer of a first conductivity type provided in the active region and the inactive region, a base region of a second conductivity type different from the first conductivity type, the base region being provided in the active region and disposed between the drift layer and the first main surface, a first semiconductor region of the first conductivity type provided in the active region, disposed on the base region, and in contact with the first electrode, a first trench provided on the first main surface in the active region, the first trench having a first sidewall in contact with the first semiconductor region and the base region, and a first bottom, the first trenches each extending along a longitudinal direction and arranged in a lateral direction intersecting the longitudinal direction, a first bottom diffusion layer of the second conductivity type provided in the first bottom of each of the first trenches, and a first bottom diffusion layer of the second conductivity type provided on the first sidewall of each of the first trenches, the first bottom diffusion layer being provided on the first sidewall of each of the first trenches, the first bottom diffusion layer being provided on the first sidewall of each of the first trenches, the first bottom diffusion layer being provided on the first bottom of each of the first trenches, and the first bottom diffusion layer being provided on the first sidewall of each of the first trenches. a first sidewall diffusion layer of the second conductivity type in contact with the first bottom diffusion layer and the base region; a second semiconductor region of the first conductivity type or the second conductivity type provided at least in the active region, disposed between the drift layer and the second main surface, and in contact with the second electrode; a second trench provided on the first main surface in the inactive region, the second sidewall in contact with the active region and having a long portion along the long direction and a short portion along the short direction, and a second bottom; a second bottom diffusion layer of the second conductivity type provided in at least a part of the second bottom of the second trench; and a second sidewall diffusion layer of the second conductivity type provided in at least one of the long portion and the short portion of the second sidewall of the second trench, in contact with the second bottom diffusion layer and the base region. The gate electrode includes a gate buried portion buried in each of the first trenches of the semiconductor substrate via the insulating film, and a gate wiring portion extending from the gate buried portion into the second trench. The second bottom diffusion layer is disposed in at least a portion of the second bottom of the second trench where the gate wiring portion is disposed in the plan view. Effect of the Invention

[0010] According to one aspect of the present disclosure, the second sidewall diffusion layer provided on the second sidewall of the second trench contacts the second bottom diffusion layer provided on at least a part of the second bottom of the second trench and the base region having the potential of the first electrode. As a result, the second sidewall in contact with the active region and the second bottom extending from the second sidewall to the inactive region are electrically connected to the potential of the first electrode, thereby preventing an excessive potential rise. Therefore, it is possible to prevent dielectric breakdown of the insulating film facing the gate electrode near the boundary between the active region and the inactive region.

[0011] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0012] [Figure 1] 1 is a plan view illustrating a schematic layout of a semiconductor device according to a first embodiment in a plan view. [Diagram 2] 2 is a partial plan view in a field of view of a dashed line region II in FIG. 1, illustrating roughly the configuration of the semiconductor device according to the first embodiment. [Diagram 3] 3 is a partial cross-sectional view taken along line III-III in FIG. 2, illustrating a schematic configuration of the semiconductor device according to the first embodiment. [Figure 4] 4 is a partial cross-sectional view taken along line IV-IV in FIG. 2, illustrating a schematic configuration of the semiconductor device according to the first embodiment. [Diagram 5] 3 is a partial cross-sectional view taken along line VV in FIG. 2, illustrating a schematic configuration of the semiconductor device according to the first embodiment. [Figure 6] 6 is a partial cross-sectional view taken along line VI-VI in FIG. 2, illustrating a schematic configuration of the semiconductor device according to the first embodiment. [Figure 7] 4 is a partial cross-sectional view in a field of view corresponding to FIG. 3, illustrating a first step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 6 is a partial cross-sectional view in a field of view corresponding to FIG. 5, illustrating a first step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9]4 is a partial cross-sectional view in a field of view corresponding to FIG. 3, illustrating a second step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 6 is a partial cross-sectional view in a field of view corresponding to FIG. 5, illustrating a second step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 4 is a partial cross-sectional view in a field of view corresponding to FIG. 3, illustrating a third step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 6 is a partial cross-sectional view in a field of view corresponding to FIG. 5, illustrating a third step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 4 is a partial cross-sectional view in a field of view corresponding to FIG. 3, illustrating a fourth step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 6 is a partial cross-sectional view in a field of view corresponding to FIG. 5, illustrating a fourth step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 5 is a partial cross-sectional view in a field of view corresponding to FIG. 3, illustrating a fifth step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 6 is a partial cross-sectional view in a field of view corresponding to FIG. 5, illustrating a fifth step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] 5 is a partial cross-sectional view in a field of view corresponding to FIG. 3, illustrating a sixth step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] 6 is a partial cross-sectional view in a field of view corresponding to FIG. 5, illustrating a sixth step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 19] 11 is a plan view illustrating a schematic layout of a semiconductor device according to a second embodiment in a plan view. FIG. [Figure 20] 20 is a partial plan view in a field of view of a dashed line region XX in FIG. 19, illustrating a schematic configuration of a semiconductor device according to a second embodiment. [Figure 21] 21 is a partial cross-sectional view taken along line XXI-XXI in FIG. 20, illustrating roughly the configuration of a semiconductor device according to a second embodiment. [Figure 22]22 is a partial cross-sectional view taken along line XXII-XXII of FIG. 20, illustrating roughly the configuration of a semiconductor device according to a second embodiment. [Figure 23] 23 is a partial cross-sectional view taken along line XXIII-XXIII in FIG. 20, illustrating roughly the configuration of a semiconductor device according to a second embodiment. [Figure 24] 24 is a partial cross-sectional view taken along line XXIV-XXIV in FIG. 20, illustrating roughly the configuration of a semiconductor device according to a second embodiment. [Diagram 25] 13 is a plan view that illustrates a schematic layout in a plan view of a semiconductor device according to a third embodiment. FIG. [Figure 26] 26 is a partial plan view in a field of view of a dashed line region XXVI in FIG. 25, illustrating roughly the configuration of a semiconductor device according to a third embodiment. FIG. [Figure 27] 27 is a partial cross-sectional view taken along line XXVII-XXVII in FIG. 26, illustrating roughly the configuration of a semiconductor device according to a third embodiment. [Figure 28] 27 is a partial cross-sectional view taken along line XXVIII-XXVIII in FIG. 26, illustrating roughly the configuration of a semiconductor device according to a third embodiment. [Figure 29] 27 is a partial cross-sectional view taken along line XXIX-XXIX in FIG. 26, illustrating roughly the configuration of a semiconductor device according to a third embodiment. [Diagram 30] 27 is a partial cross-sectional view taken along line XXX-XXX in FIG. 26, illustrating roughly the configuration of a semiconductor device according to a third embodiment. [Diagram 31] FIG. 11 is a plan view that illustrates a schematic layout in a plan view of a semiconductor device according to a fourth embodiment. [Diagram 32] 32 is a partial plan view in a field of view of a dashed line region XXXII in FIG. 31, illustrating roughly the configuration of a semiconductor device according to a fourth embodiment. FIG. [Diagram 33] 33 is a partial cross-sectional view taken along line XXXIII-XXXIII in FIG. 32, illustrating roughly the configuration of a semiconductor device according to a fourth embodiment. [Diagram 34] 34 is a partial cross-sectional view taken along line XXXIV-XXXIV in FIG. 32, illustrating roughly the configuration of a semiconductor device according to a fourth embodiment. [Diagram 35]33 is a partial cross-sectional view taken along line XXXV-XXXV of FIG. 32, illustrating roughly the configuration of a semiconductor device according to a fourth embodiment. [Diagram 36] 36 is a partial cross-sectional view taken along line XXXVI-XXXVI in FIG. 32, illustrating roughly the configuration of a semiconductor device according to a fourth embodiment. [Figure 37] FIG. 13 is a block diagram illustrating a schematic configuration of a power conversion system including a power conversion device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment will be described with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0014] <Embodiment 1> FIG. 1 is a plan view showing a layout of a semiconductor device 501 according to the first embodiment in a plan view. FIG. 2 is a partial plan view showing the configuration of the semiconductor device 501 in the field of view of a broken line region II in FIG. 1. FIG. 3 is a partial cross-sectional view showing the configuration of the semiconductor device 501 along line III-III in FIG. 2. FIG. 4 is a partial cross-sectional view showing the configuration of the semiconductor device 501 along line IV-IV in FIG. 2. FIG. 5 is a partial cross-sectional view showing the configuration of the semiconductor device 501 along line VV in FIG. 2. FIG. 6 is a partial cross-sectional view showing the configuration of the semiconductor device 501 along line VI-VI in FIG. 2. The dotted pattern in FIG. 1 shows an example of the pattern of all the surface electrodes on the upper surface SF1 of the semiconductor substrate SB. The dotted pattern in FIG. 2 shows the pattern of the gate embedded portion 18b and the internal wiring 18ew, which are part of the gate electrode 18 (typically, the pattern of the polysilicon layer). In FIG. 2, in order to make the internal structure of the semiconductor device 501 easier to see, only the edges of the gate surface electrode 18pw of the gate electrode 18 and the source electrode 11 are shown by two-dot chain lines, and the interlayer insulating film 9 is omitted from the illustration, while the contact portions CTs and CTg that penetrate it are shown by rectangles with X marks.

[0015] The semiconductor device 501 has a semiconductor substrate SB. In a plan view on the semiconductor substrate SB, the semiconductor device 501 has an active region RA and an inactive region RI. On the semiconductor substrate SB, the active region RA is a portion in which actual elements are formed, and the inactive region RI is a portion in which actual elements are not formed. The active region RA may be configured by arranging a plurality of cell structures having approximately the same structure approximately periodically. The inactive region RI has a withstand voltage holding region RIv and a gate wiring region RIg in contact with the active region RA. The gate wiring region RIg may have a pad region RIgp and an internal wiring region RIgw. The inactive region RI may further have a source wiring region RIs. The withstand voltage holding region RIv is a region for ensuring the withstand voltage of the semiconductor device 501, and therefore preferably surrounds the active region RA. In the withstand voltage holding region RIv, it is preferable that a region for securing the withstand voltage is formed on the upper surface SF1 by doping with impurities, and for example, an FLR27 (Field Limiting Ring) as shown in FIG. 23 and FIG. 24 referred to in the second embodiment described later is formed. The FLR27 is n - The gate wiring region RIg has a conductivity type different from that of the drift layer 3. The gate wiring region RIg is a region for arranging a gate wiring portion 18w, which will be described in detail later. The source wiring region RIs is a region for arranging a source wiring portion 29 (see FIGS. 23 and 42, which will be described later) that is a part of the source electrode 11.

[0016] The semiconductor substrate SB has an upper surface SF1 (first main surface) and a lower surface SF2 (second main surface opposite to the first main surface). The upper surface SF1 of the semiconductor substrate SB has a roughly flat portion and a plurality of trenches, which are portions lowered with respect to the flat region, specifically, a plurality of first trenches TR1 and at least one second trench TR2. The material of the semiconductor substrate SB is not particularly limited, and is, for example, Si or SiC. In addition to the semiconductor substrate SB, the semiconductor device 501 has a source electrode 11 (first electrode), a drain electrode 12 (second electrode), a gate electrode 18, a gate insulating film 7, a field insulating film 20, and an interlayer insulating film 9. The semiconductor device 501 according to the first embodiment is a vertical MOSFET that switches a main current flowing between the source electrode 11 on the upper surface SF1 and the drain electrode 12 on the lower surface SF2, and has a trench gate structure controlled by the potential of the gate electrode 18. This trench gate structure is a vertical MOSFET that switches a main current flowing between the source electrode 11 on the upper surface SF1 and the drain electrode 12 on the lower surface SF2, and has a trench gate structure controlled by the potential of the gate electrode 18. + A source layer 5, a p-channel doped layer 4, and a n - It is composed of the drift layer 3, the gate insulating film 7, and the gate embedded portion 18b of the gate electrode 18.

[0017] The source electrode 11 is provided on the upper surface SF1 of the semiconductor substrate SB. The source electrode 11 may have a silicide layer 11b in contact with the semiconductor substrate SB and a non-silicide layer 11a laminated thereon. The drain electrode 12 is provided on the lower surface SF2 of the semiconductor substrate SB. The drain electrode 12 may have a silicide layer 12b (barrier metal layer) in contact with the semiconductor substrate SB and a surface metal layer 12a laminated thereon. The non-silicide layer 11a and the surface metal layer 12a may be made of an electrode material containing, for example, aluminum.

[0018] The gate insulating film 7, the field insulating film 20, and the interlayer insulating film 9 are provided on an upper surface SF1 of the semiconductor substrate SB. The interlayer insulating film 9 separates the source electrode 11 and the gate electrode 18 in the thickness direction (the vertical direction in FIGS. 3 to 6). The gate electrode 18 is provided on the upper surface SF1 via either the gate insulating film 7 or the field insulating film 20. The thickness of the field insulating film 20 may be greater than the thickness of the gate insulating film 7.

[0019] The semiconductor substrate SB is an n-type (first conductivity type) - A drift layer 3, a p-type (a second conductivity type different from the first conductivity type) p-channel doped layer 4 (base region), and a n + A source layer 5 (first semiconductor region) and a p-type + A contact layer 6 (contact region), a p-type first bottom diffusion layer 14, a p-type first sidewall diffusion layer 16a, and an n-type + The semiconductor substrate SB further includes a substrate 1 (second semiconductor region), a p-type second bottom diffusion layer 17, and a p-type second sidewall diffusion layer 16b. + Substrate 1 and n - Between the drift layer 3, an n-type + The semiconductor substrate SB may include a buffer layer 2. The semiconductor substrate SB may further include an n-type sidewall diffusion layer 15.

[0020] n - The drift layer 3 is provided in the active region RA and the inactive region RI. + The substrate 1 is provided with at least an active region RA, - It is disposed between the drift layer 3 and the lower surface SF2. + The substrate 1 is in contact with a drain electrode 12 .

[0021] The p-channel doped layer 4 is provided in the active region RA. - It is disposed between the drift layer 3 and the upper surface SF1.

[0022] n + The source layer 5 is provided in the active region RA and is disposed on the p-channel doped layer 4. +The source layer 5 is in contact with a source electrode 11 .

[0023] The first trenches TR1 are provided in the upper surface SF1 in the active region RA. + The first trenches TR1 have a first sidewall SW1 in contact with the source layer 5 and the p-channel doped layer 4, and a first bottom BT1. Each of the multiple first trenches TR1 extends along a longitudinal direction (the lateral direction in FIG. 2). The multiple first trenches TR1 are arranged in a lateral direction intersecting the longitudinal direction. The lateral direction may be perpendicular to the longitudinal direction.

[0024] The first bottom diffusion layer 14 is provided on the first bottom BT1 of each of the first trenches TR1. The first sidewall diffusion layer 16a is provided on a part of the first sidewall SW1 of each of the first trenches TR1. The first sidewall diffusion layer 16a is in contact with the first bottom diffusion layer 14 and the p-channel doped layer 4. An n-type first diffusion layer 16a is provided on the portion of the first sidewall SW1 where the p-type first sidewall diffusion layer 16a is not provided. - An n-type sidewall diffusion layer 15 in contact with the drift layer 3 may be provided.

[0025] The second trench TR2 is provided on the upper surface SF1 in the inactive region RI and is in contact with the active region RA. The second trench TR2 has a second side wall SW2 and a second bottom BT2. The second side wall SW2 has a long portion SW2a along the long direction and a short portion SW2b along the short direction. In the range of the field of view of the partial plan view of FIG. 2, the second trench TR2 extends in an L-shape. In the overall plan view of the semiconductor device 501, the second trench TR2 may surround the active region RA. A plurality of first trenches TR1 may be directly connected to the second trench TR2, and in FIG. 2, the left end of each first trench TR1 is directly connected to the second trench TR2. The width of the second trench TR2 may be wider than the width of the first trench TR1 (the lateral dimension in FIG. 3 or FIG. 4).

[0026] The second bottom diffusion layer 17 is provided in at least a part of the second bottom BT2 of the second trench TR2.

[0027] The second sidewall diffusion layer 16b is provided on at least one of the long portion SW2a and the short portion SW2b of the second sidewall SW2 of the second trench TR2. As shown in FIG. 2 to FIG. 6, the second sidewall diffusion layer 16b may be provided on both the long portion SW2a and the short portion SW2b of the second sidewall SW2 of the second trench TR2. The second sidewall diffusion layer 16b may be provided on the entire long portion SW2a of the second sidewall SW2 of the second trench TR2. The second sidewall diffusion layer 16b may be provided on the entire short portion SW2b of the second sidewall SW2 of the second trench TR2. The second sidewall diffusion layer 16b is in contact with the second bottom diffusion layer 17 and the p-channel doped layer 4.

[0028] The second sidewall diffusion layer 16b may surround the active region RA in plan view. In addition, when the second sidewall SW2 of the second trench TR2 is connected to the end face of the first trench TR1 (the left end of the first trench TR1 in FIG. 2) as shown in FIG. 2, if the second sidewall diffusion layer 16b surrounds the active region RA via the end face in plan view, the second sidewall diffusion layer 16b is considered to surround the active region RA in plan view.

[0029] The source electrode 11 has at least one contact portion CTs that contacts the upper surface SF1 of the semiconductor substrate SB outside the second trench TR2. In FIG. 2, in the upper right part of the field of view (outside the second trench TR2 extending in an L-shape on the left and lower sides of the field of view), a plurality of contact portions CTs (rectangles marked with an X), each extending in the longitudinal direction, are arranged in the short-side direction (vertical direction in the figure). The source electrode 11 may have a contact portion CTs between the second trench TR2 and a trench among the plurality of first trenches TR1 that is closest to the second trench TR2 in the short-side direction. This contact portion CTs corresponds to the contact portion CTs arranged at the bottom in the field of view of FIG. 2.

[0030] p +The contact layer 6 is in contact with the contact portion CTs of the source electrode 11, specifically, in contact with the silicide layer 11b of the source electrode 11. + The contact layer 6 is in contact with the p-channel doped layer 4. + The contact layer 6 may be in contact with the second sidewall diffusion layer 16b. In this case, the contact portion CTs and the second sidewall diffusion layer 16b are p + They are electrically connected to each other by a contact layer 6 .

[0031] The gate electrode 18 has a gate buried portion 18b and a gate wiring portion 18w. The gate buried portion 18b is buried in each of the multiple first trenches TR1 of the semiconductor substrate SB via the gate insulating film 7. The gate buried portion 18b is made of, for example, polysilicon. The gate wiring portion 18w extends from the gate buried portion 18b into the second trench TR2. A second bottom diffusion layer 17 is arranged at least in a portion of the second bottom portion BT2 of the second trench TR2 where the gate wiring portion 18w is arranged in a plan view.

[0032] The gate wiring portion 18w may have an internal wiring 18ew and a gate surface electrode 18pw. The internal wiring 18ew is directly connected to the gate buried portion 18b. The internal wiring 18ew and the gate buried portion 18b may be made of the same material, for example, made of polysilicon. The gate surface electrode 18pw in the pad region RIgp (FIG. 1) can be used as a member to which a wiring (e.g., a bonding wire) for applying a gate potential to the semiconductor device 501 is connected. The gate surface electrode 18pw has a contact portion CTg in contact with the internal wiring 18ew. In a portion of the upper surface SF1 of the semiconductor substrate SB that overlaps with the gate surface electrode 18pw in a plan view, the second bottom diffusion layer 17 or the p + A p-type diffusion layer may be disposed thereon, which is the contact layer 6. In addition, in a portion overlapping with the gate surface electrode 18pw in a plan view, the internal wiring 18ew may be disposed on the field insulating film 20 and thus separated from the semiconductor substrate SB.

[0033] Next, the manufacturing method of the semiconductor device 501, in particular the process of forming the first trench TR1 having an inner surface on which the first bottom diffusion layer 14 and the first sidewall diffusion layer 16a are formed, and the second trench TR2 having an inner surface on which the second bottom diffusion layer 17 and the second sidewall diffusion layer 16b are formed, will be described below with reference to Figures 7 to 18.

[0034] 7 and 8 are partial cross-sectional views in the field of view corresponding to FIGS. 3 and 5, each of which shows a schematic first step of the method for manufacturing a semiconductor device 501. + A substrate 1 and n layers stacked in order on the substrate + Buffer layer 2 and n - A semiconductor substrate SB having a drift layer 3 is prepared. Next, an etching mask material 23 is formed on an upper surface SF1 of the semiconductor substrate SB by using, for example, a general photolithography technique. The etching mask material 23 may have, for example, a photoresist film or a plasma insulating film formed using a photoresist film.

[0035] 9 and 10 are partial cross-sectional views in a field of view corresponding to that of FIGS. 3 and 5, respectively, which roughly show a second step of the method for manufacturing the semiconductor device 501. In this step, etching is performed using an etching mask material 23. As a result, a first trench TR1 and a second trench TR2 are formed.

[0036] 11 and 12 are partial cross-sectional views in the field of view corresponding to FIG. 3 and FIG. 5, each of which shows a schematic view of a third step of the manufacturing method of the semiconductor device 501. First, an implantation mask material 23A is formed on an upper surface SF1 of the semiconductor substrate SB, for example, by using a general photolithography technique. Note that instead of forming the entire implantation mask material 23A anew, the etching mask material 23 (FIG. 9 and FIG. 10) may be used as a part or the whole of the implantation mask material 23A. Next, an impurity implanted region 26 is formed by performing ion implantation using the implantation mask material 23A. In order to efficiently perform this ion implantation on the first bottom BT1 of the first trench TR1 and the second bottom BT2 of the second trench TR2 and to substantially not affect the first sidewall SW1 of the first trench TR1 and the second sidewall SW2 of the second trench TR2, the ion implantation is performed substantially perpendicular to the semiconductor substrate SB. Note that, as a modified example, this third step may be performed after the fourth and fifth steps described later.

[0037] Next, ions are implanted into the first sidewall SW1 of the first trench TR1 and the second sidewall SW2 of the second trench TR2 from an oblique direction into the semiconductor substrate SB to form impurity implantation regions for forming the first sidewall diffusion layer 16a (FIG. 3) and the second sidewall diffusion layer 16b (FIG. 5). This process will be described below with reference to FIGS. 13 to 16.

[0038] 13 and 14 are partial cross-sectional views in the field of view corresponding to FIG. 3 and FIG. 5, each of which shows a schematic view of a fourth step of the manufacturing method of the semiconductor device 501. First, an implantation mask material 23B is formed on an upper surface SF1 of the semiconductor substrate SB, for example, by using a general photolithography technique. Instead of forming the entire implantation mask material 23A anew, the etching mask material 23 or the implantation mask material 23A may be used as a part or the whole of the implantation mask material 23B. Next, an impurity implanted region 26 is formed by performing ion implantation using the implantation mask material 23B. In this step, the direction of ion implantation is set so that the ion implantation is efficiently performed on the first sidewall SW1 of the first trench TR1 and the long portion SW2a of the second sidewall SW2 of the second trench TR2, and does not substantially affect the short portion SW2b of the second sidewall SW2 of the second trench TR2. Specifically, the direction of ion implantation is set so that the ion beam is efficiently incident on the first sidewall SW1 of the first trench TR1 and the long portion SW2a of the second sidewall SW2 of the second trench TR2 (see FIG. 13) and is not substantially incident on the short portion SW2b of the second sidewall SW2 of the second trench TR2 (see FIG. 14). Thus, in this step, ion implantation is performed on the long portion SW2a of the second sidewall SW2 of the second trench TR2 and ion implantation is not substantially performed on the short portion SW2b of the second sidewall SW2 of the second trench TR2. As a modified example, the ion implantation in this fourth step may be performed after the ion implantation in a fifth step described later.

[0039] 15 and 16 are partial cross-sectional views in the field of view corresponding to FIG. 3 and FIG. 5, each of which shows a schematic view of a fifth step of the manufacturing method of the semiconductor device 501. An impurity implanted region 26 is formed by performing ion implantation using the implantation mask material 23B. In this step, the direction of ion implantation is set so that the ion beam is efficiently implanted into the short portion SW2b of the second sidewall SW2 of the second trench TR2, and does not substantially affect the first sidewall SW1 of the first trench TR1 and the long portion SW2a of the second sidewall SW2 of the second trench TR2. Specifically, the direction of ion implantation is set so that the ion beam is efficiently incident on the short portion SW2b of the second sidewall SW2 of the second trench TR2 (see FIG. 16), and is not substantially incident on the first sidewall SW1 of the first trench TR1 and the long portion SW2a of the second sidewall SW2 of the second trench TR2 (see FIG. 15). Therefore, in this step, ions are implanted into the short portion SW2b of the second sidewall SW2 of the second trench TR2, and ions are not substantially implanted into the long portion SW2a of the second sidewall SW2 of the second trench TR2.

[0040] 17 and 18 are partial cross-sectional views in the field of view corresponding to FIG. 3 and FIG. 5, each of which shows a sixth step of the manufacturing method of the semiconductor device 501. In this step, annealing is performed on the semiconductor substrate SB in which the impurity implantation region 26 (FIG. 15 and FIG. 16) is formed. As a result, the implanted impurities are activated to form the first bottom diffusion layer 14, the first sidewall diffusion layer 16a, the second bottom diffusion layer 17, and the second sidewall diffusion layer 16b. As described above, the fourth step (FIG. 13 and FIG. 14) and the fifth step (FIG. 15 and FIG. 16) are performed separately. Therefore, in order to form the second sidewall diffusion layer 16b on the second sidewall SW2 of the second trench TR2, a plurality of ion implantation steps having different ion implantation directions are performed. In each of the above-mentioned ion implantation steps, for example, aluminum ions are used as the impurity ions. In addition, the implantation energy of each ion implantation is set so that the diffusion spread in the depth direction and in the in-plane direction of the p-type impurity diffusion layer formed by this ion implantation is sufficient to prevent electric field concentration in the gate insulating film 7 of the semiconductor device 501, while taking into consideration the effects on the main breakdown voltage and on-resistance.

[0041] In addition, in the semiconductor substrate SB of the semiconductor device 501, the p-channel doped layer 4 and the n + A source layer 5 and a p + The contact layer 6 can be formed by using the photolithography technique, ion implantation technique, and annealing technique described above. These may be formed before the fourth step (FIGS. 13 and 14). If the ion implantation for these formations is performed before the sixth step (FIGS. 17 and 18), the sixth step can also serve as the annealing for these formations. The subsequent steps can be performed by general semiconductor manufacturing techniques, and therefore the description thereof will be omitted. Furthermore, the manufacturing methods of the semiconductor devices 502 to 504 of the second to fourth embodiments described later can be performed by modifying the processing pattern in the manufacturing method of the semiconductor device 501 of the first embodiment described above, and therefore the description thereof will be omitted.

[0042] Next, the operation of the semiconductor device 501 will be described below. As described above, the semiconductor device 501 has n+ A source layer 5, a p-channel doped layer 4, and a n - The device has a MOSFET structure including the drift layer 3, the gate insulating film 7, and the gate embedded portion 18b of the gate electrode 18. When a positive voltage equal to or greater than the threshold voltage of the MOSFET structure is applied to the gate electrode 18, the MOSFET structure is turned on. This causes the drain voltage to drop, and a main current flows between the source electrode 11 and the drain electrode 12. Conversely, when a positive voltage or a negative voltage less than the threshold voltage of the MOSFET structure is applied to the gate electrode 18, the MOSFET structure is turned off. This causes the drain voltage to rise, and the source electrode 11 and the drain electrode 12 are electrically disconnected.

[0043] Next, we will explain the problems that can occur in a typical MOSFET. When the drain voltage rises due to the switching operation described above, - The voltage shared by the gate insulating film 7 in contact with the drift layer 3 also increases, so the electric field strength applied to the gate insulating film 7 becomes stronger. In general, the vicinity of the trench formed at the boundary between the breakdown voltage holding region RIv and the active region RA is subject to the electric field in the thickness direction and the electric field in the in-plane direction of the semiconductor substrate SB, and is therefore significantly affected by this. In addition, if the potential of the p-type diffusion layer provided at the bottom of the trench increases with an increase in the drain voltage, the electric field applied to the gate insulating film at the bottom of the trench becomes stronger.

[0044] According to the configuration of the semiconductor device 501 of this embodiment, the second sidewall diffusion layer 16b provided on the second sidewall SW2 of the second trench TR2 contacts each of the second bottom diffusion layer 17 provided on at least a part of the second bottom BT2 of the second trench TR2 and the p-channel doped layer 4 having a source potential (more generally, the potential of the first electrode 11). As a result, the second sidewall SW2 in contact with the active region RA and the second bottom BT2 extending therefrom to the inactive region RI are electrically connected to the source potential (more generally, the potential of the first electrode 11), thereby preventing an excessive potential rise. Therefore, it is possible to prevent dielectric breakdown of the insulating film (specifically, the gate insulating film 7 or the field insulating film 20) facing the gate electrode 18 in the vicinity of the boundary between the active region RA and the inactive region RI. In addition, by preventing the above-mentioned excessive potential rise, it is possible to avoid malfunction of the semiconductor device.

[0045] The second sidewall diffusion layer 16b may be provided on both the long side portion SW2a and the short side portion SW2b of the second sidewall SW2 of the second trench TR2, thereby making it possible to prevent an excessive potential rise in both the long side portion SW2a and the short side portion SW2b of the second sidewall SW2.

[0046] In plan view, the second trench TR2 may surround the active region RA, thereby providing a region that can prevent an excessive potential rise so as to surround the active region RA.

[0047] p-type + The contact layer 6 is in contact with the contact portion CTs and the second sidewall diffusion layer 16b. This allows the second sidewall diffusion layer 16b to be connected to the source potential (more generally, the potential of the first electrode 11), + Electrical connection can be achieved through a short electrical path passing through the contact layer 6. This makes it possible to more reliably prevent an excessive increase in potential of the second sidewall diffusion layer 16b.

[0048] The first trenches TR1 may be directly connected to the second trench TR2, so that a p-type diffusion layer provided in the second trench TR2 or a further trench (e.g., the third trench TR3 (see FIGS. 32, 35, and 36 (Embodiment 4 described later)) can be formed continuously from either or both of the first bottom diffusion layer 14 and the first sidewall diffusion layer 16a of the first trench TR1.

[0049] The ratio of the area of ​​the second sidewall diffusion layer 16b to the total area of ​​the second sidewall SW2 of the second trench TR2 may be greater than the ratio of the area of ​​the first sidewall diffusion layer 16a to the total area of ​​the first sidewall SW1 of the first trench TR1. This can make the effect of the second sidewall diffusion layer 16b more sufficient. This will be described below.

[0050] Referring to FIG. 2, the length L1, the length Lp1, the length L2, and the length Lp2 are as follows: L1: Pitch of the repeated pattern in the active region RA in plan view Lp1: the pattern length of the first sidewall diffusion layer 16a in the repeated pattern of the active region RA in plan view L2: Pitch of the repeating pattern of the second trench TR2 in plan view Lp2: the pattern length of the second sidewall diffusion layer 16b in the repeated pattern of the second trenches TR2 in plan view It represents.

[0051] Here, it is considered acceptable to approximate that the first trench TR1 has a substantially uniform depth, and the second trench TR2 also has a substantially uniform depth. Therefore, if the ratio of the area of ​​the first sidewall diffusion layer 16a to the total area of ​​the first sidewall SW1 of the first trench TR1 is defined as R1, and the ratio of the area of ​​the second sidewall diffusion layer 16b to the total area of ​​the longitudinal portion SW2a of the second sidewall SW2 of the second trench TR2 is defined as R2, then R1 = Lp1 / L1 R2 = Lp2 / L2 The following relationship is obtained between the ratio R1 and the ratio R2: R2 > R1 When the above relationship is satisfied, the potential around the long portion SW2a of the second side wall SW2 is stably grounded to the source potential. Although the detailed description here focuses on only the long portion SW2a of the second side wall SW2, substantially the same thing can be said even if R2 is calculated focusing on the entire second side wall SW2.

[0052] As described above, the ratio R1 proportional to the ratio of the first sidewall diffusion layer 16a formed may be relatively small, so that the n + The ratio of the source layer 5 formed can be secured to be relatively large. What actually functions as a MOSFET structure is not the first sidewall diffusion layer 16a but the n + Since it is the source layer 5, n + A sufficiently low on-resistance can be obtained by ensuring a relatively large ratio of the source layer 5. Therefore, according to this embodiment, a sufficiently low on-resistance can be obtained while preventing dielectric breakdown of the semiconductor device 501 by the above-mentioned effects.

[0053] According to the manufacturing method of the semiconductor device 501 of the present embodiment, a step of forming the first sidewall diffusion layer 16a and the second sidewall diffusion layer 16b by performing ion implantation from an oblique direction into the first sidewall SW1 of the first trench TR1 and the second sidewall SW2 of the second trench TR2 is performed. As a result, a desired impurity diffusion layer can be formed only by ion implantation into a relatively shallow region from the inner surface of the first trench TR1 and the second trench TR2. Therefore, it is not necessary to perform ion implantation at high energy. As a result, firstly, it is not necessary to use a high-energy ion implanter. Secondly, it is not necessary to form a thick implantation mask that can withstand high-energy ion implantation. Thirdly, it is possible to prevent the occurrence of crystal defects in the semiconductor due to high energy.

[0054] The step of implanting ions into the long portion SW2a of the second sidewall SW2 of the second trench TR2 and the step of implanting ions into the short portion SW2b of the second sidewall SW2 of the second trench TR2 may be performed separately, thereby making it possible to stably form the second sidewall diffusion layer 16b in each of the long portion SW2a and the short portion SW2b.

[0055] A process of forming the first trench TR1 and the second trench TR2 in the semiconductor substrate SB may be performed simultaneously, and a process of forming the first sidewall diffusion layer 16a and the second sidewall diffusion layer 16b by performing ion implantation from an oblique direction into the first sidewall SW1 of the first trench TR1 and the second sidewall SW2 of the second trench TR2 may be performed simultaneously. This makes it possible to suppress an increase in manufacturing costs for adding the second trench TR2 and the second sidewall diffusion layer 16b to a typical semiconductor device having the first trench TR1 and the first sidewall diffusion layer 16a.

[0056] In the above-described first embodiment, the first conductivity type is n-type and the second conductivity type is p-type. As a modification, the first conductivity type may be p-type and the second conductivity type may be n-type. This modification may be applied to the other embodiments.

[0057] In the semiconductor device 501 according to the first embodiment, a second semiconductor region (n in the present embodiment) is provided to configure a MOSFET (more generally, a MISFET (Metal Insulator Semiconductor Field Effect Transistor)). + The substrate 1) has a first conductivity type. As a modification to this, the second semiconductor region may have a second conductivity type, in which case an IGBT is obtained as the semiconductor device. This modification can also be applied to the other embodiments.

[0058] <Embodiment 2> FIG. 19 is a plan view showing a layout of the semiconductor device 502 according to the second embodiment in a plan view. FIG. 20 is a partial plan view showing the configuration of the semiconductor device 502 in the field of view of the broken line region XX in FIG. 19. FIG. 21 is a partial cross-sectional view taken along line XXI-XXI in FIG. 20 showing the configuration of the semiconductor device 502. FIG. 22 is a partial cross-sectional view taken along line XXII-XXII in FIG. 20 showing the configuration of the semiconductor device 502. FIG. 23 is a partial cross-sectional view taken along line XXIII-XXIII in FIG. 20 showing the configuration of the semiconductor device 502. FIG. 24 is a partial cross-sectional view taken along line XXIV-XXIV in FIG. 20 showing the configuration of the semiconductor device 502. The dotted pattern in FIG. 19 shows an example of an electrode pattern on the upper surface SF1 of the semiconductor substrate SB. The dotted pattern in FIG. 20 shows the pattern of the gate embedded portion 18b and the internal wiring 18ew, which are part of the gate electrode 18 (typically, a pattern of a polysilicon layer). In FIG. 20, in order to make the internal structure of the semiconductor device 502 easier to see, only the edges of the gate surface electrode 18pw of the gate electrode 18 and the source electrode 11 are indicated by dashed two-dot lines, and the interlayer insulating film 9 is omitted from the illustration, while the contact portions CTs, CTg, and CTsb that penetrate it are indicated by rectangles with X marks.

[0059] In the semiconductor device 502, each of the breakdown voltage holding region RIv, the source wiring region RIs, and the internal wiring region RIgw (FIG. 19) is disposed in the second trench TR2. In the breakdown voltage holding region RIv, a region for ensuring the breakdown voltage is preferably formed on the upper surface SF1 by doping with impurities. For example, as shown in FIGS. 23 and 24, a p-type FLR 27 and an n-type channel stopper layer 28 are provided on the upper surface SF1. The source wiring portion 29 (FIGS. 23 and 24) disposed in the source wiring region RIs (FIG. 1) is a part of the source electrode 11, and extends from a portion of the source electrode 11 disposed in the active region RA. The source wiring portion 29 may have a silicide layer 29b in contact with the semiconductor substrate SB and a non-silicide layer 29a laminated thereon. The source wiring portion 29 of the source electrode 11 may have a contact portion CTsb in contact with the second bottom diffusion layer 17.

[0060] The configuration other than the above is substantially the same as that of the first embodiment, and therefore the description thereof will not be repeated.

[0061] According to this embodiment, each of the breakdown voltage holding region RIv, the source wiring region RIs, and the internal wiring region RIgw (FIG. 19) is disposed in the second trench TR2. This makes it possible to prevent electric field concentration in each of these regions by utilizing the second trench TR2. Therefore, the semiconductor device 502 can stably ensure the main breakdown voltage (the breakdown voltage between the first electrode 11 and the second electrode 12) while preventing dielectric breakdown of the insulating film facing the gate electrode 18.

[0062] <Embodiment 3> FIG. 25 is a plan view showing a layout of the semiconductor device 503 according to the third embodiment in a plan view. FIG. 26 is a partial plan view showing the configuration of the semiconductor device 503 in the field of view of the broken line region XXVI in FIG. 25. FIG. 27 is a partial cross-sectional view taken along the line XXVII-XXVII in FIG. 26 showing the configuration of the semiconductor device 503. FIG. 28 is a partial cross-sectional view taken along the line XXVIII-XXVIII in FIG. 26 showing the configuration of the semiconductor device 503. FIG. 29 is a partial cross-sectional view taken along the line XXIX-XXIX in FIG. 26 showing the configuration of the semiconductor device 503. FIG. 30 is a partial cross-sectional view taken along the line XXX-XXX in FIG. 26 showing the configuration of the semiconductor device 503. The dotted pattern in FIG. 25 shows an example of an electrode pattern on the upper surface SF1 of the semiconductor substrate SB. The dotted pattern in FIG. 26 shows the pattern of the gate embedded portion 18b and the internal wiring 18ew, which are part of the gate electrode 18 (typically, a pattern of a polysilicon layer). In FIG. 26, in order to make the internal structure of the semiconductor device 503 easier to see, only the edges of the gate surface electrode 18pw of the gate electrode 18 and the source electrode 11 are shown by two-dot chain lines, and the interlayer insulating film 9 is omitted from the illustration, while the contact portions CTs and CTg that penetrate it are shown by rectangles with X marks.

[0063] In the semiconductor device 503, the source electrode 11 has a contact portion CTsb in contact with the second bottom diffusion layer 17 of the semiconductor substrate SB. With reference to the cross-sectional view of FIG. 29, the contact portion CTsb is disposed between the gate electrode 18 and the second sidewall SW2 of the second trench TR2 on the upper surface SF1 (in other words, in a plan view). In this configuration, unlike FIG. 23 (Embodiment 2), the gate electrode 18 is not interposed between the contact portion CTsb and the second sidewall SW2 of the second trench TR2 on the upper surface SF1 (in other words, in a plan view). Thus, in this embodiment, the contact portion CTsb can be disposed close to the second sidewall diffusion layer 16b. How close the contact portion CTsb should preferably be disposed will be described below.

[0064] On the upper surface SF1 of the semiconductor substrate SB, the first trenches TR1 are arranged at an interval in the short-side direction. This interval, as described with reference to FIG. 21, is the dimension between the right end of the opening of the left first trench TR1 and the left end of the opening of the central first trench TR1 on the upper surface SF1. In other words, this interval is the width dimension of the mesa portion of the semiconductor substrate SB between the adjacent first trenches TR1 on the upper surface SF1. In a plan view, it is preferable that the interval between the contact portion CTsb and the second sidewall SW2 on which the second sidewall diffusion layer 16b is provided is smaller than the interval.

[0065] The configuration other than the above is substantially the same as that of the first embodiment, and therefore the description thereof will not be repeated.

[0066] According to this embodiment, the contact portion CTsb can directly connect the second bottom diffusion layer 17 to the source electrode 11 having the source potential (more generally, the potential of the first electrode 11). Therefore, an excessive potential rise of the second bottom diffusion layer 17 can be more reliably avoided. Here, the distance between the contact portion CTsb of the source electrode 11 and the second sidewall SW2 on which the second sidewall diffusion layer 16b is provided may be smaller than the above-mentioned one distance. This allows the second sidewall diffusion layer 16b to be electrically connected to the source electrode 11 having the source potential (more generally, the potential of the first electrode 11) via a short electrical path. Therefore, an excessive potential rise of the second sidewall diffusion layer 16b can be more reliably avoided.

[0067] <Fourth embodiment> FIG. 31 is a plan view showing a layout of the semiconductor device 504 according to the fourth embodiment in a plan view. FIG. 32 is a partial plan view showing the configuration of the semiconductor device 504 in the field of view of the broken line region XXXII in FIG. 31. FIG. 33 is a partial cross-sectional view taken along the line XXXIII-XXXIII in FIG. 32 showing the configuration of the semiconductor device 504. FIG. 34 is a partial cross-sectional view taken along the line XXXIV-XXXIV in FIG. 32 showing the configuration of the semiconductor device 504. FIG. 35 is a partial cross-sectional view taken along the line XXXV-XXXV in FIG. 32 showing the configuration of the semiconductor device 504. FIG. 36 is a partial cross-sectional view taken along the line XXXVI-XXXVI in FIG. 32 showing the configuration of the semiconductor device 504. The dotted pattern in FIG. 31 shows an example of an electrode pattern on the upper surface SF1 of the semiconductor substrate SB. The dotted pattern in FIG. 32 shows the pattern of the gate embedded portion 18b and the internal wiring 18ew, which are part of the gate electrode 18 (typically, a pattern of a polysilicon layer). The configuration of the source electrode 11 of the semiconductor device 504 is substantially the same as that shown in Fig. 20 in the above-described second embodiment, and is therefore omitted from Fig. 32. Also, in Fig. 32, only the edges of the gate surface electrode 18pw of the gate electrode 18 are indicated by two-dot chain lines, and the interlayer insulating film 9 is omitted from the illustration, while the contact portion CTg and the contact portion CTsb penetrating it are indicated by rectangles with X marks.

[0068] As described in the third embodiment, the first trenches TR1 are arranged at an interval in the short-side direction on the first main surface SF1 of the semiconductor substrate SB. The semiconductor substrate SB has a third trench TR3 on the upper surface SF1 in the inactive region RI. The third trench TR3 has a third bottom BT3. The third trench TR3 is separated from the second trench TR2 so that a mesa portion MS of the semiconductor substrate SB is formed between the third trench TR3 and the second trench TR2. The third trench TR3 is separated from the second trench TR2 by a distance equal to or greater than the above-mentioned interval. The use of the mesa portion MS is not particularly limited, but in this embodiment, it is used as a place for arranging the internal wiring 18ew of the gate electrode 18.

[0069] In the present embodiment, the withstand voltage holding region RIv is disposed at the third bottom BT3 of the third trench TR3. Specifically, the p-type FLR 27 and the n-type channel stopper layer 28, which are also described in the second embodiment, are formed at the third bottom BT3.

[0070] The configuration other than the above is substantially the same as that of the first or second embodiment, and therefore the description thereof will not be repeated.

[0071] According to this embodiment, the third trench TR3 is spaced apart from the second trench TR2 by a distance equal to or greater than the distance between the first trenches TR1. This allows the mesa portion MS to have mechanical strength at least approximately equal to the mechanical strength of the mesa portion between the first trenches TR1. This prevents the mesa portion MS from being damaged due to thermal stress or the like.

[0072] <Embodiment 5> In the present embodiment 5, any one of the semiconductor devices 501 to 504 according to the above-mentioned embodiments 1 to 4 is applied to a power conversion device. This application is not limited to a specific power conversion device, but hereinafter, as the present embodiment 5, a case where any one of the semiconductor devices 501 to 504 according to the embodiments 1 to 4 is applied to a three-phase inverter will be described.

[0073] FIG. 37 is a block diagram showing a configuration of a power conversion system to which a power conversion device 1200 according to the fifth embodiment is applied.

[0074] The power conversion system shown in Fig. 37 is composed of a power supply 1100, a power conversion device 1200, and a load 1300. The power supply 1100 is a DC power supply, and supplies DC power to the power conversion device 1200. The power supply 1100 can be composed of various things, for example, a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 1100 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0075] The power conversion device 1200 is a three-phase inverter connected between the power source 1100 and the load 1300, converts DC power supplied from the power source 1100 into AC power, and supplies the AC power to the load 1300. As shown in Fig. 37, the power conversion device 1200 includes a main conversion circuit 1201 that converts input DC power into AC power and outputs it, a drive circuit 1202 that outputs drive signals that drive each switching element of the main conversion circuit 1201, and a control circuit 1203 that outputs a control signal for controlling the drive circuit 1202 to the drive circuit 1202.

[0076] Although the load 1300 is not limited to a specific application, in the fifth embodiment, the load 1300 is a three-phase motor driven by AC power supplied from the power conversion device 1200. The motor may be mounted in various electric devices, and is used for, for example, hybrid cars, electric cars, railroad cars, elevators, or air conditioners.

[0077] The power converter 1200 will be described in detail below. The main converter circuit 1201 includes switching elements and freewheel diodes (not shown). The switching elements switch to convert DC power supplied from the power source 1100 into AC power, and the AC power is supplied to the load 1300. There are various specific circuit configurations of the main converter circuit 1201, but the main converter circuit 1201 according to the fifth embodiment is a two-level three-phase full bridge circuit that can be configured with six switching elements and six freewheel diodes connected in reverse parallel to each switching element. Any of the semiconductor devices 501 to 504 according to the first to fourth embodiments is applied to each switching element of the main converter circuit 1201. The six switching elements are used as three pairs of switching elements. Two switching elements of each pair are connected in series to configure one upper and lower arm. Thus, the three pairs of switching elements configure three upper and lower arms for three phases (U phase, V phase, and W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 1201 are connected to a load 1300 .

[0078] The drive circuit 1202 generates drive signals for driving the switching elements of the main conversion circuit 1201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 1201. Specifically, in accordance with a control signal from a control circuit 1203 (described later), the drive circuit 1202 outputs to the control electrodes of each switching element a drive signal for turning the switching element on and a drive signal for turning the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) less than the threshold voltage of the switching element.

[0079] The control circuit 1203 controls the switching elements of the main conversion circuit 1201 so that a desired power is supplied to the load 1300. Specifically, the control circuit 1203 calculates the time (on time) that each switching element of the main conversion circuit 1201 should be in the on state based on the power to be supplied to the load 1300. For example, the main conversion circuit 1201 can be controlled by PWM control that modulates the on time of the switching elements according to the voltage to be output. Then, the control circuit 1203 outputs a control command (control signal) to the drive circuit 1202 so that an on signal is output to the switching element that should be in the on state at each time point, and an off signal is output to the switching element that should be in the off state. The drive circuit 1202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

[0080] In the power conversion device according to the fifth embodiment, by applying any one of the semiconductor devices 501 to 504 according to the first to fourth embodiments as a switching element of the main conversion circuit 1201, it is possible to improve reliability.

[0081] In the fifth embodiment, any of the semiconductor devices 501 to 504 according to the first to fourth embodiments is applied to a two-level three-phase inverter, but this application is not limited to a specific power conversion device, and may be applied to various power conversion devices. The power conversion device may be, for example, a multilevel power conversion device having three or more levels, instead of a two-level power conversion device. In addition, when power is supplied to a single-phase load, the power conversion device may be a single-phase inverter. In addition, when power is supplied to a DC load or the like, any of the semiconductor devices 501 to 504 according to the first to fourth embodiments may be applied to a DC / DC converter or an AC / DC converter.

[0082] In addition, the load to which the power conversion device supplies power is not limited to an electric motor, and may be, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system. In addition, the power conversion device can be used as a power conditioner for a solar power generation system or a power storage system.

[0083] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0084] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0085] (Appendix 1) A semiconductor device (501-504) having, in a plan view, an active region (RA), an inactive region (RI) including a breakdown voltage holding region (RIv) and a gate wiring region (RIg) in contact with the active region (RA), A semiconductor substrate (SB) having a first main surface (SF1) and a second main surface (SF2) opposite to the first main surface (SF1); A first electrode (11) provided on the first main surface (SF1) of the semiconductor substrate (SB); A second electrode (12) provided on the second main surface (SF2) of the semiconductor substrate (SB); an insulating film provided on the first main surface (SF1) of the semiconductor substrate (SB); a gate electrode (18) provided on the first main surface (SF1) via the insulating film; Equipped with The semiconductor substrate (SB) is A drift layer (3) of a first conductivity type provided in the active region (RA) and the inactive region (RI); a base region (4) of a second conductivity type different from the first conductivity type, the base region (4) being provided in the active region (RA) and disposed between the drift layer (3) and the first main surface (SF1); a first semiconductor region (5) of the first conductivity type provided in the active region (RA), disposed on the base region (4), and in contact with the first electrode (11); a plurality of first trenches (TR1) provided in the first main surface (SF1) in the active region (RA), each having a first sidewall (SW1) in contact with the first semiconductor region (5) and the base region (4) and a first bottom (BT1), each extending along a longitudinal direction and arranged in a lateral direction intersecting the longitudinal direction; a first bottom diffusion layer (14) of the second conductivity type provided in the first bottom (BT1) of each of the plurality of first trenches (TR1); a first sidewall diffusion layer (16a) of the second conductivity type provided on the first sidewall (SW1) of each of the plurality of first trenches (TR1) and in contact with the first bottom diffusion layer (14) and the base region (4); a second semiconductor region (1) of the first conductivity type or the second conductivity type provided at least in the active region (RA), disposed between the drift layer (3) and the second main surface (SF2), and in contact with the second electrode (12); a second trench (TR2) provided on the first main surface (SF1) in the inactive region (RI), contacting the active region (RA) and having a second sidewall (SW2) having a longitudinal portion (SW2a) along the longitudinal direction and a lateral portion (SW2b) along the lateral direction, and a second bottom (BT2); a second bottom diffusion layer (17) of the second conductivity type provided in at least a part of the second bottom (BT2) of the second trench (TR2); a second sidewall diffusion layer (16b) of the second conductivity type provided in at least one of the long portion (SW2a) and the short portion (SW2b) of the second sidewall (SW2) of the second trench (TR2) and in contact with the second bottom diffusion layer (17) and the base region (4); Including, The gate electrode (18) is a gate buried portion (18b) buried in each of the plurality of first trenches (TR1) of the semiconductor substrate (SB) via the insulating film; a gate wiring portion (18w) extending from the gate buried portion (18b) into the second trench (TR2); Including, A semiconductor device (501-504), wherein the second bottom diffusion layer (17) is arranged at least in a portion of the second bottom (BT2) of the second trench (TR2) where the gate wiring portion (18w) is arranged in the planar view.

[0086] (Appendix 2) The semiconductor device (501-504) according to appended claim 1, wherein the second sidewall diffusion layer (16b) is provided on both the long portion (SW2a) and the short portion (SW2b) of the second sidewall (SW2) of the second trench (TR2).

[0087] (Appendix 3) 3. The semiconductor device according to claim 1, wherein, in the plan view, the second trench (TR2) surrounds the active region (RA).

[0088] (Appendix 4) the first electrode (11) has a contact portion (CTs) that contacts the first main surface (SF1) of the semiconductor substrate (SB) outside the second trench (TR2) between the second trench (TR2) and a trench among the plurality of first trenches (TR1) that is closest to the second trench (TR2) in the short-side direction, the semiconductor substrate (SB) includes a contact region (6) of the second conductivity type in contact with the contact portion (CTs) and the second sidewall diffusion layer (16b); 4. The semiconductor device according to claim 1 ,

[0089] (Appendix 5) The semiconductor device (503) according to any one of appendices 1 to 4, wherein the first electrode (11) has a contact portion (CTsb) in contact with the second bottom diffusion layer (17) of the semiconductor substrate (SB).

[0090] (Appendix 6) the first trenches (TR1) are arranged at intervals in the short-side direction in the first main surface (SF1) of the semiconductor substrate (SB); In the plan view, a distance between the contact portion of the first electrode (11) and the second side wall (SW2) of the second trench (TR2) is smaller than the one distance. 6. The semiconductor device according to claim 5.

[0091] (Appendix 7) The semiconductor device according to any one of appendixes 1 to 6, wherein a ratio of an area of ​​the second sidewall diffusion layer (16b) to a total area of ​​the second sidewall (SW2) of the second trench (TR2) is greater than a ratio of an area of ​​the first sidewall diffusion layer (16a) to a total area of ​​the first sidewall (SW1) of the first trench (TR1).

[0092] (Appendix 8) The semiconductor device (501-503) according to any one of claims 1 to 7, wherein the plurality of first trenches (TR1) are directly connected to the second trench (TR2).

[0093] (Appendix 9) the first trenches (TR1) are arranged at intervals in the short-side direction in the first main surface (SF1) of the semiconductor substrate (SB); The semiconductor substrate (SB) includes a third trench (TR3) provided on the first main surface (SF1) in the inactive region (RI), separated from the second trench (TR2) such that a mesa portion (MS) of the semiconductor substrate (SB) is formed between the second trench (TR2) and the third trench (TR3), and having a third bottom (BT3); 9. The semiconductor device (504) according to any one of claims 1 to 8, wherein the third trench (TR3) is spaced from the second trench (TR2) by a distance equal to or greater than the one distance.

[0094] (Appendix 10) A method for manufacturing a semiconductor device (501 to 504) according to any one of claims 1 to 9, comprising the steps of: a) forming the first trench (TR1) and the second trench (TR2) in the semiconductor substrate (SB); b) forming the first sidewall diffusion layer (16a) and the second sidewall diffusion layer (16b) by implanting ions obliquely into the first sidewall (SW1) of the first trench (TR1) and the second sidewall (SW2) of the second trench (TR2); A method for manufacturing a semiconductor device (501 to 504) comprising the steps of:

[0095] (Appendix 11) The above b) is b1) performing ion implantation into the longitudinal portion (SW2a) of the second sidewall (SW2) of the second trench (TR2); b2) implanting ions into the short portion (SW2b) of the second sidewall (SW2) of the second trench (TR2); wherein b1) and b2) are carried out separately.

[0096] (Appendix 12) A main conversion circuit (1201) having a semiconductor device (501-504) according to any one of appendices 1 to 9, which converts and outputs input power; a drive circuit (1202) that outputs a drive signal for driving the semiconductor device (501 to 504) to the semiconductor device (501 to 504); A control circuit (1203) that outputs a control signal to the drive circuit (1202) for controlling the drive circuit (1202); A power conversion device (1200) comprising: [Explanation of symbols]

[0097] 7 gate insulating film, 11 first electrode, 12 second electrode, 14 first bottom diffusion layer, 16a first sidewall diffusion layer, 16b second sidewall diffusion layer, 17 second bottom diffusion layer, 18 gate electrode, 18b gate buried portion, 18w gate wiring portion, 20 field insulating film, 501 to 504 semiconductor device, 1201 power conversion device, RA active region, RIg gate wiring region, RI inactive region, RIv voltage retention region, SF1 upper surface (first main surface), SF2 lower surface (second main surface), SB semiconductor substrate, SW1 first sidewall, SW2 second sidewall, SW2a long portion, SW2b short portion, TR1 first trench, TR2 second trench.

Claims

1. A semiconductor device having, in a plan view, an active region, and an inactive region including a breakdown voltage holding region and a gate wiring region in contact with the active region, a semiconductor substrate having a first major surface and a second major surface opposite the first major surface; a first electrode provided on the first main surface of the semiconductor substrate; a second electrode provided on the second main surface of the semiconductor substrate; an insulating film provided on the first main surface of the semiconductor substrate; a gate electrode provided on the first main surface via the insulating film; Equipped with The semiconductor substrate is a drift layer of a first conductivity type provided in the active region and the inactive region; a base region of a second conductivity type different from the first conductivity type, the base region being provided in the active region and disposed between the drift layer and the first main surface; a first semiconductor region of the first conductivity type provided in the active region, disposed on the base region, and in contact with the first electrode; a plurality of first trenches provided in the first main surface in the active region, each of the first trenches having a first sidewall in contact with the first semiconductor region and the base region and a first bottom, the first trenches extending along a longitudinal direction and arranged in a lateral direction intersecting the longitudinal direction; a first bottom diffusion layer of the second conductivity type provided at the first bottom of each of the first trenches; a first sidewall diffusion layer of the second conductivity type provided on the first sidewall of each of the first trenches and in contact with the first bottom diffusion layer and the base region; a second semiconductor region of the first conductivity type or the second conductivity type provided in at least the active region, disposed between the drift layer and the second main surface, and in contact with the second electrode; a second trench provided on the first main surface in the inactive region, the second trench being in contact with the active region and having a second sidewall with a longitudinal portion along the longitudinal direction and a lateral portion along the lateral direction, and a second bottom; a second bottom diffusion layer of the second conductivity type provided in at least a portion of the second bottom of the second trench; a second sidewall diffusion layer of the second conductivity type provided on at least one of the long side portion and the short side portion of the second sidewall of the second trench and in contact with the second bottom diffusion layer and the base region; Including, The gate electrode is a gate embedded portion embedded in each of the first trenches of the semiconductor substrate via the insulating film; a gate wiring portion extending from the gate buried portion into the second trench; Including, the second bottom diffusion layer is disposed in at least a portion of the second bottom of the second trench where the gate wiring portion is disposed in the plan view.

2. 2 . The semiconductor device according to claim 1 , wherein the second sidewall diffusion layer is provided on both the long side portion and the short side portion of the second sidewall of the second trench.

3. The semiconductor device according to claim 1 , wherein the second trench surrounds the active region in the plan view.

4. the first electrode has a contact portion between the second trench and a trench among the plurality of first trenches that is closest to the second trench in the short direction, the contact portion being in contact with the first main surface of the semiconductor substrate outside the second trench; the semiconductor substrate includes a contact region of the second conductivity type in contact with the contact portion and the second sidewall diffusion layer; 3. The semiconductor device according to claim 1 or 2.

5. 3. The semiconductor device according to claim 1, wherein said first electrode has a contact portion in contact with said second bottom diffusion layer of said semiconductor substrate.

6. the first trenches are arranged at intervals in the short-side direction in the first main surface of the semiconductor substrate, In the plan view, a distance between the contact portion of the first electrode and the second sidewall of the second trench is smaller than the first distance. The semiconductor device according to claim 5 .

7. 3. The semiconductor device according to claim 1, wherein a ratio of an area of ​​the second sidewall diffusion layer to a total area of ​​the second sidewall of the second trench is greater than a ratio of an area of ​​the first sidewall diffusion layer to a total area of ​​the first sidewall of the first trench.

8. The semiconductor device according to claim 1 , wherein the first trenches are directly connected to the second trenches.

9. the first trenches are arranged at intervals in the short-side direction in the first main surface of the semiconductor substrate, the semiconductor substrate includes a third trench provided on the first major surface in the inactive region, spaced apart from the second trench such that a mesa portion of the semiconductor substrate is formed between the third trench and the second trench, the third trench having a third bottom; 3. The semiconductor device according to claim 1, wherein the third trench is spaced apart from the second trench by a distance equal to or greater than the first distance.

10. A method for manufacturing the semiconductor device according to claim 1 or 2, comprising the steps of: a) forming the first trench and the second trench in the semiconductor substrate; b) forming the first sidewall diffusion layer and the second sidewall diffusion layer by performing ion implantation from an oblique direction into the first sidewall of the first trench and the second sidewall of the second trench; A manufacturing method of a semiconductor device comprising:

11. The b) is b1) implanting ions into the longitudinal portion of the second sidewall of the second trench; b2) performing an ion implantation into the short portion of the second sidewall of the second trench; 11. The method for manufacturing a semiconductor device according to claim 10, further comprising the steps of: b1) and b2) being carried out separately.

12. A main conversion circuit having the semiconductor device according to claim 1 or 2, which converts and outputs input power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; a control circuit that outputs a control signal to the drive circuit to control the drive circuit; A power conversion device comprising:

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