Compound semiconductor chip

Abstract

To provide a compound semiconductor chip that can eliminate BPD generated in an edge termination region of the compound semiconductor chip or reduce its amount, thereby improving the long-term reliability of, for example, a power device.SOLUTION: By forming a porous layer 13 in an edge termination region 12 of an SiC chip 10, It is possible to eliminate BPD generated in the edge termination region 12 or reduce its amount. In particular, in a power device, it is possible to eliminate or suppress a phenomenon that when a large current is passed in its thickness direction, the BPD in this region 12 expands and causes stacking faults due to a thermal stress when the device is heated up by resistance heat by electric conduction and then returns to room temperature. In addition, by removing the porous layer 13 which is more fragile and easier to process than the bulk, it is also possible to realize a chip that is free of defects on the periphery and is smooth.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a compound semiconductor chip in which circuits are formed for power semiconductors and the like that control high voltages and large currents. [Background technology]

[0002] Single crystal SiC (silicon carbide) is a IV-IV group compound semiconductor with a covalent crystal composition ratio of Si:C = 1:1. Single crystal SiC has a short interatomic distance between Si and C of 0.189 nm and a high bond energy of about 4.5 eV, making it a material with high phonon energy and high thermal conductivity. As a semiconductor, the strong interatomic bond strength of Si-C realizes a wide band gap and high dielectric breakdown strength.

[0003] As a result, SiC has superior voltage resistance and heat resistance compared to Si (silicon), and can reduce device power loss by about one-tenth, making it garnering attention as a material for power devices. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5413861 DISCLOSURE OF THEINVENTION [Problem to be solved by the invention]

[0005] Such SiC chips are obtained by dicing a SiC wafer. Conventionally, the mainstream dicing method has been to use a diamond blade, in which diamond abrasive grains apply a shear force to a silicon wafer or the like, causing mechanical brittle fracture. However, compared to Si, SiC has a higher hardness and extremely low machinability, so it is not possible to increase the machining speed, resulting in low productivity. In addition, because this machining method is based on brittle fracture in which diamond abrasive grains are mechanically embedded, cracks and chipping are likely to occur on the machined surface, and dislocation strain that causes chip fracture remains in the surface layer.

[0006] In recent years, therefore, as another technology for solving the problems of low productivity and cracks and chipping, a laser dicing process for obtaining SiC chips has been developed, as described in, for example, Patent Document 1. This involves irradiating a SiC wafer with laser light in a gaseous environment, damaging the SiC at the irradiated portion, and cutting the wafer to obtain SiC chips (SiC devices).

[0007] Incidentally, power devices such as SiC that supply and control power to electrical equipment are composed of an active area where circuits are formed and current flows, and an edge termination area that is a voltage-resistance maintaining area that takes into account defects that occur during dicing. By reducing the proportion of the edge termination area in the entire chip, this device can increase the amount of current flowing per chip, i.e., processing power, for the same chip size, and can also reduce the chip size for the same amount of current flow, which increases the number of chips that can be obtained from one wafer and reduces costs.

[0008] In addition, SiC power devices can have poor long-term reliability in terms of withstand voltage, and the above-mentioned basal plane dislocations (BPDs) are known to be one of the causes. That is, because a large current flows through a power device in the thickness direction, the device is prone to become hot due to resistance heating caused by the current flow, and the thermal stress when the device returns to room temperature expands the BPDs in the edge termination region, causing stacking faults and increasing the resistance value, which may ultimately lead to chip destruction.

[0009] SiC chips obtained by dicing using the aforementioned diamond blade or the dicing method described in Patent Document 1 that utilizes damage caused by laser irradiation in a gaseous environment are both processing methods that involve brittle fracture, so mechanical damage such as cracks and residual dislocation strain such as BPDs are unavoidable on the peripheral side of the chip. The same was true for compound semiconductor chips (such as GaN chips) other than SiC chips.

[0010] Therefore, as a result of extensive research, the inventors discovered that by forming a porous layer in the edge termination region of a compound semiconductor chip, including a SiC chip, it is possible to eliminate BPDs from the edge termination region or significantly reduce the amount of BPDs generated. This makes it possible to eliminate or suppress the phenomenon in which, when a large current is passed through the thickness direction of a power device, the device heats up due to resistance heating caused by the current, and then, when the device returns to room temperature, the thermal stress causes the BPDs in the edge termination region to expand, causing stacking faults and ultimately leading to chip breakage. Thus, they completed the present invention.

[0011] The present invention has been made in consideration of these problems, and has an object to provide a compound semiconductor chip that can eliminate the occurrence of BPDs in the edge termination region of a compound semiconductor chip or reduce the amount of BPDs that occur, thereby eliminating or suppressing the phenomenon in which, for example, a power device heats up due to resistance heating caused by current flow, and then, due to thermal stress when the device returns to room temperature, the BPDs in the edge termination region expand and stacking faults occur, and that can also realize a compound semiconductor chip that is free of defects on the peripheral side by removing the porous layer, which is weaker and easier to process than the bulk. [Means for solving the problem]

[0012] The invention described in claim 1 is a compound semiconductor chip having an edge termination region arranged to surround an active region in which circuits are formed, characterized in that a porous layer is formed on the peripheral side of the edge termination region.

[0013] The compound semiconductor chip can be made of any material, including, for example, SiC (silicon carbide), GaN (gallium nitride), GaAs (gallium arsenide), InAs (indium arsenide), ZnSe (zinc selenide), and InGaAs (indium gallium arsenide), which belong to the II-VI, III-V, or IV-IV groups.

[0014] Compound semiconductor chips can be used for a variety of purposes, including power devices (power semiconductors), LEDs, photodiodes, field effect transistors, solar cells, and semiconductor lasers. The size of the compound semiconductor chip is not limited. The width of the edge termination region in plan view (hereinafter, may be simply referred to as the width) is arbitrary, and is, for example, 200 μm to 500 μm.

[0015] The term "porous layer" as used herein refers to the portion of the constituent elements that make up the substrate of a compound semiconductor chip in which the covalent bonds between elements have been broken and one of the elements has been removed, making the layer porous, without brittle fracture such as that caused by mechanical action such as diamond blade dicing or damage caused by a dry laser in a gaseous environment.

[0016] The thickness of the porous layer (porous portion) (thickness from the peripheral side surface of the edge termination region toward the inside of the chip; hereinafter, sometimes simply referred to as thickness) is arbitrary. For example, it may be 2 μm to 30 μm. If it is less than 2 μm, it may be difficult to set processing conditions to obtain a porous processed surface. If it exceeds 30 μm, the porous layer becomes too thick and the surface roughness increases, and there is a risk that cracks may occur during handling after cutting out the chip. The preferable thickness of the porous layer is 3 μm to 10 μm. Within this range, an even more preferable effect of significantly reducing the possibility of BPDs being present in the porous layer obtained by dicing can be obtained.

[0017] The compound semiconductor chip having the porous layer in the edge termination region can be obtained by any method, for example, by sublimating a part of the compound semiconductor wafer along a cutting line. That is, in a processing liquid environment, an energy beam is supplied onto the cutting line of the compound semiconductor wafer to break the covalent bonds of the constituent elements of the compound semiconductor near the cutting line, and one of the elements is sublimated to form a porous layer on the side of the diced chip. By adopting this method, it is possible to reliably obtain a compound semiconductor chip having a porous layer on the peripheral side of the edge termination region.

[0018] The type of compound semiconductor wafer is adapted to the material of the compound semiconductor chip to be obtained, such as SiC wafer, GaN wafer, GaAs wafer, InAs wafer, ZnSe wafer, InGaAs wafer, etc. Among these, for SiC wafers, wafers such as 3C-SiC, 2H-SiC, 4H-SiC, 6H-SiC, 15R-SiC, etc. can be used. However, in general, 4H-SiC wafers have high electron mobility, band gap, and dielectric breakdown field strength, small anisotropy of electrical conduction, relatively shallow donor and acceptor levels, and can produce high-quality, large-diameter wafers, as well as allowing the formation of good-quality epitaxial layers.

[0019] The size (diameter) of the compound semiconductor wafer is not limited and may be, for example, 2 to 8 inches. The compound semiconductor wafer may have any thickness. For example, in the case of a SiC wafer, the thickness may be 300 μm to 350 μm (thickness at the time of dicing: 50 μm to 200 μm).

[0020] The type of energy beam is not limited. For example, a processing method based on sublimation such as water guide laser light or fine electric discharge processing, which has been shown to be possible for processing SiC wafers, can be used. In addition, energy beam processing such as electron beam, ion beam, electrolyte flow, chemical liquid flow, etc. may be used. The type of the machining fluid is arbitrary, and examples thereof include water, machining oil, and the like.

[0021] As a dicing method for forming a porous layer on the peripheral side of the edge termination region of a compound semiconductor chip, for example, water guide laser (WGL) processing may be adopted, in which a laser beam is passed through a high-pressure water beam that moves along the cutting line, and the compound wafer is diced while the laser beam is totally reflected by the inner wall of the high-pressure water beam.

[0022] In water guide laser processing, for example, by passing a laser beam through a water flow of a high-pressure water beam (water jet) ejected from a jet nozzle with a diameter of several tens of microns, the laser beam is totally reflected by the inner wall of the high-pressure water beam and irradiated (collides) onto the cutting line of the SiC wafer. At this time, the laser beam is absorbed by the irradiated part of the SiC wafer and sublimated instantly, and immediately thereafter is cooled by the water flow of the high-pressure water beam. At the same time, debris generated from the wafer cutting part is washed and removed by the water pressure of the high-pressure water beam (water jet). As the type of laser, for example, a green laser such as an Nd:YAG laser or a semiconductor laser can be used. Among these, a green laser with a wavelength of 532 nm, which is not easily absorbed by water, is preferable.

[0023] In this way, by using water guide laser processing for dicing compound semiconductor wafers, the compound semiconductor wafers can have sharp cut grooves and almost no processing damage occurs in the cut parts of the wafer. Therefore, it is possible to reduce the proportion of the edge termination area provided on the chip periphery as a countermeasure against BPD during dicing, increase the amount of current per chip, and reduce the chip size, thereby increasing the number of chips obtained from one wafer.

[0024] The invention described in claim 2 is the compound semiconductor chip described in claim 1, characterized in that the porous layer is made porous by removing any of the constituent elements of the substrate of the compound semiconductor chip.

[0025] Here, "any of the elements of the substrate of the compound semiconductor chip is removed" means that one or more of the elements constituting the compound semiconductor are partially separated and desorbed by sublimation. Therefore, in this porous layer, the composition ratio of the elements constituting the compound semiconductor changes, and the elements on the substrate side whose bonds are broken when sublimated may combine with oxygen, etc. For example, in the compound semiconductor SiC, the constituent elements are Si (silicon) and C (carbon), but when irradiated with a water guide laser, the bonds between Si and C are broken, and Si is sublimated and separated, and the remaining porous layer has a low number of Si elements. When Si is sublimated, the C remaining on the substrate side becomes unstable and may combine with oxygen. As a result, the elemental composition of the porous layer differs from the elemental composition of the original substrate.

[0026] Furthermore, the invention described in claim 3 is the compound semiconductor chip described in claim 2, characterized in that the compound semiconductor chip is a SiC power semiconductor, which is a IV-IV group compound semiconductor of covalently bonded crystal having a composition ratio of Si:C=1:1, and the porous layer is made porous by removing Si or C from the constituent elements of this SiC.

[0027] The invention described in claim 4 is a compound semiconductor chip described in any one of claims 1 to 3, characterized in that the porous layer is formed over almost the entire edge termination region, and removal of the porous layer reduces the surface roughness of the peripheral side portion, resulting in a smooth surface.

[0028] The porous layer is more fragile and easier to process than the bulk of the compound semiconductor chip, so by removing this porous layer, it is possible to obtain a compound semiconductor chip with a defect-free (damage-free) outer periphery and a smooth surface with minimal surface roughness. Methods for removing the porous layer include polishing methods using fine abrasive grains or abrasive grains softer than SiC, and chemical removal methods include dry etching, wet etching, plasma etching, and the like, depending on the constituent elements of the porous layer. Effect of the Invention

[0029] According to the compound semiconductor chip invention described in claim 1, for example, when dicing a compound semiconductor wafer, by removing material by localized sublimation rather than brittle fracture in a liquid environment, the compound semiconductor chip can be separated without generating BPDs, thereby eliminating or reducing the amount of BPDs that cause harmful stacking faults on the peripheral portion of the edge termination region of the workpiece semiconductor chip after dicing. This makes it possible to eliminate or suppress the phenomenon in which, for example, a power device becomes hot due to resistance heating caused by current flow, and then, due to thermal stress when the device returns to room temperature, the BPDs in the edge termination region expand, causing stacking faults. In addition, in the compound semiconductor chip of the present invention, a porous layer having a thickness of, for example, the order of microns is formed on the surface of the peripheral portion. Since this porous layer is weaker and easier to process than the bulk, it is possible to realize a compound semiconductor chip with a defect-free peripheral portion and a smooth surface by removing the porous layer.

[0030] In particular, in the manufacture of compound semiconductor chips for high-performance power devices that must be able to withstand large currents, high voltages, high-speed switching, and large temperature difference environments, forming a porous layer can eliminate or reduce the amount of BPDs in the edge termination region, eliminating or suppressing the phenomenon in which, when a large current is passed through the thickness direction of a power device, the device heats up due to resistance heating caused by the current, and then the thermal stress generated when the device returns to room temperature causes the BPDs on the periphery of the edge termination region to expand, resulting in the generation of stacking faults. This improves the long-term reliability of the voltage resistance of the power device.

[0031] According to the present invention described in claim 2 or claim 3, for example, a compound semiconductor wafer (SiC in claim 3) is made porous by sublimating a portion of one of its constituent elements (Si or C in claim 3), and the sublimated element changes the element composition ratio in the surface layer from 1:1, and the element is oxidized during sublimation to form a porous layer with weaker covalent bonds than the original.

[0032] Furthermore, according to the invention described in claim 4, since the porous layer is more fragile and easier to process than the bulk of the compound semiconductor chip, a compound semiconductor chip having a defect-free (damage-free) peripheral portion can be obtained by subjecting the porous layer formed over almost the entire surface of the peripheral portion of the edge termination region to a method that does not involve brittle fracture, such as polishing. [Brief description of the drawings]

[0033] [Figure 1] FIG. 1 is a perspective view of a compound semiconductor chip according to a first embodiment of the present invention. [Diagram 2] FIG. 1 is a plan view of a compound semiconductor chip according to a first embodiment of the present invention. [Diagram 3] 2 is a partially enlarged front view of a porous layer of the compound semiconductor chip according to the first embodiment of the present invention. FIG. [Figure 4] 3 is an electron microscope photograph of a porous layer of the compound semiconductor chip according to Example 1 of the present invention. [Diagram 5] 1 is an overall perspective view of a dicing device for a compound semiconductor wafer for compound semiconductor chips according to a first embodiment of the present invention. [Figure 6] 1 is a perspective view showing a state in which a porous layer has been removed to make a peripheral side portion defect-free in the compound semiconductor chip according to Example 1 of the present invention. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Hereinafter, an embodiment of the present invention will be described in detail, taking as an example a case where a SiC chip for a power device is used as the compound semiconductor chip. EXAMPLES

[0035] In FIG. 1, 10 is a SiC chip (compound semiconductor chip) according to Example 1 of the present invention. This SiC chip 10 is a compound semiconductor chip in which a porous layer 13 is formed on the surface of the peripheral side of an edge termination region 12 that is arranged to surround an active region 11 in which a circuit is formed.

[0036] This will be explained in detail below. As shown in FIGS. 1 and 2, the SiC chip 10 is a rectangular parallelepiped with a length of 5 mm, a width of 5 mm and a thickness of 150 μm, of which the edge termination region 12 having a rectangular frame shape in plan view has a width of 300 μm. The porous layer 13 is in a state where a part of Si or C, which is one of the constituent elements of SiC, has been sublimated and separated. Here, a part of Si has been sublimated. The thickness of the porous layer 13 depends on the processing conditions during dicing, but is desirably 30 μm or less, and preferably 10 μm or less.

[0037] The surface state of the porous layer 13 is a horizontally elongated shape that coincides with the scanning direction during dicing, as shown in the electron microscope photographs of Figures 3 and 4. This is the result of the processing point, the wafer table or the processing head, moving along the cutting line on the wafer side, causing the wafer to gradually sublimate and divide, and some elements to be released. At this time, the thickness of the porous layer 13 is 5 μm to 7 μm.

[0038] Next, a method and an apparatus for dicing a SiC wafer (compound semiconductor wafer) to obtain SiC chips 10 will be described with reference to FIG. As shown in FIG. 5, a dicing device 15 for a SiC wafer W (hereinafter, sometimes simply referred to as a dicing device) performs dicing processing on a 4H-SiC wafer W having a diameter of 150 mm and a thickness of 350 μm using a water-guided laser (WGL), which is a processing mechanism that can sublimate and remove material rather than causing brittle fracture.

[0039] The dicing apparatus 15 includes a laser light oscillator (heat source supply unit) 16 that generates multiple laser beams (heat sources) R, a high-pressure water generator 18 that generates a high-pressure water beam 17 that is irradiated onto a cutting line arranged on the surface of the SiC wafer W, an XY table (moving means) 19 on which the SiC wafer W is placed and which moves it within a horizontal plane, a focusing lens L that focuses the laser light R and passes it through the high-pressure water beam 17, a water chamber 20 that introduces the laser light R from the laser light oscillator 16 and the high-pressure water from the high-pressure water generator 18 into the chamber and passes the laser light R through the high-pressure water beam 17, and a control unit 21 that controls these electrical devices.

[0040] These components will now be described in detail. The laser light oscillator 16 is a picosecond pulse laser oscillator of the Nd:YAG laser type that oscillates laser light (green laser) R with a wavelength of 532 nm.

[0041] The high-pressure water generating unit 18 is a high-pressure pump for generating the high-pressure water beam 17 jetted from the jet nozzle at 150 bar. The XY table 19 is a moving table on which the SiC wafer W is positioned on its upper surface, and which is moved in the X and Y directions by driving an X motor 23 and a Y motor 24.

[0042] The water chamber 20 is a disc-shaped casing into which the laser light R from the laser light oscillator 16 and the high-pressure water from the high-pressure water generator 18 are respectively introduced, and into which the high-pressure water beam 17 through which the laser light R has passed is ejected from the jet nozzle 22.

[0043] A transparent optical window 25 for guiding laser light R into the chamber is provided in the center of the upper plate of water chamber 20. Meanwhile, a jet nozzle 22 having a nozzle diameter of 80 μm is provided in the center of the lower plate of water chamber 20. In addition, a plurality of water inlets 26 for allowing high-pressure water from high-pressure water generator 18 to flow into the chamber are provided on the peripheral plate of water chamber 20. The control unit 21 has a built-in central processing unit (CPU) and controls the laser light oscillator 16, the high-pressure water generator 18, the X motor 23, and the Y motor 24.

[0044] Next, a method for dicing a SiC wafer W using the dicing apparatus 15 according to the first embodiment of the present invention will be described with reference to FIG. First, high-pressure water generated by the high-pressure water generator 18 is introduced into the chamber from the peripheral side surface of the water chamber 20 through each water inlet 26. Meanwhile, the laser light oscillator 16 emits a laser beam having a repetition frequency of 10 kHz, an output of 35 W, a pulse energy of 3.5 mJ, a pulse width of 200 nanoseconds, and a peak intensity of 0.51 GW / cm. 2 Laser light R having a wavelength of 532 nm oscillated at 1000 .mu.m is focused by a focusing lens L of the optical system, and then introduced into the water chamber 20 from the top surface thereof through an optical window 25.

[0045] At this time, the optical axis of the laser light R coincides with the nozzle axis of the jet nozzle 22. Therefore, in the water chamber 20, the laser light R passes through the water flow of the high-pressure water beam (water jet) 17 jetted from the jet nozzle 22 at 150 bar, and the laser light R is totally reflected by the inner wall of the water flow of the high-pressure water beam 17, and is irradiated perpendicularly onto the cutting line of the SiC wafer W disposed directly below the jet nozzle 22.

[0046] The portion of the SiC wafer W irradiated with the laser light R is sublimated by absorbing the laser light R, and immediately thereafter, this sublimated portion is cooled by the water flow of the high-pressure water beam 17. At the same time, debris (residue) remaining in the cut portion of the SiC wafer W is removed (cleaned) by the water pressure of the high-pressure water beam 17. Thereafter, the SiC wafer W is diced while appropriately moving the XY table 19 by driving the X motor 23 and the Y motor 24 based on instructions from the control unit 21 so that the high-pressure water beam 17 scans the cutting line on the surface of the SiC wafer W a predetermined number of times at a feed speed of 16.7 mm / sec.

[0047] Thus, here, when dicing the SiC wafer W, water guide laser processing is adopted, in which laser light R is passed through a high-pressure water flow and the laser light R is totally reflected by the inner wall of the water flow while cutting the SiC wafer W. This enables dicing with a vertical wafer cut surface, and also prevents cracks, chipping, and BPD (basal plane dislocation) at the wafer cut portion caused by brittle fracture or damage to the wafer cut portion during dicing by diamond blade processing or dry laser processing. In particular, since BPDs become killer defects that destroy devices when they expand into stacking faults due to repeated thermal stress at high and room temperatures accompanying device operation and shutdown, it is extremely important to prevent their occurrence.

[0048] The results of elemental analysis of the porous processed surface of the SiC wafer W processed using the dicing device 15 are shown in Table 1, which is a comparison table of the elemental analysis results of the diced surface of the present invention and the bulk. [Table 1]

[0049] For comparison, the analysis results of the SiC material part are also shown in Table 1. For elemental analysis, a laser elemental analysis head EA-300 manufactured by Keyence Corporation was used. The ratio of the numbers of elements in the material for comparison is Si:C=56:44, which is roughly close to 1:1 although there is some error. In contrast, the ratio of the number of elements in the porous layer 13 obtained by processing with the water guide laser type dicing device 15 is Si:C:O=19:53:28, with Si greatly reduced and O (oxygen) detected. This shows that the strong covalent bond between Si and C in the wafer state before processing is broken by the processing with the dicing device 15, and the Si is sublimated and removed. A high energy state is required for Si to sublimate, but since the dicing process in this case is performed in an air atmosphere, it is understood that the surface elements are oxidized and present in the porous layer 13.

[0050] As described above, according to the present invention, it is possible to reduce the proportion of the termination region 12 provided as a measure against BPD during dicing to the entire chip, and increase the amount of current flow per chip. Furthermore, it is possible to increase the yield of SiC chips 10 obtained from one SiC wafer W.

[0051] In addition, the porous layer 13 is more fragile and easier to process than the bulk of the SiC chip 10. Therefore, in the SiC chip 10 of Example 2, if the porous layer 13 formed over substantially the entire peripheral portion of the edge termination region 12 is removed by, for example, polishing with fine abrasive grains or abrasive grains softer than SiC, or by chemical removal using various etching methods, a SiC chip 10A with a defect-free (damage-free) peripheral portion as shown in FIG. [Industrial Applicability]

[0052] The present invention is useful as a compound semiconductor chip technology. [Explanation of symbols]

[0053] 10,10A SiC chip (compound semiconductor chip) 11 Active Area 12 Edge Termination Area 13 Porous layer 14 Sublimation traces (pores)

Claims

1. In a compound semiconductor chip having an edge termination region surrounding an active region in which a circuit is formed, A compound semiconductor chip, comprising: a porous layer formed on a peripheral side portion of said edge termination region.

2. 2. The compound semiconductor chip according to claim 1, wherein the porous layer is made porous by removing any one of the constituent elements of the substrate of the compound semiconductor chip.

3. The compound semiconductor chip is a SiC power semiconductor of a IV-IV group compound semiconductor having a covalent bond crystal with a composition ratio of Si:C=1:1, 3. The compound semiconductor chip according to claim 2, wherein the porous layer is made porous by removing Si or C from among the constituent elements of the SiC.

4. The compound semiconductor chip according to any one of claims 1 to 3, characterized in that the porous layer is formed over the entire surface layer of the peripheral portion of the edge termination region, and removal of the porous layer renders the peripheral portion of the edge termination region defect-free.

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