Semiconductor device

Abstract

To provide a semiconductor device in which reverse recovery loss and trade-off of forward voltage in a diode part are improved.SOLUTION: A semiconductor device includes: a transistor part 70; a diode part 80; a plurality of trench parts 30 and 40; an N- type drift region 18; a P- type base region 14 provided over the drift region in the transistor part; an N+ type emitter region 12 and a P+ type contact region provided on a front surface 21 of a semiconductor substrate; a P-- type anode region 84 provided over the drift region in the diode part; a mesa part 63 in the semiconductor substrate 10; an interlayer insulating film 38 and a front surface electrode 52 provided over the semiconductor substrate; a trench contact part 17 connecting the front surface electrode and a mesa part 62 in the transistor part; and a front surface contact part 87 connecting the front surface electrode and the mesa part 63 in the diode part and having a lower end disposed above a lower end of the trench contact part.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In a semiconductor device having a transistor portion and a diode portion, a structure in which an electrode and a semiconductor substrate are connected by a trench-shaped contact is known (see, for example, Patent Documents 1 and 2). Patent Document 1 WO2018 / 056233 Patent Document 2: JP 2021-150483 A Summary of the Invention [Problem to be solved by the invention]

[0003] It is desirable to improve the tradeoff between reverse recovery loss and forward voltage of the diode section. [Means for solving the problem]

[0004] In a first aspect of the present invention, there is provided a semiconductor device comprising: a transistor portion, a diode portion, a plurality of trench portions provided on a front surface of a semiconductor substrate, a first conductivity type drift region provided in the semiconductor substrate, a second conductivity type base region provided above the drift region in the transistor portion, an emitter region of the first conductivity type having a doping concentration higher than that of the drift region and provided on the front surface of the semiconductor substrate in the transistor portion, a contact region of the second conductivity type having a doping concentration higher than that of the base region, an anode region of the second conductivity type provided above the drift region in the diode portion, a mesa portion of the semiconductor substrate provided between the plurality of trench portions, an interlayer insulating film provided above the semiconductor substrate, a front surface electrode provided above the semiconductor substrate, and a trench contact portion in the transistor portion that connects the front surface electrode and the mesa portion, and a front surface contact portion in the diode portion that connects the front surface electrode and the mesa portion.

[0005] The width of the front surface contact portion in the trench arrangement direction may be larger than the width of the trench contact portion in the trench arrangement direction.

[0006] The front electrode may include an emitter electrode.

[0007] The front surface electrode may include a contact plug portion provided in a contact hole in the interlayer insulating film and connecting the emitter electrode and the semiconductor substrate.

[0008] The anode region may have a doping concentration lower than a doping concentration of the base region.

[0009] The doping concentration of the anode region may be the same as the doping concentration of the base region.

[0010] The doping concentration of the anode region may be higher than the doping concentration of the base region.

[0011] The diode portion may have a lifetime control region provided on the front surface side of the semiconductor substrate relative to a center of the semiconductor substrate in a depth direction of the semiconductor substrate.

[0012] The semiconductor device may further include a first plug region of a second conductivity type having a higher doping concentration than the contact region and provided at a lower end of the trench contact portion, and a second plug region of the second conductivity type having a higher doping concentration than the contact region and provided in contact with the lower end of the front surface contact portion.

[0013] The first plug regions may be provided discretely in the trench extension direction.

[0014] The second plug region may be provided extending in a trench extension direction.

[0015] The transistor portion may include an accumulation region of a first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region.

[0016] The semiconductor device may further include a boundary region provided between the transistor portion and the diode portion, and when viewed from above, an area ratio of the emitter region in a mesa portion of the boundary region is smaller than an area ratio of the emitter region in a mesa portion of the transistor portion, and the front surface contact portion may be provided in the mesa portion of the boundary region. The width of the boundary region in the trench arrangement direction may be 20 μm or more and 250 μm or less.

[0017] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a plan view showing an example of a semiconductor device 100. [Diagram 2] FIG. 2 is an enlarged view of an area D in FIG. [Figure 3A] FIG. 3 is a diagram showing an example of an ee cross section in FIG. 2. [Figure 3B] 3B is an enlarged view of the vicinity of the second mesa portion 62 and the third mesa portion 63 shown in FIG. 3A. [Figure 4A] FIG. 3 is a diagram showing an example of the ff cross section in FIG. [Figure 4B] 4B is an enlarged view of the vicinity of the second mesa portion 62 and the third mesa portion 63 shown in FIG. 4A. [Diagram 5] 13 is a diagram showing an example of a P-type doping concentration distribution of an anode region 84 and a second plug region 222 in the vicinity of the front surface of a third mesa portion 63. FIG. [Figure 6] FIG. 3 is a plan view showing another example of FIG. 2. [Figure 7A] FIG. 7 is a diagram showing an example of the gg cross section in FIG. [Figure 7B] FIG. 7 is a diagram showing an example of the hh cross section in FIG. [Figure 8] FIG. 3 is a plan view showing another example of FIG. 2. [Figure 9A] FIG. 9 is a diagram showing an example of the jj cross section in FIG. [Figure 9B] FIG. 9 is a diagram showing an example of the kk cross section in FIG. 8. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0020] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the front surface and the other surface is referred to as the back surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0021] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0022] In this specification, the orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Also, the axis perpendicular to the front and back surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Also, in this specification, the direction parallel to the front and back surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0023] The region from the center of the semiconductor substrate in the depth direction to the front surface of the semiconductor substrate may be referred to as the front surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the back surface of the semiconductor substrate may be referred to as the back surface side.

[0024] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0025] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0026] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any position is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0027] The donor has the function of supplying electrons to the semiconductor. The acceptor has the function of receiving electrons from the semiconductor. The donor and the acceptor are not limited to the impurity itself. For example, a VOH defect in which a vacancy (V), oxygen (O) and hydrogen (H) are bonded in a semiconductor functions as a donor that supplies electrons. A hydrogen donor may be a donor in which at least a vacancy (V) and hydrogen (H) are bonded. Alternatively, an interstitial Si-H in which an interstitial silicon (Si-i) and hydrogen are bonded in a silicon semiconductor also functions as a donor that supplies electrons. In this specification, the VOH defect or the interstitial Si-H may be referred to as a hydrogen donor.

[0028] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donor is a donor due to a dopant that is contained almost uniformly in the ingot when the ingot that is the base of the semiconductor substrate is manufactured. The bulk donor in this example is an element other than hydrogen. The dopant of the bulk donor is, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but is not limited thereto. The bulk donor in this example is phosphorus. The bulk donor is also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), and the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 A higher oxygen concentration tends to generate hydrogen donors more easily. The bulk donor concentration may be the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be between 90% and 100% of the chemical concentration. A non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 10 / cm 3 That's it, 5 x 10 12 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 11 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 12 / cm 3 The concentrations in the present invention may be values ​​at room temperature. For example, the values ​​at room temperature may be values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0029] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0030] In this specification, the chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may be the net doping concentration. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In addition, in an N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may be the acceptor concentration. In this specification, the doping concentration in an N-type region may be referred to as the donor concentration, and the doping concentration in a P-type region may be referred to as the acceptor concentration.

[0031] When the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. When the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atom count notation may be omitted.

[0032] The carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor. In the range where the current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to a disorder in the crystal structure caused by lattice defects, etc.

[0033] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0034] Fig. 1 is a plan view showing an example of a semiconductor device 100. Fig. 1 shows the positions of each component projected onto the front surface of a semiconductor substrate 10. Fig. 1 shows only some components of the semiconductor device 100, and other components are omitted.

[0035] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end sides 162 in a top view. When simply referred to as a top view in this specification, it means a view from the front surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of end sides 162 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to either of the end sides 162. The Z-axis is perpendicular to the front surface of the semiconductor substrate 10.

[0036] The semiconductor substrate 10 is provided with an active portion 160. The active portion 160 is a region through which a main current flows in the depth direction between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted in FIG. 1 . The active portion 160 may refer to a region overlapped by the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0037] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor), and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined first direction (X-axis direction in this example) on the front surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT). A boundary region is arranged between the transistor section 70 and the diode section 80 in the X-axis direction, but is omitted in FIG. 1.

[0038] In FIG. 1, the region in which the transistor section 70 is disposed is marked with the symbol "I", and the region in which the diode section 80 is disposed is marked with the symbol "F". In this specification, a direction different from the first direction in a top view may be referred to as a second direction (Y-axis direction in FIG. 1). The second direction may be perpendicular to the first direction. The transistor section 70 and the diode section 80 may each have a longitudinal direction in the second direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The second direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section and the longitudinal direction of the mesa section, which will be described later.

[0039] The diode section 80 has an N+ type cathode region in a region that contacts the back surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the back surface of the semiconductor substrate 10. In this specification, an extension region 81 that extends the diode section 80 in the Y-axis direction to a gate wiring described later may also be included in the diode section 80. A collector region is provided on the back surface of the extension region 81. The diode section 80 has a P- type anode region on the front surface side of the semiconductor substrate 10.

[0040] The transistor section 70 has a P+ type collector region in a region in contact with the back surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure, which has an N-type emitter region, a P+ type contact region, a P- type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the front surface side of the semiconductor substrate 10.

[0041] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an end edge 162. The vicinity of the end edge 162 refers to the region between the end edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0042] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.

[0043] The gate wiring in this example has a peripheral gate wiring 130. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region described later, and is formed from the front surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0044] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0045] The semiconductor device 100 of this example further includes an active side gate wiring 131. The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variation in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0046] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to a gate trench portion of the active section 160. The peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0047] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 is provided extending in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 sandwiching the active portion 160, so as to cross the active portion 160 at approximately the center in the Y-axis direction. When the active portion 160 is divided by the active side gate wiring 131, the transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction in each divided region.

[0048] The semiconductor device 100 may include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of a transistor section provided in the active section 160.

[0049] In the present example, semiconductor device 100 includes an edge termination structure 90 between active section 160 and edge 162 when viewed from above. In the present example, edge termination structure 90 is disposed between peripheral gate wiring 130 and edge 162. Edge termination structure 90 relieves electric field concentration on the front surface side of semiconductor substrate 10. Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf that are provided in an annular shape surrounding active section 160.

[0050] FIG. 2 is an enlarged view of region D in FIG. 1. Region D includes the transistor section 70, the diode section 80, and the active side gate wiring 131. Although omitted in FIG. 1, a boundary region 200 is disposed between the transistor section 70 and the diode section 80 in the X-axis direction. The boundary region 200 is a region having a P+ type collector region in a region in contact with the rear surface of the semiconductor substrate 10. The boundary region 200 has a smaller area ratio of the emitter region 12 than the transistor section 70. The boundary region 200 of this example does not have an emitter region on the front surface of the semiconductor substrate 10. The width of the boundary region 200 of this example in the X-axis direction is 20 μm or more and 250 μm or less.

[0051] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, a contact region 15, and an anode region 84 provided inside the front surface side of a semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active side gate wiring 131 provided above the front surface of the semiconductor substrate 10. The emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.

[0052] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the front surface of the semiconductor substrate 10, but is omitted in Fig. 2. In this example, the interlayer insulating film is provided with contact holes 54 penetrating the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with oblique lines.

[0053] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, the contact region 15, and the anode region 84. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the front surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0054] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0055] The emitter electrode 52 is formed of a material containing a metal. The emitter electrode 52 is an example of a front surface electrode. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a part of the emitter electrode 52 is formed of aluminum or an alloy mainly composed of aluminum, such as a metal alloy such as Al-Si or Al-Si-Cu. The emitter electrode 52 may have a barrier metal. Furthermore, the front surface electrode may have a contact plug portion in the contact hole, the contact plug portion having a barrier metal formed of titanium, a titanium compound, or the like on the side surface of the contact hole, and a plug formed by embedding tungsten or the like so as to contact the barrier metal and the emitter electrode 52. The contact plug portion connects the emitter electrode 52 to the semiconductor substrate 10.

[0056] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width to an area where it does not overlap with the active side gate wiring 131. The well region 11 in this example is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is P- type, and the well region 11 is P+ type.

[0057] Each of the transistor section 70, the diode section 80, and the boundary region 200 has a plurality of trench sections arranged in a first direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the first direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the first direction. In the diode section 80 of this example, no gate trench section 40 is provided. In the boundary region 200 of this example, a plurality of dummy trench sections 30 are provided along the first direction. In the boundary region 200 of this example, no gate trench section 40 is provided.

[0058] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the second direction) extending along a second direction perpendicular to the first direction, and a tip portion 41 connecting the two straight line portions 39. The second direction in FIG. 2 is the Y-axis direction.

[0059] At least a part of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0060] In the transistor section 70, the dummy trench section 30 is provided between the respective straight line portions 39 of the gate trench section 40. One dummy trench section 30 may be provided between the respective straight line portions 39, or a plurality of dummy trench sections 30 may be provided. In the transistor section 70 of this example, two dummy trench sections 30 are provided between the respective straight line portions 39. The dummy trench section 30 may have a straight line shape extending in the second direction, and may have a straight line portion 29 and a tip portion 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 has only the dummy trench section 30 having the tip portion 31, but may have both the straight line dummy trench section 30 not having the tip portion 31 and the dummy trench section 30 having the tip portion 31.

[0061] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends in the Y-axis direction of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 when viewed from above. That is, at the ends in the Y-axis direction of each trench portion, the bottoms in the depth direction of each trench portion are covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottoms of each trench portion.

[0062] A mesa portion 60 is provided between adjacent trench portions in the first direction. The mesa portion 60 refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. The front surface of the mesa portion 60 in this example is the front surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. The mesa portion 60 in this example is provided on the front surface of the semiconductor substrate 10, extending in the second direction (Y-axis direction) along the trench. The mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200 may have different structures. When simply referred to as a mesa portion 60 in this specification, it refers to each of the mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200.

[0063] A base region 14 is provided in the mesa portion 60 of the transistor portion 70, and an anode region 84 is provided in the mesa portion 60 of the diode portion 80 and the boundary region 200. In FIG. 2, the base region 14 is shown disposed at one end of each mesa portion in the second direction, but a base region 14 is also disposed at the other end of each mesa portion. At least one of an emitter region 12 of a first conductivity type and a contact region 15 of a second conductivity type may be provided in the mesa portion of the transistor portion 70 in a region sandwiched between the base regions 14 in a top view. In this example, the emitter region 12 is an N+ type, and the contact region 15 is a P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction.

[0064] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0065] Each of the contact regions 15 and the emitter regions 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the second direction (Y-axis direction) of the trench portion.

[0066] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the second direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0067] In this example, the mesa portion 60 of the diode portion 80 is not provided with an emitter region 12. The area ratio of the emitter region 12 in the mesa portion 60 of the boundary region 200 is smaller than the area ratio of the emitter region 12 in the mesa portion 60 of the transistor portion 70. In this example, the mesa portion 60 of the boundary region 200 is not provided with an emitter region 12.

[0068] An anode region 84 may be provided on the front surface of the mesa portion 60 of the diode portion 80 and the boundary region 200. The doping concentration of the anode region 84 may be the same as or different from the doping concentration of the base region 14. In this example, the doping concentration of the anode region 84 is lower than the doping concentration of the base region 14. In this example, the base region 14 is P-type, and the anode region 84 is P-- type.

[0069] The mesa portion 60 of the boundary region 200 in this example may have the same anode region 84 as the mesa portion 60 of the diode portion 80. The mesa portion 60 of the boundary region 200 may have a structure different from that of the anode region 84, and may have a P-type impurity region with a lower doping concentration than the base region 14. By providing the mesa portion 60 of the boundary region 200 with a P-type impurity region with a lower doping concentration, injection of holes from the mesa portion 60 of the boundary region 200 is suppressed, and reverse recovery loss can be reduced.

[0070] In addition, an N-type impurity region having a doping concentration similar to or lower than that of the emitter region 12 may be provided in the mesa portion 60 of the boundary region 200 instead of the anode region 84. In this case, however, the gate trench portion 40 is not provided in the boundary region 200. Also, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. In the mesa portion 60 of the boundary region 200, since the N-type impurity region is not in contact with the gate trench portion 40, the N-type impurity region does not form an inversion layer and does not become conductive. This suppresses the injection of holes from the mesa portion 60 of the boundary region 200, and reduces reverse recovery loss.

[0071] Furthermore, the boundary region 200 and the mesa portion 60 of the diode portion 80 may be provided with a base region 14. Furthermore, a contact region 15 may be provided on the front surface side of the base region 14, and the contact region 15 may be sandwiched between the base regions 14 in the Y-axis direction. That is, the area ratio of the contact region 15 in the mesa portion 60 of the boundary region 200 may be larger than the area ratio of the contact region 15 in the mesa portion 60 of the diode portion 80. In this case, holes in the semiconductor substrate 10 are easily extracted to the emitter electrode 52 via the mesa portion 60 of the boundary region 200.

[0072] A contact hole 54 is provided above each mesa portion 60. The contact hole 54 is disposed in a region sandwiched between the base region 14 or the anode region. In this example, the contact hole 54 is provided above each of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in the base region 14 or the well region 11. The contact hole 54 may be disposed in the center of the mesa portion 60 in the first direction (X-axis direction).

[0073] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the back surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the back surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0074] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0075] Fig. 3A is a diagram showing an example of an ee cross section in Fig. 2. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0076] The interlayer insulating film 38 is provided on the front surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described in FIG. 2.

[0077] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is an example of a front surface electrode. The emitter electrode 52 may contact the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. Alternatively, a contact plug portion may be provided in the contact hole 54 to connect the emitter electrode 52 and the semiconductor substrate 10. The contact plug portion may have a plug made of tungsten or the like, and a barrier metal containing titanium provided in a portion in contact with the semiconductor substrate 10. The barrier metal may have a titanium nitride layer, or may have a laminated structure of a titanium nitride layer and a titanium layer.

[0078] Collector electrode 24 is provided on rear surface 23 of semiconductor substrate 10. Emitter electrode 52 and collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting emitter electrode 52 and collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0079] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in each of the transistor portion 70, the diode portion 80, and the boundary region 200.

[0080] In this example, the multiple mesa portions 60 include a second mesa portion 62, a third mesa portion 63, and a fourth mesa portion 64. The second mesa portion 62 is provided in the transistor portion 70, the third mesa portion 63 is provided in the diode portion 80, and the fourth mesa portion 64 is provided in the boundary region 200.

[0081] In the second mesa portion 62 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the front surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the second mesa portion 62. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0082] The emitter region 12 is exposed on the front surface 21 of the semiconductor substrate 10, and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0083] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the second mesa portion 62.

[0084] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. In other words, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire back surface of the base region 14 in the second mesa portion 62.

[0085] An anode region 84 is provided in the third mesa portion 63 of the diode portion 80 in contact with the front surface 21 of the semiconductor substrate 10. The doping concentration of the anode region 84 may be the same as the doping concentration of the base region 14, or may be lower than the doping concentration of the base region 14. In this example, the doping concentration of the anode region 84 is lower than the doping concentration of the base region 14. In this example, the base region 14 is P-type, and the anode region 84 is P-- type. A drift region 18 is provided below the anode region 84. An accumulation region 16 may be provided below the anode region 84.

[0086] In the present example, a P-- type anode region 84 is provided in the fourth mesa portion 64 of the boundary region 200 in contact with the front surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the anode region 84. An accumulation region 16 may be provided below the anode region 84 in the fourth mesa portion 64.

[0087] In each of the transistor section 70, the diode section 80, and the boundary region 200, an N+ type buffer region 20 may be provided under the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may have a concentration peak having a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. The doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0088] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be provided at the same depth position as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0089] In the transistor portion 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0090] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. The elements serving as the donor and acceptor of each region are not limited to the above-mentioned examples.

[0091] In the boundary region 200, a P+ type collector region 22 is provided below the buffer region 20. That is, the boundary region 200 may be regarded as a part of the transistor section 70. The collector region 22 in the boundary region 200 may have the same doping concentration as the boundary region 200 in the transistor section 70. The boundary position in the X-axis direction between the cathode region 82 and the collector region 22 may be regarded as the boundary position in the X-axis direction between the diode section 80 and the boundary region 200.

[0092] In another example, in the boundary region 200, a part or the whole of the collector region 22 may be replaced with the cathode region 82. When the cathode region 82 is provided on the rear surface of the boundary region 200, the region sandwiched between the anode regions 84 in which the contact regions 15 and the anode regions 84 are alternately arranged may be regarded as the diode section 80, and the region sandwiched between the anode regions 84 in which the contact regions 15 are arranged in the entire region may be regarded as the boundary region 200. When the cathode region 82 is provided on the rear surface of the boundary region 200, the boundary region 200 may be regarded as part of the diode section 80.

[0093] Of the two trenches in contact with the emitter region 12 arranged closest to the diode section 80 in the X-axis direction, the trench on the diode section 80 side may be the dummy trench section 30. In this case, the dummy trench section 30 may be the boundary position in the X-axis direction between the transistor section 70 and the boundary region 200 (or the diode section 80). The center position in the X-axis direction of the dummy trench section 30 may be the boundary position in the X-axis direction between the transistor section 70 and the boundary region 200 (or the diode section 80).

[0094] An emitter region 12 may be provided in the boundary region 200. In that case, however, a gate trench portion 40 is not provided in the boundary region 200. Also, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. That is, no transistor operation occurs in the boundary region 200. A gate trench portion 40 may be provided in the boundary region 200. In that case, however, no emitter region 12 is provided in the boundary region 200. That is, no transistor operation occurs in the boundary region 200.

[0095] The collector region 22 and the cathode region 82 are exposed on the rear surface 23 of the semiconductor substrate 10, and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire rear surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0096] At least one gate trench portion 40 and at least one dummy trench portion 30 are provided on the front surface 21 side of the semiconductor substrate 10. Each trench portion is provided from the front surface 21 of the semiconductor substrate 10 through the base region 14 or the anode region 84 to below the base region 14 and the anode region 84. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doped regions. The trench portion penetrating the doped region is not limited to a case where the trench portion is formed in the order of forming the doped region and then the trench portion. A case where the trench portion is formed and then the doped region is formed between the trench portions is also included in the case where the trench portion penetrates the doped region.

[0097] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. In the present example, the diode section 80 and the boundary region 200 are provided with the dummy trench section 30, but not with the gate trench section 40. However, the gate trench section 40 or the dummy trench section 30 may be disposed at the boundary between the boundary region 200 and the transistor section 70.

[0098] The boundary region 200 is a buffer structure for arranging the different structures of the transistor section 70 and the diode section 80 in parallel. Therefore, the width of the boundary region 200 in the X-axis direction may be short. For example, the fourth mesa portion 64 of the boundary region 200 may be provided over a width of one or several portions, or may not be provided at all.

[0099] The boundary region 200 may be provided widely in the X-axis direction across the multiple fourth mesa portions 64. This makes it possible to suppress the influence of the transistor portion 70 on the characteristics of the diode portion 80, for example, the influence of the operation of the gate trench portion 40 and the injection or ejection of holes in the contact region 15 on the forward voltage and reverse recovery characteristics.

[0100] The gate trench portion 40 has a gate trench provided on the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0101] The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0102] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0103] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).

[0104] In this example, the second mesa portion 62 is provided with a trench contact portion 17. The trench contact portion 17 is a portion in which a front surface electrode (i.e., the emitter electrode 52 or a contact plug portion) is provided inside the mesa portion. The trench contact portion 17 can be formed by forming a groove in the front surface 21 of the semiconductor substrate 10 exposed by the contact hole 54 and filling the inside of the groove with a front surface electrode. In the second mesa portion 62, a region in the trench contact portion 17 where the second mesa portion 62 and the front surface electrode are connected corresponds to the contact portion.

[0105] The third mesa portion 63 in this example is provided with a front surface contact portion 87 in which a front surface electrode is in contact with the front surface of the third mesa portion 63. The lower end of the front surface contact portion 87 is disposed higher than the lower end of the trench contact portion 17. The fourth mesa portion 64 in this example may be provided with the trench contact portion 17 or with the front surface contact portion 87. Alternatively, the trench contact portion 17 may be provided on some of the fourth mesa portions 64, and the front surface contact portion 87 may be provided on the other fourth mesa portions 64.

[0106] In this example, each contact portion refers to an interface where the front surface electrode and the mesa portion 60 are in contact. The contact portion may include a surface of the front surface electrode and a surface of the mesa portion 60. Here, in the case of the front surface contact portion 87, the surface of the mesa portion 60 refers to the front surface of the mesa portion 60, i.e., the front surface 21 of the semiconductor substrate 10. In the case of the trench contact portion 17, the surface of the mesa portion 60 refers to the bottom surface of the contact hole 54 provided inside the mesa portion 60. In this example, the width Wpcn in the X-axis direction of the front surface contact portion 87 may be the same as or different from the width Wtcn in the X-axis direction of the trench contact portion 17, and may be larger than the width Wtcn.

[0107] In addition, when a metal silicide layer is formed at the interface between the front surface electrode and the mesa portion 60, the metal silicide layer may be included in the front surface electrode. In other words, the interface between the metal silicide layer and the mesa portion 60 may be used as a contact portion.

[0108] At least a part of the mesa portion 60 may have a plug region in a region in contact with the lower end of the contact portion. The plug region is a P++ type region having a higher doping concentration than the contact region 15. In the example of FIG. 3A, a second plug region 222 is provided in contact with the front surface contact portion 87.

[0109] In this example, by providing the trench contact portion 17 in the transistor portion 70, minority carriers (e.g., holes) in the base region 14 can be easily extracted. This improves the breakdown resistance, such as the latch-up resistance, caused by minority carriers. The trench contact portion 17 shown in FIG. 3A is provided to a depth partway through the emitter region 12, and the first plug region 221 is not provided on the bottom surface. In another example, the trench contact portion 17 may be provided to a depth reaching the base region 14, and the first plug region 221 may be provided on the bottom surface of the trench contact portion 17.

[0110] Moreover, the diode section 80 of this example is provided with a front surface contact section 87 instead of the trench contact section 17. When the trench contact section 17 is provided, a region of the anode region 84 with a high doping concentration near the front surface 21 of the semiconductor substrate 10 is removed, so that the trench contact section 17 comes into contact with a region of the anode region 84 with a low doping concentration. Thus, by providing the front surface contact section 87 in the third mesa section 63 of the diode section 80, the forward voltage of the diode section 80 can be reduced.

[0111] In this example, the width Wpcn in the X-axis direction of the front surface contact portion 87 is larger than the width Wtcn in the X-axis direction of the trench contact portion 17. This makes it possible to further reduce the contact resistance of the front surface contact portion 87 and further reduce the forward voltage of the diode portion 80.

[0112] There is a trade-off between the reverse recovery loss and the forward voltage of the diode section 80. If hole injection is increased when the diode section 80 is conductive, the forward voltage decreases but the reverse recovery loss increases. On the other hand, if hole extraction is promoted, the reverse recovery loss decreases but the forward voltage of the diode section 80 increases. In this example, by providing a trench contact section 17 in the transistor section 70 and a front surface contact section 87 in the diode section 80, the trade-off between the reverse recovery loss and the forward voltage of the diode section 80 can be improved.

[0113] Fig. 3B is an enlarged view of the vicinity of the second mesa portion 62 and the third mesa portion 63 shown in Fig. 3A. Fig. 3B shows one each of the second mesa portion 62 and the third mesa portion 63, with the regions between the mesas omitted.

[0114] The emitter electrode 52 of this example is provided on the front surface of the interlayer insulating film 38. The contact plug portion 250 includes a plug 251 and a barrier metal portion 252. The plug 251 of this example includes tungsten. The barrier metal portion 252 is provided above the front surface 21 of the semiconductor substrate 10. The barrier metal portion 252 is provided at least on the bottom surface of the contact hole 54. The barrier metal portion 252 may be provided at the lower end of each contact portion. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may also be provided on the side surface of the contact hole 54. The plug 251 is embedded in the contact hole 54 via the barrier metal portion 252. The plug 251 and the barrier metal portion 252 may or may not be provided on the front surface of the interlayer insulating film 38.

[0115] The barrier metal portion 252 is formed of a material having a higher hydrogen occlusion property than the emitter electrode 52. This suppresses the penetration of hydrogen ions into the semiconductor substrate 10. The barrier metal portion 252 in this example contains titanium. The barrier metal portion 252 may include a titanium nitride layer. The barrier metal portion 252 may be a laminated film of a titanium layer and a titanium nitride layer.

[0116] The emitter electrode 52 is provided above the barrier metal portion 252. The emitter electrode 52 is also provided above the interlayer insulating film 38. The emitter electrode 52 is formed of a material different from that of the barrier metal portion 252. As an example, the emitter electrode 52 contains aluminum. The emitter electrode 52 may be an alloy of aluminum and silicon.

[0117] In this example, the width Wpcn in the X-axis direction of the front surface contact portion 87 is larger than the width Wtcn in the X-axis direction of the trench contact portion 17. This reduces the contact resistance of the front surface contact portion 87 and decreases the forward voltage of the diode portion 80.

[0118] The third mesa portion 63 may have a P++ type second plug region 222 provided in contact with the lower end of the front surface contact portion 87 and having a higher doping concentration than the anode region 84. The second plug region 222 may have a higher doping concentration than the contact region 15. The anode region 84 of the third mesa portion 63 may have a lower doping concentration than the base region 14 of the transistor portion 70. In this case, injection of holes from the third mesa portion 63 to the drift region 18 can be suppressed. The second plug region 222 of this example may be provided extending in the Y-axis direction, or may be provided discretely.

[0119] 3B shows a depth position Z1 of the trench contact portion 17 and a depth position Z2 of the front surface contact portion 87 in the Z-axis direction. The depth positions of the trench contact portion 17 and the front surface contact portion 87 are the deepest positions at the interface where the semiconductor substrate 10 and a metal electrode (e.g., the barrier metal portion 252, the emitter electrode 52, etc.) contact each other at the bottom surface of the contact hole 54. The depth position may be the distance from the front surface 21 of the semiconductor substrate 10 in the depth direction (-Z-axis direction). The depth position Z2 is located at a position shallower than the depth position Z1.

[0120] Depth position Z2 in this example is the same as the front surface 21 of the semiconductor substrate 10. Moreover, depth position Z1 in this example is located at a position deeper than the front surface 21 of the semiconductor substrate 10. In other words, depth position Z1 is located at a position farther away from the front surface 21 of the semiconductor substrate 10 than depth position Z2.

[0121] In another example, depth position Z2 may be a position between depth position Z1 and the front surface 21 of the semiconductor substrate 10. In this case, with respect to the front surface 21 of the semiconductor substrate 10, depth position Z2 may be a depth that is half or less than a depth that is ¼ or less than the depth position Z1.

[0122] Fig. 4A is a diagram showing an example of the ff cross section in Fig. 2. The ff cross section is an XZ plane passing through the contact region 15 and the cathode region 82. In the ff cross section, the contact region 15 is arranged instead of the emitter region 12 in the ee cross section shown in Fig. 3A. The other structures are the same as in the ee cross section. In the ff cross section, the structures of the trench contact portion 17 and the front surface contact portion 87 are the same as in the ee cross section.

[0123] The second mesa portion 62 of this example is provided in contact with the lower end of the trench contact portion 17, and has a P++-type first plug region 221 having a higher doping concentration than the contact region 15. At least a part of the first plug region 221 is provided so as to overlap with the contact region 15 in a top view. That is, the first plug region 221 is provided in any XZ cross section passing through the contact region 15. The first plug region 221 may be provided in an XZ cross section passing through the center of the contact region 15 in the Z-axis direction. The first plug region 221 may not be provided in any XZ cross section passing through the emitter region 12. For example, the first plug region 221 is not provided in an XZ cross section passing through the center of the emitter region 12 in the Z-axis direction. The entire first plug region 221 may be provided so as to overlap with the contact region 15. In this case, the first plug region 221 does not overlap with the emitter region 12 in a top view, and the first plug region 221 is provided discretely in the Y-axis direction. By providing each plug region, holes can be easily extracted in each mesa portion, and therefore a decrease in the withstand voltage can be suppressed.

[0124] Fig. 4B is an enlarged view of the vicinity of the second mesa portion 62 and the third mesa portion 63 shown in Fig. 4A. Fig. 4B shows one each of the second mesa portion 62 and the third mesa portion 63, and the regions between the mesa portions are omitted. The structure of the third mesa portion 63 is similar to that of the third mesa portion 63 shown in Fig. 3B.

[0125] 3B, the second mesa portion 62 has a contact region 15 instead of the emitter region 12, and has a first plug region 221 in contact with the lower end of the trench contact portion 17. The other structures are similar to the example of FIG. 3B.

[0126] 5 is a diagram showing an example of a P-type doping concentration distribution of the anode region 84 and the second plug region 222 in the vicinity of the front surface of the third mesa portion 63. The vertical axis represents the doping concentration distribution in the third mesa portion 63, and the horizontal axis represents the depth position with respect to the front surface of the third mesa portion 63.

[0127] 5 shows the P-type doping concentration profile of this example with a solid line. The depth position Z2 in this example is the same as the front surface 21. The P-type doping concentration profile of this example is composed of an anode region 84 formed by diffusing P-type impurities from the front surface 21, and a second plug region 222 formed by ion implantation into the bottom surface of the contact hole 54.

[0128] 5, the doping concentration profile of the P-type in the comparative example is indicated by a dashed line. The comparative example is a doping concentration profile in the case where the trench contact portion 17 is provided in the third mesa portion 63 of the diode portion 80 as in the transistor portion 70.

[0129] In the comparative example, a region of the anode region 84 with a high doping concentration near the front surface 21 of the semiconductor substrate 10 is removed in order to provide the trench contact portion 17. The P-type doping concentration profile of the comparative example is made of a second plug region 222 formed by ion implantation into the bottom surface of the contact hole 54 formed in the anode region 84 up to the depth position Z1.

[0130] The trench contact portion 17 contacts a region of the anode region 84 with a lower doping concentration than the front surface contact portion 87. This results in less hole injection and an increase in the forward voltage. Therefore, by providing the front surface contact portion 87 in the third mesa portion 63 of the diode portion 80, the forward voltage of the diode portion 80 can be reduced.

[0131] Fig. 6 is a plan view showing another example of Fig. 2. This example differs from Fig. 2 in that the boundary region 200 includes one mesa portion 60, the front surface side is provided with the base region 14, and the front surface side of the base region 14 is provided with the contact region 15. The doping concentration of the anode region 84 of this example is higher than the doping concentration of the anode region 84 of Fig. 2 and may be the same as the doping concentration of the base region 14. The anode region 84 of this example is P-type.

[0132] Moreover, on the front surface side of the mesa portion 60 of the diode portion 80, the base region 14 is provided to sandwich the anode region 84 in the Y-axis direction, and the contact region 15 is provided between the anode region 84 and the base region 14. The contact region 15 may be provided to cover the end of the contact hole 54 in a top view.

[0133] Fig. 7A is a diagram showing an example of the gg cross section in Fig. 6. The gg cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0134] The semiconductor device 100 of this example includes a lifetime adjustment region 206 including a lifetime killer that adjusts the lifetime of carriers. The lifetime adjustment region 206 of this example is a region in which the lifetime of charge carriers is locally short. The charge carriers are electrons or holes. Charge carriers may be simply referred to as carriers. The lifetime adjustment region 206 of this example is formed by injecting charged particles such as helium from the front surface 21 side of the semiconductor substrate 10. In this example, the concentration distribution of charged particles such as helium in the depth direction of the semiconductor substrate 10 may have a shape that trails from the lifetime adjustment region 206 to the front surface 21 of the semiconductor substrate 10. In other words, the concentration ( / cm ) of charged particles such as helium from the lifetime adjustment region 206 to the front surface 21 3) may decrease monotonically. The concentration of charged particles such as helium on the front surface 21 may be greater than 0. On the other hand, the concentration of charged particles such as helium may have a tail shape in the direction from the lifetime adjusting region 206 toward the back surface 23. However, the concentration of charged particles such as helium decreases more steeply toward the back surface 23 than toward the front surface 21. The concentration of charged particles such as helium on the back surface 23 is lower than the concentration of charged particles such as helium on the front surface 21. The concentration of charged particles such as helium on the front surface 21 may be equal to or less than the measurement limit, or may be 0. The lifetime adjusting region 206 may be formed by injecting charged particles such as helium from the back surface 23 side of the semiconductor substrate 10.

[0135] By injecting charged particles such as helium into the semiconductor substrate 10, lattice defects 204 such as vacancies are formed near the injection position. The lattice defects 204 generate recombination centers. The lattice defects 204 may be mainly vacancies such as monovacancies (V) and divacancies (VV), may be dislocations, may be interstitial atoms, may be transition metals, etc. For example, atoms adjacent to the vacancies have dangling bonds. In a broad sense, the lattice defects 204 may also include donors and acceptors, but in this specification, the lattice defects 204 mainly composed of vacancies may be referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, the lattice defects 204 may be referred to simply as recombination centers or lifetime killers as recombination centers that contribute to carrier recombination. The lifetime killers may be formed by injecting helium ions into the semiconductor substrate 10. The helium chemical concentration may be the density of the lattice defects 204. Note that the lifetime killer formed by implanting helium may be terminated by hydrogen present in the buffer region 20, so the depth position of the lifetime killer density peak may not coincide with the depth position of the helium chemical concentration peak. Alternatively, the lifetime killer may be formed in a hydrogen ion passage region on the implantation surface side relative to the range when hydrogen ions are implanted into the semiconductor substrate 10.

[0136] Lattice defects 204 are an example of a lifetime killer. In FIG. 7A, lattice defects 204 at the injection position of the charged particles are typically indicated by crosses. In a region where many lattice defects 204 remain, carriers are captured by the lattice defects 204, shortening the carrier lifetime. By adjusting the carrier lifetime, it is possible to adjust the characteristics of the diode section 80, such as the reverse recovery time and reverse recovery loss. In the depth direction of the semiconductor substrate 10, the position where the carrier lifetime shows a minimum value may be set as the depth position of the lifetime adjustment region 206.

[0137] The lifetime adjusting region 206 is disposed on the front surface 21 side of the semiconductor substrate 10. The front surface 21 side is a region from the center position in the depth direction of the semiconductor substrate 10 to the front surface 21 of the semiconductor substrate 10. In this example, the lifetime adjusting region 206 is disposed below the lower end of the trench portion. When the lifetime adjusting region 206 is formed by irradiation with a particle beam having high penetrating power such as an electron beam, lattice defects are formed substantially uniformly from the front surface 21 to the back surface 23 of the semiconductor substrate 10. In this case as well, the depth position of the lifetime adjusting region 206 may be considered to be disposed on the front surface 21 side of the semiconductor substrate 10.

[0138] The lifetime adjusting region 206 may be provided in at least one of the transistor portion 70 and the diode portion 80. When the semiconductor device 100 has the boundary region 200, the lifetime adjusting region 206 may also be provided in the boundary region 200. The lifetime adjusting region 206 may be provided in the entire diode portion 80 in the X-axis direction. The lifetime adjusting region 206 may also be provided in the entire boundary region 200. In another example, the lifetime adjusting region 206 may be provided in a part of the boundary region 200.

[0139] The lifetime adjusting region 206 of the diode section 80 in this example is provided extending in the X-axis direction up to a part of the transistor section 70. The lifetime adjusting region 206 of the diode section 80 and the lifetime adjusting region 206 of the transistor section 70 are provided at the same depth position. In the transistor section 70, a region where the lifetime adjusting region 206 is provided is referred to as an adjusting region 201, and a region where the lifetime adjusting region 206 is not provided is referred to as a non-adjusting region 202. The non-adjusting region 202 is a region where the carrier lifetime at the same depth position as the lifetime adjusting region 206 is shorter than the carrier lifetime of the lifetime adjusting region 206 of the diode section 80. The non-adjusting region 202 may be a region into which charged particles such as helium are not injected to form lifetime killers such as lattice defects 204. The chemical concentration ( / cm of the charged particles such as helium in the non-adjusting region 202 is 3 ) may be the same as the chemical concentration of the charged particle at the center of the drift region 18 in the Z-axis direction.

[0140] The adjustment region 201 of this example has a trench contact portion 17 where the first mesa portion 61 and the emitter electrode 52 are in contact with each other. The trench contact portion 17 may be provided for some of the first mesas 61, or may be provided for all of the first mesas 61. Alternatively, the front surface contact portion 87 may be provided for all of the first mesas 61. The second mesa portion 62 of the non-adjustment region 202 has the same structure as the second mesa portion 62 described in FIG. 3A, and therefore a description thereof will be omitted. Note that the lifetime adjustment region 206 may not extend to the transistor portion 70, and the adjustment region 201 may not be provided. Alternatively, the lifetime adjustment region 206 may extend to the entire surface of the transistor portion 70, and the non-adjustment region 202 may not be provided.

[0141] The doping concentration of the anode region 84 may be the same as or lower than the doping concentration of the base region 14. Alternatively, the doping concentration of the anode region 84 may be higher than the doping concentration of the base region 14. Since the semiconductor device 100 of this example includes the lifetime adjusting region 206, the reverse recovery loss of the diode section 80 is reduced, and therefore the doping concentration of the anode region 84 may be made relatively high.

[0142] In the boundary region 200 of this example, the base region 14 is provided in one mesa portion 60 (fourth mesa portion 64), and the contact region 15 is provided on the front surface side of the base region 14. The end portion of the contact region 15 in the Y-axis direction is sandwiched between the base regions 14. This makes it easier for holes in the semiconductor substrate 10 to be extracted to the emitter electrode 52 through the mesa portion 60 (fourth mesa portion 64) of the boundary region 200 during a turn-off operation. In addition, the lifetime adjustment region 206 is extended to the transistor portion 70 to provide the adjustment region 201, and the injection of holes from the contact region 15 can be suppressed. Therefore, in the X-axis direction, the boundary region 200 does not need to be extended across multiple mesa portions 60, or the boundary region 200 does not need to be provided.

[0143] As another example, by providing a wide boundary region whose width in the X-axis direction spans multiple mesa portions 60 in addition to the lifetime adjusting region 206, the injection of holes from the mesa portions 60 (the first mesa portion 61, the second mesa portion 62, and the fourth mesa portion 64) can be further suppressed, and the loss during reverse recovery operation can be reduced.

[0144] 7B is an hh cross section including the contact region 15 in FIG. 6. The hh cross section is an XZ plane passing through the contact region 15 and the cathode region 82. In the hh cross section, the contact region 15 is arranged instead of the emitter region 12 in the gg cross section shown in FIG. 7A. The other structures are the same as in the gg cross section. In the hh cross section, the structures of the trench contact portion 17 and the front surface contact portion 87 are the same as in the gg cross section.

[0145] Fig. 8 is a plan view showing another example of Fig. 2. This example differs from Fig. 2 in that there is no boundary region 200. The semiconductor device 100 of this example is mainly used in a resonant circuit, and is used under conditions where reverse recovery operation is not performed.

[0146] Fig. 9A is a diagram showing an example of the jj cross section in Fig. 8. The jj cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section.

[0147] The anode region 84 in this example may have the same doping concentration as the base region 14 or a higher doping concentration than the base region 14. The anode region 84 in this example is P-type. The anode region 84 may also be formed by ion implantation at the same time that the base region 14, the contact region 15, or the well region 11 are formed.

[0148] In the present embodiment, the second mesa portion 62 of the transistor portion 70 is provided with a trench contact portion 17. In the present embodiment, the third mesa portion 63 of the diode portion 80 is provided with a front surface contact portion 87.

[0149] Although the boundary region 200 is not provided in this example, the boundary region 200 may be provided in other examples. In this case, since the device is used under conditions in which reverse recovery operation is not performed, the boundary region 200 does not need to be provided across multiple mesa portions 60 in the X-axis direction in order to suppress injection of holes from the contact region 15 of the transistor portion 70, and may be formed with a narrow width. For example, the boundary region 200 has one fourth mesa portion 64 having a front surface contact portion 87 similar to that in FIG. 7A.

[0150] FIG. 9B is a diagram showing an example of the kk cross section in FIG. 8. The kk cross section is an XZ plane passing through the contact region 15 and the cathode region 82. In the kk cross section, the contact region 15 is arranged instead of the emitter region 12 in the jj cross section shown in FIG. 9A. The other structures are similar to those in the jj cross section. In the kk cross section, the structures of the trench contact portion 17 and the front surface contact portion 87 are similar to those in the jj cross section. Note that in the diode portion 80, the base region 14 may be provided in the third mesa portion 63, and the contact region 15 may be provided on the front surface side of the base region 14.

[0151] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0152] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0153] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 trench contact portion, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 44 gate conductive portion, 52 emitter electrode, 54 contact hole, 60 mesa portion, 61 first mesa portion, 62 second mesa portion, 63 third mesa portion, 64 fourth mesa portion, 70 transistor portion, 80 diode portion, 81 extension region, 82 cathode region, 84 anode region, 87 front surface contact portion, 90 edge termination structure portion, 100 semiconductor device, 130 peripheral gate wiring, 131 active side gate wiring Line, 160... active portion, 162... edge, 164... gate pad, 200... boundary region, 201... adjustment region, 202... non-adjusted region, 204... lattice defect, 206... lifetime adjustment region, 221... first plug region, 222... second plug region, 250... contact plug portion, 251... plug, 252... barrier metal portion

Claims

1. A transistor portion; A diode portion; A plurality of trenches provided on a front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; a second conductivity type base region provided above the drift region in the transistor portion; In the transistor portion, an emitter region of a first conductivity type having a doping concentration higher than that of the drift region and a contact region of a second conductivity type having a doping concentration higher than that of the base region are provided on a front surface of the semiconductor substrate; a second conductivity type anode region provided above the drift region in the diode portion; a mesa portion of the semiconductor substrate provided between the plurality of trench portions; an interlayer insulating film provided above the semiconductor substrate; a front surface electrode provided above the semiconductor substrate; a trench contact portion in the transistor portion, the trench contact portion connecting the front surface electrode and the mesa portion; a front surface contact portion in the diode portion, the front surface electrode and the mesa portion being connected to each other; Equipped with A semiconductor device in which a lower end of the front surface contact portion is disposed higher than a lower end of the trench contact portion.

2. The width of the front surface contact portion in the trench arrangement direction is larger than the width of the trench contact portion in the trench arrangement direction. The semiconductor device according to claim 1 .

3. The front surface electrode includes an emitter electrode. The semiconductor device according to claim 1 .

4. The front surface electrode includes a contact plug portion that is provided in a contact hole in the interlayer insulating film and connects the emitter electrode and the semiconductor substrate. The semiconductor device according to claim 3 .

5. The doping concentration of the anode region is lower than the doping concentration of the base region. The semiconductor device according to claim 1 .

6. The doping concentration of the anode region is the same as the doping concentration of the base region. The semiconductor device according to claim 1 .

7. The doping concentration of the anode region is higher than the doping concentration of the base region. The semiconductor device according to claim 1 .

8. The diode portion has a lifetime control region provided on the front surface side of the semiconductor substrate relative to the center of the semiconductor substrate in a depth direction of the semiconductor substrate.

8. The semiconductor device according to claim 6 or 7.

9. a first plug region of a second conductivity type provided at a lower end of the trench contact portion and having a doping concentration higher than that of the contact region; a second plug region of a second conductivity type having a doping concentration higher than that of the contact region, the second plug region being provided in contact with a lower end of the front surface contact portion; Equipped The semiconductor device according to claim 1 .

10. The first plug regions are provided discretely in the trench extension direction. The semiconductor device according to claim 9.

11. The second plug region is provided to extend in the trench extension direction. The semiconductor device according to claim 9.

12. The transistor section includes an accumulation region of a first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region. The semiconductor device according to claim 1 .

13. a boundary region provided between the transistor portion and the diode portion, an area ratio of the emitter region in the mesa portion of the boundary region is smaller than an area ratio of the emitter region in the mesa portion of the transistor portion when viewed from above; The mesa portion in the boundary region is provided with the front surface contact portion. The semiconductor device according to claim 1 .

14. The width of the boundary region in the trench arrangement direction is 20 μm or more and 250 μm or less. The semiconductor device according to claim 13.

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