Three-dimensional semiconductor element

Abstract

To provide a three-dimensional semiconductor element with improved electric characteristics, and a manufacturing method for the same.SOLUTION: A three-dimensional semiconductor device includes a rear surface metal layer, a lower channel pattern LCH on the rear surface metal layer, first and second lower source / drain patterns LSD1, LSD2 separated from each other in a first direction through the lower channel pattern, an upper channel pattern UCH on the LCH, a first upper source / drain pattern USD1 on the LSD1, a second upper source / drain pattern USD2 on the LSD2, and a wide via WV electrically connecting the USD1 and the USD2. The first lower source / drain pattern is connected to the lower channel pattern, and the first upper source / drain pattern is connected to the upper channel pattern. The wide via includes a first via part with a first upper surface and a second via part with a second upper surface that exists at a lower level than the first upper surface.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to three-dimensional semiconductor devices, and more particularly to three-dimensional semiconductor devices including field effect transistors and methods for fabricating the same. [Background technology]

[0002] Semiconductor devices include integrated circuits made up of MOS field effect transistors (MOS (Metal Oxide Semiconductor) FETs). As the size and design rules of semiconductor devices are gradually reduced, the scale-down of MOS field effect transistors is also accelerating. As the size of MOS field effect transistors is reduced, the operating characteristics of semiconductor devices are degraded. Therefore, various methods are being researched to form semiconductor devices with better performance while overcoming the limitations imposed by the high integration of semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 11063045 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a three-dimensional semiconductor element having improved electrical characteristics.

[0005] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those having ordinary skill in the art from the following description. [Means for solving the problem]

[0006] In accordance with one aspect of the present invention, a three-dimensional semiconductor device includes a back metal layer, a lower channel pattern on the back metal layer, a first lower source / drain pattern and a second lower source / drain pattern spaced apart in a first direction by the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source / drain pattern on the first lower source / drain pattern, a second upper source / drain pattern on the second lower source / drain pattern, and a wide via electrically connecting the first upper source / drain pattern and the second lower source / drain pattern, wherein the first lower source / drain pattern is connected to the lower channel pattern and the first upper source / drain pattern is connected to the upper channel pattern, and the wide via includes a first via portion having a first upper surface and a second via portion having a second upper surface located at a level lower than the first upper surface.

[0007] According to another aspect of the present invention, a three-dimensional semiconductor device includes a back metal layer, a lower channel pattern on the back metal layer, a first lower source / drain pattern and a second lower source / drain pattern spaced apart in a first direction by the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source / drain pattern on the first lower source / drain pattern, a second upper source / drain pattern on the second lower source / drain pattern, and a wide via electrically connecting the first upper source / drain pattern and the second lower source / drain pattern, wherein the first lower source / drain pattern is connected to the lower channel pattern and the first upper source / drain pattern is connected to the upper channel pattern, and a lower portion of the wide via protrudes in the first direction further than an upper portion of the wide via.

[0008] According to another aspect of the present invention, a three-dimensional semiconductor device is provided, which includes a back metal layer, a lower channel pattern and an upper channel pattern sequentially disposed on the back metal layer, a gate electrode crossing the lower and upper channel patterns, a first lower source / drain pattern connected to the lower channel pattern in a first direction, a first upper source / drain pattern connected to the upper channel pattern in the first direction on the first lower source / drain pattern, a cutting pattern adjacent to the gate electrode in a second direction intersecting the first direction, and a wide via positioned within the cutting pattern and electrically connected to the first upper source / drain pattern, wherein the cutting pattern covers a portion of an upper surface of the wide via.

[0009] According to another aspect of the present invention, a three-dimensional semiconductor device includes a back metal layer, a lower channel pattern on the back metal layer, a first lower source / drain pattern and a second lower source / drain pattern spaced apart in a first direction by the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source / drain pattern on the first lower source / drain pattern, a second upper source / drain pattern on the second lower source / drain pattern, a first upper active contact electrically connected to the first upper source / drain pattern, a second upper active contact electrically connected to the second upper source / drain pattern, and a first lower contact electrically connected to the first lower source / drain pattern. a gate electrode between the first upper source / drain pattern and the second upper source / drain pattern; a cutting pattern adjacent to the gate electrode in a second direction intersecting the first direction; and a wide via positioned within the cutting pattern and electrically connecting the first upper active contact and the second lower contact, wherein the first lower source / drain pattern is connected to the lower channel pattern, the first upper source / drain pattern is connected to the upper channel pattern, and the wide via may include a first via portion having a first upper surface and a second via portion having a second upper surface located at a level lower than the first upper surface. Effect of the Invention

[0010] According to the present invention, a portion of an upper surface of the wide via is recessed to ensure a distance between the wide via and an upper active contact that is not connected thereto, thereby preventing a short phenomenon between the wide via and the upper active contact, thereby improving electrical characteristics and reliability of a three-dimensional semiconductor device.

[0011] In addition, the wide via electrically connects lower and upper source / drain patterns that are horizontally spaced apart from each other, thereby improving the design freedom of three-dimensional semiconductor devices. [Brief description of the drawings]

[0012] [Figure 1] 1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to a comparative example of the present invention; [Diagram 2] 1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention; [Diagram 3] 1 is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 4] FIG. 4 is an enlarged view corresponding to P1 in FIG. [Figure 5A] FIG. 4 is a cross-sectional view taken along line AA' in FIG. [Figure 5B] FIG. 4 is a cross-sectional view taken along line BB' in FIG. [Figure 5C] FIG. 4 is a cross-sectional view taken along line CC' in FIG. [Figure 5D] FIG. 4 is a cross-sectional view taken along line DD' in FIG. [Figure 5E] FIG. 4 is a cross-sectional view taken along line EE' in FIG. [Figure 6] FIG. 4 is an enlarged view corresponding to P1 in FIG. [Figure 7A] FIG. 4 is a cross-sectional view taken along line BB' in FIG. [Figure 7B] FIG. 4 is a cross-sectional view taken along line EE' in FIG. [Figure 8] 1 is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 9A] 9 is an enlarged view corresponding to P2 in FIG. 8. [Figure 9B] 9 is an enlarged view corresponding to P2 in FIG. 8. [Figure 10A] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 10B]1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 10C] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 11A] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 11B] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 11C] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 11D] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 12A] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 12B] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 12C] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 12D] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 13A] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 13B] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 13C] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 13D] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 14A] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 14B] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 14C] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 15A] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 15B] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 15C] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 15D] 1A to 1C are diagrams illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In order to more specifically explain the present invention, embodiments of the present invention will be described in more detail below with reference to the drawings.

[0014] FIG. 1 is a conceptual diagram for explaining a logic cell of a semiconductor device according to a comparative example of the present invention.

[0015] Referring to FIG. 1, a single height cell (SHC') is provided. Specifically, a first power wiring POR1 and a second power wiring POR2 are provided on a substrate 100. A drain voltage VDD, i.e., a power voltage, is applied to one of the first power wiring POR1 and the second power wiring POR2. A source voltage VSS, i.e., a ground voltage, is applied to the other of the first power wiring POR1 and the second power wiring POR2. As an example, a source voltage VSS is applied to the first power wiring POR1, and a drain voltage VDD is applied to the second power wiring POR2. As an example, each of the first power wiring POR1 and the second power wiring POR2 extends in a first direction D1 parallel to the bottom surface of the substrate 100, and is spaced apart from each other in a second direction D2 parallel to the bottom surface of the substrate 100 and intersecting the first direction D1.

[0016] A single height cell SHC' is defined between a first power wiring POR1 and a second power wiring POR2. The single height cell SHC' includes a first active area AR1 and a second active area AR2. Any one of the first active area AR1 and the second active area AR2 is a PMOSFET area, and the other one of the first active area AR1 and the second active area AR2 is an NMOSFET area. As an example, the first active area AR1 is an NMOSFET area, and the second active area AR2 is a PMOSFET area. Again, the single height cell SHC' has a CMOS structure provided between the first power wiring POR1 and the second power wiring POR2.

[0017] The semiconductor device according to this comparative example is a two-dimensional device in which transistors in a front end of line (FEOL) layer are arranged two-dimensionally. For example, an NMOSFET in a first active region AR1 and a PMOSFET in a second active region AR2 are spaced apart from each other in a second direction D2.

[0018] Each of the first active region AR1 and the second active region AR2 has a first width AW1 in the second direction D2. The length of the single height cell SHC′ according to this comparative example in the second direction D2 is defined by a first height CHT1. The first height CHT1 is substantially equal to the distance (e.g., pitch) between the first power wiring POR1 and the second power wiring POR2.

[0019] The single height cell SHC' constitutes one logic cell. In this specification, a logic cell refers to a logic element (e.g., AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. That is, a logic cell includes transistors for constituting a logic element and wiring that connects the transistors to each other.

[0020] Since the single height cell SHC' according to this comparative example includes a two-dimensional element, the first active region AR1 and the second active region AR2 are not overlapped with each other and are spaced apart from each other in the second direction D2. Therefore, the first height CHT1 of the single height cell SHC' must be defined to include all of the first and second active regions AR1 and AR2 spaced apart from each other in the second direction D2. Therefore, the first height CHT1 of the single height cell SHC' has a size that includes at least two first widths AW1. As a result, the first height CHT1 of the single height cell SHC' according to this comparative example is relatively larger than the second height CHT2 of the single height cell SHC described below. In other words, the area of ​​the single height cell SHC' according to this comparative example is relatively large.

[0021] FIG. 2 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention.

[0022] 2, a single height cell (SHC) including a three-dimensional element (e.g., a stacked transistor) is provided. Specifically, a first power wiring POR1 and a second power wiring POR2 are provided on a substrate 100. The single height cell SHC is defined between the first power wiring POR1 and the second power wiring POR2.

[0023] The single height cell SHC includes a lower active area LAR and an upper active area UAR, one of which is a PMOSFET area and the other of which is an NMOSFET area.

[0024] The semiconductor device according to the present embodiment is a three-dimensional device in which transistors in FEOL layers are vertically stacked. A lower active region LAR is provided on the substrate 100 as a bottom tier, and an upper active region UAR is stacked on the lower active region LAR as a top tier. For example, a PMOSFET in the lower active region LAR is provided on the substrate 100, and an NMOSFET in the upper active region UAR is stacked on the PMOSFET. The lower active region LAR and the upper active region UAR are spaced apart from each other in a vertical direction, i.e., a third direction D3 perpendicular to the bottom surface of the substrate 100.

[0025] Each of the lower active region LAR and the upper active region UAR has a second width AW2 in the second direction D2. The length of the single height cell SHC in the second direction D2 according to the present embodiment is defined as a second height CHT2.

[0026] Since the single height cell SHC according to the present embodiment is a three-dimensional device, i.e., includes stacked transistors, the lower active region LAR and the upper active region UAR overlap each other. Therefore, the second height CHT2 of the single height cell SHC has a size that includes one second width AW2 described above. As a result, the second height CHT2 of the single height cell SHC according to the present embodiment is smaller than the first height CHT1 of the single height cell SHC' of FIG. 1 described above. Again, the area of ​​the single height cell SHC according to the present embodiment is relatively small. The three-dimensional semiconductor device according to the present embodiment can improve the integration density of the device by reducing the area of ​​the logic cell.

[0027] Fig. 3 is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the present invention. Fig. 4 is an enlarged view corresponding to P1 in Fig. 3. Figs. 5A to 5E are cross-sectional views taken along lines A-A', B-B', CC', D-D', and E-E' in Fig. 3, respectively.

[0028] 3-5E, a single height cell SHC is provided on a substrate 100. In one embodiment of the present invention, the substrate 100 is an insulating substrate including a silicon-based insulating material (e.g., silicon oxide and / or silicon nitride). In other embodiments of the present invention, the substrate 100 is a semiconductor substrate including silicon, germanium, silicon germanium, etc.

[0029] As an example, the substrate 100 includes a first lower insulating layer LIL1 and a second lower insulating layer LIL2. The first lower insulating layer LIL1 is provided on the second lower insulating layer LIL2. The first lower insulating layer LIL1 includes a silicon-based insulating material (e.g., silicon oxide) and / or a semiconductor material (Si or SiGe). The second lower insulating layer LIL2 includes a silicon-based insulating material (e.g., silicon oxide, silicon oxynitride, or silicon nitride).

[0030] An isolation layer ST is provided in the substrate 100. The isolation layer ST defines a single height cell SHC. The isolation layer ST is interposed between a back metal layer BSM (to be described later) and a first interlayer insulating layer 110 (to be described later). As an example, the isolation layer ST includes a silicon-based insulating material (e.g., silicon oxide, silicon oxynitride, or silicon nitride).

[0031] In one embodiment of the present invention, each of the single height cells SHC is a logic cell constituting a logic circuit. Each of the single height cells SHC is a logic cell including the three-dimensional element previously described with reference to Figure 2. The single height cells SHC are arranged along a second direction D2.

[0032] Each single height cell SHC includes a lower active region LAR and an upper active region UAR sequentially stacked on the substrate 100. Any one of the lower and upper active regions LAR and UAR is a PMOSFET region, and the other of the lower and upper active regions LAR and UAR is an NMOSFET region. The lower active region LAR is provided as a bottom tier of the FEOL layer, and the upper active region UAR is provided as a top tier of the FEOL layer. The NMOSFET and PMOSFET of the lower and upper active regions LAR and UAR are vertically stacked to form a three-dimensional stacked transistor. In one embodiment, the lower active region LAR is a PMOSFET region, and the upper active region UAR is an NMOSFET region. Each of the lower and upper active regions LAR and UAR has a bar shape or a line shape extending in a first direction D1.

[0033] The lower active region LAR includes a lower channel pattern LCH and a lower source / drain pattern LSD. The lower channel pattern LCH is interposed between a pair of lower source / drain patterns LSD. The lower channel pattern LCH connects the pair of lower source / drain patterns LSD to each other.

[0034] The lower channel pattern LCH includes a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked and spaced apart from each other. Each of the first and second semiconductor patterns SP1 and SP2 includes silicon (Si), germanium (Ge), or silicon germanium (SiGe). Preferably, each of the first and second semiconductor patterns SP1 and SP2 includes crystalline silicon. Each of the first and second semiconductor patterns SP1 and SP2 is a nano sheet. As an example, the lower channel pattern LCH further includes one or more semiconductor patterns stacked and spaced apart from the second semiconductor pattern SP2.

[0035] The lower source / drain patterns LSD are provided on the substrate 100. Each of the lower source / drain patterns LSD is an epitaxial pattern formed by a selective epitaxial growth (SEG) process. As an example, the upper surface of the lower source / drain pattern LSD is higher than the upper surface of the second semiconductor pattern SP2 of the lower channel pattern LCH.

[0036] The lower source / drain pattern LSD is doped with impurities to have a first conductivity type. The first conductivity type is N-type or P-type. In the present embodiment, the first conductivity type is P-type. The lower source / drain pattern LSD includes silicon (Si) and / or silicon germanium (SiGe).

[0037] A first interlayer insulating layer 110 is provided on the lower source / drain pattern LSD. The first interlayer insulating layer 110 covers the lower source / drain pattern LSD.

[0038] A lower active contact LAC is provided under the lower source / drain pattern LSD. The lower active contact LAC is electrically connected to the lower source / drain pattern LSD. The lower active contact LAC is embedded in the substrate 100. The lower active contact LAC extends vertically from the upper surface to the lower surface of the substrate 100. The lower active contact LAC includes a metal selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0039] An upper active region UAR is provided on the first interlayer insulating film 110. The upper active region UAR includes an upper channel pattern UCH and an upper source / drain pattern USD. The upper channel pattern UCH vertically overlaps with the lower channel pattern LCH. The upper source / drain patterns USD vertically overlap with the lower source / drain patterns LSD. The upper channel pattern UCH is interposed between a pair of upper source / drain patterns USD. The upper channel pattern UCH connects the pair of upper source / drain patterns USD to each other.

[0040] The upper channel pattern UCH includes a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 stacked at a distance from each other. The third and fourth semiconductor patterns SP3 and SP4 of the upper channel pattern UCH include the same semiconductor material as the first and second semiconductor patterns SP1 and SP2 of the lower channel pattern LCH described above. Each of the third and fourth semiconductor patterns SP3 and SP4 is a nano sheet. As an example, the upper channel pattern UCH further includes one or more semiconductor patterns stacked at a distance from the fourth semiconductor pattern SP4.

[0041] At least one dummy channel pattern DSP is interposed between the lower channel pattern LCH and the upper channel pattern UCH thereon. A seed layer SDL is interposed between the dummy channel pattern DSP and the upper channel pattern UCH.

[0042] The dummy channel pattern DSP is separated from the lower and upper source / drain patterns LSD, USD. That is, the dummy channel pattern DSP is not connected to any source / drain patterns. The dummy channel pattern DSP includes a semiconductor material such as silicon (Si), germanium (Ge), or silicon germanium (SiGe), or includes a silicon-based insulating material such as a silicon oxide film or a silicon nitride film. In one embodiment of the present invention, the dummy channel pattern DSP includes a silicon-based insulating material.

[0043] The upper source / drain patterns USD are provided on the upper surface of the first interlayer insulating film 110. Each of the upper source / drain patterns USD is an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the upper surface of the upper source / drain pattern USD is higher than the upper surface of the fourth semiconductor pattern SP4 of the upper channel pattern UCH.

[0044] The upper source / drain pattern USD is doped with an impurity to have a second conductivity type. The second conductivity type is different from the first conductivity type of the lower source / drain pattern LSD. The second conductivity type is N-type. The upper source / drain pattern USD includes silicon germanium (SiGe) and / or silicon (Si).

[0045] A plurality of gate electrodes GE are provided on the single height cell SHC. Specifically, the gate electrodes GE are provided on the stacked lower and upper channel patterns LCH, UCH. In a plan view, the gate electrodes GE have a bar shape extending in a second direction D2. The gate electrodes GE vertically overlap and cross the stacked lower and upper channel patterns LCH, UCH.

[0046] The gate electrodes GE are spaced apart from each other in a first direction D1 and a second direction D2. As an example, on one single height cell SHC, the gate electrodes GE are spaced apart from each other in the first direction D1. As an example, a plurality of gate electrodes GE arranged along the second direction D2 are defined as a gate group, and the plurality of gate groups are spaced apart from each other in the first direction D1.

[0047] The gate electrode GE extends in a vertical direction (i.e., a third direction D3) from the top surface of the substrate 100 to a gate capping pattern GP (described later). The gate electrode GE extends in the third direction D3 from a lower channel pattern LCH of the lower active region LAR to an upper channel pattern UCH of the upper active region UAR. The gate electrode GE extends in the third direction D3 from a lower first semiconductor pattern SP1 to an uppermost fourth semiconductor pattern SP4.

[0048] A gate electrode GE is provided on a top surface, a bottom surface, and both sidewalls of each of the first to fourth semiconductor patterns SP1-SP4. Again, the transistor according to the present embodiment includes a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel.

[0049] The gate electrode GE includes a lower gate electrode LGE provided in a lower tier of the FEOL layer, i.e., a lower active region LAR, and an upper gate electrode UGE provided in an upper tier of the FEOL layer, i.e., an upper active region UAR. The lower gate electrode LGE and the upper gate electrode UGE are vertically overlapped with each other. In one embodiment of the present invention, the lower gate electrode LGE and the upper gate electrode UGE are connected to each other. Again, the gate electrode GE according to this embodiment is a common gate electrode in which the lower gate electrode LGE on the lower channel pattern LCH and the upper gate electrode UGE on the upper channel pattern UCH are connected to each other.

[0050] The lower gate electrode LGE includes a first inner electrode PO1 interposed between the first lower insulating film LIL1 and the first semiconductor pattern SP1, a second inner electrode PO2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third inner electrode PO3 interposed between the second semiconductor pattern SP2 and the dummy channel pattern DSP.

[0051] The upper gate electrode UGE includes a fourth inner electrode PO4 interposed between the dummy channel pattern DSP (or the seed layer SDL) and the third semiconductor pattern SP3, a fifth inner electrode PO5 interposed between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and an outer electrode PO6 on the fourth semiconductor pattern SP4.

[0052] A pair of gate spacers GS are disposed on both side walls of the gate electrode GE, respectively. A pair of gate spacers GS are disposed on both side walls of the outer electrode PO6, respectively. The gate spacers GS extend in the second direction D2 along the gate electrode GE. An upper surface of the gate spacer GS is higher than an upper surface of the gate electrode GE. An upper surface of the gate spacer GS is coplanar with an upper surface of the second interlayer insulating film 120. The gate spacer GS includes at least one of SiCN, SiCON, and SiN. As another example, the gate spacer GS includes a multi-layer including at least two of SiCN, SiCON, and SiN.

[0053] A gate capping pattern GP is provided on an upper surface of the gate electrode GE. The gate capping pattern GP extends in a second direction D2 along the gate electrode GE. For example, the gate capping pattern GP may include at least one of SiON, SiCN, SiCON, and SiN.

[0054] A gate insulating film GI is interposed between the gate electrode GE and the first to fourth semiconductor patterns SP1 to SP4. The gate insulating film GI includes a silicon oxide film, a silicon oxynitride film, and / or a high dielectric film. In one embodiment of the present invention, the gate insulating film GI includes a silicon oxide film directly covering the surfaces of the semiconductor patterns SP1 to SP4 and a high dielectric film on the silicon oxide film. In other words, the gate insulating film GI includes a multi-layer of a silicon oxide film and a high dielectric film.

[0055] The high dielectric constant film includes a high dielectric constant material having a higher dielectric constant than silicon oxide, and by way of example, the high dielectric constant material includes at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0056] A second interlayer insulating layer 120 is provided on the upper source / drain pattern USD and the gate electrode GE. The second interlayer insulating layer 120 covers the upper source / drain pattern USD. A third interlayer insulating layer 130 covers the second interlayer insulating layer 120.

[0057] Upper active contacts UAC are provided to be electrically connected to the upper source / drain patterns USD through the second and third interlayer insulating layers 120 and 130. For example, the upper surfaces of the upper active contacts UAC are coplanar with the upper surface of the third interlayer insulating layer 130.

[0058] An upper gate contact UGC is provided, which is electrically connected to the upper gate electrode UGE through the third interlayer insulating film 130 and the gate capping pattern GP. Each of the upper active contact UAC and the upper gate contact UGC includes a metal selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0059] A cutting pattern CT crosses the gate groups arranged along a first direction D1. The cutting pattern CT extends in the first direction D1. The cutting pattern CT separates adjacent gate electrodes GE in the gate group from each other in the second direction D2. Adjacent gate electrodes GE are spaced apart in the second direction D2 by the cutting pattern CT. The cutting pattern CT includes an insulating material such as silicon oxide and silicon nitride.

[0060] A fourth interlayer insulating film 140 is provided on the third interlayer insulating film 130. A first metal layer M1 is provided in the fourth interlayer insulating film 140. The first metal layer M1 includes an upper wiring UMI. The first metal layer M1 further includes an upper via UVI. The upper via UVI electrically connects the upper wiring UMI to the upper active contact UAC or the upper gate contact UGC. Each of the upper wiring UMI and the upper via UVI includes a metal selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0061] Additional metal layers (e.g., M2, M3, M4, etc.) are stacked on the first metal layer M1. The first metal layer M1 and the metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 constitute a back end of line (BEOL) layer of the semiconductor device. The metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 include routing lines for connecting logic cells to each other.

[0062] A lower interlayer insulating film 210 is provided under the lower surface of the substrate 100. A lower gate contact LGC is provided between the lower interlayer insulating film 210 and the lower gate electrode LGE, and is electrically connected to the lower gate electrode LGE. A back metal layer BSM is provided in the lower interlayer insulating film 210. The back metal layer BSM includes a lower contact LC, a lower wiring LMI, and a lower via LVI. The lower contact LC is electrically connected to the lower source / drain pattern LSD through the lower active contact LAC. The lower via LVI electrically connects the lower wiring LMI to the lower active contact LAC, the lower contact LC, or the lower gate contact LGC.

[0063] Each of the lower gate contact LGC, the lower contact LC, the lower wiring LMI, and the lower via LVI includes a metal selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0064] An additional lower metal layer is laminated under the back metal layer BSM. In one embodiment of the present invention, the lower metal layer includes a power transmission network. The power transmission network includes a wiring network for applying a source voltage VSS and a drain voltage VDD to the back metal layer BSM.

[0065] A through via THV is provided in the cutting pattern CT. The through via THV electrically connects the vertically stacked lower source / drain pattern LSD and upper source / drain pattern USD. Specifically, the through via THV is electrically connected to the upper source / drain pattern USD through an upper active contact UAC, and is electrically connected to the lower source / drain pattern LSD through a lower contact LC and a lower active contact LAC. The through via THV includes a metal selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0066] A wide via WV is provided in the cutting pattern CT. The wide via WV extends from an upper surface to a lower surface of the cutting pattern CT and extends in a first direction D1 in a plan view. In a cross-sectional view, the wide via WV has an L-shaped profile. The wide via WV includes a metal selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0067] The top surface WVa of the wide via WV includes a first top surface W1a and a second top surface W2a located at a lower level than the first top surface W1a. The first top surface W1a is the top surface of the first via portion W1 of the wide via WV, and the second top surface W2a is the top surface of the second via portion W2 of the wide via WV. The first via portion W1 and the second via portion W2 are adjacent to each other in the first direction D1. As an example, the second top surface W2a is located at a lower level than the top surface of the upper active contact UAC.

[0068] The bottom surface WVb of the wide via WV is substantially flat. As an example, the first via portion W1 and the second via portion W2 have a first bottom surface W1b and a second bottom surface W2b, respectively, and the first bottom surface W1b and the second bottom surface W2b are located at substantially the same level. Therefore, the height HT2 of the second via portion W2 in a vertical direction (e.g., the third direction D3) is smaller than the height HT1 of the first via portion W1. As an example, the height HT2 of the second via portion W2 is 20% or more and 80% or less of the height HT1 of the first via portion W1.

[0069] The lower part of the wide via WV protrudes further in the first direction D1 than the upper part. The lower part of the wide via WV is the part located below the second upper surface W2a of the wide via WV, and the upper part of the wide via WV is the other part located above the second upper surface W2a. The lower part of the wide via WV includes the lower part of the first via part W1 and the second via part W2 of the wide via WV, and the upper part of the wide via WV includes the upper part of the first via part W1. The width of the wide via WV in the first direction D1 is larger at the lower part than at the upper part.

[0070] In a cross-sectional view, the wide via WV has a first side WVc oriented in a first direction D1. The first side WVc of the wide via WV includes a first sub-side W1c which is one side of the upper portion of the wide via WV (in other words, one side of the first via portion W1) and a second sub-side W2c which is one side of the lower portion of the wide via WV (in other words, one side of the second via portion W2). The second sub-side W2c is offset in the first direction D1 compared to the first sub-side W1c. Thus, the first side WVc of the wide via WV extends discontinuously in the third direction D3. As an example, the first sub-side W1c, the second upper surface W2a, and the second sub-side W2c of the wide via WV are connected to each other while forming a stepped profile.

[0071] The wide via WV has a second side WVd opposite to the first side WVc. The second side WVd includes the other side of the upper portion and the other side of the lower portion of the wide via WV, for example, the other side of the first via portion W1. The second side WVd of the wide via WV extends continuously in the third direction D3. As an example, the second side WVd of the wide via WV extends in a straight line in the third direction D3.

[0072] The wide via WV electrically connects the lower source / drain pattern LSD and the upper source / drain pattern USD, which are horizontally spaced apart from each other. Specifically, for example, the lower source / drain pattern LSD includes a first lower source / drain pattern LSD1 and a second lower source / drain pattern LSD2 spaced apart in a first direction D1, and the upper source / drain pattern USD includes a first upper source / drain pattern USD1 and a second upper source / drain pattern USD2 spaced apart in the first direction D1. The first upper source / drain pattern USD1 is vertically stacked on the first lower source / drain pattern LSD1, and the second upper source / drain pattern USD2 is vertically stacked on the second lower source / drain pattern LSD2. The first lower active contact LAC1 and the first lower contact LC1 are electrically connected to the first lower source / drain pattern LSD1 in sequence, and the first upper active contact UAC1 is electrically connected to the first upper source / drain pattern USD1. The second lower active contact LAC2 and the second lower contact LC2 are electrically connected to the second lower source / drain pattern LSD2, and the second upper active contact UAC2 is electrically connected to the second upper source / drain pattern USD2.

[0073] The wide via WV electrically connects the first upper source / drain pattern USD1 and the second lower source / drain pattern LSD2. Specifically, the wide via WV is electrically connected to the first upper source / drain pattern USD1 through the first upper active contact UAC1, and is electrically connected to the second lower source / drain pattern LSD2 through the second lower contact LC2 and the second lower active contact LAC2. The wide via WV is separated and electrically insulated from the second upper active contact UAC2 and the first lower contact LC1. For example, the second via portion W2 of the wide via WV is separated from the second upper active contact UAC2 in the second direction D2 and the third direction D3. Therefore, the wide via WV is electrically insulated from each of the second upper source / drain pattern USD2 and the first lower source / drain pattern LSD1.

[0074] For example, the first upper active contact UAC1 vertically overlaps the first via portion W1 of the wide via WV, and the second via portion W2 of the wide via WV vertically overlaps the second bottom contact LC2. For example, the first via portion W1 of the wide via WV does not vertically overlap the first bottom contact LC1, and the second upper active contact UAC2 does not vertically overlap the second via portion W2 of the wide via WV.

[0075] The third upper source / drain pattern USD3 and the third lower source / drain pattern LSD3 are arranged to be separated from the second upper source / drain pattern USD2 and the second lower source / drain pattern LSD2 through the wide via WV. The third lower active contact LAC3 and the third lower contact LC3 are electrically connected to the third lower source / drain pattern LSD3 in sequence, and the third upper active contact UAC3 is electrically connected to the third upper source / drain pattern USD3. The wide via WV is separated (e.g., horizontally separated) from the third upper active contact UAC3 and the third lower contact LC3 and is electrically insulated from them. Therefore, the wide via WV is electrically insulated from each of the third upper source / drain pattern USD3 and the third lower source / drain pattern LSD3.

[0076] The gate electrode GE is interposed between the first and second upper source / drain patterns USD1, USD2 and between the first and second lower source / drain patterns LSD1, LSD2. The wide via WV is disposed apart from the gate electrode GE in the second direction D2. In a plan view, the wide via WV is further extended in the first direction D1 and the opposite direction relative to the gate electrode GE.

[0077] The gate electrode GE and other gate electrodes GE adjacent to each other in the second direction D2 form a first gate group G1, and the wide via WV crosses the first gate group G1. As an example, the second via portion W2 of the wide via WV is extended in the first direction D1 to cross the first gate group G1.

[0078] In the first direction D1, the width L1 of the wide via WV is larger than the width L3 of the gate electrode GE. Thus, the wide via WV crosses the first gate group G1 and is electrically connected to the first upper active contact UAC1 and the second lower contact LC2. In the first direction D1, the width L1 of the wide via WV is the same as or different from the pitch L2 of the gate electrode GE. For example, in the first direction D1, the width L1 of the wide via WV is larger than the pitch L2 of the gate electrode GE.

[0079] The cutting pattern CT includes a first cutting portion C1 surrounding the wide via WV and a second cutting portion C2 covering at least a part of the upper surface WVa of the wide via WV. As an example, the first cutting portion C1 and the second cutting portion C2 have a boundary surface and are separated from each other, or are connected to each other without a boundary surface. As an example, the second cutting portion C2 covers the second upper surface W2a of the wide via WV, and the first cutting portion C1 surrounds the second cutting portion C2 of the wide via WV. The first cutting portion C1 separates the wide via WV from the first gate group G1. The second cutting portion C2 vertically overlaps the second via portion W2. Therefore, the upper portion of the cutting pattern CT including the second cutting portion C2 vertically overlaps the lower portion of the wide via WV. As an example, the upper surface of the cutting pattern CT is located at substantially the same level as the first upper surface W1a of the wide via WV, and is coplanar.

[0080] According to the concept of the present invention, the wide via WV is recessed in a region adjacent to the second upper active contact UAC2 to have a second upper surface W2a located at a relatively low level. Therefore, the separation distance between the wide via WV and the second upper active contact UAC2 is ensured, thereby preventing a short phenomenon between the wide via WV and the second upper active contact UAC2. Therefore, the electrical characteristics and reliability of the three-dimensional semiconductor device are improved.

[0081] In addition, the wide via WV electrically connects the lower and upper source / drain patterns LSD, USD (e.g., the second lower source / drain pattern LSD2 and the first upper source / drain pattern USD1) that are horizontally spaced apart from each other, thereby improving the design freedom of three-dimensional semiconductor devices.

[0082] Hereinafter, another embodiment of the present invention will be described with reference to Figures 6 to 9B. For the sake of simplicity, description of contents that overlap with the above will be omitted.

[0083] Fig. 6 is an enlarged view corresponding to P1 in Fig. 3. Figs. 7A and 7B are cross-sectional views taken along lines BB' and EE' in Fig. 3, respectively.

[0084] 3 and 6 to 7B, a wide via WV crosses a first gate group G1. As an example, unlike the description with reference to FIGS. 4 to 5E, a first via portion W1 of the wide via WV extends in a first direction D1 between gate electrodes GE of the first gate group G1. The first via portion W1 is spaced apart in a second direction D2 from the first gate group G1 by a cutting pattern CT.

[0085] 8 is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the present invention, and FIGs. 9A and 9B are enlarged views corresponding to P2 in FIG.

[0086] 3 and 8 to 9A, a fourth lower source / drain pattern LSD4 is provided between the first and second lower source / drain patterns LSD1, LSD2, and a fourth upper source / drain pattern USD4 is provided between the first and second upper source / drain patterns USD1, USD2. A fourth lower active contact (not shown) and a fourth lower contact LC4 are electrically connected to the fourth lower source / drain pattern LSD4, and a fourth upper active contact UAC4 is electrically connected to the fourth upper source / drain pattern USD4.

[0087] A first gate group G1 is disposed between the first and fourth lower source / drain patterns LSD1, LSD4 and between the first and fourth upper source / drain patterns USD1, USD4. A second gate group G2 is disposed between the second and fourth lower source / drain patterns LSD2, LSD4 and between the second and fourth upper source / drain patterns USD2, USD4. The fourth lower and upper source / drain patterns LSD4, USD4 are disposed between the first and second gate groups G1, G2.

[0088] The wide via WV is spaced apart from the fourth lower and upper source / drain patterns LSD4, USD4 in the second direction D2. The wide via WV is spaced apart from the fourth upper active contact UAC4 and the fourth lower contact LC4 in the second direction D2 and is electrically insulated. The wide via WV crosses two or more gate groups and is electrically connected to the first upper active contact UAC1 and the second lower contact LC2. As an example, the wide via WV crosses the first gate group G1 and the second gate group G2 and is electrically connected to the first upper active contact UAC1 and the second lower contact LC2. Therefore, the wide via WV electrically connects the lower and upper source / drain patterns LSD, USD horizontally spaced apart through two or more gate groups.

[0089] The arrangement of the first via portion W1 and the second via portion W2 of the wide via WV may be varied without limitation, provided that the second via portion W2 is disposed adjacent to the second lower and upper source / drain patterns LSD2 and USD2 compared to the first via portion W1.

[0090] 9A, the second via portion W2 extends in a first direction D1 between the first and second gate groups G1, G2 and is spaced in a second direction D2 from the first and second gate groups G1, G2 and the fourth lower and upper source / drain patterns LSD4, USD4. The first via portion W1 is spaced in the second direction D2 from the first lower and upper source / drain patterns LSD1, USD1 and extends in the first direction D1 toward the second via portion W2.

[0091] 9B, the first via portion W1 extends in the first direction D1 between the first gate group G1 and is spaced apart from the first gate group G1 in the second direction D2. The second via portion W2 extends in the first direction D1 between the second gate group G2 and is spaced apart from the second gate group G2 and the fourth lower and upper source / drain patterns LSD4 and USD4 in the second direction D2.

[0092] However, the positional relationship between the first via portion W1 and the second via portion W2 shown in FIGS. 9A and 9B is merely an example, and the concept of the present invention is not limited thereto.

[0093] 10A to 15D are diagrams for explaining a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. More specifically, FIGS. 10A, 11A, 12A, and 13A are cross-sectional views taken along line A-A' in FIG. 3. FIGS. 10B, 11B, 12B, 13B, 14A, and 15A are cross-sectional views taken along line B-B' in FIG. 3. FIGS. 10C, 11C, 12C, 13C, 14B, and 15B are cross-sectional views taken along line C-C' in FIG. 3. FIG. 15C is a cross-sectional view taken along line D-D' in FIG. 3. FIGS. 11D, 12D, 13D, 14C, and 15D are cross-sectional views taken along line E-E' in FIG. 3.

[0094] Hereinafter, a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention will be described with reference to Figures 10A to 15D. For simplicity, description of contents that overlap with the above will be omitted.

[0095] 10A to 10C, a semiconductor substrate 105 is provided. The semiconductor substrate 105 includes any one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the semiconductor substrate 105 is a single crystal silicon wafer.

[0096] A first lower insulating film LIL1 is formed on the semiconductor substrate 105. The first lower insulating film LIL1 includes a silicon-based insulating material (eg, silicon oxide) and / or a semiconductor material (Si or SiGe).

[0097] A first sacrificial layer SAL1 and a first active layer ACL1 are alternately laminated on a first lower insulating film LIL1. The first sacrificial layer SAL1 includes one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the first active layer ACL1 includes another one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the first sacrificial layer SAL1 includes silicon germanium (SiGe), and the first active layer ACL1 includes silicon (Si). The concentration of germanium (Ge) in each of the first sacrificial layers SAL1 is 10 at% to 30 at%.

[0098] A separation layer DSL is formed on the uppermost first sacrificial layer SAL1. In one embodiment of the present invention, the separation layer DSL has a thickness greater than that of the first sacrificial layer SAL1. The separation layer DSL includes silicon (Si) or silicon germanium (SiGe). When the separation layer DSL includes silicon germanium (SiGe), the concentration of germanium (Ge) in the separation layer DSL is higher than the concentration of germanium (Ge) in the first sacrificial layer SAL1. For example, the concentration of germanium (Ge) in the separation layer DSL is 40 at% to 90 at%.

[0099] A seed layer SDL is formed on the separation layer DSL. The seed layer SDL contains the same material as the first active layer ACL1. A second sacrificial layer SAL2 and a second active layer ACL2 are alternately stacked on the seed layer SDL. Each of the second sacrificial layers SAL2 contains the same material as the first sacrificial layer SAL1, and each of the second active layers ACL2 contains the same material as the first active layer ACL1. The separation layer DSL is interposed between the first sacrificial layer SAL1 and the seed layer SDL.

[0100] The stacked first and second sacrificial layers SAL1 and SAL2, the first and second active layers ACL1 and ACL2, and the separation layer DSL are patterned to form a stack pattern STP. Forming the stack pattern STP includes forming a hard mask pattern on the uppermost second active layer ACL2, and etching the stacked films SAL1, SAL2, ACL1, ACL2, SDL, and DSL on the semiconductor substrate 105 using the hard mask pattern as an etching mask. While the stack pattern STP is formed, the upper part of the semiconductor substrate 105 is patterned to form a first trench TR1 defining the single height cell SHC. The stack pattern STP has a bar shape or a line shape extending in a first direction D1.

[0101] The stacked pattern STP includes a lower stacked pattern STP1 on the first lower insulating film LIL1, an upper stacked pattern STP2 on the lower stacked pattern STP1, and an isolation layer DSL between the lower and upper stacked patterns STP1, STP2. The lower stacked pattern STP1 includes a first sacrificial layer SAL1 and a first active layer ACL1 that are alternately stacked. The upper stacked pattern STP2 includes a seed layer SDL and a second sacrificial layer SAL2 and a second active layer ACL2 that are alternately stacked on the seed layer SDL. An isolation film ST filling the first trench TR1 is formed on the semiconductor substrate 105.

[0102] 11A to 11D, a plurality of sacrificial patterns PP are formed across the stack pattern STP. Each of the sacrificial patterns PP is formed in a line shape extending in the second direction D2. In detail, forming the sacrificial patterns PP includes forming a sacrificial layer on the entire surface of the semiconductor substrate 105, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer includes amorphous silicon and / or polysilicon.

[0103] A pair of gate spacers GS are formed on both side walls of the sacrificial pattern PP. Specifically, a spacer film is conformally formed on the entire surface of the semiconductor substrate 105. The spacer film covers the sacrificial pattern PP and the hard mask pattern MP. For example, the spacer film includes at least one of SiCN, SiCON, and SiN. The spacer film is anisotropically etched to form the gate spacers GS.

[0104] An etching process is performed on the stack pattern STP using the gate spacer GS and the hard mask pattern MP as an etching mask. A second trench TR2 is formed between the adjacent sacrificial patterns PP by the etching process. The stack pattern STP is formed into a vertical bar shape by the second trench TR2.

[0105] A sacrificial contact pattern PLH is formed in the semiconductor substrate 105 exposed through the second trench TR2. The sacrificial contact pattern PLH is formed in the form of a contact plug. The sacrificial contact pattern PLH is arranged along a first direction D1. The sacrificial contact pattern PLH includes a material having etch selectivity with respect to the semiconductor substrate 105, for example, silicon-germanium (SiGe). The sacrificial contact pattern PLH is formed by an epitaxial growth process. The second trench TR2 exposes the sacrificial contact pattern PLH. Again, the second trench TR2 overlaps with the sacrificial contact pattern PLH.

[0106] In one embodiment of the present invention, when the isolation layer DSL includes silicon germanium (SiGe), the isolation layer DSL is replaced with a silicon-based insulating material. The isolation layer DSL exposed by the second trench TR2 is selectively removed, and the area where the isolation layer DSL is removed is filled with a silicon-based insulating material (e.g., silicon nitride).

[0107] 12A to 12D, a lower source / drain pattern LSD is formed in the second trench TR2. Specifically, a first SEG process is performed using the sidewall of the lower stack pattern STP1 exposed by the second trench TR2 as a seed layer to form the lower source / drain pattern LSD. The lower source / drain pattern LSD is grown using the first active layer ACL1 exposed by the second trench TR2 as a seed. For example, the first SEG process includes a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0108] During the first SEG process, impurities are implanted in-situ into the lower source / drain pattern LSD. Alternatively, after the lower source / drain pattern LSD is formed, impurities are implanted into the lower source / drain pattern LSD. The lower source / drain pattern LSD is doped to have a first conductivity type.

[0109] The first active layer ACL1 interposed between the pair of lower source / drain patterns LSD constitutes a lower channel pattern LCH. That is, first and second semiconductor patterns SP1 and SP2 of the lower channel pattern LCH are formed from the first active layer ACL1. The lower channel pattern LCH and the lower source / drain patterns LSD constitute a lower active region LAR, which is a lower tier of the three-dimensional device.

[0110] The lower source / drain pattern LSD is formed to completely fill the space between the pair of lower channel patterns LCH. Again, the first SEG process is performed for a sufficient time until the lower source / drain pattern LSD fills the space between the pair of lower channel patterns LCH and connects them to each other.

[0111] A first interlayer insulating film 110 is formed to cover the lower source / drain pattern LSD. For example, an etch stop film conformally covering the lower source / drain pattern LSD is further formed before the formation of the first interlayer insulating film 110. For example, before the formation of the lower source / drain pattern LSD, a portion of the first interlayer insulating film 110 is first formed under the lower source / drain pattern LSD, and after the formation of the lower source / drain pattern LSD, another portion of the first interlayer insulating film 110 is further formed.

[0112] The first interlayer insulating film 110 covers the sidewall of the upper stack pattern STP2 in the second trench TR2. Then, the upper portion of the first interlayer insulating film 110 is removed to expose the sidewall of the upper stack pattern STP2 in the second trench TR2 again. The upper source / drain pattern USD is formed on the exposed sidewall of the upper stack pattern STP2. Specifically, the upper source / drain pattern USD is formed by performing a second SEG process using the sidewall of the upper stack pattern STP2 exposed by the second trench TR2 as a seed layer. The upper source / drain pattern USD is grown using the second active layer ACL2 exposed by the second trench TR2 as a seed. The upper source / drain pattern USD is doped to have a second conductivity type different from the first conductivity type.

[0113] The second active layer ACL2 interposed between the pair of upper source / drain patterns USD constitutes the upper channel pattern UCH. That is, the third and fourth semiconductor patterns SP3, SP4 of the upper channel pattern UCH are formed from the second active layer ACL2. The upper channel pattern UCH and the upper source / drain patterns USD constitute an upper active region UAR, which is an upper tier of the three-dimensional device. The second SEG process is also performed for a sufficient time so that the upper source / drain patterns USD completely fill the space between the pair of upper channel patterns UCH.

[0114] A second interlayer insulating layer 120 is formed to cover the upper source / drain patterns USD. For example, before the formation of the second interlayer insulating layer 120, an etch stop layer is further formed to conformally cover the upper source / drain patterns USD.

[0115] The second interlayer insulating film 120 is planarized until the top surface of the sacrificial pattern PP is exposed. The planarization of the second interlayer insulating film 120 is performed using an etch back or CMP (Chemical Mechanical Polishing) process. During the planarization process, the hard mask pattern MP on the sacrificial pattern PP is entirely removed. As a result, the top surface of the second interlayer insulating film 120 is coplanar with the top surfaces of the sacrificial pattern PP and the gate spacer GS.

[0116] 13A to 13D, the exposed sacrificial pattern PP is selectively removed. The removal of the sacrificial pattern PP includes wet etching using an etchant that selectively etches polysilicon. As the sacrificial pattern PP is removed, the first and second sacrificial layers SAL1 and SAL2 are exposed.

[0117] An etching process is performed to selectively etch the first and second sacrificial layers SAL1, SAL2, leaving the first to fourth semiconductor patterns SP1-SP4 and the dummy channel pattern DSP as they are, and removing only the first and second sacrificial layers SAL1, SAL2. The etching process has a high etching rate for silicon-germanium. For example, the etching process has a high etching rate for silicon-germanium having a germanium concentration greater than 10 at %.

[0118] A gate insulating film GI is conformally formed in the region where the sacrificial pattern PP and the first and second sacrificial layers SAL1, SAL2 have been removed. A gate electrode GE is formed on the gate insulating film GI. The gate electrode GE is formed to include first to fifth inner electrodes PO1 to PO5 between the first to fourth semiconductor patterns SP1 to SP4, and an outer electrode PO6 in the region where the sacrificial pattern PP has been removed.

[0119] Forming the gate electrode GE includes filling a gate electrode line in an area where the sacrificial pattern PP and the first and second sacrificial layers SAL1 and SAL2 have been removed, forming a recess on an upper part of the gate capping line, forming the gate capping line in the recess, forming a third interlayer insulating film 130 to cover the gate electrode line and the second interlayer insulating film 120, and forming a cutting trench CTR crossing the gate electrode line in a first direction D1. The gate electrode line is separated into a plurality of gate electrodes GE by the cutting trench CTR, and the gate capping line is separated into a plurality of gate capping patterns GP. The cutting trench CTR is formed in a line shape extending in the first direction D1.

[0120] A first cutting portion C1 of the cutting pattern CT is formed in the cutting trench CTR. The first cutting portion C1 fills the cutting trench CTR. The first cutting portion C1 is formed to cross between the gate electrodes GE in a first direction D1.

[0121] 14A to 14D, a preliminary wide via WVp is formed in a first cutting portion C1 of a cutting pattern CT. The preliminary wide via WVp penetrates the first cutting portion C1 of the cutting pattern CT in a vertical direction (e.g., in a third direction D3). Forming the preliminary wide via WVp includes forming a first recess RS1 in the first cutting portion C1 of the cutting pattern CT and filling the first recess RS1 of the preliminary wide via WVp. As an example, a through via THV is formed together with the preliminary wide via WVp.

[0122] The top surface of the spare wide via WVp is flat. For example, the top surface of the spare wide via WVp is located at substantially the same level as the top surface of the first cutting portion C1 and is coplanar. For example, the spare wide via WVp completely fills the first recess RS1.

[0123] 15A to 15D, a portion of the preliminary wide via WVp is removed to form a wide via WV. A second recess RS2 is defined in the area where the portion of the preliminary wide via WVp has been removed. A first via portion W1 and a second via portion W2 of the wide via WV are defined by the second recess RS2. The second via portion W2 is a portion of the wide via WV that vertically overlaps the second recess RS2, and the first via portion W1 is another portion of the wide via WV outside the second via portion W2. The second recess RS2 is formed within the first recess RS1 and is defined by the wide via WV and a first cutting portion C1 of the cutting pattern CT.

[0124] As an example, the height HT2 of the second via portion W2 is 20% or more and 80% or less of the height HT1 of the first via portion W1. By providing the height HT2 of the second via portion W2 to be 20% or more of the height HT1 of the first via portion W1, the process becomes easier than when the second recess RS2 is formed deeper. By providing the height HT2 of the second via portion W2 to be 80% or less of the height HT1 of the first via portion W1, a short phenomenon between the second upper active contact UAC2 and the wide via WV is effectively prevented.

[0125] Depending on the formation regions of the first recess RS1 and the second recess RS2, the structures of the first via portion W1 and the second via portion W2 of the wide via WV may be formed in various ways as described with reference to Figures 3 to 9B. However, this is merely an example, and the structures of the first via portion W1 and the second via portion W2 of the wide via WV are not limited thereto.

[0126] 3 to 5E again, the second cutting portion C2 of the cutting pattern CT is formed in the second recess RS2. The second cutting portion C2 is formed on the second via portion W2 of the wide via WV and covers the second via portion W2. The second cutting portion C2 is formed to vertically overlap the second via portion W2.

[0127] An upper active contact UAC is formed to be connected to the upper source / drain patterns USD through the second and third interlayer insulating layers 120 and 130. As an example, a first upper active contact UAC1 is formed to be electrically connected to the first upper source / drain pattern USD1 and the wide via WV. An upper gate contact UGC is formed to be connected to the gate electrode GE through the second and third interlayer insulating layers 120 and 130.

[0128] A fourth interlayer insulating film 140 is formed on the third interlayer insulating film 130. A first metal layer M1 including an upper wiring UMI is formed in the fourth interlayer insulating film 140. An upper via UVI is formed to electrically connect the first metal layer M1 to the gate contact GC and the upper active contact UAC. BEOL layers including additional metal layers (e.g., M2, M3, M4, etc.) are formed on the first metal layer M1.

[0129] Thereafter, the semiconductor substrate 105 is inverted to expose the rear surface of the semiconductor substrate 105. The exposed semiconductor substrate 105 is selectively removed, thereby exposing the sacrificial contact pattern PLH and the first lower insulating layer LIL1.

[0130] A second lower insulating film LIL2 is formed on the exposed sacrificial contact pattern PLH and the exposed first lower insulating film LIL1. For example, the second lower insulating film LIL2 is formed of a silicon-based insulating material (for example, silicon oxide, silicon oxynitride, or silicon nitride). In one embodiment, the second lower insulating film LIL2 is formed of the same material as the device isolation film ST. The first lower insulating film LIL1 and the second lower insulating film LIL2 constitute the substrate 100. A planarization process is performed on the substrate 100 until the sacrificial contact pattern PLH is exposed.

[0131] The sacrificial contact pattern PLH is replaced with a lower active contact LAC. Specifically, the sacrificial contact pattern PLH is selectively removed. An etching process is further performed on the region where the sacrificial contact pattern PLH is removed to expose the lower source / drain pattern LSD. The lower active contact LAC is formed to connect to the exposed lower source / drain pattern LSD. The lower active contact LAC is formed in a self-aligned manner using the sacrificial contact pattern PLH. A lower gate contact LGC is formed to penetrate the substrate 100 and connect to the gate electrode GE.

[0132] A back metal layer BSM is formed on the lower active contact LAC. The back metal layer BSM includes a lower contact LC, a lower wiring LMI, and a lower via LVI. As an example, a second lower active contact LAC2 is formed to be electrically connected to the second lower source / drain pattern LSD2 and the wide via WV. An additional back metal layer is formed on the back metal layer BSM. In one embodiment of the present invention, the additional back metal layer includes a power transmission network.

[0133] The above description of the embodiments of the present invention provides examples for explaining the present invention. Therefore, the present invention is not limited to the above embodiments, and it is apparent that various modifications and changes can be made by those skilled in the art within the technical concept of the present invention, such as by combining and implementing the embodiments. [Explanation of symbols]

[0134] 100 Substrates 110, 120, 130, 140: first to fourth interlayer insulating films 210 Lower interlayer insulating film BSM back metal layer CT cutting pattern GE gate electrode LAC, UAC Lower and Upper Active Contacts LAR, UAR lower and upper active area LC Lower Contact LCH, UCH Lower and Upper Channel Patterns LGC, UGC Lower and upper gate contacts LGE, UGE lower and upper gate electrodes LMI, UMI Lower wiring and upper wiring LSD, USD Lower and Upper Source / Drain Patterns LVI, UVI bottom via and top via PLH Sacrificial Contact Pattern ST element separation membrane WV Wide Via

Claims

1. A back metal layer; a lower channel pattern on the back metal layer; a first lower source / drain pattern and a second lower source / drain pattern spaced apart in a first direction by the lower channel pattern; an upper channel pattern on the lower channel pattern; a first upper source / drain pattern on the first lower source / drain pattern; a second upper source / drain pattern on the second lower source / drain pattern; a wide via electrically connecting the first upper source / drain pattern and the second lower source / drain pattern; the first lower source / drain pattern is connected to the lower channel pattern; the first upper source / drain pattern is connected to the upper channel pattern; The wide via includes a first via portion having a first upper surface and a second via portion having a second upper surface located at a lower level than the first upper surface.

2. The three-dimensional semiconductor device of claim 1 , wherein in cross-section, the wide via has an L-shaped profile.

3. The first via portion has a first lower surface, the second via portion has a second lower surface; The three-dimensional semiconductor device of claim 1 , wherein the first lower surface and the second lower surface are located at the same level.

4. The first via portion has a first sub-side surface facing the first direction, the second via portion has a second sub-side surface facing the first direction, The three-dimensional semiconductor device of claim 1 , wherein the second sub-side is offset in the first direction from the first sub-side.

5. The three-dimensional semiconductor device of claim 1 , wherein the first via portion and the second via portion are arranged along the first direction.

6. The three-dimensional semiconductor device according to claim 1 , wherein the height of the second via portion is 20% or more and 80% or less of the height of the first via portion in the vertical direction.

7. a first upper active contact electrically connecting the first upper source / drain pattern and the wide via; a second upper active contact electrically connected to the second upper source / drain pattern and electrically insulated from the wide via; The three-dimensional semiconductor device of claim 1 , wherein the second top surface is located at a level lower than a top surface of the second upper active contact.

8. a gate electrode between the first upper source / drain pattern and the second upper source / drain pattern, The three-dimensional semiconductor device of claim 1 , wherein the wide via is spaced apart from the gate electrode in a second direction intersecting the first direction.

9. The three-dimensional semiconductor device of claim 8 , wherein a width of the wide via is greater than a width of the gate electrode in the first direction.

10. 10. The three-dimensional semiconductor device of claim 8, wherein the gate electrode comprises a plurality of gate electrodes spaced apart from each other in the first direction between the first upper source / drain pattern and the second upper source / drain pattern.

11. 2. The three-dimensional semiconductor device of claim 1, further comprising a fourth upper source / drain pattern between the first upper source / drain pattern and the second upper source / drain pattern.

12. Further comprising a cutting pattern surrounding the wide via, The three-dimensional semiconductor device of claim 1 , wherein the cutting pattern covers the second upper surface of the second via portion.

13. A back metal layer; a lower channel pattern on the back metal layer; a first lower source / drain pattern and a second lower source / drain pattern spaced apart in a first direction by the lower channel pattern; an upper channel pattern on the lower channel pattern; a first upper source / drain pattern on the first lower source / drain pattern; a second upper source / drain pattern on the second lower source / drain pattern; a wide via electrically connecting the first upper source / drain pattern and the second lower source / drain pattern; the first lower source / drain pattern is connected to the lower channel pattern; the first upper source / drain pattern is connected to the upper channel pattern; A three-dimensional semiconductor device, wherein a lower portion of the wide via protrudes in the first direction more than an upper portion of the wide via.

14. The three-dimensional semiconductor device of claim 13 , wherein one side of the wide via extends discontinuously in a vertical direction and the other side of the wide via extends continuously in the vertical direction.

15. the top portion of the wide via has a first sub-side facing a first direction; the lower portion of the wide via has a second sub-side facing in a first direction; The three-dimensional semiconductor device of claim 13 , wherein the second sub-side is offset in the first direction from the first sub-side.

16. The three-dimensional semiconductor device of claim 13 , wherein a width of the bottom of the wide via is greater than a width of the top of the wide via in the first direction.

17. a first upper active contact electrically connecting the first upper source / drain pattern and the wide via; a second upper active contact electrically connected to the second upper source / drain pattern and electrically insulated from the wide via; The three-dimensional semiconductor device of claim 13 , wherein an upper surface of the lower portion of the wide via is positioned at a lower level than an upper surface of the second upper active contact.

18. The three-dimensional semiconductor device of claim 13, further comprising one or more gate electrodes between the first upper source / drain pattern and the second upper source / drain pattern.

19. Further comprising a cutting pattern surrounding the wide via, The three-dimensional semiconductor device of claim 13 , wherein the cutting pattern vertically overlaps the bottom of the wide via.

20. A back metal layer; a lower channel pattern and an upper channel pattern disposed in sequence on the rear metal layer; a gate electrode across the lower and upper channel patterns; a first lower source / drain pattern connected to the lower channel pattern in a first direction; a first upper source / drain pattern connected to the upper channel pattern in the first direction on the first lower source / drain pattern; a cutting pattern adjacent to the gate electrode in a second direction intersecting the first direction; a wide via located within the cutting pattern and electrically connected to the first upper source / drain pattern; The three-dimensional semiconductor device, wherein the cutting pattern covers a portion of an upper surface of the wide via.

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