Circuit board and manufacturing method thereof

Abstract

To provide a circuit board and a manufacturing method thereof that allow the thickness of the circuit board to be reduced by controlling the height of a conductive layer.SOLUTION: A circuit board 100 includes a substrate 110 having a first surface including a first region and a second region that are different from each other, a connection pad 120 disposed in the first region and having a first height measured in a direction perpendicular to the first surface, circuit wirings 130, 140 disposed in the second region and including a different metal layer and having a second height higher than the first height, and an insulating pattern layer 151 covering the circuit wiring in the second region and protruding from the first surface to have a step with the first region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit board and a manufacturing method thereof, and more particularly to a circuit board capable of reducing the thickness of the circuit board and a manufacturing method thereof. [Background technology]

[0002] Today's semiconductor technology is experiencing continuous innovation in terms of performance and size. Recent trends in packaging technology are focused on improving connection speed and integrating a variety of functions. Additionally, the rise of mobile devices and wearable electronic products has increased the need for smaller sizes and thinner packages.

[0003] The small size and thin thickness of the package provide two main advantages. First, it makes mobile devices more portable and wearable. This creates an environment where consumers can use and connect their devices more conveniently. Second, it allows for improved thermal management and energy efficiency, and allows for more functionality to be integrated. Small package sizes optimize heat distribution and power consumption to improve product performance and sustainability. In order to achieve a thinner semiconductor package, it is essential to reduce the thickness of a printed circuit board on which various electronic elements are integrated and on which a multi-layer circuit pattern is provided. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems with conventional circuit boards, and an object of the present invention is to provide a circuit board and a method for manufacturing the circuit board, which can reduce the thickness of the circuit board by controlling the height of the conductive layer in order to achieve a thinner semiconductor package. [Means for solving the problem]

[0005] The circuit board according to the present invention, which has been made to achieve the above-mentioned object, is characterized by comprising a substrate having a first surface including a first region and a second region that are different from each other, a connection pad disposed in the first region and having a first height measured in a direction perpendicular to the first surface, a circuit wiring disposed in the second region and including a different metal layer and having a second height higher than the first height, and an insulating pattern layer covering the circuit wiring in the second region and protruding from the first surface to have a step with the first region.

[0006] It is preferable that the connection pads and the circuit wiring protrude from the first surface. The circuit wiring preferably includes a copper layer and a nickel layer. The circuit wiring is preferably formed by laminating a first copper layer, a nickel layer, and a second copper layer in this order. The height of the first copper layer is preferably the same as the height of the connection pads. The connection pads preferably comprise copper. The substrate and the insulating pattern layer preferably comprise different insulating materials. The insulating pattern layer is preferably a solder resist layer. It is preferable that the circuit wiring includes a signal wiring and a connection portion, and the insulating pattern layer is opened so as to expose an upper surface of the connection portion. The first region and the second region are preferably adjacent to each other. Preferably, said first region provides a recess surrounded by said insulating pattern layer arranged in said second region. An electronic element is preferably disposed in the first region, and the electronic element is configured to be connected to the connection pad.

[0007] In order to achieve the above-mentioned object, a manufacturing method for a circuit board according to the present invention includes the steps of forming a first conductive layer from a first metal on a first surface of a substrate having a seed layer, forming a second conductive layer from a second metal different from the first metal on the first conductive layer, forming a third conductive layer from the first metal on the second conductive layer, dividing the first surface into a first region and a second region which are different from each other and removing the second conductive layer and the third conductive layer arranged in the first region, removing a portion of the seed layer where the first conductive layer is not formed to form a connection pad in the first region and forming a circuit wiring in the second region, and forming an insulating pattern layer covering the circuit wiring in the second region.

[0008] It is preferable that the step of forming the first conductive layer includes a step of applying and patterning a first plating resist and plating with the first metal, the step of forming the second conductive layer includes a step of plating with the second metal, and the step of forming the third conductive layer includes a step of plating with the first metal. The step of removing the second conductive layer and the third conductive layer preferably includes the step of covering the second region with a second plating resist to expose the first region. Preferably, the insulating pattern layer is not formed in the first region. Effect of the Invention

[0009] According to the circuit board and manufacturing method thereof of the present invention, the height of the conductive layer located on the board can be controlled to be different between the area where the electronic elements are mounted and the other areas, thereby reducing the thickness of the circuit board and achieving a thinner semiconductor package. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a schematic configuration of an electronic element package in a state in which an electronic element is mounted on a circuit board according to an embodiment of the present invention. [Diagram 2]2A to 2C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Diagram 3] 2A to 2C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 4] 2A to 2C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Diagram 5] 2A to 2C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 6] 2A to 2C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 7] 2A to 2C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 8] 2A to 2C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 9] 2A to 2C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 10] 2A to 2C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 11] 2A to 2C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, specific examples of embodiments for carrying out the circuit board and the manufacturing method thereof according to the present invention will be described with reference to the drawings.

[0012] In the drawings, in order to clearly explain the present invention, parts unnecessary for the explanation are omitted, and the same reference numerals are used for the same or similar components throughout the specification. In addition, in the accompanying drawings, some components are exaggerated, omitted, or illustrated diagrammatically, and the size of each component does not entirely reflect the actual size. The attached drawings are merely intended to facilitate understanding of the embodiments disclosed in this specification, and the attached drawings do not limit the technical ideas disclosed in this specification, and it should be understood that the attached drawings include all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention.

[0013] Terms including ordinal numbers, such as first, second, etc., are used to describe various elements, but the elements are not limited by the terms. The terms are used only to distinguish one component from another. In addition, when a part such as a layer, film, region, or plate is said to be "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when one part is said to be "directly above" another, it means that there is no other part in between. Furthermore, being "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the direction opposite to gravity.

[0014] Throughout the specification, the use of terms such as "comprise" or "have" is intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth in the specification, and should be understood as not precluding the presence or additional possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Thus, when a part is said to "comprise" certain elements, this does not exclude other elements and means that it may further include other elements, unless specifically stated to the contrary.

[0015] Also, throughout the specification, a reference to "in a plane" means when the subject part is viewed from above, and a reference to "in cross section" means when the subject part is cut vertically and viewed from the side. Furthermore, throughout the specification, when the term "connected" is used, this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected via other components, or that they are not only physically connected but also electrically connected, or that they are referred to by different names depending on their location or function but are integrated.

[0016] FIG. 1 is a cross-sectional view showing a schematic configuration of an electronic element package in a state in which an electronic element is mounted on a circuit board according to an embodiment of the present invention. Referring to FIG. 1, an electronic device package is configured by mounting an electronic device 80 on a circuit board 100 according to an embodiment of the present invention.

[0017] The electronic device 80 may include a variety of devices, such as active devices, passive devices, and integrated circuits (ICs), and may be, for example, a semiconductor chip. The circuit board 100 is used for a semiconductor package and is made up of a printed circuit board. The circuit board 100 includes a substrate 110, connection pads 120 protruding on the substrate 110, and circuit traces (130, 140). The substrate 110 has a first surface 110a and a second surface 110b facing each other, and the first surface 110a is divided into a first region A1 and a second region A2 which are different from each other. The connection pads 120 are disposed in a first area A1 on the first surface 110a, and the circuit wiring (130, 140) is disposed in a second area A2 on the first surface 110a.

[0018] On the first surface 110a of the substrate 110, the first region A1 and the second region A2 may be adjacent to each other. The first region A1 is located in the center on the plane of the first surface 110a, and the second region A2 is located on both sides of the first region A1, but the present invention is not limited to this. The relative positions of the first area A1 and the second area A2 may be selected in various ways depending on the design of the electronic device package.

[0019] The substrate 110 includes a resin insulating layer. The substrate 110 may be made of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin impregnated with a reinforcing material such as glass fiber or an inorganic filler, for example, a prepreg, and may also include, but is not limited to, a thermosetting resin and / or a photocurable resin. In the embodiment shown in the figures, one side of the substrate 110 is shown to include connection pads 120 and circuit traces (130, 140), but this is not limited thereto and the substrate may include more insulating layers and more circuit patterns, which also fall within the scope of the present invention.

[0020] The connection pads 120 and the circuit traces (130, 140) protrude from the first surface 110a of the substrate 110. The circuit wiring (130, 140) is formed higher than the connection pad 120 in terms of height measured from the first surface 110a in a direction perpendicular thereto. That is, the connection pad 120 has a first height h1, and the circuit wiring (130, 140) has a second height h2, with the second height h2 being greater than the first height h1.

[0021] The circuitry (130, 140) having the second height h2 may include dissimilar metal layers. The circuit wiring (130, 140) includes copper (Cu) layers (131, 133, 141, 143) and nickel (Ni) layers (132, 142). The circuit wiring (130, 140) is formed by laminating a first copper layer (131, 141), a nickel layer (132, 142), and a second copper layer (133, 143) in this order from the first surface 110a of the substrate 110. That is, the circuit wiring (130, 140) has a laminated structure of Cu / Ni / Cu. At this time, the height of the first copper layer (131, 141) in contact with the first surface 110a is greater than the height of the nickel layer (132, 142) or the second copper layer (133, 143).

[0022] The connection pad 120 having the first height h1 is made of a single metal layer. The connection pad 120 includes a copper layer, which has the same height as the first copper layer (131, 141) of the circuit traces (130, 140). That is, the first copper layers (131, 141) of the circuit wiring (130, 140) and the connection pad 120 have the same first height h1. On the first side 110a of the substrate 110, in the second area A2, an insulating pattern layer 151 is arranged. The insulating pattern layer 151 is configured to cover the circuit traces (130, 140) and comprises an insulating material different from that of the substrate 110. The insulating pattern layer 151 may include a solder resist layer. The insulating pattern layer 151 made of a solder resist layer serves as a protective layer for protecting the circuitry on the outermost layer, and is formed for electrical insulation. The insulating pattern layer 151 made of a solder resist layer can be made of, for example, a solder resist ink, a solder resist film, or an encapsulant, according to techniques known in the art, but is not limited thereto.

[0023] The insulating pattern layer 151 is applied in the second area A2 and has a step with the first area A1. The insulating pattern layer 151 is applied to a height higher than the height of the circuit wiring (130, 140) in the second area A2, and is not applied in the first area A1. Therefore, a step having a difference in height of the insulating pattern layer 151 is formed between the first region A1 and the second region A2. On the first surface 110a of the substrate 110, the first region A1 is surrounded by the second region A2. At this time, the insulating pattern layer 151 is applied to the second region A2 to form a step with the first region A1, so that the first region A1 provides a recess 154 surrounded by the insulating pattern layer 151. The circuit wiring ( 130 , 140 ) covered with the insulating pattern layer 151 includes a signal wiring portion 130 and a connection portion 140 . The upper surface 143a of the connection portion 140 is at least partially exposed so as to be connected to an external circuit or the like. The insulating pattern layer 151 is partially opened to expose the upper surface 143a of the connection portion 140, forming an opening 151a.

[0024] The electronic element 80 is disposed in the first area A1 and is connected to the connection pad 120 so as to be electrically connected to the circuit board 100. The electronic element 80 is bonded to the connection pad 120 through a conductive connection member 126, for example a solder ball. The first region A1 is formed of a recess 154 having an area larger than at least the plane area of ​​the electronic element 80 . The electronic element 80 is therefore accommodated in a recess 154 provided in the first area A1. The connection pads 120 arranged in the first area A1 are lower than the circuit traces (130, 140) arranged in the second area A2 or the insulating pattern layer 151 applied to the second area A2. Therefore, the electronic element 80 that connects to the connection pad 120 is disposed with a portion of its thickness in a direction perpendicular to the substrate 110 within the recess 154 . That is, the lower end of the electronic device 80 partially overlaps with the upper end of the insulating pattern layer 151 in a direction perpendicular to the substrate 110, thereby reducing the overall thickness of the electronic device package.

[0025] 2 to 11 are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. As shown in FIGS. 2 and 3, a first plating resist 61 is applied onto a first surface 110a of a substrate 110 having a seed layer 111, and after patterning, a first conductive layer 121 is formed from a first metal. The first plating resist 61 is patterned by leaving the portions on which the connection pads 120 or the circuit wirings (130, 140) are not to be formed and removing the remaining portions. The substrate 110 includes a resin insulating layer. The substrate 110 may be made of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin impregnated with a reinforcing material such as glass fiber or an inorganic filler, for example, a prepreg, and may include, but is not limited to, a thermosetting resin and / or a photocurable resin.

[0026] After the first plating resist 61 is patterned, a plating process is performed on the exposed seed layer 111 to form a first conductive layer 121 . The seed layer 111 and the first conductive layer 121 are made of the same first metal material, which contains copper (Cu). The first conductive layer 121 is plated onto the exposed portions of the seed layer 111 and is integral with the seed layer 111 . When measuring the height from the first surface 110 a of the substrate 110 in a direction perpendicular thereto, the portion where the first conductive layer 121 is located is higher than the seed layer 111 covered with the first plating resist 61 .

[0027] Referring to FIG. 4, a second conductive layer 122 is formed on a first conductive layer 121 using a second metal. The second metal is made of a material different from the first metal and contains nickel (Ni). The second conductive layer 122 is formed by plating on the first conductive layer 121 exposed by the first plating resist 61, and has the same width as the first conductive layer 121.

[0028] Referring to FIG. 5, a third conductive layer 123 is formed on the second conductive layer 122 using a first metal. The third conductive layer 123 is made of the first metal, and is therefore made of the same material as the first conductive layer 121 . The third conductive layer 123 is formed by plating on the second conductive layer 122 exposed by the first plating resist 61 , and has the same width as the second conductive layer 122 .

[0029] Referring to FIG. 6, a first surface 110a of a substrate 110 is divided into a first region A1 and a second region A2, which are different from each other, and the second region A2 is covered with a second plating resist 65. A second plating resist 65 is applied onto the first surface 110a of the substrate 110 on which the first conductive layer 121, the second conductive layer 122, and the third conductive layer 123 have been formed, and is patterned to divide the first region A1 and the second region A2. The second plating resist 65 applied to the first region A1 is removed by patterning. Therefore, the third conductive layer 123 disposed in the first region A1 is exposed to the outside. The first area A1 is reserved as an area in which electronic elements are mounted. For example, the first region A1 is disposed in the center on the plane of the first surface 110a, the second regions A2 are disposed on both sides of the first region A1, and electronic elements are mounted in the first region A1.

[0030] 7 and 8, the second conductive layer 122 and the third conductive layer 123 disposed in the first region A1 are removed. With the second region A2 covered with the second plating resist 65, a copper etchant is applied to remove the third conductive layer 123 in the first region A1 (see FIG. 7). At this time, the second conductive layer 122 is made of nickel and serves as an etching barrier against a copper etchant. Thereafter, with the second region A2 covered with the second plating resist 65, a nickel etchant is applied to remove the second conductive layer 122 in the first region A1 (see FIG. 8). At this time, the first conductive layer 121 is made of copper and serves as an etching barrier against the nickel etching solution. In the first region A1, when the second conductive layer 122 and the third conductive layer 123 are removed, the first conductive layer 121 is exposed to the outside. The first conductive layer 121 forms the connection pads 120 (see FIG. 10) by removing the seed layer 111 covered with the first plating resist 61.

[0031] Referring to FIG. 9, the first plating resist 61 and the second plating resist 65 are removed. The first conductive layer 121 is formed on the seed layer 111 by patterning the first plating resist 61, and therefore, is connected to each other via the seed layer 111.

[0032] Referring to FIG. 10, the portion of the seed layer 111 where the first conductive layer 121 is not formed is removed. The seed layer 111 is removed from the substrate 110 through quick etching. When the seed layer 111 is removed in this manner, the first conductive layer 121 arranged in the first region A1 forms the connection pad 120, and the first conductive layer 121, the second conductive layer 122, and the third conductive layer 123 arranged in the second region A2 form the circuit wiring (130, 140). The connection pad 120 is formed by integrally bonding a first conductive layer 121 and the underlying seed layer 111 together. The circuit wiring (130, 140) is formed by sequentially stacking a first conductive layer 121, a second conductive layer 122, and a third conductive layer 123 on a seed layer 111. The height of the connection pad 120 can be adjusted by the plating amount of the first conductive layer 121. For example, the connection pads 120 have a height in the range of 2-3 μm, and the circuit traces (130, 140) have a height of approximately 15 μm.

[0033] Referring to FIG. 11, an insulating pattern layer 151 is patterned and formed in the second area A2. The insulating pattern layer 151 comprises an insulating material different from that of the substrate 110 and includes a solder resist. The insulating pattern layer 151 is not formed in the first area A1. The insulating pattern layer 151 is formed by applying a solder resist onto the first surface 110a of the substrate 110 and removing the solder resist applied in the first area A1. The circuit wiring (130, 140) includes a signal wiring portion 130 and a connection portion 140, and an opening 151a is formed by partially removing the insulating pattern layer 151 corresponding to the upper surface of the connection portion 140. The insulating pattern layer 151 made of a solder resist layer serves as a protective layer for protecting the circuitry on the outermost layer, and is formed for electrical insulation. The insulating pattern layer 151 made of a solder resist layer can be made of, for example, a solder resist ink, a solder resist film, or an encapsulant, according to techniques known in the art, but is not limited thereto.

[0034] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0035] 80 Electronic elements 100 Circuit Board 110 Substrate 111 Seed layer 120 Connection Pad 121 First conductive layer 122 Second conductive layer 123 Third conductive layer 126 Conductive connecting member 130 (Circuit wiring) Signal wiring section 140 (Circuit Wiring) Connection 131, 141 First copper layer 132, 142 Nickel layer 133, 143 Second copper layer 151 Insulation pattern layer 154 Recess

Claims

1. A substrate having a first surface including a first region and a second region that are distinct from each other; a connection pad disposed in the first area and having a first height measured in a direction perpendicular to the first surface; a circuit wiring disposed in the second region, the circuit wiring including a different metal layer, the circuit wiring having a second height greater than the first height; an insulating pattern layer covering the circuit wiring in the second region and protruding from the first surface to have a step with the first region.

2. 2. The circuit board according to claim 1, wherein the connection pads and the circuit wiring protrude from the first surface.

3. The circuit board according to claim 1 , wherein the circuit wiring includes a copper layer and a nickel layer.

4. 4. The circuit board according to claim 3, wherein the circuit wiring is formed by laminating a first copper layer, a nickel layer, and a second copper layer in sequence.

5. 5. The circuit board according to claim 4, wherein the height of the first copper layer is the same as the height of the connection pads.

6. 2. The circuit board of claim 1, wherein the connection pads comprise copper.

7. 2. The circuit board of claim 1, wherein the substrate and the insulating pattern layer comprise different insulating materials.

8. 8. The circuit board according to claim 7, wherein the insulating pattern layer is a solder resist layer.

9. the circuit wiring includes a signal wiring and a connection portion; 2. The circuit board according to claim 1, wherein the insulating pattern layer is opened to expose an upper surface of the connection portion.

10. The circuit board according to claim 1 , wherein the first region and the second region are adjacent to each other.

11. 11. The circuit board of claim 10, wherein the first region provides a recess surrounded by the insulating pattern layer disposed in the second region.

12. An electronic element is disposed in the first region; The circuit board of claim 1 , wherein the electronic elements are configured to be connected to the connection pads.

13. forming a first conductive layer of a first metal on a first surface of a substrate having a seed layer; forming a second conductive layer on the first conductive layer, the second conductive layer being made of a second metal different from the first metal; forming a third conductive layer on the second conductive layer using the first metal; dividing the first surface into a first region and a second region that are different from each other, and removing the second conductive layer and the third conductive layer disposed in the first region; removing a portion of the seed layer where the first conductive layer is not formed to form a connection pad in the first region and to form a circuit wiring in the second region; forming an insulating pattern layer covering the circuit wiring in the second region.

14. forming the first conductive layer includes applying a first plating resist, patterning the first plating resist, and plating the first conductive layer with the first metal; forming the second conductive layer includes plating the second metal; The method of claim 13, wherein the forming of the third conductive layer comprises plating the third conductive layer with the first metal.

15. 14. The method of claim 13, wherein removing the second conductive layer and the third conductive layer comprises covering the second region with a second plating resist to expose the first region.

16. The method of claim 13, wherein the insulating pattern layer is not formed in the first region.

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