Method and apparatus for applying ECC to memory in artificial neural network based system semiconductor

Abstract

To provide a method for applying ECC to a memory in an artificial neural network based system semiconductor.SOLUTION: A method for applying ECC to a memory in an artificial neural network-based system semiconductor according to an embodiment of the present invention includes steps of: dividing memory cells into first to n-th groups of memory cell arrays corresponding to first to n-th frames based on word lines (n is a natural number greater than or equal to 2); performing ECC write or read operation by applying an error correction code (ECC) to a memory cell array of a group corresponding to each of the first to n-th frames; and performing general write or read operation without application of the error correction code to the memory cell array of remaining groups excluding the group corresponding to each of the first to n-th frames.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an object recognition system used in a semiconductor artificial neural network-based system, and more particularly to a method and apparatus for applying ECC to a memory in a semiconductor artificial neural network-based system. [Background technology]

[0002] A common method for improving the failure rate of memories used in semiconductor artificial neural network based systems is to use Error Correction Code (ECC) in the memories.

[0003] ECC is a method that uses check bits when storing data in memory. An ECC code that represents the bit order for each data unit is calculated and stored with the data. When reading a data unit, the ECC code is regenerated using the read data, and the regenerated ECC code is compared with the read ECC code to determine whether there is a data error.

[0004] In conventional ECC application technology, when ECC is used, additional memory space is allocated to check for data errors. This has the disadvantage of increasing the ECC memory space. When ECC is used using the SEC-DEC (Single Error Detection Double Error Detection) method, the number of check bits generated per data unit is 6 bits per 16 bits, 7 bits per 32 bits, 8 bits per 64 bits, and 9 bits per 128 bits. The memory space required for adding check bits is 38%, 22%, 13%, and 7% for 16 bits, 32 bits, 64 bits, and 128 bits, respectively.

[0005] On the other hand, in the prior art, a method for mitigating the effects of failures in adjacent memory cells can be used in which a first ECC circuit receives information from even memory cells and a second ECC circuit receives information from odd memory cells. Therefore, although such first and second ECC circuits can mitigate the effects of failures by using non-adjacent memory cells, it can be said that adding an ECC circuit necessarily increases the memory area. Summary of the Invention [Problem to be solved by the invention]

[0006] Embodiments of the present invention provide a method and apparatus for applying ECC to memories in an artificial neural network-based system semiconductor for efficient ECC application in consideration of diagnostic coverage and area in an artificial neural network-based system semiconductor.

[0007] However, the problem to be solved by the present invention is not limited thereto, and may be expanded in various environments without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0008] According to an embodiment of the present invention, there may be provided a method for applying ECC to a memory in a system semiconductor based on an artificial neural network, the method including the steps of: dividing memory cells into first through n-th groups of memory cell arrays corresponding to first through n-th frames based on word lines (n is a natural number equal to or greater than 1); performing an ECC write or read operation applying an error correction code (ECC) to the memory cell arrays of the group corresponding to each frame for each of the first through n-th frames; and performing a general write or read operation without applying an ECC to the memory cell arrays of the remaining groups excluding the group corresponding to each of the first through n-th frames for each of the first through n-th frames.

[0009] The number of times that the ECC write or read operation and the general write or read operation can be applied can be adjusted according to a fault handing time interval (FTTI) time and a frame processing time.

[0010] In the ECC write operation, an ECC code is generated by an ECC encoder based on write data in a memory cell array of a group corresponding to each frame selected by an address decoder based on a word line, the write data is stored in memory, and the generated ECC code can be stored in an ECC memory.

[0011] In the ECC read operation, after the address decoder regenerates the ECC code in the memory cell array of the group corresponding to each frame selected based on the word line, the regenerated ECC code can be compared with the ECC code read from the ECC memory.

[0012] The step of performing the ECC write or read operation may apply an error correction code to a group of memory cell arrays corresponding to each frame selected based on the least significant bit (LSB) of the address decoder input information.

[0013] The step of performing the general write or read operation may perform a write or read operation with an error detection parity bit added to the memory cell arrays of the remaining groups excluding the group corresponding to each frame for each of the first to nth frames.

[0014] The step of performing the general write or read operation can detect whether there is an error by calculating the number of bits by combining the read data and parity bit of the selected word line based on the least significant bit of the address decoder input information in the memory cell array of the remaining groups excluding the group corresponding to each frame.

[0015] Meanwhile, according to another embodiment of the present invention, there may be provided an apparatus for applying ECC to a memory in an ANN-based system semiconductor, the apparatus comprising: memory cells for storing data generated in the ANN-based system semiconductor; an ECC memory for storing ECC codes associated with an ECC write or read operation; a storage module for storing one or more programs; and a processor for executing the one or more stored programs, wherein the processor divides the memory cells into first through n-th groups of memory cell arrays corresponding to first through n-th frames based on word lines (n is a natural number equal to or greater than 2), and performs an ECC write or read operation applying an error correction code (ECC) to the memory cell arrays of the group corresponding to each frame for each of the first through n-th frames, and performs a normal write or read operation without applying an ECC to the memory cell arrays of the remaining groups excluding the group corresponding to each of the first through n-th frames for each of the first through n-th frames.

[0016] The number of times that the ECC write or read operation and the general write or read operation can be applied can be adjusted according to a fault handing time interval (FTTI) time and a frame processing time.

[0017] In the ECC write operation, an ECC code is generated by an ECC encoder based on write data in a memory cell array of a group corresponding to each frame selected by an address decoder based on a word line, the write data is stored in memory, and the generated ECC code can be stored in an ECC memory.

[0018] In the ECC read operation, after the address decoder regenerates the ECC code in the memory cell array of the group corresponding to each frame selected based on the word line, the regenerated ECC code can be compared with the ECC code read from the ECC memory.

[0019] The processor can apply an error correction code to a group of memory cell arrays corresponding to each frame selected based on the least significant bit (LSB) of the address decoder input information.

[0020] The processor may perform a write or read operation for each of the first to nth frames, adding a parity bit for error detection to the memory cell arrays of the remaining groups excluding the group corresponding to each frame.

[0021] The processor can detect whether there is an error by calculating the number of bits by combining the read data of the selected word line and the parity bit based on the least significant bit of the address decoder input information in the memory cell array of the remaining groups excluding the group corresponding to each frame. [Effects of the Invention]

[0022] The disclosed technology can have the following effects. However, this does not mean that a particular embodiment should include all or only the following effects, and therefore the scope of the disclosed technology should not be understood to be limited thereby.

[0023] Embodiments of the present invention can apply efficient ECC in artificial neural network-based system semiconductors with considerations of diagnostic coverage and area.

[0024] Embodiments of the present invention can improve the additional ECC memory area that occurs using ECC by selectively applying ECC to a group of memory cell arrays corresponding to a frame.

[0025] Embodiments of the present invention take into account memory usage strategies used in semiconductor artificial neural network-based systems, and can reduce the additional memory space required when using ECC.

[0026] Embodiments of the present invention can further reduce the memory area by applying ECC to memory cells to the maximum extent possible, taking into account the frame processing time interval of an artificial neural network that can be processed within a vehicle-level Fault Handling Time Interval (FTTI).

[0027] The embodiments of the present invention can reduce memory consumption by adjusting the number of ECC applications according to the FTTI time and frame processing time.

[0028] Embodiments of the present invention can improve memory latency by performing selective ECC encoding on a frame-by-frame basis during write operations in a memory cell array, thereby reducing the ECC decoding work required during read operations by half. [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 illustrates a semiconductor architecture for an artificial neural network based system in which an embodiment of the present invention may be used. [Figure 2] 1 is a flowchart illustrating a method for applying ECC to a memory in a system semiconductor based on an artificial neural network according to an embodiment of the present invention. [Figure 3] 1A and 1B are diagrams illustrating examples of write and read operations using an ECC application method for a memory according to an embodiment of the present invention. [Figure 4]1A and 1B are diagrams illustrating examples of write and read operations using an ECC application method for a memory according to an embodiment of the present invention. [Figure 5] FIG. 10 shows an example truth table for an address decoder used in one embodiment of the present invention. [Figure 6A] 10A and 10B are diagrams illustrating selective ECC write and read operations in a method for applying ECC to a memory according to an embodiment of the present invention. [Figure 6B] 10A and 10B are diagrams illustrating selective ECC write and read operations in a method for applying ECC to a memory according to an embodiment of the present invention. [Figure 7A] 10A and 10B are diagrams illustrating selective ECC write and read operations in a method for applying ECC to a memory according to an embodiment of the present invention. [Figure 7B] 10A and 10B are diagrams illustrating selective ECC write and read operations in a method for applying ECC to a memory according to an embodiment of the present invention. [Figure 8A] 10A and 10B are diagrams illustrating selective ECC write and read operations using a parity bit in a method for applying ECC to a memory according to an embodiment of the present invention. [Figure 8B] 10A and 10B are diagrams illustrating selective ECC write and read operations using a parity bit in a method for applying ECC to a memory according to an embodiment of the present invention. [Figure 9A] 10A and 10B are diagrams illustrating selective ECC write and read operations using a parity bit in a method for applying ECC to a memory according to an embodiment of the present invention. [Figure 9B] 10A and 10B are diagrams illustrating selective ECC write and read operations using a parity bit in a method for applying ECC to a memory according to an embodiment of the present invention. [Figure 10] 1 is a block diagram of an ECC application device for memory in a system semiconductor based on an artificial neural network according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0030] The present invention can be modified in various ways and can have various embodiments, and specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to the specific embodiments, and it can be understood that the present invention includes all modifications, equivalents, and alternatives that fall within the technical spirit and scope of the present invention. In describing the present invention, if it is determined that detailed descriptions of related publicly known technologies may obscure the gist of the present invention, such detailed descriptions will be omitted.

[0031] Terms such as "first" and "second" may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0032] The terms used in the present invention are merely used to describe specific embodiments and are not intended to limit the present invention. The terms used in the present invention are generally selected based on current widespread usage, taking into account the functions of the present invention. However, these terms may change depending on the intentions of those skilled in the art, legal precedents, or the emergence of new technologies. In addition, in certain cases, the applicant may arbitrarily select terms, and in such cases, the meanings of these terms will be described in detail in the relevant description of the invention. Therefore, the terms used in the present invention should be defined based on the meanings of the terms and the overall content of the present invention, rather than simply by their names.

[0033] The singular expression includes the plural expression unless the context clearly indicates otherwise. In the present invention, the terms "comprise" or "have" and the like are intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should be understood not to preclude the presence or additional possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0034] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, identical or corresponding components will be given the same reference numerals, and redundant description thereof will be omitted.

[0035] FIG. 1 is a diagram illustrating the architecture of a semiconductor artificial neural network based system in which an embodiment of the present invention may be used.

[0036] First, an ECC application device for a memory according to an embodiment of the present invention is intended to reduce the memory area generated by adding check bits when using ECC.

[0037] As shown in FIG. 1, a system semiconductor based on an artificial neural network for recognizing objects in an artificial neural network comprises an NPU cluster (Neural Processing Unit cluster) 110, an AXI (Advanced eXtensible Interface) 120, and a memory 130 made of DRAM.

[0038] The NPU cluster 110 is composed of an NPU core 111, a buffer memory 112, and a DMA (113). Data received from the camera is stored in memory 130. This data is transferred to the buffer memory 112 in the NPU core 111, which allows the NPU core 111 to calculate successive images, and the results are transferred to memory 130 again.

[0039] This method processes continuous image data. Because this data is stored in memory 130, any corruption of the data in memory 130 will result in a drop in the object recognition rate. However, because the data is processed continuously, a momentary memory failure will only affect one frame, but a permanent memory defect will cause a sustained drop in the object recognition rate.

[0040] Therefore, ECC memory protection is essential to prevent a decline in object recognition rate in artificial neural networks. However, improving object recognition performance requires multi-processing cores, which in turn increases memory capacity, resulting in a continuous increase in chip size. As the ECC memory area for memory protection also continues to increase, a method to reduce it is essential.

[0041] To solve this problem, an ECC application device according to an embodiment of the present invention can improve the additional ECC memory area generated by using ECC by selectively applying ECC to a group of memory cell arrays corresponding to a frame.

[0042] FIG. 2 is a flowchart illustrating a method for applying ECC to a memory in a system semiconductor based on an artificial neural network according to an embodiment of the present invention.

[0043] In step S101, the ECC application device divides memory cells into a plurality of groups of memory cell arrays corresponding to first to n-th frames based on word lines.

[0044] In step S102, the ECC application device checks whether the memory cell array is in the group corresponding to the current frame.

[0045] In step S103, the ECC application device performs an ECC write or read operation applying an error correction code to the memory cell array of the group corresponding to each frame if the memory cell array is in the group corresponding to the current frame.

[0046] In step S104, if the memory cell array is not in the group corresponding to the current frame, the ECC application device performs a general write operation without applying an error correction code to the memory cell arrays in the remaining groups excluding the group corresponding to each frame.

[0047] As described above, the ECC application device according to an embodiment of the present invention selectively controls word lines (WL) that turn on / off transistors in memory cells to reduce the number of memory cells to which ECC is applied. An address decoder applies the ECC code only to memory cell arrays (e.g., one specific row) selected, and does not apply the ECC code to unselected memory cell arrays. Although data error detection cannot be performed on unselected memory cell arrays, applying the ECC code to unselected memory cell arrays during processing of the next frame allows detection of all memory cell arrays.

[0048] Here, when the ECC application device according to an embodiment of the present invention selectively applies ECC to a portion of the memory cell array, it can apply ECC to all memory cells within a vehicle-level Fault Handing Time Interval (FTTI).

[0049] Here, FTTI represents the minimum time range from the occurrence of a vehicle defect to the occurrence of a possible hazardous event if the vehicle safety mechanism is not activated. The minimum time range must be evaluated for all hazardous events because it can vary depending on the characteristics of the hazard. FTTI is associated with a hazard that occurs due to a vehicle malfunction and can be used as an attribute associated with a safety goal derived from the hazard. If the vehicle remains in a safe state, switches to a safe state, or switches to emergency operation within the associated FTTI, the defect can be handled in a timely manner by the safety mechanism. The occurrence of a hazardous event depends on the existing defect and the scenario in which the defect can affect vehicle behavior.

[0050] To illustrate an example of ECC operation in a memory cell taking FTTI into consideration, assuming that the vehicle-level FTTI is 100 ms and an artificial neural network can process 30 frames per second, the interval for processing one frame is 33 ms. Therefore, the entire memory cell array can apply selective ECC codes a total of three times within the FTTI of 100 ms. An ECC application device according to an embodiment of the present invention can reduce the ECC memory area to which ECC codes are applied by one-third. Alternatively, if the vehicle-level FTTI is 200 ms and an artificial neural network can process 30 frames per second, the ECC code can be applied up to six times within the FTTI of 200 ms. In this case, an ECC application device according to an embodiment of the present invention can reduce the ECC memory area to which ECC codes are applied by one-sixth. In this way, the number of ECC application times at which ECC write or read operations and general write or read operations can be applied can be adjusted depending on the FTTI time and frame processing time. As a result, the adjusted number of ECC application times can produce an ECC memory reduction effect.

[0051] 3 and 4 are diagrams illustrating examples of write and read operations in which an ECC application method for a memory according to an embodiment of the present invention is used.

[0052] First, an ECC code is generated by an ECC encoder based on write data, the write data is stored in a memory, and the ECC code is stored in an ECC memory.

[0053] 3 and 4 show examples in which memory cells are alternately divided based on word lines, and ECC operations are selectively applied alternately based on the word lines to perform write and read operations. As an example, the ECC application device may divide all memory cells into even-numbered memory cell arrays and odd-numbered memory cell arrays based on word lines. The ECC application device may apply the ECC operation to even-numbered memory cell arrays in even frames and odd-numbered memory cell arrays in odd frames. Here, the memory cells are not limited to being divided into a specific number. Taking into account vehicle-level Fast Transition Time (FTTI), all memory cells may be divided into n groups of memory cell arrays (n is a natural number greater than or equal to 2).

[0054] During a write operation, the ECC application device stores data in a memory area and stores an ECC code in an ECC memory according to an ECC address location. The input address is passed through an address decoder to select the address to be stored. The ECC application device uses a selective ECC application method in which ECC operation is applied only to word lines N+1, N+3, ... during the first write operation, and only to word lines N, N+2, ... during the write operation of the next frame.

[0055] When generating an ECC code, the ECC application device uses a selective ECC method in which an address decoder generates an ECC code for WL_0 based on the word line (WL) and does not generate an ECC code for WL_1. This selective ECC application method is selectively applied to the entire memory cell area, up to WL_N, thereby reducing the ECC memory used in the entire memory cell area by half.

[0056] The ECC application device also applies the same method to read operations, where the address decoder regenerates an ECC code from the memory read on WL_0 based on the word line WL and compares it with the read ECC code, and the ECC application device reads the memory on WL_1 directly through a normal read operation without ECC comparison, i.e., without applying ECC.

[0057] By performing the above operation, the memory area according to the ECC code can be reduced by half. If the memory cells are divided into n groups of memory cell arrays, the memory area can be reduced by 1 / n. In addition, the ECC application device can reduce the latency incurred in decoding the encoded ECC code.

[0058] Here, ECC codes are used to detect and correct memory errors, but if the ECC code covers only half of the memory area, it can be determined that the effectiveness of error detection and correction is reduced by half.

[0059] On the other hand, memories used in semiconductor systems based on artificial neural networks are updated every frame and perform new write and read operations. Therefore, an ECC application device can detect errors in all memories every two frames by applying ECC to word lines that could not be ECC-operated in the next frame.

[0060] FIG. 5 shows an example truth table for an address decoder used in one embodiment of the present invention.

[0061] When an ECC-applied device uses an n-bit address decoder, it can use 2^n outputs as word lines. For example, in the case of a 3x8 address decoder, the truth table is as shown in Figure 5.

[0062] In the truth table shown in Figure 5, when C, which is the least significant bit of the LSB (LSB), is used as a reference, 0 and 1 are alternated. Therefore, when ECC operations are applied alternately based on word lines, the ECC application device can apply ECC operations only to word lines whose LSB is 0 in the first input frame, and only to word lines whose LSB is 1 in the second frame.

[0063] 6A, 6B, 7A, and 7B are diagrams illustrating selective ECC write and read operations in a method for applying ECC to a memory according to an embodiment of the present invention.

[0064] First, the ECC write and read operations shown in Figures 6A, 6B, 7A, and 7B illustrate an example of detecting errors in all memories every two frames. The ECC application device checks the least significant bit (LSB) of address decoder input information through the address decoder every odd and even frames, and selectively applies the ECC operation to the memory cell array of the odd or even word line corresponding to the least significant bit (LSB) based on the word line.

[0065] As shown in FIGS. 6A and 6B, in step S201, the ECC application device starts a write operation to the memory.

[0066] In step S202, the ECC application device checks the frame number (#) of the data for the write operation.

[0067] In step S203, the ECC application device checks the least significant bit (LSB) of the address decoder input information through the address decoder when the frame number (#) is #N+0, #N+2, . . .

[0068] In step S204, if the least significant bit (LSB) is 0 (LSB=0), the ECC application device encodes ECC data #0 using the current address and data.

[0069] In step S205, the ECC application device stores the data in the memory and stores the calculated ECC data in the ECC memory. In this way, the ECC application device performs ECC operations on the memory cell array when the least significant bit (LSB) is 0 (LSB=0).

[0070] On the other hand, in step S206, the ECC application device stores data in memory if the least significant bit (LSB) is 1 (LSB=1). In this way, if the least significant bit (LSB) is 1 (LSB=1), the ECC application device performs a general write operation on the memory cell array without performing an ECC operation.

[0071] On the other hand, in step S207, if the frame number (#) is #N+1, #N+3, . . . , the ECC application device checks the least significant bit (LSB) through the address decoder.

[0072] In step S208, if the least significant bit (LSB) is 1 (LSB=1), the ECC application device encodes ECC data #1 using the current address and data.

[0073] In step S209, the ECC application device stores the data in the memory and stores the calculated ECC data in the ECC memory. In this way, the ECC application device performs ECC operations on the memory cell array when the least significant bit (LSB) is 1 (LSB=1).

[0074] On the other hand, in step S210, the ECC application device stores data in memory if the least significant bit (LSB) is 0 (LSB=0). In this way, if the least significant bit (LSB) is 0 (LSB=0), the ECC application device performs a general write operation on the memory cell array without performing an ECC operation.

[0075] Then, in step S211, the ECC application device completes the write operation to the memory cells after steps S205, S206, S209, and S210.

[0076] In this way, in the case of a write operation, the ECC application device checks the frame number (frame #) information, and then performs ECC encoding on word lines whose LSB is 0 in even frames, and can store only data on word lines whose LSB is 1.

[0077] Conversely, in the case of a write operation, the ECC application device performs an ECC encoding operation on word lines whose LSB is 1 in odd frames, and stores only data on word lines whose LSB is 0.

[0078] Meanwhile, as shown in FIGS. 7A and 7B, in step S301, the ECC application device starts a memory read operation.

[0079] In step S302, the ECC application device checks the frame number (#) of the data for the read operation.

[0080] In step S303, the ECC application device checks the least significant bit (LSB) of the address decoder input information through the address decoder when the frame number (#) is #N+0, #N+2, . . .

[0081] In step S304, if the least significant bit (LSB) is 0 (LSB=0), the ECC application device reads the data from the memory and reads ECC data #0 from the ECC memory.

[0082] In step S305, the ECC application device regenerates ECC data #2 using the data read from the memory and the current address.

[0083] In step S306, the ECC application device compares the read ECC data #0 with the regenerated ECC data #2.

[0084] In step S307, the ECC application device checks whether the data read from the memory is non-defective data or defective data that requires one or two bits to be corrected.

[0085] In step S308, if correction of one or two bits is required, the ECC application device performs a data correction operation for the bit.

[0086] On the other hand, in step S309, the ECC application device reads the data from the memory if the least significant bit (LSB) is 1 (LSB=1).

[0087] Meanwhile, in step S310, if the frame number (#) is #N+1, #N+3, . . . , the ECC application device checks the least significant bit (LSB) through the address decoder.

[0088] In step S311, if the least significant bit (LSB) is 1 (LSB=1), the ECC application device reads data from the memory and reads ECC data #1 from the ECC memory.

[0089] In step S312, the ECC application device regenerates ECC data #3 using the data read from the memory and the current address.

[0090] In step S313, the ECC application device compares the read ECC data #1 with the regenerated ECC data #3.

[0091] In step S314, the ECC applicator checks whether the data read from the memory is non-defective data or defective data that requires one or two bits to be corrected.

[0092] In step S315, if correction of one or two bits is required, the ECC application device performs a data correction operation for the bit.

[0093] On the other hand, in step S316, the ECC application device reads the data in the memory if the least significant bit (LSB) is 0 (LSB=0).

[0094] Then, in step S317, the ECC application device completes the read operation on the memory cells after steps S308, S309, S315, and S316.

[0095] In this way, in the case of a read operation, the ECC application device checks the frame number (frame #) information, and then performs ECC decoding operations on word lines whose LSB is 0 in even frames, and can only load data on word lines whose LSB is 1.

[0096] Conversely, in the case of a read operation, the ECC application device can perform an ECC decoding operation on word lines whose LSB is 1 in odd frames and load data only on word lines whose LSB is 0.

[0097] 6A, 6B, 7A, and 7B, the error detection and correction effect can be maintained for all memory cells within the vehicle-level FTTI. However, the error detection and correction effect may be reduced in certain frames. Therefore, an embodiment of the present invention using a parity bit that can improve the reduced error detection and correction effect in certain frames will be described with reference to FIGS. 8A, 8B, 9A, and 9B.

[0098] 8A, 8B, 9A, and 9B are diagrams illustrating selective ECC write and read operations using parity bits in a method for applying ECC to a memory according to an embodiment of the present invention.

[0099] As shown in FIGS. 8A and 8B, in step S401, the ECC application device starts a write operation to the memory.

[0100] In step S402, the ECC application device checks the frame number (#) of the data for the write operation.

[0101] In step S403, the ECC application device checks the least significant bit (LSB) of the address decoder input information through the address decoder when the frame number (#) is #N+0, #N+2, . . .

[0102] In step S404, if the least significant bit (LSB) is 0 (LSB=0), the ECC application device encodes ECC data #0 using the current address and data.

[0103] In step S405, the ECC application device stores the data in the memory and stores the calculated ECC data in the ECC memory. In this way, the ECC application device performs ECC operations on the memory cell array when the least significant bit (LSB) is 0 (LSB=0).

[0104] On the other hand, in step S406, the ECC application device calculates the parity bit if the least significant bit (LSB) is 1 (LSB=1).

[0105] In step S407, the ECC application device stores the data and the calculated parity bit in the memory. In this way, when the least significant bit (LSB) is 1 (LSB=1), the ECC application device stores the data and the parity bit without performing an ECC operation on the memory cell array.

[0106] On the other hand, in step S408, if the frame number (#) is #N+1, #N+3, . . . , the ECC application device checks the least significant bit (LSB) through the address decoder.

[0107] In step S409, if the least significant bit (LSB) is 1 (LSB=1), the ECC application device encodes ECC data #1 using the current address and data.

[0108] In step S410, the ECC application device stores the data in the memory and stores the calculated ECC data in the ECC memory. In this way, the ECC application device performs an ECC operation on the memory cell array when the least significant bit (LSB) is 1 (LSB=1).

[0109] On the other hand, in step S411, the ECC application device calculates the parity bit if the least significant bit (LSB) is 0 (LSB=0).

[0110] In step S412, the ECC application device stores the data and the calculated parity bit in the memory. In this way, if the least significant bit (LSB) is 0 (LSB=0), the ECC application device stores the data and the parity bit without performing an ECC operation on the memory cell array.

[0111] Then, in step S413, the ECC application device completes the write operation to the memory cell.

[0112] Then, in step S413, the ECC application device completes the write operation to the memory cells after steps S405, S407, S410, and S412.

[0113] In this way, the ECC application device applies ECC operation only to word lines whose least significant bit (LSB) is 0 in the first frame and adds a parity bit to word lines whose least significant bit (LSB) is 1. This improves the error detection effect for word lines to which ECC operation is not applied. However, parity protection using the parity bit detects errors in data cells but does not correct them. However, the ECC application device improves the error correction effect for word lines that are not covered by the data cells of the first frame by the ECC operation effect, and adds only one check bit, thereby minimizing memory area.

[0114] Meanwhile, as shown in FIGS. 9A and 9B, in step S501, the ECC application device starts a memory read operation.

[0115] In step S502, the ECC application device checks the frame number (#) of the data for the read operation.

[0116] In step S503, the ECC application device checks the least significant bit (LSB) of the address decoder input information through the address decoder when the frame number (#) is #N+0, #N+2, . . .

[0117] In step S504, if the least significant bit (LSB) is 0 (LSB=0), the ECC application device reads the data from the memory and reads ECC data #0 from the ECC memory.

[0118] In step S505, the ECC application device regenerates ECC data #2 using the data read from the memory and the current address.

[0119] In step S506, the ECC application device compares the read ECC data #0 with the regenerated ECC data #2.

[0120] In step S507, the ECC application device checks whether the data read from the memory is non-defective data or defective data that requires one or two bits to be corrected.

[0121] In step S508, if correction of one or two bits is required, the ECC application device performs a data correction operation for the bit.

[0122] On the other hand, in step S509, the ECC application device reads the data from the memory if the least significant bit (LSB) is 1 (LSB=1).

[0123] In step S510, the ECC application device compares the data read from the memory with the parity bits.

[0124] In step S511, the ECC application device compares the data with the parity bit and checks whether the data read from the memory is a data reject.

[0125] In step S512, if the data read from the memory is data reject, the ECC application device rejects the data. If the data read from the memory is not data reject, the ECC application device ends the read operation.

[0126] On the other hand, in step S513, if the frame number (#) is #N+1, #N+3, . . . , the ECC application device checks the least significant bit (LSB) through the address decoder.

[0127] In step S514, if the least significant bit (LSB) is 1 (LSB=1), the ECC application device reads the data from the memory and reads ECC data #1 from the ECC memory.

[0128] In step S515, the ECC application device regenerates ECC data #3 using the data read from the memory and the current address.

[0129] In step S516, the ECC application device compares the read ECC data #1 with the regenerated ECC data #3.

[0130] In step S517, the ECC applicator checks whether the data read from the memory is non-defective data or defective data that requires one or two bits to be corrected.

[0131] In step S518, if correction of one or two bits is required, the ECC application device performs a data correction operation for the bit.

[0132] On the other hand, in step S519, the ECC application device reads the data from the memory if the least significant bit (LSB) is 0 (LSB=0).

[0133] In step S520, the ECC application device compares the data read from the memory with the parity bits.

[0134] In step S521, the ECC application device compares the data with the parity bit and checks whether the data read from the memory is a data reject.

[0135] In step S522, if the data read from the memory is data reject, the ECC application device rejects the data. If the data read from the memory is not data reject, the ECC application device ends the read operation.

[0136] Then, in step S523, the ECC application device completes the read operation on the memory cells after steps S508, S512, S518, and S522.

[0137] In this way, the ECC application device checks frame number information during a read operation and then performs ECC decoding on word lines whose least significant bit (LSB) is 0 in even frames. The ECC application device can then calculate the number of bits by combining data and parity bits for word lines whose least significant bit (LSB) is 1, and check for data errors.

[0138] FIG. 10 is a block diagram of an apparatus for applying ECC to a memory in a system semiconductor based on an artificial neural network according to an embodiment of the present invention.

[0139] 10, an ECC application device 200 for a memory according to an embodiment of the present invention includes memory cells 210, an ECC memory 220, a storage module 230, and a processor 240. However, not all of the components shown are required. The ECC application device 200 may be realized with more or fewer components than those shown.

[0140] The specific configuration and operation of each component of the ECC application device 200 in FIG. 10 will now be described.

[0141] The memory cell 210 stores data generated in a semiconductor based artificial neural network system.

[0142] The ECC memory 220 stores ECC codes associated with ECC write or read operations.

[0143] The storage module 230 stores one or more programs related to the ECC application method for memory in a system semiconductor based on an artificial neural network.

[0144] The processor 240 executes one or more programs stored in the storage module 230. The processor 240 divides memory cells into first through nth groups of memory cell arrays (n is a natural number equal to or greater than 2) corresponding to first through nth frames based on word lines, and performs an ECC write or read operation applying an ECC to the memory cell arrays of the group corresponding to each frame for each of the first through nth frames, and performs a general write or read operation not applying an ECC to the memory cell arrays of the remaining groups excluding the group corresponding to each frame for each of the first through nth frames.

[0145] According to the embodiment, the number of ECC applications to which the ECC write or read operation and the general write or read operation can be applied can be adjusted according to a fault handling time interval (FTTI) time and a frame processing time.

[0146] According to the embodiments, in an ECC write operation, an ECC code is generated by an ECC encoder based on write data in a memory cell array of a group corresponding to each frame selected by an address decoder based on a word line, the write data is stored in a memory, and the generated ECC code can be stored in an ECC memory.

[0147] According to embodiments, in an ECC read operation, after the address decoder regenerates the ECC code in the memory cell array of the group corresponding to each frame selected based on the word line, the regenerated ECC code can be compared with the ECC code read from the ECC memory.

[0148] According to some embodiments, the processor 240 may apply an error correction code to a group of memory cell arrays corresponding to each frame selected based on the least significant bit (LSB) of the address decoder input information.

[0149] According to the embodiment, for each of the first to nth frames, the processor 240 can perform a write or read operation in which a parity bit for error detection is added to the memory cell array of the remaining groups excluding the group corresponding to each frame.

[0150] According to an embodiment, the processor 240 can detect whether there is an error by calculating the number of bits by combining the read data and parity bit of the selected word line based on the least significant bit of the address decoder input information in the memory cell array of the remaining groups excluding the group corresponding to each frame.

[0151] In this way, the ECC application device 200 according to one embodiment of the present invention can reduce the additional memory space required when using ECC operations by taking into account the memory usage method used in a system semiconductor based on an artificial neural network.

[0152] The ECC application device 200 according to an embodiment of the present invention can reduce the additional memory area required when applying the ECC operation by half by selectively applying the ECC operation based on the word line of the memory. In addition, when considering an application in which the memory is updated every frame, the ECC application device 200 can detect failures in all memory areas within a frame (e.g., two frames, three frames, etc.) within the FTTI.

[0153] The ECC application device 200 according to one embodiment of the present invention can further reduce the memory area required when considering the frame processing time interval of an artificial neural network that can be processed within a vehicle-level Fault Handling Time Interval (FTTI).

[0154] The ECC application device 200 according to an embodiment of the present invention can improve memory latency by reducing the decoding work generated after ECC encoding by half.

[0155] Meanwhile, according to one embodiment of the present invention, the various embodiments described above may be implemented as software including instructions stored in a machine-readable storage medium. The machine is a device that can access instructions stored in the storage medium and operate according to the accessed instructions, and may include an electronic device (e.g., electronic device (A)) according to the disclosed embodiments. When instructions are executed by a processor, the processor may perform the function corresponding to the instructions directly or using other components under the control of the processor. The instructions may include code generated or executed by a compiler or interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, "non-transitory" means that the storage medium does not include a signal and is tangible, and does not distinguish between data being stored semi-permanently or temporarily on the storage medium.

[0156] Furthermore, according to an embodiment of the present invention, the methods according to the various embodiments described above may be provided as being included in a computer program product. The computer program product may be traded as a commodity between a seller and a buyer. The computer program product may be distributed in the form of a device-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)) or online via an application store (e.g., Play Store™). In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored in a storage medium such as the memory of a manufacturer's server, an application store server, or an intermediary server, or may be temporarily generated.

[0157] Furthermore, according to one embodiment of the present invention, the various embodiments described above may be implemented in a recording medium readable by a computer or similar device using software, hardware, or a combination thereof. In some cases, the embodiments described herein may be implemented in a processor itself. In a software implementation, the procedures and functions described herein may be implemented in separate software modules. Each of the software modules may perform one or more of the functions and operations described herein.

[0158] Meanwhile, computer instructions for performing the processing operations of the devices according to the various embodiments described above may be stored in a non-transitory computer-readable medium. When executed by a processor of a particular device, the computer instructions stored in such a non-transitory computer-readable medium cause the particular device to perform the processing operations of the device according to the various embodiments described above. A non-transitory computer-readable medium refers to a medium that stores data semi-permanently and can be read by a device, rather than a medium that stores data for a short period of time, such as a register, cache, or memory. Specific examples of non-transitory computer-readable media include CDs, DVDs, hard disks, Blu-ray discs, USBs, memory cards, and ROMs.

[0159] Furthermore, each of the components (e.g., modules or programs) according to the various embodiments described above may be composed of one or more entities, and some of the subcomponents described above may be omitted, or other subcomponents may be further included in various embodiments. Generally or additionally, some components (e.g., modules or programs) may be integrated into a single entity to perform the same or similar functions as those performed by the respective components before integration. Operations performed by modules, programs, or other components according to the various embodiments may be performed sequentially, in parallel, iteratively, or heuristically, or at least some operations may be performed in a different order, omitted, or other operations may be added.

[0160] While the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and various modifications may be made by a person having ordinary skill in the art to which the disclosure pertains without departing from the gist of the present invention as claimed in the claims. Such modifications should not be understood individually from the technical ideas and perspectives of the present invention. [Explanation of symbols]

[0161] 100 Artificial Neural Network-Based Systems Semiconductors 110 NPU 120 AXI 130 memory 111 NPU cores 112 buffer memory 113 DMA 200 ECC application equipment 210 memory cells 220 ECC memory 230 Storage Module 240 processors

Claims

1. A method for applying ECC to a memory by a memory ECC applying device in a system semiconductor based on an artificial neural network, comprising: dividing memory cells into first through n-th groups of memory cell arrays corresponding to first through n-th frames based on word lines (n being a natural number equal to or greater than 2); performing an error correction code (ECC) write or read operation for each of the first through n-th frames, the ECC being applied to a memory cell array of a group corresponding to each frame; performing a general write or read operation without applying an error correction code on a remaining group of memory cell arrays excluding a group corresponding to each frame of the first through n-th frames; A method for applying ECC to a memory in a system semiconductor based on an artificial neural network, comprising:

2. 2. The method of claim 1, wherein the number of times that the ECC write or read operation and the general write or read operation can be applied is adjusted according to a Fault Handling Time Interval (FTTI) time and a frame processing time.

3. 2. The method of claim 1, wherein in the ECC write operation, an ECC code is generated by an ECC encoder based on write data in a memory cell array of a group corresponding to each frame selected by an address decoder based on a word line, the write data is stored in a memory, and the generated ECC code is stored in an ECC memory.

4. 2. The method for applying ECC to a memory in a system semiconductor based on an artificial neural network as claimed in claim 1, wherein in the ECC read operation, after an address decoder regenerates an ECC code in a memory cell array of a group corresponding to each frame selected based on a word line, the regenerated ECC code is compared with an ECC code read from an ECC memory.

5. The step of performing an ECC write or read operation includes:

2. The method of claim 1, further comprising the step of: applying an error correction code to a group of memory cell arrays corresponding to each frame selected based on the least significant bit (LSB) of the address decoder input information.

6. The step of performing a general write or read operation includes:

2. The method for applying ECC to a memory in a system semiconductor based on an artificial neural network as claimed in claim 1, wherein, for each of the first through n-th frames, a write or read operation is performed with an error detection parity bit added to the memory cell array of the remaining groups excluding the group corresponding to each frame.

7. The step of performing a general write or read operation includes:

2. The method for applying ECC to a memory in a system semiconductor based on an artificial neural network as claimed in claim 1, wherein the number of bits is calculated by combining the read data of the selected word line and the parity bit based on the least significant bit of the address decoder input information in the remaining groups of the memory cell array except for the group corresponding to each frame, and detecting whether an error has occurred.

8. A memory cell for storing data generated in a system semiconductor based on an artificial neural network; an ECC memory for storing an ECC code associated with an ECC write or read operation; a storage module for storing one or more programs; a processor for executing said stored one or more programs; Equipped with The processor, The memory cells are divided into first through n-th groups of memory cell arrays corresponding to first through n-th frames based on word lines (n is a natural number equal to or greater than 2); performing an error correction code (ECC) write or read operation for each of the first through n-th frames, the ECC being applied to a memory cell array of a group corresponding to each frame; A device for applying ECC to a memory in a system semiconductor based on an artificial neural network, which performs a general write or read operation without applying an error correction code to a memory cell array of a remaining group excluding a group corresponding to each frame of the first to nth frames.

9. 9. The ECC application device for memory in a system semiconductor based on an artificial neural network as claimed in claim 8, wherein the number of times that the ECC application can be applied to the ECC write or read operation and the general write or read operation is adjusted according to a Fault Handling Time Interval (FTTI) time and a frame processing time.

10. 9. The device for applying ECC to a memory in a system semiconductor based on an artificial neural network as claimed in claim 8, wherein in the ECC write operation, an ECC code is generated by an ECC encoder based on write data in a memory cell array of a group corresponding to each frame selected by an address decoder based on a word line, the write data is stored in a memory, and the generated ECC code is stored in an ECC memory.

11. 9. The ECC application device for memory in a system semiconductor based on an artificial neural network as claimed in claim 8, wherein in the ECC read operation, after the address decoder regenerates the ECC code in the memory cell array of the group corresponding to each frame selected based on the word line, the regenerated ECC code is compared with the ECC code read from the ECC memory.

12. The processor, 9. The apparatus for applying ECC to a memory in a semiconductor system based on an artificial neural network as claimed in claim 8, further comprising: applying an error correction code to a group of memory cell arrays corresponding to each frame selected based on a least significant bit (LSB) of address decoder input information.

13. The processor, 9. The device for applying ECC to a memory in a system semiconductor based on an artificial neural network as claimed in claim 8, wherein, for each of the first to n-th frames, a write or read operation is performed with an error detection parity bit added to the memory cell array of the remaining group excluding the group corresponding to each frame.

14. The processor, 9. The device for applying ECC to a memory in a system semiconductor based on an artificial neural network as claimed in claim 8, wherein the read data of a selected word line and a parity bit are combined based on the least significant bit of address decoder input information in the remaining groups of memory cell arrays excluding the group corresponding to each frame to calculate the number of bits and detect whether an error has occurred.

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