Test measurement device, test measurement system, and electrical signal operational signal timing / parameter measurement method
Patent Information
- Application Number
- JP2024144485
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-08-16
- Filing Date
- 2024-08-26
- Publication Date
- 2025-03-07
Smart Images
Figure 2025031704000001_ABST
Abstract
Description
[Technical field]
[0001] The present disclosure relates generally to test and measurement equipment that acquires, decodes, and tests electrical signals communicated over an electrical bus, and more specifically to a test and measurement equipment, test and measurement system, and method for measuring operational signal timing parameters of an electrical signal that acquires waveform data of the electrical signal and determines whether the electrical signal meets required timing characteristics defined by the bus protocol of the electrical bus. [Background technology]
[0002] In test and measurement equipment, such as oscilloscopes, protocol decoding is the process of translating or decoding the electrical signals that a device under test (DUT) communicates over a serial electrical bus. Protocol decoding converts these electrical signals into the corresponding bit sequences defined by the bus protocol of the electrical bus. This ability of test and measurement equipment allows designers to decode and use the messages or frames communicated on the electrical bus to verify the design and operation of the DUT. There are many different types of serial buses in use today, and each serial bus has an associated bus protocol defined by a corresponding standard. Each bus protocol contains a protocol layer that specifies the encoding techniques, definitions of various frames and packets, specific bit patterns, and error handling of the electrical signals communicated over the electrical bus.
[0003] In protocol decoding, the DUT under test is coupled to an electrical bus and the test and measurement instrument acquires the electrical signals sent to and received from the DUT as waveform data communicating over the electrical bus. As part of this process, the user configures the protocol decoder in the test and measurement instrument through the protocol decoder bus configuration menu, which includes selecting the type of electrical bus under test and setting thresholds and other related settings defined for the selected bus. The protocol decoder in the test and measurement instrument then translates or decodes the acquired electrical signals according to the bus protocol and generates the corresponding frames formed by these electrical signals. This decoding process includes identifying frame information such as the start of a frame and the end of a frame according to the bus protocol of the electrical bus, as well as checking the values of various packets communicated as part of the frames. The protocol decoder identifies errors in the decoded packets and displays the decoded packets with indicators of the detected errors for the user to review. Errors may include, for example, a packet with an improper value (i.e., a sequence of bits) or an error check, such as a cyclic redundancy check (CRC) or a parity check, on the decoded packet.
[0004] The configuration of the protocol decoder includes setting thresholds that are used during the decoding of the electrical signal to decode "1" and "0" bits in the bit sequence or bit stream communicated over the electrical bus. The protocol decoder uses these thresholds and information about the bus protocol of the electrical bus over which the electrical signal is communicated to decode the electrical signal. For example, the protocol decoder uses information about the frame format defined in the bus protocol to detect the start and end of a frame and to detect different types of frames, such as address frames and data frames.
[0005] The signal timing characteristics of the electrical signals communicated over the electrical bus are also defined by the bus protocol. Specifically, the signal timing characteristics are defined by nominal signal timing parameters defined in the bus protocol. For example, the nominal signal timing parameters may include rise and fall time parameters for rising and falling edges of the electrical signals, time parameters for setup and hold start conditions, setup and hold time parameters for data, setup time parameters for stop conditions, buffer time parameters that define the minimum time between stopping and starting the electrical bus, etc., depending on the particular electrical bus protocol being utilized. [Prior art documents] [Patent documents]
[0006] [Patent Document 1] Special Publication No. 2021-518595 [Non-patent literature]
[0007] [Non-Patent Document 1] "Tektronix oscilloscope" introduction site, Tektronix, [online], [searched August 18, 2024], Internet<https: / / www.tek.com / ja / products / oscilloscopes> Summary of the Invention [Problem to be solved by the invention]
[0008] Electrical signals communicated over an electrical bus must meet or comply with timing characteristics defined by the associated nominal signal timing parameters to ensure proper operation of the electrical bus. If the electrical signals do not comply with these nominal signal timing parameters, erroneous information may be communicated over the electrical bus. Improved techniques are needed for test and measurement equipment to verify that the acquired electrical signals that are decoded by a protocol decoder as part of the process of decoding the acquired electrical signals meet the required timing characteristics defined by the corresponding bus protocol. [Means for solving the problem]
[0009] Embodiments of the disclosed technology relate to methods for analyzing timing characteristics of electrical signals communicated by a device under test (DUT) over an electrical bus, test and measurement instruments for testing the DUT, and test and measurement systems for implementing these methods in accordance with embodiments of the disclosed technology.
[0010] According to an embodiment of the disclosed technique, a bus timing characteristic analyzer of a test and measurement instrument determines whether timing characteristics of electrical signals communicated over an electrical bus meet required timing criteria or characteristics of those electrical signals as defined by the bus protocol of the electrical bus. The bus timing characteristic analyzer is configured for a desired type of electrical bus to be used in response to user input, and loads or acquires nominal signal timing parameters of the electrical signals of the desired bus in response to the user input. The nominal signal timing parameters are defined by the bus protocol and define the timing criteria of the electrical signals. The test and measurement instrument acquires waveform data of electrical signals transmitted to and received from the DUT communicated over the bus, and the bus timing characteristic analyzer measures operational signal timing parameters of the acquired electrical signals. The bus timing characteristic analyzer then compares the operational signal timing parameters to the nominal signal timing parameters to determine whether the operational signal timing parameters meet the defined timing criteria. A visual display is then displayed on the test and measurement instrument by the bus timing characteristic analyzer to indicate the results of the comparison. A visual display indicates to the user whether the operational signal timing parameters of the electrical signals meet the timing criteria. The Bus Timing Characteristics Analyzer also provides a display on the test and measurement equipment's user interface that allows the user to view the comparison results of each signal timing parameter, allowing the user to more closely examine the specific occurrences of errors detected in the electrical signal timing characteristics as part of the testing of the DUT. [Brief description of the drawings]
[0011] [Figure 1] FIG. 1 is a block diagram of a test and measurement system having a test and measurement instrument including a bus timing characteristic analyzer for analyzing timing characteristics of electrical signals communicated over an electrical bus in accordance with an embodiment of the disclosed technique. [Diagram 2]Figure 2 is a signal timing diagram illustrating numerous nominal signal timing parameters associated with the data and clock signals of the I2C electrical bus. [Diagram 3] FIG. 3 is a signal timing diagram illustrating the data and clock signals of an I2C bus and illustrating address and data frames communicated on the bus in accordance with the I2C bus protocol. [Figure 4] FIG. 4 is a signal timing diagram illustrating the data and clock signals acquired by the test and measurement instrument, and the decoded data and address frames generated by the protocol decoder of the test and measurement instrument. [Diagram 5] FIG. 5 is a flowchart of a process performed by the bus timing characteristic analyzer of FIG. 1 to analyze timing characteristics of data signals and clock signals communicated over an I2C bus in accordance with an embodiment of the disclosed technique. [Figure 6] FIG. 6 illustrates an example of a configuration display according to an embodiment of the disclosed technique that is rendered on a user interface by a bus timing characteristic analyzer to allow a user to configure the bus timing characteristic analyzer of FIG. [Figure 7] 7 is a bus configuration display in accordance with an embodiment of the disclosed technique as displayed on a user interface of a test and measurement instrument by the bus timing characteristic analyzer of FIG. [Figure 8] FIG. 8 illustrates a bus timing results configuration display in accordance with an embodiment of the disclosed technology that is rendered on a user interface of a test and measurement instrument by a bus timing characteristic analyzer. [Figure 9] FIG. 9 illustrates a bus timing results display that a bus timing characteristic analyzer may display on a user interface of a test and measurement instrument according to an embodiment of the disclosed technique. [Figure 10] FIG. 10 illustrates another example of a bus timing results display according to an embodiment of the disclosed technique that further includes a time domain display of the acquired electrical signals. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0012] FIG. 1 illustrates a test and measurement system 100 including a test and measurement instrument 102 including a bus timing characteristic analyzer 104 that determines whether timing characteristics of electrical signals ES communicated over an electrical bus EB meet required timing criteria or characteristics for those electrical signals as defined by the bus protocol of the electrical bus. The electrical signals ES are communicated over the electrical bus EB by one or more devices 106 coupled to the electrical bus, one of which is a device under test (DUT). The test and measurement instrument 102 captures or acquires the electrical signals ES communicated by the DUT over the electrical bus for a period of time and generates "acquired data" or "acquired waveform data" (or simply referred to as "waveform") of the electrical signals. The bus timing characteristic analyzer 104 analyzes the acquired waveform to determine whether the electrical signals ES communicated over the electrical bus EB meet required timing characteristics for those electrical signals as defined by the bus protocol of the electrical bus. In the example embodiment of FIG. 1, the electrical bus EB is an inter-integrated circuit (I2C) bus (I 2 The I2C bus is an I2C bus (also referred to as an I2C bus) in which there are three devices 106 coupled to the bus in the form of a bus controller 108 and two bus target devices 110 and 112. For example, the bus controller 108 may be a microcontroller and the bus target devices 110 and 112 may be an Electrically Erasable Programmable Read Only Memory (EEPROM) and a real-time clock module, respectively.
[0013] The test and measurement instrument 102 includes one or more processors 114 that may be configured to execute instructions from the memory 116 and may perform any method or associated steps corresponding to such instructions. A user interface 118 is coupled to the one or more processors 114 and may include, for example, a keyboard, mouse, touch screen, output display, file storage, or any other operating device available for a user to interact with the test and measurement instrument 102. In some embodiments, the user interface 118 is connected to or controlled by a remote interface (not shown) such that a user can control the operation of the test and measurement instrument 102 from a location that is physically separate from the test and measurement instrument 102. The display portion of the user interface 118 may be a digital screen such as an LCD, LED, or any other monitor for displaying waveforms, measurements, and other data to a user. In some embodiments, the main output display of the user interface 118 may also be located remotely from the test and measurement instrument 102.
[0014] The test and measurement instrument 102 further includes one or more measurement units 120, which perform functions to measure parameters and other characteristics of signals from the DUT being measured or tested by the test and measurement instrument 102. Typical measurements include measuring the voltage, current, and power of the signals in the time domain, and measuring the characteristics of the signals in the frequency domain. The measurement units 120 generally represent any measurements made on the test and measurement instrument, and the bus and timing characteristic analyzer 104 may be integrated within or coupled to such measurement units 120. The test and measurement instrument 102 is coupled via cables 122a, 122b and probes 124a, 124b to sense or detect electrical signals ES communicated over the I2C bus. The coupling to the electrical signals ES is represented by dashed lines for each of the probes 124a, 124b. The probes 124a, 124b may be, for example, probes that detect signals using electromagnetic induction.
[0015] When the electrical bus EB is an I2C bus as in the example embodiment of FIG. 1, the electrical signal ES corresponds to the serial data signal SDA and the serial clock signal SCL. Although the embodiments of the disclosed technology take an I2C bus as an example, the embodiments of the disclosed technology are not limited to test devices coupled to an I2C bus. The electrical bus EB may be any of various types of electrical buses. The electrical bus EB may be any electrical bus in which the characteristics of electrical signals according to the bus protocol are clearly defined in the bus specification. In some embodiments of the disclosed technology, the electrical bus EB is any of an I2C bus, an I3C or "SenseWire" bus, an RS-232 bus, a Universal Serial Bus (USB) bus, an embedded USB (eUSB) bus, a Serial Peripheral Interface (SPI) bus, an embedded SPI (eSPI) bus, and a SENT (i.e., SAE J2716) bus.
[0016] In operation of the bus timing characteristic analyzer 104, a user first provides inputs through the user interface 118 of the test and measurement instrument 102 to configure the bus timing characteristic analyzer for testing a DUT. The DUT under test corresponds to one of a number of devices 106, and thus in the example embodiment of FIG. 1, is either a bus controller 108, a bus target device 110, or a bus target device 112. These user inputs include identifying the type of electrical bus EB used by the DUT. In response to the user inputs, the bus timing characteristic analyzer 104 is configured to analyze specific timing characteristics of electrical signals ES communicated over the identified electrical bus EB, which in the example embodiment of FIG. 1 is an I2C bus. Thus, in this example, the user input identifies the I2C bus, and the bus timing characteristic analyzer 104 then retrieves from the memory 116 nominal signal timing parameters corresponding to the I2C bus that define the signal timing characteristics of the I2C bus. These nominal signal timing parameters may be stored in another memory (not shown) instead of in memory 116 , such as a memory in bus timing characteristic analyzer 104 or a memory external to test and measurement instrument 102 .
[0017] In some embodiments, the nominal signal timing parameters of the I2C bus include a rise time parameter tRise for the rising edges of the SDA and SCL signals, a fall time parameter tFall for the falling edges of the SDA and SCL signals, and a clock period tFreq that defines the clock frequency fsCL of the SCL signal. Each of the nominal signal timing parameters tRise, tFall, and tFreq has a range of allowable values, defined by corresponding minimum and maximum values for these signal timing parameters, such that the SDA and SCL signals conform to the bus protocol specifications of the I2C bus. Thus, in some embodiments, the nominal signal timing parameters of the I2C bus include a maximum rise time tRisemax and a minimum rise time tRisemin for the rising edges of the SDA and SCL signals, a maximum fall time tFallmax and a minimum fall time tFallmin for the falling edges of the SDA and SCL signals, and a maximum clock period tFreqmax and a minimum clock period tFreqmin for the SCL signal. Instead of the clock period of the SCL signal, the reciprocal of the clock period, that is, the clock frequency of the SCL signal, may be used. Either method can be used for conversion by a simple calculation.
[0018] In addition to these nominal signal timing parameters, in some embodiments of the present disclosure, the bus timing characteristic analyzer 104 may utilize additional or alternative nominal signal timing parameters. Additional nominal signal timing parameters that may be used by the bus timing characteristic analyzer 104 include, for example, the setup and hold times of the SDA signal and the setup and hold times of the start and stop conditions defined in the bus protocol specification for the I2C bus. FIG. 2 is a signal timing diagram illustrating several nominal signal timing parameters associated with the SDA and SCL signals. In the example signal timing diagram of FIG. 2, the I2C nominal signal timing parameters tRise and tFall are set to tRise and tFall, respectively. r and t f2, the clock period tFreq is not explicitly shown. FIG. 2 also illustrates additional nominal signal timing parameters that may be utilized by the bus timing characteristics analyzer 104 in further embodiments of the present disclosure. These additional signal timing parameters include a start condition hold time tHD;STA, a minimum low clock period tLOW, a minimum high clock period tHIGH, a data hold time tHD;DAT, a data setup time tSU;DAT, a repeated start condition setup time tSU;STA, a start condition hold time tHD;STA, a setup stop condition time tSU;STO, and a bus free time tBUF. Each of these additional signal timing parameters is defined by the bus protocol of the I2C bus and will be understood by one of ordinary skill in the art and will not be described in detail herein.
[0019] Before describing the operation of the bus timing characteristic analyzer 104 in more detail, we will first briefly describe the operation of the protocol decoder (PD) 119 of the test and measurement instrument 102. Typically, a user uses the bus timing characteristic analyzer 104 in combination with the protocol decoder (PD) 119 of the test and measurement instrument 102. The protocol decoder (PD) 119 is coupled to the measurement unit 120 and receives acquired waveform data of the SDA and SCL signals from the measurement unit 120 (see FIG. 1). The protocol decoder 119 then decodes bit sequences in the waveform data of the SDA and SCL signals communicated over the I2C bus and converts them into frames defined by the bus protocol of the I2C bus. A designer uses the protocol decoder (PD) 119 to verify the design and operation of the DUT under test by examining the decoded frames sent to or received from the DUT communicated over the I2C bus.
[0020] FIG. 3 is a signal timing diagram showing the SDA and SCL signals, and the address and data frames communicated on the I2C bus according to the bus protocol. The protocol decoder PD uses the SCL signal to decode the sequence of bits communicated by the SDA signal and generates corresponding decoded data. FIG. 4 is a signal timing diagram generated by the protocol decoder PD, with the upper part of the diagram showing the SCL and SDA signals captured by the test and measurement instrument 102, and the lower part of the diagram showing the decoded data of the bit sequence of the SDA signal generated by the protocol decoder. Since the correct values of the communicated address frame A and data frame D are known during testing of the DUT, the protocol decoder PD can detect errors in the decoded values of the address and data frames. The protocol decoder can flag or indicate errors detected in the decoded data when displayed for user review.
[0021] The protocol decoder PD does not analyze the timing characteristics of the SDA and SCL signals communicated over the I2C bus. Therefore, errors in the decoded data caused by timing characteristics of the SDA and SCL signals that do not meet the specifications given by the nominal signal timing parameters of the I2C bus cannot be identified by the protocol decoder PD. The bus timing characteristics analyzer 104 according to an embodiment of the disclosed technology allows identification of these types of errors caused by errors in the timing characteristics of the SDA and SCL signals. The overall operation of the bus timing characteristics analyzer 104 will be described in further detail with reference to the flowchart of FIG. 5.
[0022] FIG. 5 is a flow chart of a process 500 performed by the bus timing characteristic analyzer 104 to analyze the timing characteristics of the SDA and SDL signals, according to an embodiment of the disclosed technique. Before the bus timing characteristic analyzer 104 begins executing the process 500, a user makes an input through the user interface 118 (FIG. 1) of the test and measurement instrument 102 to select a “Protocol Utility” option in a settings menu presented by the user interface. When the protocol utility is selected, the user inputs information to identify the type of electrical bus EB being used, after which the bus timing characteristic analyzer 104 performs an analysis of the timing characteristics of the electrical signals ES communicated on the electrical bus EB. The configuration of the bus timing characteristic analyzer 104 is described in more detail below with reference to FIGS. 6-8.
[0023] Once the user has entered the information to select the I2C bus, the bus timing characteristic analyzer 104 begins executing process 500 at step 502 to load or obtain nominal signal timing parameters for the I2C bus (i.e., the selected bus). As discussed above, in some embodiments, the nominal signal timing parameters include the rise time tRise of the rising edges of the SDA and SCL signals, the fall time tFall of the falling edges of the SDA and SCL signals, and the clock frequency fsCL or clock period tFreq of the SCL signal. The nominal signal timing parameters may be specified in terms of maximum and minimum values on a nominal basis, and thus in some embodiments may include the maximum rise time tRisemax, minimum rise time tRisemin, maximum fall time tFallmax, minimum fall time tFallmin, maximum clock period tFreqmax, and minimum clock period tFreqmin of the SCL signal.
[0024] After obtaining the tRisemax, tRisemin, tFallmax, tFallmin, tFreqmax, and tFreqmin parameters in step 502, the process 500 proceeds to step 504 where rising and falling edges are detected in the currently acquired waveform data of the SDA and SCL signals acquired by the test and measurement instrument 102. The bus timing characteristic analyzer 104 may detect these edges, or the edge detection may be performed by other components within the test and measurement instrument 102, such as the measurement unit 120. Whether performed by the bus timing characteristic analyzer 104 or other components within the test and measurement instrument 102, once the rising and falling edges in the currently acquired waveform data are detected in step 504, the process 500 proceeds to step 506 where it initializes a number of operational variables that are used to calculate operational signal timing parameters for the currently acquired waveform data of the SDA and SCL signals. The operating variables include a current edge index EDGE, an edge count total EDGECNT, a rise time tRise, a fall time tFall, and a clock period tFreq associated with the current acquired waveform data and the frequency of the SCL signal for each unit interval (UI) of the SCL signal. Each of EDGE, tRise, tFall, and tFreq are initialized to zero, and the edge count total EDGENT is set to the total number of edges detected in the acquired waveform data in step 506.
[0025] From step 506, process 500 proceeds to step 508 to determine whether the currently detected edge in the acquired waveform data defined by the value of edge index EDGE is less than the total edge count EDGENT. If the determination at step 508 is true, process 500 proceeds to step 510 to measure or calculate the rise time tRise of the detected rising edge corresponding to the current value of edge index EDGE. At step 510, process 500 also measures or calculates the fall time tFall of the detected falling edge corresponding to the current value of edge index EDGE. From step 510, process 500 proceeds to step 512 to calculate or measure the clock period tFreq or clock frequency fsCL in terms of a current unit interval UI of the SCL signal. Process 500 then proceeds from step 512 to step 514, where it calculates and stores values of the rise time tRise, fall time tFall, and clock period tFreq associated with the current value of the edge index EDGE for the current waveform data in the form of a measurement vector MV.
[0026] Process 500 then proceeds from step 514 to step 516 to determine whether each of the rise time tRise, fall time tFall, and clock period tFreq associated with the current value of edge index EDGE meets the timing characteristics or criteria defined by the corresponding nominal signal timing parameters obtained in step 502. To this end, in step 516, process 500 determines whether the currently measured or calculated rise time tRise is greater than the minimum rise time tRisemin and less than the maximum rise time tRisemax required by the I2C bus protocol for the rising edges of the SDA and SCL signals. Similarly, in step 516, process 500 determines whether the currently measured or calculated fall time tFall is greater than the minimum fall time tFallmin and less than the maximum fall time tFallmax required by the I2C bus protocol for the falling edges of the SDA and SCL signals. Finally, in step 516, the process 500 also determines whether the current measured or calculated clock period, tFreq, is greater than a minimum clock period, tFreqmin, and less than a maximum clock period, tFreqmax, required by the I2C bus protocol for the SCL signal.
[0027] If one or more of the determinations in operation 516 are negative, process 500 proceeds to operation 518 and generates an individual failure vector FV for each detected failure in operation 516. To this end, in operation 518, process 500 generates a rising-edge failure vector FV-R indicating whether the rising time tRise of the current rising edge corresponding to the current value of edge index EDGE meets the timing criteria defined by the corresponding nominal signal timing parameter (i.e., whether tRisemin < tRise < tRisemax). The pass or fail value is stored in the rising-edge failure vector FV-R in operation 518, indicating whether the rising time tRise of the current rising edge meets or fails the timing criteria. Process 500 similarly generates a falling-edge failure vector FV-F and a clock period failure vector FV-CF in operation 518. In operation 518, for each of the falling-edge failure vector FV-F and the clock period failure vector FV-CF, a falling time tFall and a clock frequency fsCL for the falling edge corresponding to the value of the current edge index EDGE, and a clock period tFreq, are stored with a pass or fail value indicating whether they meet or fail the corresponding timing criteria.
[0028] From step 518, process 500 proceeds to step 520 where the value of the current edge index EDGE is incremented and then the process returns to step 508 to determine whether the current value of the edge index EDGE is less than the total edge count EDGENT. Process 500 also proceeds directly to step 520 if all determinations in step 516 are positive, i.e., no failures are detected for any of the analyzed signal timing parameters tRise, tFall, and tFreq. Each of the rising edge fail vector FV-R, the falling edge fail vector FV-F, and the clock period fail vector FV-CF initially stores the pass values of tRise, tFall, and tFreq corresponding to the current edge index EDGE. Thus, if all determinations at step 516 are positive, process 500 proceeds immediately to step 520, where the current edge index EDGE is incremented and all initial values of tRise, tFall and tFreq corresponding to the current edge index EDGE remain at the pass values initially set in the FV-R, FV-F and FV-CF vectors, respectively.
[0029] Process 500 continues to execute steps 508-520 as shown until the determination at step 508 is negative, which indicates that the timing characteristics of all edges detected in the currently acquired waveform data are measured and determined to pass or fail against the corresponding timing criteria. If the determination at step 508 is negative, process 500 proceeds to step 522 and displays, via user interface 118 (FIG. 1), whether each of the measured operational signal timing parameters tRise, tFall, and tFreq passed or failed the I2C bus timing criteria defined by the corresponding nominal signal timing parameters tRisemin, tRisemax, tFallmin, tFallmax, tFreqmin, and tFreqmax.
[0030] The measured operational signal timing parameters tRise, tFall, tFreq are determined to have failed an associated timing criterion if at least one of the rising edges, falling edges, or at least one clock period of unit interval UI does not meet the timing criterion defined by the corresponding nominal signal timing parameter. At step 522, the process 500 displays a "pass" indication for the measured signal timing parameters tRise, tFall, tFreq when all edges and all periods of unit interval UI of the SDA and SCL signals meet the associated timing criterion. Conversely, if a failure is detected, the process 500 displays a "fail" indication for the measured signal timing parameters tRise, tFall, tFreq at step 522. Additionally, if a failure is detected for the measured signal timing parameters tRise, tFall, tFreq, process 500, at step 522, utilizes the associated fail vectors FV-R, FV-F, FV-CF to allow a user to view the fail vectors and examine each instance of failure for the corresponding SDA and SCL signals. The operation of bus timing characteristic analyzer 104 to perform step 522 to provide an indication of passes and fails and enable a user to view and examine the failures in more detail is described in more detail below with reference to Figures 6-8. After step 522, process 500 proceeds to step 524 and ends.
[0031] 6 illustrates an exemplary configuration view 600 rendered on the user interface 118 by the bus timing characteristic analyzer 104 to allow a user to configure the bus timing characteristic analyzer 104 in accordance with an embodiment of the disclosed technique. The configuration view 600 adds a "Protocol Utilities" option to the existing configuration menu, which a user can select to configure the bus timing characteristic analyzer 104 to perform analysis of timing characteristics of electrical signals generated by the DUT. The configuration view 600 also includes an existing configuration menu, which provides several signal analysis options that can be performed on waveform data acquired by the test and measurement instrument 102. These analysis options are selected through additional tabs at the top of the configuration view 600 and may include a WBG-DPT tab for selecting a Wide Band Gap Double Pulse test for the DUT, a DPM tab for selecting a Digital Power Management test for the DUT, an IMDA tab for selecting an Inverter Motor Drive Analysis test for the DUT, a Power tab for selecting a Power test for the DUT, and a Jitter tab for selecting a Jitter analysis for the DUT.
[0032] The user selects Protocol Utilities through the Standard tab displayed in the upper left corner of the configuration display 600. Once the user selects the Standard tab, the user then selects the Protocol Utilities option, which is presented in the lower left portion of the configuration display 600 as one of many different types of bus measurements that the test and measurement instrument 102 may perform on the electrical signals of the DUT. In FIG. 6, the Standard tab is shown in bold and the Protocol Utilities menu is shown in dashed lines, indicating that these two items have been selected by the user. The user then selects a bus source, which defines the type of bus to be analyzed, such as an I2C bus, through a Source field displayed in the center left portion of the configuration display 600. The Source field is shown in FIG. 6 as Bus 1.
[0033] Depending on the selection of the "source" field, the parameters of the selected type of bus that is the source of the electrical signal to be analyzed can be set. Selection of the source field causes a bus configuration display 700 to be displayed on the user interface 118 of the test and measurement instrument 102, as shown in FIG. 7. The bus configuration display 700 has a display field that allows the user to select whether or not to display the output of the bus timing characteristic analyzer 104 on the user interface 118. FIG. 7 shows an example where the display field is selected as on. The label field allows the user to assign a desired label to the bus to be analyzed. The type of bus to be analyzed is set in the bus type field, and in the example of FIG. 7, an I2C bus is shown. As mentioned above, various types of buses can be analyzed, and the bus type field allows the user to select the appropriate bus.
[0034] The user then selects the appropriate channel CH on the test and measurement instrument for the corresponding electrical signals of the selected bus type. The I2C bus includes SDA and SCL signals as described above. In the example of FIG. 1, one of the SDA and SCL signals is coupled to a first channel CH1 of the test and measurement instrument 102, and the other of the SDA and SCL signals is coupled to a second channel CH2 of the test and measurement instrument 102. The threshold field of the bus configuration display 700 is used to set the threshold voltages of each of the SDA and SCL signals coupled to the first and second channels CH1 and CH2, respectively, of the test and measurement instrument 102. The R / W bit field of the bus configuration display 700 provides the user with the option to include a read / write bit R / W in the decoded address on the I2C bus. The Display Format field allows the user to select the desired format for displaying the SDA and SCL signals, whether they are displayed as decoded frames on a bus (selecting the "Bus" format as shown in Figure 7) or whether they are displayed as time varying voltage levels. When the Bus format is selected, each value of each decoded frame is displayed as shown in the I2C bus at the bottom of Figure 4. The Display Format field allows the user to select the desired format for displaying the decoded frame values, such as hex, binary, decimal, or other format options.
[0035] FIG. 8 illustrates a bus timing results configuration display 800 that allows a user to configure the desired results of the bus timing characteristic analyzer 104 analysis that will be displayed for user review. More specifically, the bus timing results configuration display 800 includes a "View Source" field in the lower left portion of the display that allows a user to select the desired timing characteristic or criterion that will be displayed for user review. The View Source field is Bus 1 in the example of FIG. 8, which corresponds to the I2C bus. In this manner, the View Source field provides a user with the option to select a desired timing parameter from among multiple timing parameters to be analyzed by the bus timing characteristic analyzer 104.
[0036] As discussed above, in an embodiment of the disclosed technique, these timing parameters include the period (or frequency) of the SCL signal, which is a clock signal, the rise time of the rising edge of the SCL signal, the fall time of the falling edge of the SCL signal, the rise time of the rising edge of the SDA signal, which is a data signal, and the fall time of the falling edge of the SDA signal. These various timing parameters are shown in the drop down subfields available in the View Signal Source field of the configuration display 800 of FIG. 8. For example, the rising edge of the SCL signal is selected as shown by the thick line in this subfield. A View Measurement Format field is also present as part of the configuration display 800, allowing the user to determine whether to review all events of the selected timing parameter or only those events for which a failure has occurred. This selection is made by the "All Events" and "Fail" subfields of the "View Measurement Format" field. For example, if the rise time of the rising edge of the SCL signal is selected, as in the example of FIG. 8, selecting the All Events subfield, as in the example of FIG. 8, allows the user to view and review the rise time parameters calculated for all rising edges of the SCL signal in the currently acquired waveform data being analyzed by the bus timing characteristic analyzer 104.
[0037] FIG. 9 illustrates a bus timing results display 900 by the bus timing characteristic analyzer 104 via the user interface 118 of the test and measurement instrument 102, which allows a user to review the results of the timing characteristic analysis for the timing parameters analyzed. In the example of FIG. 9, the bus timing results display 800 illustrates the measured operational signal timing parameters described above for the I2C bus, namely, the rise and fall time parameters of the rising and falling edges of the SDA and SCL signals, along with the frequency of the SCL signal. These operational signal timing parameters are specified in the bus timing results display 900 as follows: The rise time of the rising edge of the SCL signal is specified as the clock rise time, trCL; The fall time of the falling edge of the SCL signal is specified as the clock fall time, tfCL; The rise time of the rising edge of the SDA signal is specified as the data rise time, trDA; The fall time of the falling edge of the SDA signal is specified as the data fall time, tfDA; and the frequency of the SCL signal is specified as the clock frequency, fsCL.
[0038] The bus timing results display 900 also includes value fields for each of the timing parameters trCL, tfCL, trDA, tfDA, and fsCL, which indicate the value of each of the timing parameters. A status field for each timing parameter indicates whether the timing parameter passed or failed analysis by the bus timing characteristic analyzer 104. The user can then use navigation buttons 902, 904 to browse through the selected signal timing parameters and identify events for a desired one of the parameters. The user view button 904 is shown as selected in the example of FIG. 9 with a bold line. In some embodiments, if there are no failures (no violations) for a given signal timing parameter, navigation for that parameter may be disabled. For example, in the example of Figure 9, the trDA, tfCL, and fsCL parameters passed analysis as indicated by the corresponding status fields, so viewing of events for these parameters may not be possible. However, the trCL and trDA parameters failed analysis as indicated by the corresponding status fields, so they can be viewed using view buttons 902, 904. The minimum button "min" and maximum button "max" on the bus timing results display 900 allow the user to specify minimum and maximum values for the selected timing parameter.
[0039] In an embodiment, the bus timing characteristic analyzer 104 performs additional analysis on each of the analyzed signal timing parameters. For example, in an embodiment, the bus timing characteristic analyzer 104 calculates the mean, minimum, maximum, and standard deviation for each of the signal timing parameters tfCL, trCL, tfCL, trDA, and tfDA. Additionally, in an embodiment, for a selected signal timing parameter, the corresponding SDA and SCL signals are shown in a time domain display in the user interface 118, and the view buttons 902, 904 can be used to browse through the selected signal timing parameter, allowing a user to visually confirm events of the analyzed signal timing parameter in the time domain display of the corresponding SDA and SCL signals. FIG. 10 illustrates another example bus timing results display 1000, which includes the bus timing results display 900 of FIG. 9 in the upper right corner, along with a time domain display of the SDA and SCL signals and a decoded frame in the left portion of the frame. In this embodiment, particular failure events of the timing parameters displayed in the bus timing results display 900 are also identified or tagged by dashed boxes 1000 in the time domain display of the SDA and SCL signals.
[0040] In some embodiments, the nominal signal timing parameters of the I2C bus include parameters for a standard mode and a fast mode of operation. For the standard mode, the nominal signal timing parameters may include a rise time parameter tRise of 1000 nanoseconds (ns) for the rising edges of the SDA and SCL signals, a fall time parameter tFall of 300 ns for the falling edges of the SDA and SCL signals, a clock frequency fsCL of 100 kHz or less, a minimum low clock period tLOW of 4.7 microseconds (μs), and a minimum high clock period tHIGH of 4.0 μs. For the fast mode, the nominal signal timing parameters may include a rise time parameter tRise of 20 ns to 300 ns for the rising edges of the SDA and SCL signals, a fall time parameter tFall of 20 ns to 300 ns for the falling edges of the SDA and SCL signals, a clock frequency fsCL of 400 kHz or less, a minimum low clock period tLOW of 1.3 μs, and a minimum high clock period tHIGH of 0.6 μs.
[0041] Aspects of the disclosed technology can operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. The term "controller" or "processor" in this application contemplates microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the disclosed technology can be implemented in computer-available data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including a monitoring module) or other devices. Generally, program modules include routines, programs, objects, components, data structures, and the like, which, when executed by a processor in a computer or other device, perform particular tasks or implement particular abstract data formats. The computer-executable instructions may be stored in computer-readable storage media, such as hard disks, optical disks, removable storage media, solid-state memory, RAM, and the like. As will be appreciated by those skilled in the art, the functionality of the program modules may be combined or distributed as desired in various embodiments. Furthermore, such functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. Certain data structures may be used to more effectively implement one or more aspects of the disclosed techniques, and such data structures are considered to be within the scope of the computer-executable instructions and computer-usable data described herein.
[0042] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable media that may be read and executed by one or more processors. Such instructions may be referred to as computer program products. A computer-readable medium as described herein means any medium that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may include computer storage media and communication media.
[0043] Computer storage media means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disc (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile removable or non-removable media implemented in any technology. Computer storage media excludes signals themselves and transitory forms of signal transmission.
[0044] A communication medium refers to any medium that can be used to communicate computer readable information. By way of example, and not limitation, communication media may include coaxial cable, fiber optic cable, air, substrate integrated waveguide (SIW), glass / quartz substrate waveguide, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals. Working Example
[0045] In the following, examples useful for understanding the technology disclosed in the present application are presented. The embodiment of the technology may include one or more of the examples described below and any combination thereof.
[0046] Example 1 is a test and measurement device, one or more processors configured to control acquisition as waveform data of a plurality of electrical signals communicated over the electrical bus according to a bus protocol of the device under test; Bus Timing Characteristics Analyzer and Equipped with The bus timing characteristics analyzer identifying nominal signal timing parameters of the acquired electrical signals defined by the bus protocol, the nominal signal timing parameters defining a timing reference for the acquired electrical signals; measuring operational signal timing parameters for each of the acquired electrical signals; comparing said operational signal timing parameters to said nominal signal timing parameters for each of said plurality of acquired electrical signals to determine whether said operational signal timing parameters meet said timing criteria; displaying, on the test and measurement instrument, a visual indication indicating whether the operational signal timing parameters meet the timing criteria for each of the plurality of electrical signals. The present invention is configured to:
[0047] Example 2 is the test and measurement apparatus of Example 1, wherein, in order to measure the operational signal timing parameters for each of the acquired electrical signals, the bus timing characteristic analyzer is further configured to perform a process of detecting edges of each of the acquired electrical signals, a process of determining whether each of the edges is a rising edge or a falling edge, and a process of measuring the operational signal timing parameters of each of the acquired electrical signals using the rising edges and the falling edges of the electrical signals.
[0048] Example 3 is the test and measurement instrument of Example 1 or Example 2, wherein the acquired electrical signals include at least one data signal, and the operational signal timing parameters of the at least one data signal include rise times and fall times measured for the rising edges and falling edges, respectively, of the at least one data signal.
[0049] Example 4 is the test and measurement instrument of any of Examples 1 to 3, wherein the nominal signal timing parameters include a nominal rise time signal timing parameter and a nominal fall time signal timing parameter, and the bus timing characteristic analyzer is further configured to compare the rise time measured for each of the rising edges of the at least one data signal to the nominal rise time signal timing parameter, and to compare the fall time measured for each of the falling edges of the at least one data signal to the nominal fall time signal timing parameter.
[0050] Example 5 is the test and measurement instrument of any of Examples 1 to 4, wherein the nominal rise time signal timing parameter has a range based on a nominal value, the range being defined by a minimum and a maximum allowed value of the nominal rise time signal timing parameter, and the nominal fall time signal timing parameter has a range based on a nominal value, the range being defined by a minimum and a maximum allowed value of the nominal fall time signal timing parameter, and the bus timing characteristic analyzer is further configured to perform a process of determining whether the rise time measured for each of the rising edges of the at least one data signal has a value within the range of the nominal rise time signal timing parameter, and a process of determining whether the fall time measured for each of the falling edges of the at least one data signal has a value within the range of the nominal fall time signal timing parameter.
[0051] Example 6 is the test and measurement instrument of any of Examples 1 to 5, wherein the nominal signal timing parameters further include a setup time tSU and a hold time tHD of the at least one data signal.
[0052] Example 7 is the test and measurement instrument of any of Examples 1 to 6, wherein the acquired electrical signals further include a clock signal, and the nominal signal timing parameters of the clock signal include a nominal clock frequency or a nominal clock period, a nominal rise time signal timing parameter, and a nominal fall time signal timing parameter.
[0053] Example 8 is the test and measurement instrument of any of Examples 1 to 7, wherein the visual indication for each of the plurality of electrical signals indicates a pass condition if all of the operational signal timing parameters meet the timing criteria for the electrical signal, and indicates a fail condition if one or more of the operational signal timing parameters do not meet the timing criteria.
[0054] Example 9 is a test and measurement device according to any one of Examples 1 to 8, wherein the electrical bus is any one of an I2C (Inter-Integrated Circuit) bus, an I3C or SenseWire bus, an RS-232 bus, a USB (Universal Serial Bus) bus, an eUSB (embedded USB) bus, an SPI (Serial Peripheral Interface) bus, an eSPI (embedded SPI), and a SENT bus.
[0055] A tenth embodiment is the test and measurement apparatus according to any one of the first to ninth embodiments, wherein the test and measurement apparatus includes an oscilloscope.
[0056] Example 11 is a test and measurement system, comprising: A plurality of electronic devices including one device under test (DUT); an electrical bus interconnecting the plurality of electronic devices, the electrical bus communicating electrical signals having nominal signal timing parameters defined by a bus protocol of the electrical bus and timing references defined by the nominal signal timing parameters; one or more processors configured to control acquisition of the electrical signals as waveform data; Bus Timing Characteristics Analyzer and A test and measurement device having Equipped with The above bus timing characteristics analyzer Identifying nominal signal timing parameters of the acquired electrical signal; measuring operational signal timing parameters of the acquired electrical signals; comparing said operational signal timing parameters to said nominal signal timing parameters for said captured electrical signal to determine whether said operational signal timing parameters meet said timing criteria; displaying a visual indication on said test and measurement instrument indicating whether said operational signal timing parameters meet said timing criteria for said electrical signal. The present invention is configured to:
[0057] Example 12 is the test and measurement system of Example 11, wherein the electrical bus is any one of an Inter-Integrated Circuit (I2C) bus, an I3C or SenseWire bus, an RS-232 bus, a Universal Serial Bus (USB) bus, an embedded USB (eUSB) bus, a Serial Peripheral Interface (SPI) bus, an embedded SPI (eSPI) and a SENT bus.
[0058] Example 13 is the test and measurement system of example 11 or example 12, wherein the test and measurement instrument further comprises a memory, and the nominal signal timing parameters are stored in the memory.
[0059] A fourteenth embodiment is the test and measurement system according to any one of the eleventh to thirteenth embodiments, in which the test and measurement device includes an oscilloscope.
[0060] Example 15 is a test and measurement system of any of Examples 11 to 14, wherein the acquired electrical signals include a clock signal and a data signal, and the nominal signal timing parameters include rise time and fall time signal timing parameters of rising edges and falling edges of the clock signal and the data signal, and further include a frequency or period signal timing parameter of the clock signal.
[0061] Example 16 is a test and measurement system of any of Examples 11 to 15, wherein the test and measurement device may further include a protocol decoder configured to convert a bit sequence in the acquired electrical signal into a frame according to a bus protocol of the electrical bus.
[0062] Example 17 is a method for measuring an operational signal timing parameter of an electrical signal communicated over an electrical bus, comprising: obtaining, by a test and measurement instrument, nominal signal timing parameters of the electrical signal, the nominal signal timing parameters being defined by a bus protocol of the electrical bus and defining a timing reference for the electrical signal; acquiring the electrical signal as waveform data in the test and measurement device; detecting edges of the acquired electrical signal in the test and measurement device; measuring, in the test and measurement instrument, an operational signal timing parameter associated with a detected edge of the acquired electrical signal; comparing, in the test and measurement instrument, the operational signal timing parameters to the nominal signal timing parameters to determine whether the operational signal timing parameters meet the timing criteria; storing, in the test and measurement device, a result of the comparison; displaying, in the test and measurement instrument, an indication of pass or fail of the electrical signal based on the stored results of the comparison. Equipped with.
[0063] Example 18 is the method of example 17, in which the electrical bus is an I2C bus, and the electrical signal includes a clock signal and a data signal.
[0064] Example 19 is the method of example 17 or example 18, wherein the nominal signal timing parameters include a rise time tRise for each of the rising edges of the clock signal and the data signal, a fall time tFall for each of the falling edges of the clock signal and the data signal, a clock period tFreq or clock frequency fsCL of the clock signal, a hold start condition time tHD;STA, a minimum low clock period tLOW, a minimum high clock period tHIGH, a data hold time tHD;DAT, a setup start condition time tSU;DAT, a setup start condition time tSU;STA, a hold start condition time tHD;STA, a setup stop condition time tSU;STO, and a bus free time tBUF.
[0065] Example 20 is the method of any of examples 17-19, wherein the nominal signal timing parameters include maximum and minimum values of each of the nominal signal timing parameters.
[0066] The above-described versions of the presently disclosed subject matter have many advantages that have been described or will be apparent to those skilled in the art. Nevertheless, not all of these advantages or features are required in every version of a disclosed device, system or method.
[0067] In addition, the present description refers to specific features. It should be understood that the disclosure herein includes all possible combinations of those specific features. When a specific feature is disclosed in connection with a particular aspect or embodiment, that feature can also be used in connection with other aspects and embodiments, to the extent possible.
[0068] Furthermore, when the application refers to a method having two or more defined steps or processes, those defined steps or processes may be performed in any order or simultaneously, unless the context precludes such a possibility.
[0069] For convenience of illustration, specific embodiments of the invention have been illustrated and described, but it will be understood that various modifications can be made therein without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited, except as by the appended claims. [Explanation of symbols]
[0070] 100 Test and Measurement Systems 102 Test and measurement equipment 104 Bus Timing Characteristics Analyzer 106 Devices 108 Controller 110 Bus Target Device 112 Bus Target Device 114 One or more processors 116 Memory 118 User Interface 119 Protocol Decoder (PD) 120 measurement units 122a 1st Cable 122b 2nd cable 124a First probe 124b Second probe
Claims
1. 1. A test and measurement device comprising: one or more processors configured to control acquisition as waveform data of a plurality of electrical signals communicated over the electrical bus in accordance with a bus protocol of the device under test; Bus Timing Characteristics Analyzer and Equipped with The bus timing characteristic analyzer identifying nominal signal timing parameters of the plurality of electrical signals defined by the bus protocol, the nominal signal timing parameters defining a timing reference for the plurality of acquired electrical signals; measuring operational signal timing parameters for each of the acquired electrical signals; comparing said operational signal timing parameters to said nominal signal timing parameters for each of said acquired electrical signals to determine whether said operational signal timing parameters meet said timing criteria; displaying, on the test and measurement instrument, a visual indication of whether the operational signal timing parameters meet the timing criteria for each of the plurality of electrical signals.
4. A test and measurement device configured to:
2. To measure the operational signal timing parameters for each of the acquired electrical signals, the bus timing characteristic analyzer comprises: A process of detecting edges of each of the acquired electrical signals; determining whether each of the edges is a rising edge or a falling edge; measuring said operating signal timing parameters of each of said acquired electrical signals using said rising edges and said falling edges of said electrical signals; The test and measurement instrument of claim 1 , further configured to:
3. 3. The test and measurement instrument of claim 2, wherein the acquired plurality of electrical signals includes at least one data signal, and the operational signal timing parameters of the at least one data signal include measured rise times and fall times for the rising edges and the falling edges, respectively, of the at least one data signal.
4. the nominal signal timing parameters include a nominal rise time signal timing parameter and a nominal fall time signal timing parameter, the bus timing characteristic analyzer comprising: comparing the measured rise time for each of the rising edges of the at least one data signal to the nominal rise time signal timing parameter; comparing the measured fall time for each of said falling edges for said at least one data signal to said nominal fall time signal timing parameter; The test and measurement instrument of claim 3 , further configured to:
5. the nominal rise time signal timing parameter has a nominal value based range, the range being defined by a minimum and a maximum allowed value of the nominal rise time signal timing parameter, the nominal fall time signal timing parameter has a nominal value based range, the range being defined by a minimum and a maximum allowed value of the nominal fall time signal timing parameter, and the bus timing characteristic analyzer comprises: determining whether the measured rise time for each of the rising edges of the at least one data signal has a value within the range of the nominal rise time signal timing parameter; determining whether the measured fall time for each of the falling edges of the at least one data signal has a value within the range of the nominal fall time signal timing parameter; The test and measurement instrument of claim 4 , further configured to:
6. 6. The test and measurement instrument of claim 5, wherein said nominal signal timing parameters further include a set-up time, tSU, and a hold time, tHD, of said at least one data signal.
7. 2. The test and measurement instrument of claim 1, wherein the acquired electrical signals further comprise a clock signal, and the nominal signal timing parameters of the clock signal include a nominal clock frequency or a nominal clock period, a nominal rise time signal timing parameter, and a nominal fall time signal timing parameter.
8. 2. The test and measurement instrument of claim 1, wherein the visual indication for each of the plurality of electrical signals indicates a pass condition when all of the operational signal timing parameters meet the timing criteria for the electrical signal and indicates a fail condition when one or more of the operational signal timing parameters do not meet the timing criteria.
9. 1. A test and measurement system comprising: a plurality of electronic devices including one device under test (DUT); an electrical bus interconnecting the plurality of electronic devices, the electrical bus communicating electrical signals having nominal signal timing parameters defined by a bus protocol of the electrical bus and timing references defined by the nominal signal timing parameters; one or more processors configured to control acquisition of the electrical signals as waveform data; Bus Timing Characteristics Analyzer and A test and measurement device having Equipped with The above bus timing characteristics analyzer is determining nominal signal timing parameters of the acquired electrical signal; measuring operational signal timing parameters of the acquired electrical signals; comparing said operational signal timing parameters to said nominal signal timing parameters for said captured electrical signal to determine whether said operational signal timing parameters meet said timing criteria; displaying a visual indication on the test and measurement instrument indicating whether the operational signal timing parameters of the electrical signal meet the timing criteria.
4. A test and measurement system configured to:
10. 1. A method for measuring operational signal timing parameters of an electrical signal communicated over an electrical bus, comprising: acquiring, by a test and measurement instrument, nominal signal timing parameters of the electrical signal, the nominal signal timing parameters being defined by a bus protocol of the electrical bus and defining a timing reference for the electrical signal; acquiring the electrical signal as waveform data in the test and measurement device; detecting edges of the acquired electrical signal in the test and measurement device; measuring, in the test and measurement instrument, an operational signal timing parameter associated with a detected edge of the acquired electrical signal; comparing, in the test and measurement instrument, the operational signal timing parameters to the nominal signal timing parameters to determine whether the operational signal timing parameters meet the timing criteria; storing, in the test and measurement device, a result of the comparison; displaying, in the test and measurement instrument, an indication of pass or fail of the electrical signal based on the stored results of the comparison.
13. A method for measuring operational signal timing parameters of an electrical signal, comprising:
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Integrated development environment for protocol design, evaluation and debugging
JP2021518595A