Manufacturing method for semiconductor device

Abstract

To provide a semiconductor device with excellent electric characteristics, a semiconductor device with stable electric characteristics, and a semiconductor device with high reliability.SOLUTION: A semiconductor device has a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer has an island-shaped upper surface shape. The first insulating layer is provided in contact with an upper surface and a side surface of the semiconductor layer. The first conductive layer has a portion that is located on the first insulating layer and overlaps with the semiconductor layer. The semiconductor layer includes a metal oxide, and the first insulating layer includes an oxide. The semiconductor layer has a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer. The first insulating layer has a third region overlapping with the first conductive layer and a fourth region not overlapping with the first conductive layer. The second region and the fourth region contain phosphorus or boron.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a display device. One embodiment relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, and a , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof A semiconductor device functions by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials that can be used for transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the ratio of indium to that of gallium, the field effect mobility (simply called the mobility A semiconductor device having improved mobility, or μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed by using a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. The company plans to improve some of its production facilities for transistors using polycrystalline silicon and amorphous silicon. This allows the use of metal oxide transistors, which reduces capital investment. The field effect mobility of the transistor is higher than that of amorphous silicon, so the driver circuit It is possible to realize a high-performance display device having the above-mentioned structure.

[0005] In addition, Patent Document 2 discloses that aluminum, boron, and gallium are added to the source and drain regions. The group consisting of lithium, indium, titanium, silicon, germanium, tin, and lead. The present invention relates to an oxide semiconductor film having a low-resistance region containing at least one of the above elements as a dopant. A thin film transistor having the same structure is disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-7399 A [Patent Document 2] JP 2011-228622 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of the present invention is to provide a semiconductor device having stable electrical characteristics. An object of the present invention is to provide a semiconductor device with high performance.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from descriptions in the specification, drawings, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device having a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer has an island-like top surface. The first insulating layer is formed on the top and side surfaces of the semiconductor layer. The first conductive layer is disposed on the first insulating layer and overlaps the semiconductor layer. The semiconductor layer includes a metal oxide, and the first insulating layer includes an oxide. The semiconductor layer has a first region that overlaps with the first conductive layer and a second region that does not overlap with the first conductive layer. The first insulating layer has a third region overlapping the first conductive layer, and a second region overlapping the first conductive layer. and a fourth region that does not overlap with the first element. The first element is phosphorus, boron, magnesium, aluminum, or silicon. Preferably, the first element is a silicon atom. The first element is preferably present in a state of being bonded to oxygen. It is preferred.

[0010] In the above, the second region or the fourth region is analyzed by X-ray photoelectron spectroscopy. It is preferable that a peak due to the oxidation state of the first element is observed.

[0011] In the above, the second region is a region having a higher concentration of the first element than the fourth region. It is preferable to have

[0012] In the above, the first element is concentrated in the second region closer to the first insulating layer. It is preferable to have a high concentration gradient.

[0013] In the above, the concentration of the first element in the fourth region is higher in the vicinity of the semiconductor layer. It is preferable to have a high concentration gradient.

[0014] In the above, the semiconductor layer has a first element concentration of 1×1020 atoms / c m 3 That's it, 1×10 22 atoms / cm 3 It is preferred to have a region where:

[0015] In the above, it is preferable that the semiconductor layer has a second insulating layer. It is preferable that the first insulating layer is provided on the second insulating layer in contact with the semiconductor layer. In the region where the second insulating layer is not formed, it is preferable that the second insulating layer has a portion in contact with the second insulating layer. The insulating layer preferably has a fifth region that does not overlap with the semiconductor layer and contains the first element. It is nice.

[0016] In the above, it is preferable that the second conductive layer is provided. In this case, the second conductive layer The region is located below the second insulating layer and overlaps with the semiconductor layer and the first conductive layer. It is preferable to have

[0017] In the above, a metal oxide layer is provided between the first insulating layer and the first conductive layer. In this case, it is preferable that the metal oxide layer contains at least one of the same elements as the semiconductor layer. preferable.

[0018] Another embodiment of the present invention is a first process for forming an island-shaped semiconductor layer including a metal oxide. a second step of forming a first insulating layer containing an oxide on the island-shaped semiconductor layer; A third step of forming a first conductive layer on the insulating layer so as to overlap a portion of the semiconductor layer; a fourth step of supplying a first element into the first insulating layer and the semiconductor layer in a region not covered by the fourth step; The first element is phosphorus, boron, Magnesium, aluminum or silicon is preferred.

[0019] In the fourth step, the first element is present in the semiconductor layer at a concentration of It is preferable that the concentration be distributed so that the concentration becomes higher closer to the insulating layer.

[0020] In the fourth step, the first element is doped by a plasma ion doping method. Alternatively, it is preferably supplied by using an ion implantation method.

[0021] In addition, the method may further include a fifth step of performing a heat treatment after the fourth step. In this case, the heat treatment is preferably performed at a temperature in the range of 200° C. to 400° C. It is preferred. Effect of the Invention

[0022] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. It is possible to provide a semiconductor device having stable properties, or a display device having high reliability.

[0023] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief description of the drawings]

[0024] [Figure 1] An example of a transistor configuration. [Diagram 2] An example of a transistor configuration. [Diagram 3] An example of a transistor configuration. [Figure 4] An example of a transistor configuration. [Diagram 5] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 6] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 7] FIG. [Figure 8] FIG. [Figure 9] FIG. [Figure 10] FIG. [Figure 11] 1A and 1B are a block diagram and a circuit diagram of a display device. [Figure 12] FIG. [Figure 13] 1 shows an example of a display module configuration. [Figure 14] Example of electronic device configuration. [Figure 15] Example of electronic device configuration. [Figure 16] Example of electronic device configuration. [Figure 17] Calculation results of impurity concentration. [Figure 18] Sheet resistance measurement results. [Figure 19] Sheet resistance measurement results. [Figure 20] Sheet resistance measurement results. [Figure 21] Impurity concentration measurement results. [Figure 22] Electrical characteristics of a transistor. [Diagram 23] Electrical characteristics of a transistor. [Figure 24] Transistor electrical characteristics and reliability evaluation results. [Diagram 25] TDS analysis results. [Figure 26] TDS analysis results. [Figure 27] XPS analysis results. [Figure 28] XPS analysis results. [Figure 29] Electrical characteristics of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, the embodiments will be described with reference to the drawings. The present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily understood by those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0026] In addition, in each figure described in this specification, the size, layer thickness, or area of ​​each component is May be exaggerated for clarity.

[0027] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the This is added to avoid confusion and is not intended to limit the number.

[0028] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0029] In this specification, the functions of the source and drain of a transistor are different. When using polarity transistors, or when the direction of current changes during circuit operation, etc. For this reason, the terms source and drain are often used interchangeably. It is possible to do so.

[0030] In this specification, the channel length direction of a transistor is the direction between the source region and the drain region. This refers to one of the directions parallel to the line that connects the two gate regions at the shortest distance. That is, the channel length The direction corresponds to one of the directions of current flow through the semiconductor layer when the transistor is in the on state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction are determined as one. This may not be possible.

[0031] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0032] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchanged with "conductive film" and The term "insulating film" may sometimes be used interchangeably.

[0033] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source gs is the threshold voltage V th (For p-channel transistors, V th Higher than (i) This refers to a state of being.

[0034] In this specification, a display panel, which is one aspect of a display device, displays (outputs) images on a display surface. Therefore, the display panel is one aspect of an output device.

[0035] In the present specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). inted Circuit) or TCP (Tape Carrier Packa ge) or COG (Chip On Gauge) connectors attached to the board. Display module is a device that has ICs mounted using a method such as display glass. It may be called a display panel, a display unit, or simply a display panel.

[0036] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images, etc. on a display surface. The function of displaying information and detecting when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. The touch panel also functions as a touch sensor that detects the touch of the touch panel. A card is one form of input / output device.

[0037] The touch panel is, for example, a display panel (or display device) with a touch sensor, A touch panel can also be called a display panel (or display device) with touch function. A display panel and a touch sensor panel may be used. It may also be configured to have a touch sensor function inside or on the surface.

[0038] In addition, in this specification, a touch panel substrate on which a connector or IC is mounted is referred to as a touch panel. It may be called a touch panel module, a display module, or simply a touch panel. be.

[0039] (Embodiment 1) In this embodiment, a semiconductor device, a display device, and a manufacturing method thereof according to one embodiment of the present invention will be described. I will explain it below.

[0040] One embodiment of the present invention is a semiconductor layer in which a channel is formed on a formation surface, and a gate insulating film on the semiconductor layer. A gate insulating layer (also called a first insulating layer) and a conductive layer that functions as a gate electrode on the gate insulating layer. The semiconductor layer is a semiconductor specific conductive layer. It is preferable that the semiconductor layer is made of a metal oxide (hereinafter, also referred to as an oxide semiconductor) exhibiting a high conductivity type. .

[0041] The gate insulating layer is provided in contact with the upper surface and the side surface of the island-shaped semiconductor layer. In particular, when a metal oxide is used for the semiconductor layer, the gate insulating layer contains an oxide. It is preferable to do so.

[0042] The semiconductor layer includes a channel forming region where a channel can be formed, a source region, and a drain region. The channel forming region has a pair of low resistance regions which function as a gate region in the semiconductor layer. The pair of low resistance regions are set on either side of the channel forming region. This region has a lower resistance than the channel formation region.

[0043] The pair of low resistance regions preferably contains an impurity element. The impurity element may be hydrogen, Boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon Representative examples of rare gases include helium, neon, etc. , argon, krypton, and xenon. In particular, they may contain boron or phosphorus. preferable.

[0044] In particular, the pair of low resistance regions preferably contains an impurity element that easily bonds with oxygen. For example, boron, phosphorus, aluminum, magnesium, silicon, etc. can be mentioned.

[0045] The impurity elements contained in the pair of low resistance regions have a concentration gradient that increases toward the gate insulating layer. It is preferred that the compound has a structure similar to that of the compound shown in FIG.

[0046] Note that due to the influence of heat during the manufacturing process, the channel formation region may be included in the low resistance region. In such a case, a part of the impurity element in the channel forming region may diffuse. The concentration of the impurity element in the low resistance region is 1 / 10 or less, preferably 1 / 100 of the concentration in the low resistance region. It is preferable that:

[0047] In addition, the gate insulating layer is provided with a portion that contacts the pair of low resistance regions, i.e., the gate electrode and It is preferable that the non-overlapping portion also contains the above impurity element. The portion in contact with the channel forming region, i.e., the portion overlapping with the gate electrode, is It is preferred that no impurities are added.

[0048] A heat treatment is performed in a state where a gate insulating layer containing an oxide is provided in contact with the upper surface of the semiconductor layer. By this, oxygen released from the gate insulating layer can be supplied to the semiconductor layer. This makes it possible to compensate for oxygen vacancies in the semiconductor layer, resulting in highly reliable transistors. It is possible.

[0049] On the other hand, when oxygen is supplied to the low resistance region, the carrier density decreases and the electrical resistance increases. However, in one embodiment of the present invention, the gate insulating layer is provided with a low resistance region. The above-mentioned impurity elements are added to the part where the oxide film is heated. In addition, the amount of oxygen released can be reduced by adding the above-mentioned impurity elements. As a result, the supply of oxygen from the gate insulating layer to the low resistance region is suppressed, The resistive region can maintain a low electrical resistance.

[0050] By adopting such a structure, oxygen vacancies are sufficiently reduced, and the carrier density is extremely low. It has a channel forming region and a source region and a drain region with extremely low electrical resistance. As a result, a semiconductor device having excellent electrical characteristics and high reliability can be realized.

[0051] Such a transistor is formed by, for example, forming a gate insulating layer and a semiconductor layer using a gate electrode as a mask. The conductor layer is subjected to the above-mentioned treatment for supplying the impurity element and then subjected to a heat treatment. It can be made.

[0052] At this time, the impurity element is supplied by a plasma ion doping method or an ion implantation method. These methods are preferred because they make it easier to adjust the depth to which ions are added. This makes it easier to target the region including the gate insulating layer and the semiconductor layer with ions.

[0053] In addition, when doping the impurity element, the region of the semiconductor layer on the gate insulating layer side or the semiconductor layer The ion supply conditions are set so that the impurity concentration near the interface between the gate insulating layer and the semiconductor substrate is the highest. This allows for appropriate deposition of both the semiconductor layer and the gate insulating layer in a single process. Furthermore, it is possible to add impurity elements at a high concentration to the upper part of the low resistance region. By adding a pure element to reduce the resistance, the low resistance region and the source or drain electrode In addition, the contact resistance of the gate insulating layer near the low resistance region can be reduced. By forming a region with a high concentration of impurity elements in the This effectively suppresses the diffusion of oxygen in the gate insulating layer into the low resistance region. This can be done.

[0054] For example, the low resistance region of the semiconductor layer has an impurity concentration of 1×10 19 atoms / cm 3 Below Top, 1×10 23 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 That's it, 1×10 22 atoms / cm 3 It is preferable that the region is equal to or smaller than 1. The low resistance region of the conductor layer has a higher impurity concentration than the region in contact with the low resistance region of the gate insulating layer. It is preferable that the region has a low resistance. This makes it possible to form a low resistance region with extremely low resistance. Cut.

[0055] In addition, the region of the gate insulating layer that does not overlap with the gate electrode has a higher impurity concentration than the low resistance region. It is preferable that the gate electrode includes a region that is lower and higher than the portion that overlaps the gate electrode.

[0056] In addition, when an element that easily bonds with oxygen is used as an impurity element, the impurity element In other words, the impurity element does not take away oxygen from the semiconductor layer. In this case, oxygen vacancies occur in the semiconductor layer, and the oxygen vacancies combine with hydrogen in the film to form carriers. Furthermore, since the impurity elements in the semiconductor layer are stable in an oxidized state, A stable low resistance region can be realized without desorption due to heat applied during the process. For example, if temperatures of 400°C or higher, 600°C or higher, or 800°C or higher are applied during the process, Even if the resistance of the semiconductor device is low, a stable low resistance region can be maintained.

[0057] Generally, when a silicon film is used as a semiconductor layer, impurities are added to the semiconductor. A donor that supplies electrons or an acceptor that supplies holes is used, and the donor Alternatively, acceptors can replace silicon atoms to create N-type or P-type conductivity in the semiconductor layer. On the other hand, as described above, in one embodiment of the present invention, Impurity elements contained in the conductor remove oxygen from the oxide semiconductor, causing oxygen vacancies in the semiconductor layer. The impurity element itself must have the function of generating carriers. In this respect, the mechanism for reducing the resistance of the semiconductor layer in one embodiment of the present invention is as follows: It can be said that this is completely different from the case of silicon, etc.

[0058] It is also preferable to use an insulating film containing an oxide as the gate insulating layer. It is preferable that the insulating layer contains oxygen (also called excess oxygen) that is desorbed by heating. At this time, the impurity elements in the gate insulating layer are bonded to the excess oxygen in the gate insulating layer. The excess oxygen and the impurity element are bonded and stabilized, and the impurity element is added. In the region where the oxygen is diffused, almost no oxygen is desorbed even when the material is heated. This makes it difficult for oxygen to be supplied from the gate insulating layer to the low resistance region. While preventing the increase in resistance due to oxygen deficiency, oxygen is supplied to the channel formation region, This reduces the loss, resulting in a highly reliable transistor with good electrical characteristics. .

[0059] The impurity elements used are those that bond with oxygen in the semiconductor layer and the gate insulating layer to stabilize the oxide. For example, it is preferable to use an element whose oxide can exist in a solid state under standard conditions. Particularly preferred elements are rare gases, typical nonmetallic elements other than hydrogen, typical metal elements, and the like. In particular, boron, phosphorus, aluminum, It is preferable to use aluminum, magnesium, silicon, etc.

[0060] A more specific example will be described below with reference to the drawings.

[0061] [Configuration example 1] FIG. 1A is a top view of a transistor 100, and FIG. 1B is a top view of the transistor 100 shown in FIG. FIG. 1C is a cross-sectional view taken along the dashed line A1-A2 shown in FIG. It corresponds to a cross-sectional view taken along the dashed line B1-B2. Some of the components of the transistor 100 (such as a gate insulating layer) are omitted in the figure. The dashed line A1-A2 direction is the channel length direction, and the dashed line B1-B2 direction is the channel width direction. In addition, the top view of the transistor is the same as that of FIG. Similarly, some of the components are omitted in the drawings.

[0062] The transistor 100 is provided on a substrate 102, an insulating layer 103, a semiconductor layer 108, an insulating The insulating layer 116 is a dielectric layer 118. The insulating layer 118 is a dielectric layer 116. The insulating layer 118 is a dielectric layer 118. The insulating layer 116 is a dielectric layer. The island-shaped semiconductor layer 108 is provided on the insulating layer 103. The insulating layer 110 is The metal oxide layer 114 and the semiconductor layer 108 are provided in contact with each other. The conductive layer 112 is stacked in this order on the insulating layer 110 and overlaps with the semiconductor layer 108. The insulating layer 116 has a portion that is in contact with the upper surface of the insulating layer 110, a side surface of the metal oxide layer 114, The insulating layer 118 is provided to cover the upper surface of the insulating layer 116 and the conductive layer 112. It is set up as follows.

[0063] A portion of the conductive layer 112 functions as a gate electrode. A portion of the insulating layer 110 functions as a gate insulator. The transistor 100 includes a gate electrode provided on the semiconductor layer 108. This is a so-called top-gate transistor.

[0064] As shown in FIGS. 1A and 1B, the transistor 100 is formed on an insulating layer 118. The conductive layer 120a and the conductive layer 120b may be included. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. 1 and 2 correspond to the openings 141 provided in the insulating layer 118, the insulating layer 116, and the insulating layer 110, respectively. The opening 141b is electrically connected to a region 108n, which will be described later.

[0065] The semiconductor layer 108 preferably comprises a metal oxide.

[0066] For example, the semiconductor layer 108 may be made of indium and M (where M is gallium, aluminum, or silicon). Boron, Yttrium, Tin, Copper, Vanadium, Beryllium, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium one or more selected from the group consisting of aluminum, tantalum, tungsten, and magnesium; and zinc. In particular, M is aluminum, gallium, yttrium, or It is preferable to use one or more elements selected from tin.

[0067] In particular, the semiconductor layer 108 is made of an oxide containing indium, gallium, and zinc. It is preferred.

[0068] The semiconductor layer 108 may be a layer having a different composition, a layer having a different crystallinity, or a layer having a different impurity concentration. Alternatively, a laminate structure in which different layers are laminated may be used.

[0069] The conductive layer 112 and the metal oxide layer 114 are processed so that their top surface shapes are roughly the same as each other. It has been done.

[0070] In this specification, the term "approximately coincident upper surface shapes" means that there is at least a slight difference between the layers. For example, the upper and lower layers have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where a part of the surface is processed using the same mask pattern. The shells do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In this case too, it is said that "the top surface shapes roughly match."

[0071] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is It functions as a barrier film that prevents oxygen contained therein from diffusing into the conductive layer 112. The metal oxide layer 114 is formed by diffusing hydrogen and water contained in the conductive layer 112 to the insulating layer 110 side. The metal oxide layer 114 also functions as a barrier film to prevent, for example, A material that is less permeable to oxygen and hydrogen than 0 can be used.

[0072] The metal oxide layer 114 makes it easier for the conductive layer 112 to absorb oxygen, such as aluminum or copper. Even if a thin metal material is used, oxygen does not diffuse from the insulating layer 110 to the conductive layer 112. Even when the conductive layer 112 contains hydrogen, the conductive layer 112 can be prevented from Therefore, it is possible to prevent hydrogen from diffusing into the semiconductor layer 108 through the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 is made extremely low. It is possible.

[0073] The metal oxide layer 114 can be made of an insulating material or a conductive material. If the metal oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. If the metal oxide layer 114 is conductive, it functions as a part of the gate electrode.

[0074] The metal oxide layer 114 is made of an insulating material having a higher dielectric constant than silicon oxide. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable. It is preferable to use a gate film or the like since the driving voltage can be reduced.

[0075] The metal oxide layer 114 may be, for example, indium oxide or indium tin oxide (ITO). Conductive oxides such as silicon-doped indium tin oxide (ITSO) In particular, conductive oxides containing indium are preferred because of their high conductivity. .

[0076] The metal oxide layer 114 may be an oxide material containing at least one of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use the same structure as the semiconductor layer 108 as the metal oxide layer 114. By applying metal oxide films formed using sputtering targets, equipment can be standardized This is preferable because it is possible to

[0077] Alternatively, both the semiconductor layer 108 and the metal oxide layer 114 may contain indium and gallium. In the case of using a metal oxide material containing gallium, the composition (content) of gallium is higher than that of the semiconductor layer 108. It is preferable to use a material having a high oxygen blocking property. At this time, the semiconductor layer 108 contains a material having a higher indium content than the metal oxide layer 114. By using such a material, the field-effect mobility of the transistor 100 can be increased.

[0078] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering device, it is formed in an atmosphere containing oxygen gas. This allows oxygen to be suitably added to the insulating layer 110 and the semiconductor layer 108.

[0079] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions sandwiching the region. The region of the semiconductor layer 108 that overlaps with the conductive layer 112 is a transistor On the other hand, the region 108n functions as a channel forming region of the transistor 100. The source and drain regions of the transistors are connected to the source and drain electrodes of the transistors.

[0080] The region 108n is a region having a lower resistance and a higher carrier concentration than the channel formation region. These regions are also called regions with high oxygen vacancy density, regions with high impurity concentration, or regions that are n-type. can be done.

[0081] The region 108n of the semiconductor layer 108 is a region containing an impurity element. Examples of such elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and Representative examples of rare gases include helium, neon, and arsenic. In particular, it is preferable to use boron or phosphorus. In addition, two or more of these elements may be contained.

[0082] The insulating layer 110 is a region that contacts the channel formation region of the semiconductor layer 108, i.e., the conductive layer 1 The insulating layer 110 has a region overlapping with the low resistance region 12 of the semiconductor layer 108. 08n and has a region that does not overlap with the conductive layer 112.

[0083] In addition, the insulating layer 103 and the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 are It is preferable to use an oxide film. For example, a silicon oxide film, a silicon oxynitride film, an oxide An oxide film such as an aluminum film can be used. In the manufacturing process, oxygen is removed from the insulating layer 103 and the insulating layer 110 by heat treatment, etc., and the semiconductor The oxygen vacancies in the semiconductor layer 108 can be reduced by supplying the oxygen to the channel formation region of the semiconductor layer 108. can.

[0084] FIG. 2 shows an enlarged cross-sectional view of a region P surrounded by a dashed line in FIG.

[0085] The insulating layer 110 has a region 110d containing the above-mentioned impurity element. The region 110d is The region 110d is located at least near the interface with the region 108n. In a region where the insulating layer 108 is not provided and does not overlap with the conductive layer 112, at least the insulating layer 10 It is also located near the interface with 3. As shown in Figs. 1(B), (C), and 2, The region 110d is not provided in a portion that contacts the channel formation region of the semiconductor layer 108. It is preferred.

[0086] The insulating layer 103 contains the above-mentioned impurity element near the interface where the insulating layer 103 contacts the insulating layer 110. As shown in FIG. 2, the region 103d is connected to the region 108n. In this case, impurities in the portion overlapping with the region 108n may be removed. The concentration of the substance is lower than that in the portion in contact with the insulating layer 110.

[0087] Here, the impurity concentration in the region 108n becomes higher as it approaches the insulating layer 110. It is preferable that the upper part of the region 108n has a lower resistance and a higher concentration gradient. Therefore, the contact resistance with the conductive layer 120a (or the conductive layer 120b) can be reduced more effectively. In addition, compared to the case where the concentration is uniform across the entire region 108n, The total amount of impurity elements in 108n can be reduced, so that the cha The amount of impurities that can diffuse into the panel formation region can be kept low.

[0088] Moreover, the impurity concentration in the region 110d becomes higher as it approaches the semiconductor layer 108. It is preferable to have such a concentration gradient. In the insulating layer 110, the region 110d to which the above-mentioned impurity element is added is different from the other regions. Therefore, the region 108n of the insulating layer 110 can be prevented from releasing oxygen. The region 110d located near the interface functions as a blocking layer against oxygen, and the region 1 This effectively reduces the amount of oxygen supplied to the 08n.

[0089] As will be described later, the process of doping the regions 108n and 110d with impurity elements is a conductive process. This can be done by using layer 112 as a mask. This allows the formation of region 108n and at the same time, Region 110d may be formed in a self-aligned manner.

[0090] In FIG. 2 and other figures, the portion of the insulating layer 110 with a high impurity concentration is To exaggerate the proximity of the semiconductor layer 110, region 110d is shown as Although the hatched pattern is only shown near 08, the insulating layer 110 The impurity element may be contained throughout the thickness direction.

[0091] The regions 108n and 110d each have an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×10 23 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3 Less than or equal to 1×10 20 at oms / cm 3 That's it, 1×10 22 atoms / cm 3 It is preferred to include a region that is In addition, the region 108n has a higher impurity concentration than the region 110d of the insulating layer 110. It is preferable for the region 108n to have a component, since this can more effectively reduce the electrical resistance of the region 108n.

[0092] The concentrations of impurities contained in the regions 108n and 110d are measured by, for example, secondary ion mass spectrometry. Secondary Ion Mass Spectrometry (SIMS) and , X-ray Photoelectron Spectroscopy (XPS) When XPS analysis is used, By combining ion sputtering from the front or back side with XPS analysis, The concentration distribution in the thickness direction can be known.

[0093] In the region 108n, the impurity element is preferably present in an oxidized state. For example, impurity elements such as boron, phosphorus, magnesium, aluminum, and silicon are used. It is preferable to use an element that is easily oxidized. Since it can combine with the oxygen in 108 and exist stably in an oxidized state, it can be used at high temperatures ( For example, even if exposed to temperatures of 400°C or higher, 600°C or higher, or 800°C or higher, In addition, the impurity element removes oxygen from the semiconductor layer 108, Many oxygen vacancies are generated in the region 108n. These oxygen vacancies combine with hydrogen in the film, Since the region 108n becomes a carrier supply source by this, the region 108n becomes in a state of extremely low resistance.

[0094] In addition, when performing a process at high temperatures in a later step, the film near the outside or the region 108n may be damaged. If too much oxygen is supplied to the region 108n, the resistance may increase. Therefore, when performing a high-temperature process, the insulating layer 1 having a high barrier property against oxygen is required. It is preferable to treat the substrate while covered with 16.

[0095] Also in the region 110d, the impurity element is preferably present in an oxidized state. Such easily oxidizable elements are bonded to oxygen in the insulating layer 110 and remain in an oxidized state. Because it can exist stably, it is prevented from being desorbed even when exposed to high temperatures in later processes. In particular, the insulating layer 110 contains oxygen (also called excess oxygen) that can be desorbed by heating. In this case, the excess oxygen and the impurity element are bonded and stabilized, so that the region 110d It is possible to suppress the supply of oxygen to the region 108n. Since the region 110d containing the pure element is in a state in which oxygen is difficult to diffuse, the region 110d It is also possible to prevent oxygen from being supplied to the region 108n from above through the region 110d. This can be done.

[0096] For example, when boron is used as an impurity element, the impurity elements contained in the regions 108n and 110d are The boron in the sample can exist in a state bound to oxygen. This is because the B2 This can be confirmed by observing the spectrum peaks due to O3 bonds. In the case of or the peak intensity is so small that it is buried in the background noise at the lower limit of measurement. It becomes smaller.

[0097] The insulating layer 116 and the insulating layer 118 function as protective layers to protect the transistor 100. In addition, either the insulating layer 116 or the insulating layer 118 may be formed by discharging the insulating layer 110. It is preferable that the oxide has a function of preventing oxygen from diffusing to the outside. Inorganic insulating materials such as nitrides can be used. A more specific example is silicon nitride. silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, Using inorganic insulating materials such as aluminum nitride, hafnium oxide, and hafnium aluminate It is possible.

[0098] In this example, a laminated structure of an insulating layer 116 and an insulating layer 118 is used as the protective layer. However, either the insulating layer 116 or the insulating layer 118 may not be provided if it is not necessary. .

[0099] Here, the semiconductor layer 108 and oxygen vacancies that may be formed in the semiconductor layer 108 will be described. do.

[0100] The oxygen vacancies formed in the semiconductor layer 108 are problematic because they affect the transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen bonds to the oxygen vacancies. When a carrier source is generated in the semiconductor layer 108, This causes a change in the electrical characteristics of the transistor 100, typically a shift in the threshold voltage. In addition, it is preferable that the semiconductor layer 108 have fewer oxygen vacancies.

[0101] Therefore, in one aspect of the present invention, the insulating film near the semiconductor layer 108, specifically, the semiconductor The insulating layer 110 located above the dielectric layer 108 and the insulating layer 103 located below the dielectric layer 108 are made of oxide. The insulating layer 103 and the insulating layer 110 are heated during the manufacturing process, and the insulating layer 103 and the insulating layer 110 are turned into a semiconductor film. By transferring oxygen to the semiconductor layer 108, oxygen vacancies in the semiconductor layer 108 can be reduced. It becomes Noh.

[0102] In addition, the semiconductor layer 108 preferably has a region in which the atomic ratio of In is greater than the atomic ratio of M. The higher the atomic ratio of In, the more the field effect mobility of the transistor can be improved. Cut.

[0103] In the case of metal oxides containing In, Ga, and Zn, the bonding strength between In and oxygen is greater than that between Ga and oxygen. Since the bonding strength is weaker than that of the element, when the atomic ratio of In is large, oxygen deficiency occurs in the metal oxide film. The same problem occurs when the metal element M is used instead of Ga. If there are many oxygen vacancies in the metal oxide film, the electrical characteristics of the transistor tend to deteriorate. This can result in degradation and reduced reliability.

[0104] However, in one embodiment of the present invention, the semiconductor layer 108 containing a metal oxide contains a very large amount of Since oxygen can be supplied, it is possible to use metal oxide materials with a high In atomic ratio. This allows the device to have extremely high field-effect mobility, stable electrical characteristics, and high reliability. It is possible to realize a transistor having such a structure.

[0105] For example, the atomic ratio of In is 1.5 times or more, or 2 times or more, or Preferably, the metal oxide has a concentration of 1000 or more times the surface area of ​​the metal oxide, 3 times or more, 3.5 times or more, or 4 times or more. It is possible.

[0106] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is In:M:Zn=5:1. : 6 or close thereto (when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 or more, including 7 or less). Alternatively, the ratio of the numbers of In, M, and Zn atoms is It is preferable that the composition ratio of In:M:Zn is 4:2:3 or in the vicinity thereof. As for the composition, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 108 may be approximately equal. That is, the ratio of the numbers of In, M, and Zn atoms is In:M:Zn=1:1:1 or It may also include nearby materials.

[0107] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. By using this in a driver, it is possible to provide a display device with a narrow frame width (also called a narrow frame). In addition, the above-mentioned high field effect mobility transistor is used as a source driver (especially the source It can be used for a demultiplexer connected to the output terminal of a shift register of a driver. As a result, it is possible to provide a display device having a small number of wires connected to the display device.

[0108] Even if the semiconductor layer 108 has a region in which the atomic ratio of In is greater than the atomic ratio of M, However, when the crystallinity of the semiconductor layer 108 is high, the field effect mobility may be reduced. The crystallinity of 108 can be measured, for example, by X-ray diffraction (XRD). Analyze using a transmission electron microscope (TEM) or This can be analyzed using a 3D electron microscope.

[0109] Here, impurities such as hydrogen or moisture that are mixed into the semiconductor layer 108 may affect the transistor characteristics. Therefore, in the semiconductor layer 108, hydrogen or water The fewer the impurities such as fluorine, the better. By using a thin film, a transistor having excellent electrical characteristics can be fabricated. The low impurity concentration and low defect level density (reduced oxygen vacancies) allow the The carrier density can be reduced. The electrical characteristics of a transistor are such that the threshold voltage is negative (also called normally-on). In addition, a transistor using such a metal oxide film has a significantly low off-state current. Therefore, extremely small characteristics can be obtained.

[0110] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0111] For example, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different compositions. For example, when an In-M-Zn oxide is used, the number of atoms of In, M, and Zn is The ratio is In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn=1 :1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M:Zn =1:3:2 or a film formed using a sputtering target with a ratio of approximately It is preferable to use two or more of them in a laminate.

[0112] In addition, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different crystallinity. In this case, the same oxide target can be used, but the deposition conditions can be changed to reduce the exposure to air. It is preferable that they are formed continuously and without touching.

[0113] For example, the oxygen flow rate during deposition of the first metal oxide film is set to be equal to or lower than the oxygen flow rate during deposition of the second metal oxide film. The oxygen flow rate ratio is set to be smaller than that during deposition of the first metal oxide film. During the film formation, oxygen is not allowed to flow. This prevents oxygen from being introduced during the formation of the second metal oxide film. In addition, the first metal oxide film is more effective in supplying the element than the second metal oxide film. The film has lower crystallinity and higher electrical conductivity than the first film. The second metal oxide film is made to have higher crystallinity than the first metal oxide film, so that the semiconductor layer 1 Damage during processing of 08 and during deposition of the insulating layer 110 can be suppressed.

[0114] More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is set to 0% or more and less than 50%. Preferably, it is 0% or more and 30% or less, more preferably, it is 0% or more and 20% or less, typically, it is 10%. The oxygen flow rate during the formation of the second metal oxide film is set to 50% or more and 100% or less. Preferably, the ratio is 60% or more and 100% or less, more preferably, 80% or more and 100% or less, and even more preferably, The ratio is preferably 90% or more and 100% or less, and typically 100%. The first and second metal oxide films may be formed under different conditions such as pressure, temperature, and power. By keeping all other conditions the same except for the oxygen flow rate, the time required for the film formation process can be shortened. This is preferable.

[0115] By adopting such a configuration, the transistor 100 has excellent electrical characteristics and high reliability. This can be achieved.

[0116] The above is a description of configuration example 1.

[0117] [Configuration example 2] Hereinafter, a configuration example of a transistor having a partly different configuration from the above configuration example 1 will be described. In the following, explanations of parts that overlap with the above-mentioned configuration example 1 may be omitted. In the drawings shown below, parts having the same functions as those in the above configuration example 1 are indicated by hatching. In some cases, the turns are the same and no code is assigned.

[0118] FIG. 3A is a top view of a transistor 100A, and FIG. 3B is a top view of a transistor 100B. 3(C) is a cross-sectional view of the channel length direction of transistor 100A, and FIG. 3(D) is a cross-sectional view of the channel width direction of transistor 100A. 4 is a cross-sectional view in the direction.

[0119] The transistor 100A has a conductive layer 106 between the substrate 102 and the insulating layer 103. The main difference from the configuration example 1 is that the conductive layer 106 overlaps the semiconductor layer 108 and the conductive layer 112. It has a folding area.

[0120] In the transistor 100A, the conductive layer 106 is a first gate electrode (bottom gate electrode). The conductive layer 112 functions as a second gate electrode (also called a top gate electrode). A part of the insulating layer 103 functions as a first gate insulating layer. and a portion of the insulating layer 110 functions as a second gate insulating layer.

[0121] A portion of the semiconductor layer 108 overlapping with at least one of the conductive layer 112 and the conductive layer 106 In the following description, for ease of explanation, the semiconductor layer 10 The portion of the conductive layer 112 of the conductive layer 8 is sometimes called a channel formation region. The portion that does not overlap with the layer 112 but overlaps with the conductive layer 106 (the portion including the region 108n) is also A channel can be formed.

[0122] As shown in FIG. 3C, the conductive layer 106 includes a metal oxide layer 114 and an insulating layer 110. and is electrically connected to the conductive layer 112 through an opening 142 provided in the insulating layer 103. In this way, the conductive layer 106 and the conductive layer 112 can be given the same potential. can be done.

[0123] The conductive layer 106 may be made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, when a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. This is preferable because

[0124] As shown in FIGS. 3A and 3C, the conductive layer 112 and It is preferable that the conductive layer 106 protrudes outward beyond the end of the semiconductor layer 108. At this time, as shown in FIG. 3C, the entire semiconductor layer 108 in the channel width direction is covered with the insulating layer 11. 0 and the insulating layer 103, the conductive layer 112 and the conductive layer 106 cover the conductive layer 106.

[0125] With this configuration, the semiconductor layer 108 is subjected to an electric field generated by a pair of gate electrodes. In this case, the conductive layer 106 and the conductive layer 112 are electrically surrounded by the same material. It is preferable to apply a potential to the semiconductor layer 108 in order to induce a channel in the semiconductor layer 108. Since the electric field can be effectively applied, the on-current of the transistor 100A can be increased. This also makes it possible to miniaturize the transistor 100A.

[0126] The conductive layer 112 and the conductive layer 106 may not be connected to each other. A constant potential is applied to one of the gate electrodes of the transistor 100A, and a signal for driving the transistor 100A is applied to the other gate electrode. In this case, the transistor 100A may be turned on by applying a potential to one electrode. It is also possible to control the threshold voltage when driving the device with one electrode.

[0127] This concludes the description of configuration example 2.

[0128] [Application example] In the following description, a semiconductor film containing impurities is used as one electrode of a capacitor element, and a transistor is An example in which a capacitance element is formed on the same surface will be described.

[0129] In the cross-sectional view shown in FIG. 4A, a capacitor is arranged next to the transistor 100 illustrated in Configuration Example 1. An element 130A is provided.

[0130] In the cross-sectional view shown in FIG. 4B, the transistor 100A illustrated in the configuration example 2 is A capacitive element 130A is provided.

[0131] The capacitive element 130A is provided between the semiconductor layer 108c and the conductive layer 120b and functions as a dielectric. The insulating layer 110, the insulating layer 116, and the insulating layer 118 are provided.

[0132] The semiconductor layer 108c is provided on the same surface as the semiconductor layer 108. For example, the semiconductor layer 1 The region 108c is a region obtained by processing the same metal oxide film as the semiconductor layer 108, and then forming a region having the same impurity as the region 108n. It can be formed by adding pure elements.

[0133] With this configuration, the capacitance element 130A can be manufactured without increasing the number of steps. can be done.

[0134] The capacitor 130B shown in FIG. 4C has a structure in which a conductive layer 106c and a semiconductor layer 108c are connected to each other. 1, and has an insulating layer 103 that functions as a dielectric.

[0135] The conductive layer 106c is provided on the same surface as the conductive layer 106. The conductive layer 106 can be formed by processing the same conductive film.

[0136] Since the thickness of the dielectric of the capacitive element 130B can be made thinner than that of the capacitive element 130A, A large-capacitance capacitive element can be formed.

[0137] The above is a description of the application example.

[0138] [Components of Semiconductor Devices] Next, components included in the semiconductor device of this embodiment will be described in detail.

[0139] 〔substrate〕 There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, single crystals made of silicon or silicon carbide are Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates A plate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. are used as the substrate 102. In addition, the substrate 102 may be a substrate on which a semiconductor element is provided. It may be used.

[0140] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100, etc. The release layer may be removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 100 can be separated from the other substrate and transferred to another substrate. The above can be transferred to substrates with poor heat resistance or flexible substrates.

[0141] [Insulating layer 103] The insulating layer 103 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The insulating layer 103 can be formed by appropriately using a photo-induced laser deposition (PLD) method or the like. The insulating film can be formed as a single layer or a stack of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the semiconductor layer 108, at least a semiconductor A region in contact with the insulating layer 108 is preferably formed using an oxide insulating film. It is preferable to use a film that releases oxygen when heated.

[0142] The insulating layer 103 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitrogen. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The above may be used, and the layer may be formed as a single layer or a multilayer.

[0143] In addition, the insulating layer 103 may have a film other than an oxide film such as a silicon nitride film on the side in contact with the semiconductor layer 108. When the above-mentioned film is used, a pretreatment such as an oxygen plasma treatment is performed on the surface in contact with the semiconductor layer 108. and oxidizing the surface or the vicinity of the surface.

[0144] [Conductive Film] The conductive layer 112 and the conductive layer 106 function as a gate electrode and a source electrode, respectively. The conductive layer 120a and the conductive layer 120b functioning as a drain electrode may be made of chromium, copper, or alumina. Aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, Metal elements selected from nickel, iron, and cobalt, or alloys containing the above metal elements. They can be formed using gold or an alloy combining the above-mentioned metal elements.

[0145] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are made of In. -Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti -Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. Alternatively, an oxide conductor or a metal oxide film may be used.

[0146] Here, an oxide conductor (OC) will be described. For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. When the metal oxide is heated, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. The metal oxide that has been made conductive can be called an oxide conductor.

[0147] In addition, as the conductive layer 112, etc., a conductive film containing the oxide conductor (metal oxide) and a metal Alternatively, a laminated structure of a conductive film containing a metal or an alloy may be used. In this case, the insulating film that functions as a gate insulating film is It is preferable to apply a conductive film containing an oxide conductor to the side in contact with the edge layer.

[0148] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are made of the above-mentioned gold. Among the group elements, titanium, tungsten, tantalum, and molybdenum are particularly preferred. It is preferable to use one or more of the above. In particular, it is preferable to use a tantalum nitride film. The tantalum nitride film has electrical conductivity and has the following properties with respect to copper, oxygen, and hydrogen: Since it has a high barrier property and releases little hydrogen from itself, it is in contact with the semiconductor layer 108. The conductive film can be preferably used as a conductive film for forming a conductive layer or a conductive film in the vicinity of the semiconductor layer 108.

[0149] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film for the transistor 100, etc., is formed by PECVD. The insulating layer 110 can be formed by a sputtering method or the like. Silicon oxide film, silicon nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film tungsten oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, Magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film, or more The insulating layer 110 may have a laminated structure of two layers or three or more layers. The above laminated structure may also be used.

[0150] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film. It is more preferable to have a region containing oxygen in excess of the stoichiometric composition. The insulating layer 110 is an insulating film capable of releasing oxygen. For example, The insulating layer 110 is formed by the above-mentioned method, and the insulating layer 110 after the film formation is subjected to a heat treatment in an oxygen atmosphere. Alternatively, an oxide film is formed on the insulating layer 110 in an oxygen atmosphere. Oxygen can also be supplied into the insulating layer 110 by, for example, forming a film therein.

[0151] In addition, the insulating layer 110 is made of a material having a higher dielectric constant than silicon oxide or silicon oxynitride. Materials such as hafnium oxide can also be used. This allows the thickness of the insulating layer 110 to be increased. It is possible to suppress leakage current caused by tunnel current. In particular, hafnium oxide, which has crystallinity, is It is preferable because it has a higher relative dielectric constant than crystalline hafnium oxide.

[0152] [Semiconductor Layer] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form an In-M-Zn oxide film, The sputtering target used in the present invention must have an atomic ratio of In equal to or greater than that of M. The atomic ratio of the metal elements in such a sputtering target is preferably In:M :Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5: 1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn= 6:1:6, In:M:Zn=5:2:5, etc.

[0153] In addition, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because the semiconductor layer 108 having crystallinity can be easily formed. The atomic ratio of the semiconductor layer 108 is determined by the atomic ratio of the metal elements contained in the sputtering target. For example, the sputtering used for the semiconductor layer 108 may vary by ±40%. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], the film is formed. The composition of the semiconductor layer 108 is approximately In:Ga:Zn=4:2:3 [atomic ratio]. There may be cases where this occurs.

[0154] In addition, when the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, When the atomic ratio of Ga is 4, the atomic ratio of Ga is 1 to 3, and the atomic ratio of Zn is 2. The atomic ratio of In:Ga:Zn is 5:1:6 or less. When describing it as being in the vicinity of , when the atomic ratio of In is 5, the atomic ratio of Ga is 0. The atomic ratio of Zn is greater than 1 and less than 2, and includes the case where the atomic ratio of Zn is greater than 5 and less than 7. When describing that the atomic ratio of In:Ga:Zn is 1:1:1 or close to that, When the atomic ratio of Ga is 1, the atomic ratio of Zn is 0.1 or more and 2 or less. This includes cases where the numerical ratio is greater than 0.1 and less than 2.

[0155] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wider energy gap than silicon, As a result, the off-state current of the transistor can be reduced.

[0156] In addition, the semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure is, for example, This includes the CAAC structure, polycrystalline structure, microcrystalline structure, and amorphous structure described below. In the structure, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density. low.

[0157] Below, we explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0158] The CAAC structure has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystal structures of thin films, etc., and each nanocrystal has a c-axis oriented in a specific direction and a-axis and The b-axis and b-axis do not have any orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, thin films with CAAC structure have the following characteristics: The c-axis of the thin film is oriented in the thickness direction, the normal direction to the surface on which the film is formed, or the normal direction to the surface of the thin film. It has the characteristic of being easy to use.

[0159] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur. The crystallinity may be reduced by the inclusion of impurities or the generation of defects. It can be said that CAAC- is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). The physical properties of an oxide semiconductor having an OS are stable. The oxide semiconductor used is heat resistant and highly reliable.

[0160] In crystallography, the three axes that make up a unit cell, the a-axis, the b-axis, and the c-axis (crystal It is common to take a unit cell with a specific axis as the c-axis for the lattice. In a crystal with this structure, the two axes parallel to the plane direction of the layers are the a-axis and the b-axis, and the axis that intersects the layers is the Generally, the c-axis is taken as the c-axis. A typical example of a crystal with such a layered structure is Graphite is classified as a hexagonal crystal, and the a- and b-axes of the unit cell are parallel to the cleavage plane. The c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure The InGaZnO4 crystal can be classified as a hexagonal system, and the a-axis and The a- and b-axes are parallel to the plane of the layer, and the c-axis is perpendicular to the layers (i.e., the a- and b-axes).

[0161] An example of the crystal structure of a metal oxide will be described. In the following, In-Ga-Zn oxide Sputtering was performed using a Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). A metal oxide film formed by the ring method will be described as an example. Metal oxide formed by sputtering at a plate temperature of 100°C to 130°C is either the nc (nano crystal) structure or the CAAC structure. On the other hand, the substrate temperature is set to room temperature (RT). Metal oxides formed by sputtering tend to have an nc crystal structure. Room temperature (RT) as used herein includes the temperature at which the substrate is not intentionally heated.

[0162] [Example of manufacturing method] An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below. The transistor 100A illustrated in the second configuration example will be described as an example.

[0163] The thin films (insulating film, semiconductor film, conductive film, etc.) constituting the semiconductor device are formed by sputtering. Chemical Vapor Deposition (CVD) method , vacuum deposition, pulsed laser deposition (PLD) ion) method, Atomic Layer Deposition (ALD) The CVD method can be a plasma-enhanced chemical vapor deposition (PEC) method. There are methods such as the VD (Plasma Enhanced CVD) method and the thermal CVD method. One of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD). c CVD) method.

[0164] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are formed by spin coating, Dip, spray application, inkjet, dispensing, screen printing, offset Printing, doctor knife, slit coat, roll coat, curtain coat, knife coat It can be formed by the above method.

[0165] In addition, when processing the thin films that constitute the semiconductor device, photolithography and other methods are used. In addition, nanoimprinting, sandblasting, lift-off, The thin film may be processed by a method such as a masking method using a metal mask. The island-shaped thin film may be directly formed by the film method.

[0166] There are two typical photolithography methods. A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the mask after forming a photosensitive thin film. Then, development is performed to process the thin film into a desired shape.

[0167] In the photolithography method, the light used for exposure is, for example, i-line (wavelength 365 nm), Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may be performed by immersion lithography. Using extreme ultraviolet (EUV) and X-rays, Also, instead of light for exposure, an electron beam can be used. The use of light, X-rays or electron beams is preferable because it allows extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask is It is not necessary.

[0168] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as the above can be used.

[0169] 5 and 6 show the transistor 100A at each stage of the manufacturing process. The cross sections in the channel length direction and the channel width direction are shown side by side.

[0170] [Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a gate electrode. A functional conductive layer 106 is formed.

[0171] [Formation of insulating layer 103] Subsequently, an insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 5(A)). The insulating layer 103 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like. can.

[0172] After the insulating layer 103 is formed, a treatment for supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere can be performed. In the first embodiment, oxygen is supplied to the insulating layer 103 by plasma ion doping or ion implantation. Good too.

[0173] [Formation of Semiconductor Layer 108] Next, a metal oxide film is formed on the insulating layer 103 and processed to form island-shaped semiconductor layers. The conductor layer 108 is formed (FIG. 5(B)).

[0174] The metal oxide film is formed by a sputtering method using a metal oxide target. is preferred.

[0175] In addition, when forming a metal oxide film, in addition to oxygen gas, an inert gas (e.g., helium Gas such as argon gas, xenon gas, etc. may be mixed. The higher the ratio of oxygen gas in the total deposition gas (hereinafter referred to as the oxygen flow ratio), the better the deposition efficiency. This can improve the crystallinity of the metal oxide film, resulting in highly reliable transistors. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. The transistor may be a transistor having a gate insulating film.

[0176] The metal oxide film is formed under the following conditions: the substrate temperature is from room temperature to 200° C. For example, the substrate temperature may be set to be equal to or higher than room temperature and equal to or lower than 140° C. If the temperature is less than 100° C., the productivity is increased, which is preferable. By forming the metal oxide film without heating, the crystallinity can be reduced.

[0177] In addition, before the metal oxide film is formed, water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 103 are removed. It is preferable to perform a treatment for removing the above-mentioned elements and a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70°C to 200°C in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. When plasma treatment is performed in an atmosphere containing nitrogen gas, organic matter on the surface of the insulating layer 103 is removed. After such a treatment, the surface of the insulating layer 103 is exposed to the atmosphere. It is preferable to form the metal oxide film continuously without performing the above-mentioned process.

[0178] Metal oxide films are processed using either wet etching or dry etching. In this case, the part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be used. The part may be etched and thinned.

[0179] After the metal oxide film is formed or processed into the semiconductor layer 108, the metal oxide film or Alternatively, heat treatment may be performed in order to remove hydrogen or water from the semiconductor layer 108. The temperature is typically 150° C. or higher but lower than the strain point of the substrate, or 250° C. or higher but lower than 450° C. or 300° C. or higher and 450° C. or lower.

[0180] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. After heating in air, the substrate may be heated in an atmosphere containing oxygen. It is preferable that the mixture does not contain hydrogen, water, etc. The heat treatment is carried out using an electric furnace, an RTA device, etc. By using an RTA device, the heat treatment time can be shortened.

[0181] [Formation of insulating layer 110 and metal oxide film 114f] Next, the insulating layer 110 and the metal oxide film 11 are formed on the insulating layer 103 and the semiconductor layer 108. 4f is laminated to form a film (Figure 5(C)).

[0182] The insulating layer 110 is made of an oxide such as a silicon oxide film or a silicon oxynitride film. The film is formed using a plasma enhanced chemical vapor deposition (PECVD) device, or simply a plasma CVD device. It is preferable to form the insulating film by using a PECVD method using microwaves. It may be formed.

[0183] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. It is preferable to form the insulating film by sputtering in an atmosphere containing oxygen. Oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f.

[0184] The metal oxide film 114f is formed by an oxide film containing the same metal oxide as that of the semiconductor layer 108. When forming the film by a sputtering method using a target, the above method is used. can be done.

[0185] For example, the deposition conditions for the metal oxide film 114f are as follows: oxygen is used as the deposition gas; The metal oxide film may be formed by reactive sputtering using a metal target. When aluminum is used as the base, an aluminum oxide film is formed. can be done.

[0186] When the metal oxide film 114f is formed, the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus is The higher the oxygen flow rate ratio to the total oxygen flow rate (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the greater the insulating layer 1 The oxygen supplied during the experiment can be increased by, for example, 5 0% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more The oxygen flow rate ratio is preferably 10% or less, and more preferably 90% or more and 100% or less. It is preferable to set the oxygen partial pressure to 0% and to make the oxygen partial pressure as close to 100% as possible.

[0187] In this manner, the metal oxide film 114f is formed by the sputtering method in an atmosphere containing oxygen. By forming the metal oxide film 114f, oxygen is supplied to the insulating layer 110 during the formation of the metal oxide film 114f. In addition, it is possible to prevent oxygen from being released from the insulating layer 110. 10, and then by the subsequent heat treatment, A large amount of oxygen can be supplied to the conductor layer 108. As a result, the oxygen in the semiconductor layer 108 This reduces defects and enables the realization of highly reliable transistors.

[0188] In addition, after the formation of the metal oxide film 114f, a heat treatment is performed to remove the semiconductor layer from the insulating layer 110. Oxygen may be supplied to the conductor layer 108. The heat treatment is carried out in a gas atmosphere containing at least one of nitrogen, oxygen, and a rare gas. The reaction can be carried out in an atmosphere containing the above-mentioned compound at a temperature of 200° C. or higher and 400° C. or lower.

[0189] Next, after the metal oxide film 114f is formed, the metal oxide film 114f, the insulating layer 110, and Then, a part of the insulating layer 103 is etched to form an opening reaching the conductive layer 106 . This allows the conductive layer 112 and the conductive layer 106 to be formed later to be electrically connected through the opening. It can be connected.

[0190] [Formation of Conductive Layer 112 and Metal Oxide Layer 114] Next, a conductive film 112f that will become the conductive layer 112 is formed on the metal oxide film 114f ( FIG. 5(D)). The conductive film 112f is formed by sputtering a metal or alloy target. It is preferable to form the film by a sputtering method.

[0191] Next, the conductive film 112f and the metal oxide film 114f are partially etched to leave the conductive layer 11 2 and a metal oxide layer 114 are formed (FIG. 5(E)). It is preferable that the same resist mask is used for processing the electrodes 114 and 114f. The metal oxide film 114f is etched using the etched conductive layer 112 as a hard mask. You may also use the

[0192] This forms the conductive layer 112 and the metal oxide layer 114 whose top surface shapes are roughly the same. It is possible.

[0193] In this manner, the upper and side surfaces of the semiconductor layer 108 and the In addition, the insulating layer 103 is covered with the insulating layer 110, so that the conductive layer 112 and the like can be etched. In this case, the semiconductor layer 108 and the insulating layer 103 are prevented from being partially etched and thinned. It is possible.

[0194] [Supply of impurity elements] Next, impurity elements are implanted into the insulating layer 110 and the semiconductor layer 108 using the conductive layer 112 as a mask. 140 is supplied (also called added or injected) to the region 108n and the region 110. d and region 103d are formed (FIG. 6(A)). That is, in a region overlapping with the conductive layer 112, the conductive layer 112 serves as a mask, and the impurity element 140 is Not supplied.

[0195] The impurity element 140 is preferably supplied by a plasma ion doping method or an ion implantation method. These methods can be used to measure the concentration profile in the depth direction by ion acceleration. It is possible to control the voltage and dose with high precision. Plasma ion doping By using this method, productivity can be increased. In addition, ion implantation using mass separation is also used. By using this, the purity of the impurity element supplied can be increased.

[0196] In the supplying process of the impurity element 140, the interface between the semiconductor layer 108 and the insulating layer 110, is a portion close to the interface in the semiconductor layer 108, or a portion close to the interface in the insulating layer 110. It is preferable to control the treatment conditions so that the highest concentration is obtained. In this way, the semiconductor layer 108 and the insulating layer 110 are both supplied with the impurity element 140 at an optimal concentration. It is possible.

[0197] The impurity elements 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, Examples of the material include aluminum, magnesium, silicon, and rare gases. Representative examples include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon. It is.

[0198] As a source gas of the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, typically B2H6 gas or BF3 gas can be used. In addition, when supplying phosphorus, PH3 gas can be typically used. Alternatively, a mixed gas in which these source gases are diluted with a rare gas may be used.

[0199] Other raw gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases can be used. In addition, the ion source is not limited to gas, and a solid or liquid vaporized by heating can also be used. good.

[0200] The addition of the impurity element 140 affects the composition, density, thickness, etc. of the insulating layer 110 and the semiconductor layer 108. This can be controlled by setting conditions such as acceleration voltage and dose amount taking into consideration the above.

[0201] For example, when boron is added by ion implantation or plasma ion doping, The acceleration voltage is, for example, 5 kV to 100 kV, preferably 7 kV to 70 kV, more preferably The voltage can be preferably in the range of 10 kV to 50 kV. Ba1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Below, preferably 1 ×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 More preferably, 1 ×10 15 ions / cm 2That's it, 3 x 10 16 ions / cm 2 The following range should be met: can be done.

[0202] In addition, when phosphorus ions are added by ion implantation or plasma ion doping, The acceleration voltage is, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less. More preferably, the voltage can be in the range of 40 kV to 80 kV. For example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 The following are the preferred Or 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 The following is more preferred: Or 1×10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 The following range and It is possible.

[0203] The method of supplying the impurity element 140 is not limited to this. For example, plasma processing, A treatment utilizing thermal diffusion by heating may be used. In the case of the plasma treatment method, the added By generating plasma in a gas atmosphere containing impurity elements and performing plasma processing, The impurity element can be added by the plasma generation device. Etching equipment, Ashing equipment, Plasma CVD equipment, High density plasma CVD equipment, etc. can be used.

[0204] In one embodiment of the present invention, the impurity element 140 is supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystallinity, impurities can be It is possible to prevent the crystallinity from being damaged when the element 140 is supplied. This is preferable in cases where a decrease in the capacitance results in an increase in electrical resistance.

[0205] [Formation of insulating layers 116 and 118] Next, the insulating layer 116 and the insulating layer 118 are formed in this order (FIG. 6(B)).

[0206] When the insulating layer 116 or the insulating layer 118 is formed by the plasma CVD method, the film formation temperature is If the temperature is too high, the impurities contained in the region 108n etc. may cause the channel formation region of the semiconductor layer 108 to deteriorate. There is a risk that the insulating layer 108n may diffuse into the surrounding area, including the insulating layer 108, and the electrical resistance of the insulating layer 108n may increase. The deposition temperature of the edge layer 116 or the insulating layer 118 is, for example, 150° C. or more and 400° C. or less. Preferably, the temperature is 180° C. or higher and 360° C. or lower, and more preferably, 200° C. or higher and 250° C. or lower. It is preferable to form the insulating layer 116 or the insulating layer 118 at a low temperature. Even in a transistor having a short length, good electrical characteristics can be imparted.

[0207] [Heat Treatment] After the insulating layer 116 or the insulating layer 118 is formed, heat treatment is performed. , in an atmosphere containing one or more of rare gases, at 150° C. or higher and 450° C. or lower, preferably 20 It is preferable to carry out the heat treatment at a temperature of 0°C or higher and 400°C or lower. For example, the region 108n can be made to have a low resistance by performing a heat treatment at the above temperature. The impurity element 140 is diffused appropriately and locally uniformed, resulting in an ideal impurity element concentration. The gradient regions 108n and 110d can be formed. If the temperature is too high (for example, 500° C. or higher), the impurity element 140 may diffuse into the channel forming region. This may cause deterioration in the electrical characteristics and reliability of the transistor.

[0208] In addition, when the impurity element 140 is supplied to the region 108n, the semiconductor layer 108 and the insulating layer 11 In some cases, defects in the 0 can be repaired by heat treatment.

[0209] In addition, oxygen is introduced from the insulating layer 110 to the channel formation region of the semiconductor layer 108 by the heat treatment. At this time, the insulating layer 110 has an impurity near the interface with the region 108n. Since the region 110d to which the pure element 140 is supplied is formed, the pure element 140 is released from the insulating layer 110. As a result, the oxygen in the region 108n is prevented from diffusing into the region 108n. In addition, the insulating layer 110 can be effectively prevented from becoming highly resistive. The region 110d is not formed in the portion of the semiconductor layer 108 that overlaps with the channel formation region. Therefore, oxygen released from the insulating layer 110 is selectively supplied to the channel forming region. can be done.

[0210] In addition, since the region 108n has more oxygen vacancies than the channel formation region, The oxygen vacancies are then used to getter the hydrogen contained in the channel formation region by the heat treatment. This is expected to have the effect of reducing the hydrogen concentration in the channel formation region. This allows for the realization of a more reliable transistor. The hydrogen that is released combines with the oxygen vacancies in the region 108n to generate carriers, so that the lower A resistive region 108n can be realized.

[0211] Note that the heat treatment may be performed before the insulating layer 116 is formed. It is more preferable to perform this process after forming the insulating layer 116 or the insulating layer 118. 8, by using an insulating film that does not easily diffuse oxygen, the oxygen is released from the insulating layer 110 by heat treatment. The oxygen is prevented from diffusing to the outside and is supplied to the channel forming region of the semiconductor layer 108. This allows for a greater amount of oxygen to be absorbed.

[0212] [Formation of Openings 141a and 141b] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer 118, insulating layer 116, and a portion of insulating layer 110 are etched to form regions 108n The opening 141a and the opening 141b are formed.

[0213] [Formation of Conductive Layer 120a and Conductive Layer 120b] Next, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is formed and processed into a desired shape to form the conductive layer 120a and the conductive layer 120b. (Figure 6(C)).

[0214] Through the above steps, the transistor 100A can be manufactured. When the sta 100A is applied to a pixel of a display device, a protective insulating layer, a planarizing layer, A step of forming at least one of the pixel electrodes and the wiring may be added.

[0215] The above is an explanation of the example of the manufacturing method.

[0216] The configuration examples and manufacturing method examples illustrated in this embodiment and the corresponding drawings, etc. Also, parts of the present invention may be implemented in appropriate combination with other configuration examples, manufacturing method examples, drawings, etc. can be done.

[0217] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0218] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described. This article provides an explanation of the above.

[0219] [Configuration example] FIG. 7A shows a top view of a display device 700. The display device 700 is provided with a sealant 712. The device has a first substrate 701 and a second substrate 705 that are bonded together. 1, the second substrate 705, and the area sealed by the sealant 712. 1, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided. The pixel portion 702 is provided with a plurality of display elements.

[0220] In addition, an FPC 716 (FP C: Flexible printed circuit) is connected to the FPC terminal 7 The FPC terminal portion 708 and the signal line 710 are connected by the FPC 716. Through the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 Various signals are supplied to each of these.

[0221] A plurality of gate driver circuit sections 706 may be provided. The path portion 706 and the source driver circuit portion 704 are separately formed on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip may be mounted on the first substrate 70. 1, or can be mounted on FPC716.

[0222] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 have The transistor can be a transistor that is a semiconductor device of one embodiment of the present invention. do.

[0223] Examples of the display element provided in the pixel portion 702 include a liquid crystal element and a light emitting element. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, etc. are used. The light emitting element can be LED (Light Emitting Diode). Diode), OLED (Organic LED), QLED (Quantum-do Examples of self-luminous light-emitting elements include LEDs and semiconductor lasers. MEMS (Micro Electro Mechanical Systems) using the optical interferometry or optical interference method l Systems) elements, microcapsule type, electrophoretic type, electrowet type Display elements using the electronic powder method or the like can be used. It is also possible.

[0224] The display device 700A shown in FIG. 7B can be suitably used in electronic devices having a large screen. The display device 700A is, for example, a television device, a monitor device, , personal computers (including notebook and desktop computers), tablet devices, It can be suitably used for digital signage and the like.

[0225] The display device 700A includes a plurality of source driver ICs 721 and a pair of gate driver circuits. The sensor 722 has a first section 722.

[0226] The source driver ICs 721 are each attached to an FPC 723. In addition, the plurality of FPCs 723 are arranged such that one terminal is connected to the first board 701 and the other terminal is connected to the printed board. The FPC 723 is bent to connect the printed circuit board 7 24 can be disposed on the back side of the pixel section 702 and mounted on the electronic device, thereby reducing the space required for the electronic device. It is possible to pace things.

[0227] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize electronic devices with narrow frames.

[0228] With this configuration, a large-sized and high-resolution display device can be realized. The surface size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. It can also be applied to the above display devices. In addition, the resolution is 4K2K, 8K4K, etc. It is possible to realize a display device with extremely high resolution.

[0229] [Cross-section example] In the following, a configuration in which a liquid crystal element and an EL element are used as a display element will be described with reference to FIGS. 8 to 1. 8 to 10 are respectively taken along the dashed line Q- in FIG. 8 and 9 are cross-sectional views taken along the line R. FIG. 8 and FIG. 9 show configurations in which liquid crystal elements are used as display elements. FIG. 10 shows a configuration using an EL element.

[0230] [Description of common parts of the display device] A display device 700 shown in FIGS. 8 to 10 includes a wiring portion 711, a pixel portion 702, and The wiring section 71 includes a source driver circuit section 704 and an FPC terminal section 708. 1 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. 7 shows the case where the capacitance element 790 is not present.

[0231] The transistor 750 and the transistor 752 are the transistors exemplified in the first embodiment. can be applied.

[0232] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. The retention time of the image signal can be extended, and the interval between writing image signals etc. can be set longer when the power is on. This reduces the frequency of refresh operations, resulting in reduced power consumption. Play.

[0233] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a display device. By using this in a device, the switching transistor in the pixel section and the driver circuit section In other words, a separate driver circuit can be formed on the same substrate. Since there is no need to use semiconductor devices formed from silicon wafers, etc., The number of points can be reduced. Also, in the pixel area, transistors that can be driven at high speed can be used. By using this, high quality images can be provided.

[0234] The capacitor 790 shown in FIG. 8 and FIG. 10 has the same semiconductor layer as the transistor 750. The lower electrode is formed by processing the film and has a low resistance, and the source electrode or drain electrode is and an upper electrode formed by processing the same conductive film. Between them, two insulating films are provided to cover the transistor 750. 90 is a laminated structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. .

[0235] In addition, a planarization insulating layer is formed on the transistor 750, the transistor 752, and the capacitor 790. A veneer 770 is provided.

[0236] A transistor 750 included in the pixel portion 702 and a transistor 751 included in the source driver circuit portion 704 A transistor having a structure different from that of the transistor 752 may be used. A top-gate transistor is applied to one side, and a bottom-gate transistor is applied to the other side. The source driver circuit section 704 may be replaced with a gate driver circuit. It may also be read as "road section."

[0237] The signal line 710 is the same as the source and drain electrodes of the transistors 750 and 752. In this case, if a low-resistance material such as a material containing copper is used, the wiring This is preferable because it reduces signal delays caused by line resistance and enables display on a large screen.

[0238] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780. Here, the connection electrode 760 is connected to the source electrodes of the transistors 750 and 752. The gate electrode is formed from the same conductive film as the gate electrode and drain electrode.

[0239] The first substrate 701 and the second substrate 705 are, for example, a glass substrate or a plastic substrate. A flexible substrate such as a plastic substrate can be used.

[0240] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and insulating films in contact with these are provided. A border membrane 734 is provided.

[0241] [Example of the configuration of a display device using a liquid crystal element] The display device 700 shown in FIG. 8 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive layer 7 72, a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 774 is The conductive layer 772 is provided on the substrate 705 side and functions as a common electrode. The conductive layer 7 is electrically connected to the source electrode or drain electrode of the transistor 750. The pixel electrode 72 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0242] The conductive layer 772 is made of a material that transmits visible light or a material that reflects visible light. Examples of the light-transmitting material include indium, zinc, tin, etc. The reflective material may be, for example, an oxide material containing aluminum, silver, etc. It is advisable to use materials that

[0243] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive type. In the case of a liquid crystal display device of the transmission type, a polarizing plate is provided on the viewing side. A pair of polarizing plates is provided to sandwich the liquid crystal element.

[0244] The display device 700 shown in FIG. 9 includes a liquid crystal element 775 of a horizontal electric field type (for example, an FFS mode). A conductive layer 772 is provided with an insulating layer 773 interposed therebetween, and a conductive layer 773 is provided on the conductive layer 772 to function as a common electrode. An electric field is generated between the conductive layer 772 and the conductive layer 774, causing the liquid The orientation of the crystal layer 776 can be controlled.

[0245] In FIG. 9, a storage capacitor is formed by a laminated structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, it is not necessary to provide a separate capacitance element, and the aperture ratio can be increased. It is possible.

[0246] Although not shown in FIGS. 8 and 9, an alignment film in contact with the liquid crystal layer 776 may be provided. In addition, optical members (optical substrates) such as polarizing members, phase difference members, and anti-reflection members may be used. , and light sources such as a backlight and a sidelight can be provided as appropriate.

[0247] The liquid crystal layer 776 may include a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, a polymer dispersion liquid, etc. Liquid crystals, polymer network type liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. In addition, when the in-plane switching method is adopted, liquid crystals exhibiting a blue phase without using an alignment film may be used. stomach.

[0248] The liquid crystal element modes are Twisted Nematic (TN) mode, VA (Vertical Alignment) mode, IPS (In-Plane-S witching) mode, FFS(Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro- cell) mode, OCB (Optical Compensated Birefri) ngence) mode, ECB (Electrically Controlled B irefringence mode, guest-host mode, etc. can be used.

[0249] [Display device using light-emitting element] The display device 700 shown in FIG. 10 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer The EL layer 786 includes an organic compound, has inorganic compounds such as quantum dots.

[0250] Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, etc.

[0251] In the display device 700 shown in FIG. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788. Note that the light-emitting element 782 emits light toward the conductive layer 772. A bottom emission structure in which light is emitted from the bottom of the conductive layer 772 and the conductive film 788 can be used. It may also be a dual emission structure.

[0252] The colored film 736 is provided at a position overlapping the light emitting element 782, and the light shielding film 738 is an insulating film. 730, the lead wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. 86 is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, by painting. In some cases, the colored film 736 may not be provided.

[0253] [Example of configuration in which an input device is provided on a display device] An input device may be provided in the display device 700 shown in FIGS. For example, a touch sensor is included.

[0254] For example, the sensor types include capacitance type, resistive film type, surface acoustic wave type, infrared type, etc. Various methods can be used, such as a pressure-sensitive, optical, or pressure-sensitive method. Or, two or more of these can be used. may be used in combination.

[0255] The touch panel is configured as a so-called in-cell type, in which the input device is formed inside a pair of substrates. A touch panel of the type, an input device is formed on the display device 700, so-called an on-cell type touch panel. or a so-called out-cell type touch panel that is attached to the display device 700. There are some.

[0256] The configuration examples exemplified in this embodiment and the corresponding drawings are at least partially The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0257] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0258] (Embodiment 3) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0259] The display device shown in FIG. 11A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 505. 6 and a terminal portion 507. Note that the protection circuit 506 may be omitted. .

[0260] The transistors in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. In addition, the protection circuit 506 can also use the transistor of one embodiment of the present invention. may be applied.

[0261] The pixel section 502 is a multi-layered pixel array arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). The pixel circuit 501 includes a number of pixel circuits 501 for driving a number of display elements.

[0262] The driving circuit unit 504 includes a gate driver that outputs scanning signals to the gate lines GL_1 to GL_X. a source driver 504a, which supplies data signals to the data lines DL_1 to DL_Y; The gate driver 504a includes at least a shift register The source driver 504b may be, for example, a plurality of analog switches. Also, the source driver 504 is configured using a shift register, etc. b may be constructed.

[0263] The terminal unit 507 is a terminal for inputting power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals are provided for connecting the power supply to the power source.

[0264] The protection circuit 506 is configured to detect when a potential outside a certain range is applied to the wiring to which it is connected. The protection circuit 506 shown in FIG. 11A is a circuit that connects the wiring to another wiring. For example, the scanning line GL, which is a wiring between the gate driver 504a and the pixel circuit 501, or various wiring such as a data line DL which is a wiring between the source driver 504b and the pixel circuit 501. is connected to the line.

[0265] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver circuit or the source driver circuit may be provided on the same substrate. A separately formed substrate (for example, a driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film) The circuit board is bonded to the board by COG or TAB (Tape Automated Bonding). It may also be configured to be mounted on a substrate.

[0266] In addition, the pixel circuits 501 shown in FIG. 11A may be, for example, The configuration shown in FIG.

[0267] The pixel circuit 501 shown in FIG. 11B includes a liquid crystal element 570, a transistor 550, and a capacitor. The pixel circuit 501 also includes a data line DL_n, a scanning line GL_ m, a potential supply line VL, etc. are connected.

[0268] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0269] The pixel circuit 501 shown in FIG. 11C includes transistors 552 and 554 and a capacitor. The pixel circuit 501 includes a data line DL_n , the scanning line GL_m, the potential supply line VL_a, the power supply line VL_b, etc. are connected to the pixel electrodes GL_m, GL_m.

[0270] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. A low power supply potential VSS is applied to the gate of the transistor 554. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the light-emitting element 572. The brightness of the light emitted from 72 is controlled.

[0271] The configuration examples exemplified in this embodiment and the corresponding drawings are at least partially The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0272] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0273] (Embodiment 4) In the following, a pixel circuit having a memory for correcting the gradation displayed in the pixel and a The transistors exemplified in Embodiment 1 will be described below. The present invention can be applied to transistors used in pixel circuits.

[0274] [Circuit configuration] 12A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. The wiring S1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0275] The transistor M1 has a gate connected to a wiring G1, a source and a drain connected to a wiring S1, The other end is connected to one electrode of the capacitor C1. The gate of the transistor M2 is G2, one of the source and drain is the wiring S2, and the other is the other electrode of the capacitance C1, and 401 and 402, respectively.

[0276] The circuit 401 is a circuit including at least one display element. Representative examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystal element, or MEMS (Micro Electro Mechanical Systems) ems) elements, etc. can be applied.

[0277] The node connecting the transistor M1 and the capacitor C1 is designated as N1, and the transistor M2 and the circuit 40 are designated as Let N2 be the node connecting to 1.

[0278] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. In addition, by turning off the transistor M2, the voltage of the node N2 can be maintained. In addition, when the transistor M2 is in the off state, the transistor By writing a predetermined potential to node N1 via transistor M1, capacitive coupling via capacitor C1 This makes it possible to change the potential of the node N2 in response to a change in the potential of the node N1.

[0279] Here, in one or both of the transistors M1 and M2, The transistor using an oxide semiconductor, which is exemplified in 1, can be used. Therefore, the potentials of the nodes N1 and N2 can be maintained for a long period of time due to the extremely low off-current. In addition, when the period for which the potential of each node is held is short (specifically, when the frame In cases where the system frequency is 30 Hz or more, transistors using semiconductors such as silicon A meter may also be used.

[0280] [Driving method example] Next, an example of a method of operating the pixel circuit 400 will be described with reference to FIG. 4B is a timing chart relating to the operation of the pixel circuit 400. For ease of understanding, we have not included various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, The effects of the transistor threshold voltage, etc. are not taken into account.

[0281] In the operation shown in FIG. 12B, one frame period is divided into a period T1 and a period T2. T1 is a period during which a potential is written to node N2, and T2 is a period during which a potential is written to node N1. It is a period.

[0282] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the line S1 is connected to a fixed potential V ref The first data is supplied to the wiring S2. Voltage V w supplies.

[0283] The node N1 is connected to a potential V ref is given. In addition, the node N2 is supplied with a first data potential V w is given. Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0284] [Period T2] In the next period T2, a potential is applied to the wiring G1 to turn on the transistor M1. A potential for turning off the transistor M2 is applied to the line G2. Data potential V data A predetermined constant potential is applied to the wiring S2, or a floating potential is applied to the wiring S3. The state may be a locking state.

[0285] A second data potential V data is given. At this time, due to the capacitive coupling of the capacitor C1, the second data potential V data Depending on node N That is, the first data potential Vw and the potential In FIG. 12B, dV is a positive value. However, it may be negative. That is, the potential V data is the potential V re f It may be lower.

[0286] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV becomes the second Data potential V data The potential becomes close to

[0287] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential to be supplied to the line 401 can be generated, the gray scale correction can be performed within the pixel circuit 400. It will be possible to do so.

[0288] In addition, the pixel circuit 400 generates a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, a high dynamic range ( In addition, when liquid crystal elements are used, overdriving is possible. It is possible to realize drive such as a spring.

[0289] [Example of application] [Example using liquid crystal element] The pixel circuit 400LC shown in FIG. 12C includes a circuit 401LC. has a liquid crystal element LC and a capacitance C2.

[0290] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitance C2, and the other electrode connected to the Potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0291] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted. Cut.

[0292] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, Achieving high-speed display through overdrive operation and using liquid crystal materials with high drive voltage In addition, by supplying a correction signal to the wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the deterioration state of the liquid crystal element LC.

[0293] [Example using light-emitting element] The pixel circuit 400EL shown in FIG. 12D includes a circuit 401EL. includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0294] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and drain connected to the One of the drains is a wiring to which a potential VH is applied, and the other is one electrode of the light-emitting element EL. The capacitor C2 is connected to the other electrode at potential V comConnect with the wiring given. The other electrode of the light-emitting element EL is at a potential V L Connect with the wiring given.

[0295] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0296] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, a transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value of can be changed appropriately.

[0297] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of the transistor M3. Since a large current can be passed through the child EL, it is possible to realize, for example, HDR display. In addition, by supplying a correction signal to the wiring S1 or the wiring S2, the transistor It is also possible to correct the variations in the electrical characteristics of M3 and the light-emitting element EL.

[0298] In addition, the circuit is not limited to the circuits shown in FIG. 12(C) and (D), and may include other transistors, capacitors, etc. may be added.

[0299] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0300] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described. I will explain it below.

[0301] The display module 6000 shown in FIG. 13(A) includes an upper cover 6001 and a lower cover 6002. A display device 6006, a frame 6009, and a printer 6002 are connected to the FPC 6005. The semiconductor device has a support substrate 6010 and a battery 6011.

[0302] For example, a display device manufactured according to one embodiment of the present invention can be used as the display device 6006. The display device 6006 realizes a display module with extremely low power consumption. It is possible.

[0303] The upper cover 6001 and the lower cover 6002 are adapted to the size of the display device 6006. The shape and dimensions can be changed as appropriate.

[0304] The display device 6006 may have a function as a touch panel.

[0305] The frame 6009 has a function of protecting the display device 6006 and a function of preventing the display device 6006 from being damaged by the operation of the printed circuit board 6010. The insulating film may have a function of blocking electromagnetic waves generated by the insulating film, a function as a heat sink, etc.

[0306] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. It has a signal processing circuit, a battery control circuit, etc.

[0307] FIG. 13B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. It is.

[0308] The display module 6000 includes a light emitting section 6015 and a receiving section 6016 provided on a printed circuit board 6010. The optical unit 6016 is surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guiding portions (light guiding portion 6017a, light guiding portion 6017b).

[0309] The display device 6006 is connected to a printed circuit board 6010 and a battery via a frame 6009. The display device 6006 and the frame 6009 are disposed on top of the light guide unit 6011. 017a and fixed to light guiding portion 6017b.

[0310] Light 6018 emitted from the light emitting portion 6015 is guided to the display device 600 by the light guiding portion 6017a. 6, and reaches the light receiving part 6016 through the light guiding part 6017b. A touch operation is detected when the light 6018 is blocked by a detection object such as an illustration. It is possible.

[0311] A plurality of light emitting sections 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light receiving sections 6016 are provided at positions facing the light emitting sections 6015. It is possible to obtain information on the position where the touch operation was performed.

[0312] The light emitting unit 6015 may be a light source such as an LED element, and in particular, may be a light source that emits infrared rays. It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that can receive light and convert it into an electrical signal can be used. A photodiode such as a photodiode can be used.

[0313] The light guiding portion 6017a and the light guiding portion 6017b transmit light 6018. The light receiving unit 6016 can be disposed under the display device 6006, and external light is received by the light receiving unit 601. 6, which prevents the touch sensor from malfunctioning. By using a resin that allows wires to pass through, malfunction of the touch sensor can be more effectively prevented.

[0314] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0315] (Embodiment 6) In this embodiment, an electronic device including a display device manufactured according to one embodiment of the present invention will be described. I will explain it below.

[0316] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and large screen It is possible to provide an electronic device that is compatible with both.

[0317] The display unit of the electronic device according to one embodiment of the present invention may be a display device that supports, for example, full high definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher.

[0318] Examples of electronic devices include television sets, notebook personal computers, Equipped with relatively large screens such as monitor devices, digital signage, pachinko machines, and game machines In addition to electronic devices that can be used for personal computers, digital cameras, digital video cameras, digital photo frames, mobile phones, etc. Examples of the portable electronic device include mobile phones, portable game machines, portable information terminals, and audio playback devices.

[0319] An electronic device to which one aspect of the present invention is applied is installed on the inner or outer wall of a house or building, the interior of a car, etc. The sensor can be installed along a flat or curved surface of a housing or exterior.

[0320] FIG. 14A shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0321] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0322] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0323] The camera 8000 can be operated by pressing the shutter button 8004 or by using a touch panel. By touching the display portion 8002, an image can be captured.

[0324] The housing 8001 has a mount having electrodes, and is equipped with a finder 8100 and a strobe. It is possible to connect devices such as a

[0325] The finder 8100 includes a housing 8101, a display unit 8102, a button 8103, and the like. .

[0326] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The Finder 8100 is attached to the Camera 8000. The information can be displayed on the display unit 8102 .

[0327] The button 8103 has a function such as a power button.

[0328] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied to a camera having a built-in viewfinder. It may be La 8000.

[0329] FIG. 14B is a diagram showing the external appearance of the head mounted display 8200.

[0330] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0331] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and can display received video information on a display unit 8204. The main body 8203 is also equipped with a camera, and can input information on the movements of the user's eyes and eyelids. It can be used as a step.

[0332] In addition, the attachment part 8201 is provided with a flow sensor that flows in accordance with the movement of the user's eyeball at a position where the attachment part 8201 touches the user. A plurality of electrodes capable of detecting a current passing through the sensor may be provided, and the sensor may have a function of recognizing the line of sight. In addition, the device may have a function of monitoring the pulse rate of the user by measuring the current flowing through the electrodes. In addition, the mounting part 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function to display the user's biological information, and the head of the user may have a function to display the user's biological information on the display unit 8204. The display portion 8204 may have a function of changing an image displayed on the display portion 8204 in accordance with the user's movement.

[0333] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0334] 14(C), (D), and (E) are diagrams showing the appearance of the head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, and a backlight. The optical element has a band-shaped fixture 8304 and a pair of lenses 8305.

[0335] A user can view the display on the display unit 8302 through the lens 8305 . If the display unit 8302 is curved, the user can feel a high sense of presence. In addition, it is preferable to display different images in different areas of the display unit 8302 through the lens 8304. By viewing through 305, it is possible to perform a three-dimensional display using parallax. The present invention is not limited to a configuration in which one display unit 8302 is provided, but may be configured in such a way that two display units 8302 are provided and one of the display units is One display unit may be arranged for each eye.

[0336] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition. Even if the image is magnified using the lens 8305, the pixels are not visible to the user, and the image is more This makes it possible to display images with a higher sense of reality.

[0337] The electronic device shown in FIG. 15A to FIG. 15G includes a housing 9000, a display portion 9001, a switch A speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared rays), 9008, etc.

[0338] The electronic devices shown in FIGS. 15A to 15G have various functions. Function to display various information (still images, videos, text images, etc.) on the display unit, touch panel function , calendar, date or time display functions, various software (programs) a function for controlling processing by a wireless communication function, a program recorded on a recording medium, or The electronic device can have the function of reading and processing data, etc. The electronic device may have a variety of functions, but is not limited to these. Also, a camera or the like may be provided in the electronic device to take still images or videos and store them on a recording medium (external It has the functions of storing the captured image on a memory card (built into the camera or the internal memory) and displaying the captured image on the display. It is okay to do so.

[0339] The electronic devices shown in FIGS. 15A to 15G will be described in detail below.

[0340] FIG. 15A is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen, for example, 50 inches or more or 100 inches or more It is possible to incorporate.

[0341] FIG. 15B is a perspective view showing a portable information terminal 9101. For example, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple surfaces. In the example shown in FIG. 9, three icons 9050 are displayed. 051 can be displayed on another surface of the display unit 9001. , notifications of incoming e-mails, SNS, phone calls, etc., subject of e-mails and SNS, sender Name, date, time, battery level, antenna reception strength, etc. An icon 9050 or the like may be displayed in the position where 51 is displayed.

[0342] FIG. 15C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example in which information 9053 and information 9054 are displayed on different sides is shown. The person holds the mobile information terminal 9102 in the breast pocket of his / her clothes. The user can also check information 9053 displayed in a position that can be observed from above 2. The display can be checked without taking the mobile information terminal 9102 out of a pocket, and for example, a telephone call can be made. You can decide whether to accept it or not.

[0343] 15(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The display unit 9001 can be used as a smart watch, for example. The display surface is curved, and the display can be performed along the curved display surface. In addition, the mobile information terminal 9200 can be made to communicate with, for example, a wireless headset. In addition, the mobile information terminal 9200 can also be connected to The terminal 9006 can be used to transmit data to and from other information terminals and can also be used for charging. The charging operation may be performed by wireless power supply.

[0344] 15(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 15(E) shows the portable information terminal 9201 in an unfolded state, and FIG. 15(G) shows the portable information terminal 9201 in a folded state. Figure 15(F) shows the state where the two are changing from one of Figure 15(E) and Figure 15(G) to the other. The portable information terminal 9201 is highly portable when folded and is unfolded and is in a perspective view. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. For example, the display unit 9001 is curved with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0345] FIG. 16A shows an example of a television device. A television device 7100 includes a housing 7 A display unit 7500 is built into the housing 7101. 101 is shown as a supported configuration.

[0346] The television device 7100 shown in FIG. 16A is operated by an operation switch provided in a housing 7101. This can be done by a separate remote control 7111 or a display unit 75 A touch panel is applied to the television device 7100, and the television device 7100 can be operated by touching the touch panel. The remote control operation device 7111 may have a display unit in addition to the operation buttons.

[0347] The television device 7100 may be a television broadcast receiver or a network connection device. The communication device may include:

[0348] FIG. 16B shows a notebook personal computer 7200. The mobile computer 7200 includes a housing 7211, a keyboard 7212, a pointing device, The display unit 7500 is assembled in the housing 7211. It is embedded in the

[0349] Figure 16 (C) and (D) show digital signage. An example of a sub-sign is shown below.

[0350] The digital signage 7300 shown in FIG. 16C includes a housing 7301, a display unit 7500, and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0351] FIG. 16(D) shows a digital signage 740 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit provided along the curved surface of a pillar 7401. It has 7500.

[0352] The larger the display 7500, the more information can be provided at once, and the closer it is to the human eye. Since it is easy to attach to the skin, it has the effect of increasing the effectiveness of advertising, for example.

[0353] It is preferable that a touch panel be applied to the display unit 7500 so that a user can operate it. This will enable the use of the information not only for advertising purposes, but also for route information, traffic information, and commercial facility guidance information. It can also be used to provide users with information they are looking for.

[0354] Also, as shown in FIG. 16(C) and (D), the digital signage 7300 or the digital The signage 7400 is connected wirelessly to an information terminal 7311 such as a smartphone carried by a user. For example, the advertisement displayed on the display unit 7500 may be The information is displayed on the screen of the information terminal 7311, and the information terminal 7311 is operated. In this way, the display on the display unit 7500 can be switched.

[0355] In addition, the Digital Signage 7300 or Digital Signage 7400 can be equipped with an information terminal. It is also possible to run games using the 7311 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0356] The display device of one embodiment of the present invention is applied to the display portion 7500 in FIGS. It is possible.

[0357] Although the electronic device of the present embodiment has a display unit, the present invention can be applied to electronic devices that do not have a display unit. One embodiment of the present invention can also be applied to the above-mentioned semiconductor device.

[0358] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. EXAMPLES

[0359] In this example, the oxide semiconductor film was doped with impurities to reduce its resistance. In addition, a process of supplying oxygen to the oxide semiconductor film was performed, and the sheet resistance was measured. The changes were evaluated.

[0360] [simulation] First, for boron and phosphorus used as impurity elements, The injection volume was calculated.

[0361] For the calculation, we used software to calculate the ion implantation process using the Monte Carlo method. TRIM (Transport of Ion in Matter) was used.

[0362] The implanted films used in the calculation were a 100 nm thick silicon oxide film as the second insulating film, and a 100 nm thick silicon oxide film as the second insulating film. The semiconductor film was a 40 nm thick InGaZnO4 film, and the first insulating film was a 10 nm thick InGaZnO4 film. The layered film was made by stacking a 0 nm silicon oxide film in sequence. Boron and phosphorus were used as impurity elements. The dose was calculated for two types of 15 cm -2 In addition, For uran, the beam energies were 10 keV, 15 keV, 20 keV, and 30 keV. For phosphorus, the energy levels were 50 keV, 60 keV, and 70 keV. The three conditions were V.

[0363] In Fig. 17(A), boron ( 11 The calculation results for phosphorus ( 31 P The vertical axis shows the volume concentration of boron or phosphorus. tion), and the horizontal axis indicates depth.

[0364] As shown in FIG. 17A, the higher the beam energy, the more the impurities in the oxide semiconductor film are reduced. It was confirmed that the concentration of impurities increased. Also, the higher the beam energy, the higher the impurity concentration. It was confirmed that the position of the high peak became deeper and the profile became broader. In addition, under the condition of a beam energy of 20 keV, the oxide semiconductor film (IGZO) and the first insulating film were It was confirmed that the impurity concentration was highest near the interface with the insulating film (SiO2 on the left).

[0365] In FIG. 17B, the higher the beam energy, the higher the impurity concentration in the oxide semiconductor film. In addition, it was confirmed that the oxide semiconductor film and the first insulating film were It was confirmed that a region with the highest impurity concentration could be formed near the interface with the film.

[0366] [Evaluation of sheet resistance] In the following, impurities are added to a film in which an oxide insulating film is stacked over an oxide semiconductor film. The results of measuring the sheet resistance will be described.

[0367] [Evaluation method] The evaluation was carried out according to the following procedure.

[0368] First, an oxide semiconductor film was formed to a thickness of about 40 nm to 50 nm over a glass substrate. The semiconductor film is a metal oxide target with an atomic ratio of In:Ga:Zn=1:1:1.2. The film was formed by sputtering using a tantalum.

[0369] Next, a silicon oxide film having a thickness of about 100 nm was formed on the oxide semiconductor film. The silicon film was formed by the plasma CVD method using silane gas and dinitrogen monoxide gas as the deposition gas. The substrate temperature during the film formation was 350°C.

[0370] Next, a treatment for supplying oxygen into the oxide semiconductor film was performed. A metal oxide film is formed on the silicon oxide film by sputtering in an atmosphere containing oxygen. After forming the film and supplying oxygen into the silicon oxide film, a heat treatment is performed at 400°C for 1 hour. Oxygen was supplied from the silicon oxide film to the oxide semiconductor film. Then, the metal oxide film was etched. The metal oxide film was formed under the same conditions as those for the oxide semiconductor film.

[0371] Next, impurities were added. The impurities were added using a plasma ion implantation system that does not have a mass separation mechanism. The experiment was carried out using two types of equipment: an on-doping device and an ion implantation device with a mass separation mechanism. In addition, the gas used to supply boron was B2H6 gas in the ion doping device. The gas used to supply phosphorus was BF3 gas in the ion implantation equipment. H3 gas was used. The dose of impurities and the acceleration voltage were set to In the ion implantation device, multiple samples with different doses and beam energies are implanted. For comparison, a sample without any added impurities was also prepared.

[0372] Then, the above-described treatment for supplying oxygen into the oxide semiconductor film was performed again. The temperature of the heat treatment after the metal oxide film was formed was set to three conditions: 250℃, 350℃, and 400℃. Four types of samples were prepared: a sample with different temperature and pressure, and a sample that was not heat-treated.

[0373] Finally, the silicon oxide film was removed, and a titanium electrode was formed by sputtering. The sheet resistance was measured.

[0374] [Sheet resistance] Each figure in Fig. 18 shows the results of the sequence of the samples doped with boron by the plasma doping method. The results of the electrochemical resistance are shown in Fig. 18(A) at an accelerating voltage of 20 kV and Fig. 18(B) at an accelerating voltage of 40 kV. Figure 18(C) shows the results for an acceleration voltage of 60 kV. ×10 15 cm -2 From 1.5 × 10 16 cm -2 Each condition up to the end is shown. In addition, for each dose, the results were compared between those without heat treatment and those with heat treatment at each temperature. The following are listed in order.

[0375] As shown in FIGS. 18A to 18C, the oxide semiconductor film has a low resistance due to the addition of boron. In addition, it can be seen that the accelerating voltage is 40 kV and the ion beam is 100 kV. Under the conditions of 60 kV and 60 kV, the sheet resistance increased as the dose increased. Therefore, when combined with the simulation results for TRIM shown in Figure 17(A), The impurity concentration is highest near the interface between the oxide semiconductor film and the oxide insulating film on top of it. It was confirmed that the addition of impurities resulted in a stable low resistance state.

[0376] In addition, under the lowest dose condition (1×10 15 cm -2 Except for the above condition, boron was added. In the samples, the phenomenon of increasing the resistance due to heat treatment was hardly observed. The low resistance state is maintained before and after the heat treatment.

[0377] Figure 19 (A) and (B) show the results for samples doped with phosphorus by plasma doping. The results of the sheet resistance at an accelerating voltage of 60 kV are shown in FIG. 19(A) and 19(B). The result is 70kV.

[0378] It was confirmed that the resistance of the oxide semiconductor film was reduced even when phosphorus was added as an impurity element. In addition, the resistance tends to increase with increasing dose, and the optimum dose range is unclear. It can be seen that there is a boundary.

[0379] Next, we investigated the behavior of the impurity element added by an ion implantation device with a mass separation mechanism. The evaluation results of the gate resistance are shown below. The ion implantation method uses a mass separation mechanism, and the plasma doping method Compared to the conventional method, there is less contamination with impurity ions other than the target ions, so more precise control can be performed. This is a method that can be used.

[0380] In Figure 20(A), boron ( 11 B) in Fig. 20(B)31 P) was added, respectively. 20(A) and (B) show the results when an impurity element is added. Samples that have not been tested are also listed.

[0381] When an ion implantation device is used, the same tendency as the plasma doping method is observed. Confirmed.

[0382] In addition, when comparing the plasma ion doping method with the ion implantation method, the plasma ion doping method The doping method tends to produce low and stable resistance values ​​with a small dose. This is because the plasma ion doping device does not have a mass analysis mechanism, and only the target ions are detected. It is considered that the impurity ions affect the resistance value of the oxide semiconductor film.

[0383] [Evaluation of impurity concentration] In the following, the concentration distribution of the impurity elements in the depth direction was measured using the sample prepared above. The results are explained below. The measurements were performed using secondary ion mass spectrometry (SIMS). The sample was an oxide semiconductor. The film is implanted with boron ( 11 B) was added, and phosphorus ( 31 P) was added The boron doping conditions were as follows: beam energy 20 keV, doping The amount of zoom is 5×10 15 cm -2 The phosphorus doping conditions were: beam energy 60 keV , dose amount is 5×10 15 cm -2 It was decided.

[0384] FIG. 21(A) shows the SIMS analysis result of the sample doped with boron, and FIG. 21(B) shows the SIMS analysis result of the sample doped with phosphorus. The SIMS analysis results of the samples with and without the silicon oxide film (S The profile was quantified using a standard sample of IGZO (Indium-Glycerol) and Two quantified profiles are shown side by side.

[0385] As shown in FIG. 21A, the closer to the interface with the oxide semiconductor film, the greater the amount of boron in the silicon oxide film. On the other hand, in the oxide semiconductor film, the concentration of silicon oxide increases. It can be seen that the concentration of boron increases toward the interface with the carbon film. In other words, it was confirmed that the areas with the highest boron concentration were located near these interfaces. In addition, it was found that the gradient of the concentration was larger in the oxide semiconductor film than in the silicon oxide film. .

[0386] The phosphorus-added sample shown in FIG. 21(B) shows a similar tendency to that shown in FIG. 21(A). That is, even in the sample to which phosphorus was added, the silicon oxide film and the oxide semiconductor film The area with the highest phosphorus concentration is located near the interface of the oxide. It was found that the oxide semiconductor film had a larger thickness than the silicon oxide film.

[0387] From the above results, it is possible to inject impurity elements such as boron and phosphorus into the oxide semiconductor layer through the oxide insulating film. It has been confirmed that the addition of ZnO to the oxide semiconductor film makes it possible to form a stable oxide semiconductor film with extremely low resistance. In addition, a region with the highest concentration was formed near the interface between the oxide insulating film and the oxide semiconductor film. Therefore, even if a treatment for supplying oxygen to the oxide semiconductor film is performed, an increase in the resistance value is not observed. This result was confirmed by adding impurity elements such as boron and phosphorus to the oxide insulating film. This provides the oxide insulating film with blocking properties against oxygen, making it difficult for oxygen to diffuse. It can be inferred that this is the situation. EXAMPLES

[0388] Below, a transistor of one embodiment of the present invention was manufactured and its electrical characteristics were evaluated.

[0389] [Sample preparation] The structure of the manufactured transistor is the same as that of the transistor 100 illustrated in Embodiment 1 and FIG. In this study, boron and phosphorus were used as impurity elements, and the doping conditions were different. For comparison, a sample without any added impurity elements was also prepared. Made.

[0390] First, a tungsten film with a thickness of about 100 nm was formed on a glass substrate by sputtering. This was then processed to obtain a first gate electrode. A silicon nitride film having a thickness of about 240 nm, a silicon nitride film having a thickness of about 60 nm, and a silicon nitride film having a thickness of about 5 nm. A silicon oxynitride film was formed by laminating the silicon oxynitride film using a plasma CVD method.

[0391] Next, a metal oxide film with a thickness of about 40 nm is formed on the first gate insulating layer and processed. The metal oxide film was formed using an In-Ga-Zn oxide target (In The layer was formed by sputtering using a Zn / Ga alloy (atomic ratio: 1:1:1.2). After that, the sample was heated at 400°C for 1 hour in a nitrogen atmosphere, followed by a nitrogen and oxygen atmosphere. Heat treatment was carried out in a mixed atmosphere at 400°C for 1 hour.

[0392] Next, a silicon oxynitride film with a thickness of about 100 nm, which will become the second gate insulating layer, is plasma-etched. It was formed by the CVD method. After that, it was heated in a nitrogen atmosphere at 400℃ for 1 hour. Next, as an oxygen supply process, a plasma process was performed in an atmosphere containing oxygen. Ta.

[0393] Next, a metal oxide film having a thickness of about 20 nm is deposited on the second gate insulating layer by sputtering. The metal oxide film was formed using an In-Ga-Zn oxide target (In:Ga The film was formed by sputtering using a ZnO film (atomic ratio:Zn = 1:1:1.2).

[0394] Next, a molybdenum film with a thickness of about 100 nm was deposited on the metal oxide film by sputtering. The molybdenum film and the metal oxide film were then partially removed by etching. As a result, a second gate electrode and a metal oxide layer were obtained.

[0395] Next, an impurity element was added using the second gate electrode as a mask. The boron was added using a plasma ion doping device. B2H6 gas was used as the gas for supplying phosphorus, and PH3 gas was used as the gas for supplying phosphorus. For comparison, we also prepared samples with impurities added. A sample without the film was also prepared.

[0396] Next, a silicon oxynitride film about 300 nm thick is applied as a protective insulating layer to cover the transistor. The silicon oxynitride film was formed by plasma CVD at a temperature of 220°C. Then, the sample was heat-treated in a nitrogen atmosphere at 350°C for one hour. A portion of the insulating layer covering the transistor and the second gate insulating layer is opened, and a molybdenum film is sputtered. After forming a film by a deposition method, the film was processed to obtain a source electrode and a drain electrode. After that, an acrylic film with a thickness of about 1.5 μm was formed as a flattening layer, and the substrate was heated at 250 Heat treatment was carried out at 100° C. for 1 hour.

[0397] Through the above steps, a transistor was formed on a glass substrate.

[0398] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistor fabricated as described above were measured.

[0399] The Id-Vg characteristics of the transistor were measured under the following conditions: (hereinafter also referred to as gate voltage (Vg)), and the voltage applied to the second gate electrode ((Vb g) was applied from -15V to +20V in steps of 0.25V. The voltage applied to the source electrode (hereinafter referred to as the source voltage (Vs)) is set to 0V (comm). The voltage applied to the drain electrode (hereinafter referred to as drain voltage (Vd)) is set to 0.1 V. and 20V.

[0400] Figure 22 shows the Id-Vg characteristics of a boron-doped (B-Dope) transistor, and Figure 23 shows the Id-Vg characteristics of a boron-doped (B-Dope) transistor. The Id-Vg characteristics of the transistors with and without phosphorus added are shown in Figs. 22 and 23, respectively. The figures show the results for different impurity addition conditions arranged horizontally. A non-doped transistor is also shown. In FIG. 22 and FIG. 23, the channel width of the transistor is 50 μm and the channel length is 2 μm. , 3 μm, and 6 μm transistors are shown.

[0401] As shown in FIG. 22, the boron-doped transistor has a higher conductivity than the undoped transistor. It was found that a larger current can be passed through the transistor compared to the source. This shows that the resistance of the ion implantation region and the drain region is sufficiently low. At 20 kV, the channel length of the transistor was short at 2 μm, regardless of the dose. On the other hand, at a high accelerating voltage of 60 kV, the characteristics are not as good as those at other conditions. This tendency is due to the fact that the current value is lower than that of the sheet resistance in Example 1. This is consistent with the trends observed in the results.

[0402] As shown in FIG. 23, the transistors doped with phosphorus have the same effect as those doped with boron. Similarly, good electrical characteristics are shown. Note that, under high dose conditions, There are a number of transistors whose threshold voltages vary toward the negative side.

[0403] The device used to add impurity elements was a plasma ion implanter without a mass separation mechanism. Because a micro-ion doping device was used, there is a possibility that hydrogen may have been added in addition to the target element. Therefore, the threshold voltages observed in the transistors with short channel lengths in FIGS. The negative voltage shift may be due to the effect of hydrogen. By using an ion implanter with a dose separation mechanism, transistors with better electrical characteristics can be produced. It is speculated that it is possible to create a star. EXAMPLES

[0404] In the following, a transistor according to one embodiment of the present invention was manufactured and its reliability was evaluated.

[0405] The transistors for which the reliability was evaluated can be fabricated using the manufacturing process exemplified in Example 2 above. Boron is used as the impurity element, and the impurity element is added by a plasma ion doping device. The acceleration voltage was 20 kV and the dose was 5 × 10 15 cm -2 Also, The deposition temperature of the silicon oxynitride film functioning as a protective layer was set to 350°C.

[0406] The Id-Vg characteristics of the fabricated transistor are shown in Figure 24(A). has a channel length of 3 μm and a channel width of 50 μm.

[0407] Next, a gate bias stress test was performed to evaluate the reliability of the transistor. The GBT test was conducted by heating the substrate on which the transistor was formed to 60°C. The transistor is held at 0V on the source and drain, and the gate is held at 20V or -20V. The test environment was kept dark, and a positive voltage was applied to the gate. A test that applies a voltage is called PBTS, and a test that applies a negative voltage is called NBTS. PBTS and NBTS in the state where the sample is irradiated with light are expressed as PBITS and NBITS, respectively. The light was emitted from a white LED of approximately 10,000 lx.

[0408] FIG. 24(B) shows the change in threshold voltage (ΔV As shown in FIG. 24B, the variation in threshold voltage of the fabricated transistor was found to be extremely small.

[0409] As described above, the transistor of one embodiment of the present invention has favorable electrical characteristics and high reliability. I was able to confirm that I was prepared. EXAMPLES

[0410] In this example, a thermal desorption spectroscopy was performed on an insulating film containing an oxide to which an impurity element was added. Thermal Desorption Spectroscopy (TDS) was used. The oxygen blocking properties were evaluated.

[0411] [Rating 1] Here, after a process of supplying oxygen to the oxide insulating film over the oxide semiconductor film, A sample was prepared by supplying the material and the TDS was measured.

[0412] [Sample Preparation] First, an oxide semiconductor film was formed on a glass substrate to a thickness of about 40 nm. The atomic ratio of In:Ga:Zn was 1:1:1.2. The film was formed by a sputtering method.

[0413] Next, a silicon oxide film having a thickness of about 100 nm was formed on the oxide semiconductor film. The silicon film was formed by the plasma CVD method using silane gas and dinitrogen monoxide gas as the deposition gas. The substrate temperature during the film formation was 350°C.

[0414] Next, a treatment for supplying oxygen into the oxide semiconductor film was performed. A metal oxide film is formed on the silicon oxide film by sputtering in an atmosphere containing oxygen. After forming the film and supplying oxygen into the silicon oxide film, a heat treatment is performed at 400°C for 1 hour. Oxygen was supplied from the silicon oxide film to the oxide semiconductor film. Then, the metal oxide film was etched. The metal oxide film was formed under the same conditions as those for the oxide semiconductor film.

[0415] Next, impurities were added. The impurities were added using an ion implantation device with a mass separation mechanism. Here, boron ( 11 B), phosphorus ( 31 P), and argon( 40 In addition, as a comparison sample, we prepared samples implanted with impurities of 10 ... A sample was also prepared without injection.

[0416] The impurity implantation is optimized so that ions reach the oxide semiconductor film through the silicon oxide film. The boron implantation conditions were a beam energy of 20 keV and a dose of 100 μg / cm2. Amount 5 x 10 15 cm -2 The phosphorus implantation conditions were beam energy of 60 keV and The dose is 5×10 15 cm -2 The argon injection conditions were: beam energy The energy was set to 70 keV, and the dose was set to 5×10 15 cm -2 It was decided.

[0417] [TDS analysis results] FIG. 25 shows the results of a TDS analysis of oxygen molecules (mass-to-charge ratio (M / z) 32). In each figure, the vertical axis represents the detected intensity, and the horizontal axis represents the substrate temperature.

[0418] In the sample without ion implantation, oxygen was increased at a substrate temperature of about 150°C to 300°C. On the other hand, in the samples implanted with boron and phosphorus, the release of oxygen was From this result, it can be seen that the implantation of boron and phosphorus This stabilizes the excess oxygen in the silicon oxide film, thereby suppressing outward diffusion.

[0419] On the other hand, in the sample injected with argon, oxygen was released significantly, indicating that outward diffusion of oxygen was suppressed. It was confirmed that the effect of the suppression was weak. In addition to oxygen, argon (M / z=20 and M / z=40) was added at substrate temperatures from 250°C to 43°C. The results showed that argon, a rare gas, is released at temperatures in the range of about 0°C. The interaction with oxygen in silicon dioxide is small, so the effect of stabilizing excess oxygen is not very promising. It is assumed that this will not be possible.

[0420] [Rating 2] Here, a second oxide insulating film is formed on the first oxide insulating film that has been subjected to oxygen supply treatment. A sample was prepared by forming a film and supplying impurities to the second oxide insulating film, and TDS measurements were performed. The oxygen-blocking property of the second oxide insulating film was evaluated by measurement.

[0421] [Sample Preparation] First, a silicon oxide film with a thickness of about 150 nm was formed on a glass substrate as a first oxide insulating film. The silicon oxide film was formed under the same conditions as in Evaluation 1 above.

[0422] Next, a treatment for supplying oxygen to the first oxide insulating film was performed. A metal oxide film is formed on the silicon oxide film by sputtering in an atmosphere containing oxygen. The metal oxide film was then etched away by oxygen. The metal oxide film was removed using a silicon-containing indium tin oxide target. A film was formed.

[0423] Next, as a second oxide insulating film, a silicon oxide film having a thickness of about 100 nm is formed in the same manner as above. The film was formed by the same method.

[0424] Next, impurities were added. The impurities were added using an ion implantation device with a mass separation mechanism. As in Evaluation 1, boron ( 11 B), phosphorus ( 31 P) , and argon ( 40 Ar) were implanted into the sample. A sample without implantation of impurities was also prepared.

[0425] The impurity implantation conditions were optimized so that ions were implanted only into the second silicon oxide film. The boron implantation conditions were a beam energy of 5 keV and a dose of 5×10 15 cm -2 The phosphorus implantation conditions were a beam energy of 10 keV and a dose of 5×10 15 cm -2 The argon injection conditions were: beam energy of 10 keV The dose is 5×10 15 cm -2 It was decided.

[0426] [TDS analysis results] FIG. 26 shows the results of the TDS analysis.

[0427] In the sample without ion implantation, the substrate temperature increased from around 250°C to around 450°C. On the other hand, in the samples implanted with boron and phosphorus, the amount of oxygen released is It can be seen that almost no emission is observed. From this result, it can be seen that the implantation of boron and phosphorus It is understood that this stabilizes the excess oxygen in the silicon oxide film and suppresses outward diffusion.

[0428] On the other hand, the sample implanted with argon was heated at a lower temperature (15 It was confirmed that oxygen was released from the surface (around 0°C). This is due to the formation of a second oxygen atom during ion implantation. This is because the oxide insulating film is damaged, making it more susceptible to oxygen desorption and diffusion. It is presumed that this is the cause.

[0429] From the above results, it is clear that the excess oxygen is eliminated by implanting boron and phosphorus into the oxide insulating film. Furthermore, by injecting boron or phosphorus, the oxide insulation It was confirmed that the membrane could be given the function of blocking oxygen diffusion. EXAMPLES

[0430] In this example, we will explain the results of XPS analysis of a sample prepared by ion implantation. Reveal.

[0431] Here, the following two types of samples were fabricated and analyzed. The second sample is a sample in which an oxide insulating film is stacked on an oxide semiconductor film. The sample was obtained by implanting ions into the laminated film.

[0432] [Sample Preparation] First, the first sample is described. A 40-nm-thick oxide semiconductor film is formed on a glass substrate. A conductive film was formed. The film formation method can be the same as that in Example 4. Next, the oxide semiconductor film was Boron ( 11 B) was implanted. The boron implantation conditions were beam energy The energy was set to 5 keV, and the dose was set to 1×10 16 cm -2 It was decided.

[0433] For the second sample, the description of Evaluation 1 in Example 4 can be applied except for the ion implantation conditions. The implantation is carried out by ion implantation, using boron ( 11B) Optimized to reach the oxide semiconductor film The boron implantation conditions were as follows: beam energy 20 keV, dose 1×10 16 cm -2 It was decided.

[0434] [XPS analysis] The two samples prepared above were subjected to XPS analysis. The XPS analysis was performed in combination with sputtering. The depth direction was analyzed by sputtering with argon ions. The voltage was set to 2.0 kV, and the sputtering rate was approximately 5 nm / min in terms of SiO2.

[0435] FIG. 27A shows the results of XPS analysis of a sample in which ions were directly implanted into an oxide semiconductor film. The horizontal axis indicates the sputtering time. The vertical axis indicates the composition ratio.

[0436] As shown in FIG. 27, boron is present in the vicinity of the surface of the oxide semiconductor film (IGZO) at a concentration of several atomic percent. It has been detected in concentrations.

[0437] Figure 27(B) shows the structure of the 1s orbital of boron in an oxide semiconductor (IGZO). The XPS spectrum shows the energy range in which peaks are obtained. The horizontal axis shows the binding energy. The vertical axis is the binding energy, and the vertical axis is the intensity of the photoelectron. ) A peak is observed around 192 eV and a peak is observed around 188 eV. Therefore, boron in the oxide semiconductor film exists in an oxidized state, and boron alone is hardly present. I found out it didn't exist.

[0438] FIG. 27(C) shows the 3d 5 / 2 Energy at which the orbital-related peak is obtained The XPS spectrum in the range is shown. A peak is observed near 443 eV. This indicates that metallic indium is present. It is presumed that this removes the oxygen that is bonded to dium, causing oxygen deficiency.

[0439] FIG. 28A shows a case where ions are implanted into a stacked film in which an oxide insulating film is stacked on an oxide semiconductor film. The depth profile of the sample was obtained by XPS analysis. Boron was detected at a concentration of several atomic percent near the interface between the silicon dioxide (ON) and the oxide semiconductor film (IGZO). is.

[0440] FIG. 28(B) shows the structure of the 1s orbital of boron in an oxide insulating film (SiON). The XPS spectrum shows the energy range in which the peaks are obtained. However, boron exists in an oxidized state, as in the case of an oxide semiconductor film, and boron itself is hardly present. This indicates that boron is not present in the oxide insulating film. It was confirmed that this was the case.

[0441] From the above results, it is considered that boron implanted into the oxide semiconductor film and the oxide insulating film acts on the oxide It was confirmed that the element exists in the form of an oxide. EXAMPLES

[0442] In this example, a transistor of one embodiment of the present invention was manufactured, and its electrical characteristics were evaluated.

[0443] [Sample preparation] First, a first gate electrode and a second gate electrode were formed on a glass substrate by the same method as that shown in Example 2. A first gate insulating layer, a semiconductor layer, and a second gate insulating layer were formed. An aluminum oxide film with a thickness of about 10 nm is formed on the edge layer by sputtering, followed by A titanium film with a thickness of about 5 nm, an aluminum film with a thickness of about 300 nm, and a titanium film with a thickness of about 50 nm A titanium film is formed in sequence, and the metal film and part of the aluminum oxide film are removed by etching. A second gate electrode and a metal oxide layer were obtained.

[0444] Next, impurity elements are implanted by ion implantation using the second gate electrode as a mask. Here, boron ( 11 B) and phosphorus ( 31 P) was injected into two samples. The boron implantation conditions were a beam energy of 15 keV and a dose of 3. ×10 15 cm -2 The phosphorus implantation conditions were beam energy of 45 keV and doped The amount of sugar is 1×10 15 cm -2 It was decided.

[0445] Thereafter, a protective insulating layer was formed and a heat treatment was performed in the same manner as in Example 2. The source and drain electrodes were made of tandem films with a thickness of about 50 nm, which were formed by sputtering. The product of the fluorine-containing film, the aluminum film having a thickness of about 400 nm, and the titanium film having a thickness of about 100 nm was Subsequently, a flattening layer was formed and a heat treatment was carried out in the same manner as in Example 2.

[0446] Through the above process, two types of samples were obtained, one using boron and the other using phosphorus as the impurity element.

[0447] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistor fabricated above were measured. 2 can be used.

[0448] Figure 29 shows a transistor using boron as an impurity element and a transistor using phosphorus. In Fig. 29, the Id-Vg characteristics of the transistor are shown. The figure shows three types of transistors with lengths of 2 μm, 3 μm, and 6 μm. The number of measurements was 20.

[0449] As shown in FIG. 29, a boron-doped transistor and a phosphorus-doped transistor It was confirmed that both the MOS and the MOS capacitors exhibited extremely good electrical properties. [Explanation of symbols]

[0450] 100, 100A: transistor, 102: substrate, 103, 110, 116, 118: insulator Marginal layer, 103d, 108n, 110d: area, 106, 106c, 112, 120a, 1 20b: conductive layer, 108, 108c: semiconductor layer, 112f: conductive film, 114: metal oxide layer, 114f: metal oxide film, 130A, 130B: capacitance element, 140: impurity element, 1 41a, 141b, 142: Opening

Claims

1. A method for manufacturing a semiconductor device including an oxide semiconductor layer, comprising the steps of: forming an oxide film having a region in contact with a side surface of the oxide semiconductor layer and a region in contact with a top surface of the oxide semiconductor layer; forming a first conductive layer located above the oxide film and overlapping with the oxide semiconductor layer; adding an impurity element to the oxide semiconductor layer through the oxide film and the first conductive layer; forming an insulating layer having a region located above the first conductive layer and a region in contact with the oxide film, the insulating layer including silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, or hafnium aluminate; and performing a heat treatment in a state where the oxide film and the oxide semiconductor layer are in contact with each other to release oxygen from the oxide film to the oxide semiconductor layer. the impurity element to be added is phosphorus, boron, magnesium, aluminum, or silicon; The addition is performed so that the oxide semiconductor layer has a region in which a concentration of the impurity element becomes higher toward the oxide film.

2. In claim 1, The heat treatment is performed in a temperature range of 200° C. or more and 400° C. or less.

3. In claim 1 or 2, The method for manufacturing a semiconductor device, wherein the insulating layer is formed at a temperature in the range of 150° C. or more and 400° C. or less.

4. In any one of claims 1 to 3, the addition is performed so that the oxide film has a region in which a concentration of the impurity element becomes higher toward the oxide semiconductor layer.

5. In any one of claims 1 to 4, the addition is performed so that a concentration of the impurity element is highest at an interface between the oxide semiconductor layer and the oxide film, a portion of the oxide semiconductor layer close to the oxide film, or a portion of the oxide film close to the oxide semiconductor layer.

6. In any one of claims 1 to 5, The method for manufacturing a semiconductor device, wherein the addition is carried out by a plasma ion doping method or an ion implantation method.

Images