Display device

Abstract

To provide a display device with good display quality.SOLUTION: A display unit in which a plurality of pixels is arranged in a matrix is divided into regions A and B on the upstream side and the downstream side, respectively, in a scanning direction, and signal wiring for supplying an image signal is provided to each region. The regions A and B are adjacent to each other so that a boundary line indicating a boundary between both regions is bent. Bending the boundary line reduces split fringes that are generated at the boundary part. For example, in any column, the total number of pixels electrically connected to the signal wiring in the region A is made different from the total number of pixels electrically connected to the signal wiring in the region B.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] One embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. One aspect of the invention disclosed in this specification is a process, a machine, a manufacture, or Composition of matter. In particular, display devices and the construction of display devices. It relates to the manufacturing method.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electrical Optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices are all semiconductor devices. Alternatively, they may be said to include semiconductor devices. [Background technology]

[0003] An active matrix display having a transistor for driving a display element in each pixel For example, an active matrix type liquid crystal display device using a liquid crystal element as a display element is known. LCDs and organic EL (Electro Luminescence) displays e) Active matrix type light emitting display devices using light emitting elements such as These active matrix display devices have the following advantages over simple matrix display devices: In all cases, it is easy to increase the size and resolution of the screen, and this is advantageous in terms of reducing power consumption.

[0004] In addition, for active matrix display devices, the screen size must be 30 inches or more. There is a trend toward larger screen sizes, with diagonal sizes of 60 inches or more and even 120 inches or more. The development is being carried out with the aim of meeting the needs of the consumer. In addition, the screen resolution is set to full HD (picture Prime 1920 x 1080, also known as "2K".) Ultra Hi-Vision (3840 x 2160 pixels, also known as "4K"), Super Hi-Vision The trend towards higher resolution (7680 x 4320 pixels, also known as "8K") It is in that direction.

[0005] The increase in screen size and resolution tends to increase the wiring resistance within the display unit. In Reference 1, the increase in wiring resistance in liquid crystal display devices using amorphous silicon transistors is In order to suppress this, a technology for forming a low-resistance wiring layer using copper (Cu) has been disclosed. . [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2004-163901 A Summary of the Invention [Problem to be solved by the invention]

[0007] Increased wiring resistance can cause delays in signal transmission to the end of the signal line, distortion of the signal waveform, and voltage drops in the power line. This can result in degradation of display quality, such as uneven display and poor gradation, and power consumption. In addition, the increase in parasitic capacitance in the signal lines also leads to a decrease in display quality. This leads to an increase in power consumption. For example, amorphous silicon transistors have a field effect transistor. In display devices using amorphous silicon transistors, the wiring resistance increases due to the low mobility of the transistors. This tends to result in insufficient writing of image signals.

[0008] Therefore, as screen sizes become larger and resolution becomes higher, there is a demand for further reduction in wiring resistance. Similarly, there is a demand for reducing the parasitic capacitance that occurs in signal lines.

[0009] An object of one embodiment of the present invention is to provide a display device, an electronic device, or the like with high display quality. Alternatively, the present invention provides a display device or electronic device with low power consumption. Another object of the present invention is to provide a display device, electronic device, or the like that is highly productive. Another object of the present invention is to provide a display device, electronic device, or the like having high reliability. One of the objects of the present invention is to provide a novel display device or electronic device. It shall be one.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a liquid crystal display (LCD) including a display unit including a plurality of pixels, a plurality of scanning lines, and a plurality of first signal lines. and a plurality of second signal lines, wherein at least one of the plurality of pixels is a display element. and a transistor, the first signal lines and the second signal lines extending in the scanning direction. The first signal lines are provided on the upstream side in the scanning direction, and the second signal lines are provided on the downstream side in the scanning direction. A plurality of pixels are provided on the downstream side and are electrically connected to any one of a plurality of first signal lines. a first pixel and a second pixel electrically connected to any one of a plurality of second signal lines; The plurality of scanning lines include a first scanning line, a second scanning line, and a third scanning line, and the first scanning line is A region including a plurality of first signal lines and a plurality of second signal lines that overlap only with the plurality of first signal lines. The second scanning lines are the first signal lines and the second signal lines. The third scanning line includes an area overlapping at least one of the first signal lines, and the third scanning line includes an area overlapping at least one of the first signal lines. and a region overlapping at least one of the plurality of second signal lines. be.

[0012] Alternatively, in one aspect of the present invention, a plurality of pixels are arranged in m rows and n columns (m and n are integers of 1 or more). a display device including a display unit having n first signal lines, n second signal lines, and m scanning lines; At least one of the pixels includes a display element and a transistor, The first signal lines and the n second signal lines extend in the scanning direction, and the n first signal lines extend in the scanning direction. The n second signal lines are provided on the upstream side in the scanning direction, and the n second signal lines are provided on the downstream side in the scanning direction, and the plurality of pixels are The first pixel located in the jth column (j is an integer between 1 and n) and the second pixel located in the jth column a pixel electrically connected to the j-th first signal line, and a pixel electrically connected to the j-th first signal line, The m scanning lines are electrically connected to the second signal line, and the m scanning lines are the first scanning line, the second scanning line, and the third scanning line. a first scanning line, the first scanning line being selected from among the n first signal lines and the n second signal lines; The second scanning line includes an area overlapping only with the n first signal lines, and the second scanning line includes an area overlapping only with the n first signal lines and the n second signal lines. The third scanning line includes an area overlapping only with the n second signal lines among the two signal lines, and the third scanning line includes an area overlapping only with the n first signal lines among the two signal lines. a region overlapping at least one of the signal lines and a region overlapping at least one of the n second signal lines; A display device comprising:

[0013] Alternatively, one aspect of the present invention is a method for manufacturing a semiconductor device comprising the steps of: a display section including pixels (p is an integer of 4 or more), n first signal lines, and n second signal lines; m scanning lines, at least one of the p pixels being a display element; a transistor, and the n first signal lines and the n second signal lines extend in the scanning direction. , n first signal lines are provided on the upstream side in the scanning direction, and n second signal lines are provided on the downstream side in the scanning direction. The p pixels are electrically connected to the k-th (k is an integer equal to or greater than 1 and less than n) first signal line. a plurality of first pixels electrically connected to the k-th second signal line; a plurality of third pixels electrically connected to the (k+1)th first signal line; and a plurality of fourth pixels electrically connected to the second signal line, and the total number of the plurality of first pixels is a plurality of The display device is characterized in that the total number of the plurality of first pixels is different from the total number of the third pixels. the total number of the plurality of second pixels, the total number of the plurality of third pixels, and the total number of the plurality of fourth pixels It is preferred that the sum of the total numbers is equal.

[0014] Alternatively, one aspect of the present invention is a method for manufacturing a semiconductor device comprising the steps of: a display section including pixels (p is an integer of 4 or more), n first signal lines, and n second signal lines; m scanning lines, at least one of the p pixels being a display element; a transistor, and the n first signal lines and the n second signal lines extend in the scanning direction. , n first signal lines are provided on the upstream side in the scanning direction, and n second signal lines are provided on the downstream side in the scanning direction. The p pixels are electrically connected to the k-th (k is an integer equal to or greater than 1 and less than n) first signal line. a plurality of first pixels electrically connected to the k-th second signal line; a plurality of third pixels electrically connected to the (k+1)th first signal line; and a plurality of fourth pixels electrically connected to the second signal line, The ratio of the total number of the plurality of second pixels to the total number of the plurality of third pixels is The display device is characterized by a difference from the above.

[0015] The semiconductor material used for the semiconductor layer of the transistor is an amorphous semiconductor, a crystalline semiconductor, or a Conductors (microcrystalline semiconductors, polycrystalline semiconductors, single crystal semiconductors, or semiconductors with partially crystalline regions) For example, the semiconductor material used for the semiconductor layer of a transistor may be Silicon, germanium, etc. can be used. Silicon carbide, gallium Compound semiconductors such as arsenic, metal oxide, and nitride semiconductors, as well as organic semiconductors, can be used. can. Effect of the Invention

[0016] According to one aspect of the present invention, the screen size is 30 inches or more, and further 60 inches or more. According to one embodiment of the present invention, a display device having a high display quality can be provided. This makes it possible to provide display devices with good display quality at resolutions of up to 8K or higher.

[0017] According to one embodiment of the present invention, a display device, an electronic device, or the like with high display quality can be provided. Alternatively, a display device or electronic device with low power consumption can be provided. It is possible to provide a display device or electronic device having good reliability. It is possible to provide an electronic device, etc. Alternatively, it is possible to provide a novel display device, electronic device, etc. .

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0019] [Figure 1] 1A and 1B are diagrams illustrating a display device. [Diagram 2] FIG. [Diagram 3] FIG. [Figure 4] FIG. [Diagram 5] FIG. [Figure 6] 1A and 1B are diagrams illustrating a display device. [Figure 7] FIG. [Figure 8] FIG. 4 is a diagram for explaining a sub-pixel. [Figure 9] FIG. 2 is a diagram illustrating an example of the configuration of a pixel circuit. [Figure 10] 1A to 1C illustrate examples of the structure of a transistor. [Figure 11] 1A to 1C illustrate examples of the structure of a transistor. [Figure 12] 1A to 1C illustrate examples of the structure of a transistor. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor used in a display device. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor used in a display device. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor used in a display device. [Figure 16] 1A and 1B are diagrams illustrating a display device. [Figure 17] 1A and 1B are diagrams illustrating a display device. [Figure 18] FIG. 2 is a diagram illustrating a display module. [Figure 19] 1A to 1C are diagrams illustrating electronic devices. [Figure 20] 1A to 1C are diagrams illustrating electronic devices. [Figure 21] 1A to 1C are diagrams illustrating a laser irradiation method and a laser crystallization apparatus. [Figure 22] 1A to 1C are diagrams illustrating a laser irradiation method. [Figure 23] 1A and 1B are a block diagram showing a display module according to a first embodiment and a circuit diagram showing a pixel according to the first embodiment. [Figure 24] FIG. 2 is a top view showing a pixel layout according to the first embodiment. [Diagram 25] 13 is an approximate result of a data writing time in the first embodiment. [Figure 26] 13 is an approximate result of a data writing time in the first embodiment. [Figure 27] 1A and 1B are a block diagram showing a display module according to a first embodiment and a circuit diagram showing a pixel according to the first embodiment. [Figure 28] FIG. 2 is a top view showing a pixel layout according to the first embodiment. [Figure 29] 13 is an approximate result of a data writing time in the first embodiment. [Diagram 30] 13 is an approximate result of a data writing time in the first embodiment. [Diagram 31] 1A and 1B are a block diagram showing a display module according to a first embodiment and a circuit diagram showing a pixel according to the first embodiment. [Diagram 32] FIG. 2 is a top view showing a pixel layout according to the first embodiment. [Diagram 33] 13 is an approximate result of a data writing time in the first embodiment. [Diagram 34] 13 is an approximate result of a data writing time in the first embodiment. [Diagram 35] 13 is an approximate result of a data writing time in the first embodiment. [Diagram 36] 13 is an approximate result of a data writing time in the first embodiment. [Figure 37]13 is an approximate result of a data writing time in the first embodiment. [Figure 38] 5 is a diagram showing the relationship between the size of a pixel area and a frame frequency. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. In addition, the present invention is not limited to the above embodiment. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In some cases, the detailed description will be omitted.

[0021] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily intended to facilitate understanding of the invention. Therefore, the actual location, size, range, etc. may not be shown. The invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. For example, in the actual manufacturing process, layers and resist masks are removed by processes such as etching. Although it may be unintentionally omitted, it is preferable to omit it in order to make the invention easier to understand. be.

[0022] In addition, in particular in top views (also called "plan views") and perspective views, etc., the invention is easily understood. In order to simplify the illustration, some of the components may be omitted. may be omitted.

[0023] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It does not indicate any order or ranking, such as the order of processes or stacking. In addition, even if a term is not accompanied by an ordinal number in this specification, etc., it is possible to avoid confusion of the constituent elements. In order to avoid this, ordinal numbers may be used in the claims. In some cases, the ordinal numbers used in the description may differ from the ordinal numbers used in the claims. In addition, even if a term is given an ordinal number in this specification, etc., it may be included in the claims, etc. In some cases, the ordinal numbers may be omitted.

[0024] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is installed as an integral part.

[0025] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode (the part of the semiconductor through which current flows) overlaps with the The source region or source potential in the region where the This refers to the distance between the drain (drain region or drain electrode) and the In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is defined as any one value, maximum value, or The minimum or average value.

[0026] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. This refers to the length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0027] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter also referred to as the "effective channel width") shown in the top view of the transistor The channel width actually observed (hereinafter also referred to as the "apparent channel width") may differ from the For example, when the gate electrode covers the side surface of the semiconductor layer, the effective channel width becomes In some cases, the effect of the channel width becomes larger than that of the conventional method. In a transistor in which the gate electrode covers the side surface of the semiconductor, the channel formed on the side surface of the semiconductor In this case, the ratio of the channel formation region may be larger than the apparent channel width. , the effective channel width becomes larger.

[0028] In such a case, it may be difficult to estimate the effective channel width through actual measurement. For example, to estimate the effective channel width from the design value, the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known precisely, the effective It is difficult to measure channel width accurately.

[0029] Therefore, in this specification, the apparent channel width is defined as the "surrounding channel width (SCW)". In addition, in this specification, So, when we simply write "channel width," it means the enclosed channel width or the apparent channel width. In this specification, when the term "channel width" is used, it refers to the actual In addition, the channel length, channel width, and effective channel The width, apparent channel width, and enclosed channel width can be determined by analyzing cross-sectional TEM images. The value can be determined by, for example,

[0030] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0031] In the present specification and the like, a resist mask is formed by a photolithography method, and the If an etching process (removal process) is performed later, the resist mask is The mask shall be removed after the etching process is completed.

[0032] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0033] In this specification, a transistor includes a gate, a drain, and a source. It is an element that has at least three terminals. And the drain (drain terminal, drain Between the source (source terminal, source region or source electrode) and the A channel forming region is provided between the source and the drain. In this specification and the like, the term "channel formation region" refers to a region through which a current can flow. , the region through which current mainly flows.

[0034] In addition, unless otherwise specified, the transistors shown in this specification are enhancement type (non- The transistor shown in this specification is a field effect transistor of a 1000V type. Unless otherwise specified, the transistors are n-channel transistors. Unless otherwise specified, the voltage (also referred to as "Vth") is greater than 0 V.

[0035] In this specification and the like, the Vth of a transistor having a back gate is If there is no back gate potential, Vth is calculated by setting the back gate potential to the same potential as the source or gate. cormorant.

[0036] Unless otherwise specified in this specification, the off-state current refers to the current that flows when a transistor is in an off-state. The drain current when the device is in the off state (also called the non-conducting state or cut-off state). Unless otherwise specified, for n-channel transistors, the gate When the potential difference between the source and the gate (hereinafter referred to as "Vg") is lower than the threshold voltage Vth, In the p-channel transistor, the voltage between the gate and source, Vg, is equal to the threshold voltage, Vt For example, the off-state current of an n-channel transistor is when Vg is higher than h. When referring to the drain current when it is lower than the threshold voltage (hereinafter also referred to as "Vth") There is.

[0037] The off-state current of a transistor may depend on Vg. The current is I or less means that there exists a value of Vg at which the off-state current of the transistor is I or less. The off-state current of a transistor is the off-state current at a given Vg, Off-state at Vg in the range, or at Vg where a sufficiently reduced off-state current is obtained In some cases, it may refer to the off-state current in an off-state in which a transistor is turned on.

[0038] As an example, when Vth is 0.5 V and Vg is 0.5 V, the drain current is 1×10 -9 A, and the drain current at Vg of 0.1 V is 1×10 -13 A and Vg Drain current at -0.5V is 1×10 -19 A, and Vg is -0.8V Drain current is 1×10 -22 Assume an n-channel transistor with A. The drain current of the transistor is at or below Vg of -0.5V. 1×10 V to -0.8 V -19 Since it is less than A, the transistor The off-state current is 1×10 -19 A or less. The input current is 1×10 -22 Since there exists a Vg below A, the off-state current of the transistor Flow is 1×10 -22 It may be said that it is below A.

[0039] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the temperature is room temperature (RT), 60℃, 8 It may represent the off-state current at 5°C, 95°C, or 125°C. The temperature at which the reliability of a semiconductor device that includes a transistor is guaranteed, or At temperatures where the semiconductor device, etc. contained in the device is used (for example, temperatures between 5°C and 35°C) The off-state current of a transistor is sometimes expressed as RT, 6 0℃, 85℃, 95℃, 125℃, the reliability of the semiconductor device including the transistor is guaranteed The temperature at which the transistor is certified, or the temperature at which a semiconductor device or the like that contains the transistor is used (e.g. For example, the V It may refer to the existence of a value of g.

[0040] The off-state current of a transistor is determined by the voltage between the drain and source when the source is used as the reference (hereafter referred to as In this specification, the off-state current may depend on the If no voltage is present, Vd is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, or 3V. , may represent off-state current at 3.3V, 10V, 12V, 16V, or 20V Or, Vd that ensures the reliability of a semiconductor device or the like that includes the transistor, or , an off-state current at Vd used in a semiconductor device or the like including the transistor, The off-state current of a transistor is I or less when Vd is 0.1 V, 0 .8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16 V, 20V, Vd at which the reliability of the semiconductor device in which the transistor is included is guaranteed, or , Vd, which is used in a semiconductor device or the like including the transistor, This may refer to the existence of a value of Vg at which the off-state current of a transistor is equal to or less than I.

[0041] In the above description of the off-state current, the drain may be read as the source. may also refer to the current that flows through the source when the transistor is in the off state.

[0042] In addition, in this specification and the like, the term "leak current" may be used to mean the same thing as the "off current." In this specification, the off-state current refers to, for example, the current flowing when a transistor is in an off state. It can refer to the current that flows between the source and drain.

[0043] In this specification, the terms "above" and "below" refer to the positional relationship of components directly above or below each other. For example, "the electrode on insulating layer A is directly in contact with the insulating layer A" is not limited to the above. If the expression is "electrode B", it is not necessary for electrode B to be directly on insulating layer A. The inclusion of other components between the edge layer A and the electrode B is not excluded.

[0044] In this specification, unless otherwise specified, "parallel" means that two lines are -1 This refers to a state in which the object is arranged at an angle between 0° and 10°. Therefore, the angle is between -5° and 5°. In addition, "almost parallel" means that the two straight lines are -3 This refers to a state in which the two objects are arranged at an angle between 0° and 30°. Unless otherwise specified, this means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it includes the case where the angle is between 85° and 95°. " means that two straight lines are arranged at an angle of 60° or more and 120° or less, unless otherwise specified. This refers to the state in which something is being done.

[0045] In this specification, the terms "same," "the same," and "equal" are used to refer to counting values ​​and measurement values. " or "uniform" (including their synonyms), unless expressly stated The measurements are subject to a margin of error of plus or minus 20%.

[0046] (Embodiment 1) A display device 100 according to one embodiment of the present invention will be described with reference to the drawings.

[0047] <Configuration example> FIG. 1 is a block diagram for explaining a configuration example of a display device 100. The display device 100 includes: , a display unit 101, a scanning line driving circuit 102, a scanning line driving circuit 103, and a signal line driving circuit 104. 102, and a signal line driver circuit 105. The general term for circuits included in the signal line driver circuit 103, the signal line driver circuit 104, and the signal line driver circuit 105 is It may be called the "peripheral drive circuit" or "drive circuit". The peripheral drive circuit includes a shift register. Various circuits such as transistors, level shifters, inverters, latches, analog switches, and logic circuits can be used.

[0048] The display unit 101 has a plurality of pixels 110. For example, the display unit 101 has m rows and n columns (m and n are each 1 or greater). The display device 100 has a plurality of pixels 110 arranged in a matrix of (integer). has m wirings GL. Each of the m wirings GL extends in the row direction. Each of the m wirings GL is connected to a plurality of pixels 110 arranged in a row direction in the display unit 101. Connect emotionally.

[0049] In FIG. 1, the wiring GL electrically connected to the pixels 110 in the first row is indicated as wiring GL_1. In addition, a wiring electrically connected to the pixel 110 in the i-th row (i is an arbitrary integer of 1 to m) The line GL is indicated as a wiring GL_i. GL is shown as wiring GL_m.

[0050] One end of the wiring GL is electrically connected to the scanning line driving circuit 102, and the other end of the wiring GL is The scanning line driving circuit 102 is electrically connected to the scanning line driving circuit 103. The circuits 103 are provided in positions facing each other across the display unit 101. is sometimes called a "scan line."

[0051] The scanning line driver circuit 102 and the scanning line driver circuit 103 are connected to the wiring GL_1 to the wiring GL_m. In other words, the scanning line driver circuit 102 and the scanning The scanning line driver circuit 103 has a function of sequentially scanning the wirings GL_1 to GL_m. After scanning up to line GL_m, scanning starts again from line GL_1.

[0052] The wiring GL is connected to a selection signal supplied from the scanning line driving circuit 102 and the scanning line driving circuit 103. to the pixel 110.

[0053] The same wiring GL is supplied with a selection signal from the scanning line driving circuit 102 and the scanning line driving circuit 103 at the same time. By supplying the selection signal to the wiring GL, the supply capability of the selection signal can be improved. Depending on the above, either the scanning line driver circuit 102 or the scanning line driver circuit 103 may be omitted. stomach.

[0054] In the display device 100 according to one embodiment of the present invention, the display unit 101 is a display unit 101a located upstream in the scanning direction. The display unit 101 is provided in two parts, one on the upstream side in the scanning direction and the other on the downstream side in the scanning direction. The boundary between display unit 101a and display unit 101b is indicated by boundary line 108.

[0055] The display device 100 also has n wirings SLa and n wirings SLb. In this specification, when indicating both the wiring SLa and the wiring SLb, or the wiring SLa and the wiring S When explaining things common to Lb, it is sometimes called "wiring SL". n wirings SLa Each extends in the scanning direction (column direction) and corresponds to a plurality of pixels arranged in the column direction in the display unit 101a. The n wirings SLb are electrically connected to the pixels 110. ) and electrically connects to a plurality of pixels 110 arranged in a column direction in the display unit 101b. .

[0056] In FIG. 1, the wiring SLa electrically connected to the pixels 110 in the first column in the display unit 101a is The wiring is indicated as SLa_1. Also, the pixel in the jth column (j is an arbitrary integer between 1 and n) The wiring SLa electrically connected to the pixel 110 is indicated as wiring SLa_j. The wiring SLa electrically connected to the element 110 is indicated as wiring SLa_n.

[0057] In addition, in the display unit 101b, a wiring SLb electrically connected to the pixels 110 in the first column is provided. In addition, a wiring SLb electrically connected to the j-th pixel 110 is arranged. The line SLb_j is a line that is electrically connected to the pixel 110 in the nth column. The wiring is indicated as SLb_n.

[0058] One end of the wiring SLa is electrically connected to the signal line driver circuit 104, and one end of the wiring SLb is is electrically connected to the signal line driver circuit 105. The driving circuits 105 are disposed in positions facing each other across the display unit 101. SL may be called the "signal line."

[0059] The signal line driver circuit 104 has a function of supplying an image signal to the wiring SLa. The signal line driver circuit 104 has a function of transmitting an image signal to the pixel 110. The line driver circuit 105 has a function of supplying an image signal to the wiring SLb. The signal line driver circuit 105 has a function of transmitting an image signal to the pixel 110 .

[0060] FIG. 2 is a diagram showing the vicinity of the boundary between the display unit 101a and the display unit 101b. The line up to GL_i+4 is the display unit 101a, and the line from GL_i+5 onwards is the display unit 101b. be.

[0061] When all the pixels 110 provided in the jth column of the display unit 101 are connected with a single wiring, Due to the influence of resistance and parasitic capacitance, signal delay and distortion are likely to occur. In display devices with a diagonal size of 30 inches or more, this can easily cause a decrease in display quality. This can easily lead to a decrease in display quality even in display devices with a resolution of 4K or more.

[0062] As shown in FIG. 1 and FIG. 2, the wiring connected to the pixel 110 provided in the j-th column is By dividing it in half, like line SLa and wiring SLb, the wiring resistance and parasitic capacitance are each 1 Therefore, the effect on signal delay and distortion (time constant) can be reduced to 1 / 4. That is, the display quality of the display device can be improved.

[0063] In addition, the length of the wiring SLa_j included in the display unit 101a and the length of the wiring SLa_j included in the display unit 101b are It is preferable that the lengths of the lines SLb_j are equal. The wiring resistance of the display unit 101 can be made equal to the wiring resistance of the wiring SLb_j. The sum of the wiring resistances of the n wirings SLa included in the display unit 101a and the sum of the wiring resistances of the n wirings SLa included in the display unit 101b The total wiring resistance of the lines SLb can be made equal.

[0064] In addition, the number of pixels 110 electrically connected to the wiring SLa_j and the number of pixels electrically connected to the wiring SLb_j are It is preferable that the number of pixels 110 to be connected is equal. The parasitic capacitance occurring in the wiring SLb_j can be made substantially equal to the parasitic capacitance occurring in the wiring SLb_j. Therefore, the total parasitic capacitance of the n wirings SLa included in the display unit 101a and the The total parasitic capacitance of the n wirings SLb included in 1b can be made equal.

[0065] [Variation 1] On the other hand, when the boundary line 108 is a straight line as shown in FIG. The boundary between the display area 101b and the display area 101b may be recognized by the viewer as a dividing stripe. In this way, by making the boundary line 108 not a straight line, the display quality of the display device can be improved. can be increased to.

[0066] For example, in the display unit 101, the lengths of the wirings SLa and SLb are randomly changed for each column. By doing so, the boundary line 108 can be bent. The length of the wiring SLa in the jth column (wiring SLa_j) and the length of the wiring SLa in the j+1th column (wiring SLa_ Similarly, in the display unit 101, the length of the jth column wiring SLb ( The length of the wiring SLb_j) and the length of the wiring SLb in the j+1th column (wiring SLb_j+1) are changed. Alternatively, in the display unit 101, the length of the wiring SLa for each column may be The ratio of the length of b can be changed. Note that the above-mentioned variation in the length and ratio of the wiring is not limited to each row. , or may be performed for each set of several columns.

[0067] By bending the boundary line 108, the dividing stripes can be made less noticeable. The display quality of the display device 100 can be further improved.

[0068] In addition, the number of pixels 110 electrically connected to the wiring SLa_j and the number of pixels electrically connected to the wiring SLa_j+1 are The number of pixels 110 electrically connected to the wiring SLb_j may be different. The number of pixels 110 electrically connected to the wiring SLb_j+1 is different from the number of pixels 110 electrically connected to the wiring SLb_j+1. In this way, the boundary line 108 can be curved. In the display device 100, the number of pixels 110 electrically connected to the wiring SLa_j and the number of wirings S The sum of the number of pixels 110 electrically connected to the wiring SLa_j+1 and the number of pixels 110 electrically connected to the wiring SLa_j+1 the total number of pixels 110 electrically connected to the wiring SLb_j+1 and the total number of pixels 110 electrically connected to the wiring SLb_j+1 will be equal.

[0069] Here, the number of pixels 110 included in the display unit 101a is equal to the number of pixels 110 included in the display unit 101b. If the difference in the number of 0s is large, the difference in the wiring resistance and parasitic capacitance between the two will also be large. Therefore, the number of pixels 110 included in the display unit 101a and the display It is preferable that the number of pixels 110 included in the display unit 101b is equal to that of the display unit 101a. The difference between the number of pixels 110 included in the display unit 101b and the number of pixels 110 included in the display unit 101 is It is preferable that the number of pixels 110 included is 20% or less, and more preferably 10% or less. More preferred.

[0070] In other words, it is preferable that the area of ​​display portion 101a is equal to the area of ​​display portion 101b. The difference between the area of ​​the display unit 101a and the area of ​​the display unit 101b is 20% or less of the area of ​​the display unit 101. It is preferable that the ratio is 10% or less, and more preferable that the ratio is 10% or less.

[0071] [Modification 2] The display unit 101 may be of a dual source type. 1 shows the display unit 101 with the display portion 108 bent.

[0072] A double source type display unit has two wirings SL for one column of pixels 110. 10 is a display unit that switches the electrically connected wiring SL for each row (see FIG. 4 and See Figure 5(A). In addition, in the case of a double source type display, two lines of wiring GL can be selected at the same time. Therefore, the time for writing the image signal can be extended. Even during high-speed driving with an increased frequency, it is possible to prevent insufficient writing of image signals. For example, even when the frame frequency is 120Hz or more, the insufficient writing of the image signal is prevented. It is possible.

[0073] The frame frequency may be variable between 1 Hz and 120 Hz. In this case, the power consumption of the display device can be reduced by lowering the frame frequency. In addition, by increasing the frame frequency, visibility during video display can be improved. Cut.

[0074] In addition, the present invention is not limited to the double source type, and may be applied to a transistor in which three wirings SL are provided for one column of pixels 110. It may be a pull source type, or a quad type in which four wirings SL are provided for one column of pixels 110. For one column of pixels 110, five or more wirings SL may be provided. It may be provided.

[0075] [Modification 3] The display unit 101 of the display device 100 may be divided into four parts. A is a display unit 101 including display unit 101a, display unit 101b, display unit 101c, and display unit 6 and 7, the display unit 101a and the display unit 101d are divided into four areas. The boundary between the display unit 101b and the display unit 101c and the display unit 101d is indicated by a boundary line 108. 6 and 7, the display unit 101a and the display unit 101b are The boundary between the display unit 101c and the display unit 101d is indicated by a boundary line 109. The differences from the display device 100 of A will be described.

[0076] In the display device 100A, m wirings GLa are provided in the display unit 101a and the display unit 101b. Each of the m wirings GLa is connected to the display unit 101a and the display unit 101b. The wiring GLa is electrically connected to a plurality of pixels 110 arranged in the row direction. 2 is electrically connected to

[0077] The scanning line driver circuit 102 has a function of supplying a selection signal to the wiring GLa. The pixel 110 has a function of transmitting a selection signal supplied from the scanning line driver circuit 102 to the pixel 110 .

[0078] In the display device 100A, m wirings are provided in the display unit 101c and the display unit 101d. Each of the m wirings GLb is connected to a display unit 101c and a display unit 101d. The wiring GLb is electrically connected to a plurality of pixels 110 arranged in the row direction in the scanning line driving circuit. It is electrically connected to the line 103.

[0079] The scanning line driver circuit 103 has a function of supplying a selection signal to the wiring GLb. The scanning line driver circuit 103 has a function of transmitting a selection signal to the pixel 110 .

[0080] The wiring GL is divided into wiring GLa and wiring GLb to drive the display device 100A. The wiring resistance and parasitic capacitance of the GL can be reduced. In addition, the load on the scanning line driving circuit 103 is reduced, and the high-speed operation of the display device 100A is facilitated. It can be said that:

[0081] Similarly to the above-mentioned boundary line 108, the boundary line 109 may be curved.

[0082] In addition, a pixel 110 that controls red light, a pixel 110 that controls green light, and a pixel 110 that controls blue light are also provided. The pixels 110 are grouped together to function as one pixel 120, and the emission of each pixel 110 is By controlling the amount of light (luminance), a full color display can be achieved. Each of the three pixels 110 functions as a sub-pixel. Each controls the amount of red, green, or blue light emitted (see Figure 8(A)). The three sub-pixels control the colors of light: red (R), green (G), and blue (B). The combination is not limited to cyan (C), magenta (M), and yellow (Y) (Figure 8( See B). ).

[0083] In addition, four sub-pixels may be combined to function as one pixel. For example, red light, green light, A subpixel for controlling white light may be added to the three subpixels for controlling colored light and blue light, respectively. (See FIG. 8(C)). By adding a sub-pixel that controls white light, the brightness of the display area can be increased. In addition, the three sub-pixels that control red, green, and blue light, respectively, A sub-pixel for controlling yellow light may be added (see FIG. 8(D)). In addition to the three sub-pixels that control the primary light, secondary light, and yellow light, a sub-pixel that controls white light is also added. (See FIG. 8(E)).

[0084] By increasing the number of sub-pixels that function as one pixel, red, green, blue, cyan, magenta, and By appropriately combining sub-pixels that control light such as yellow and red, the reproduction of intermediate tones is improved. Therefore, the display quality can be improved.

[0085] In addition, the display device of one embodiment of the present invention can reproduce color gamuts of various standards. For example, PAL (Phase Alternating Line) used in television broadcasting Standards and NTSC (National Television System Com mittee) standard, personal computers, digital cameras, printers and other electronic devices The sRGB (standard RGB) standard is widely used in display devices for electronic equipment. Adobe RGB standard, HDTV (High Definition Television) ITU-R BT.709 (International Television Standards ational Telecommunication Union Radiocom munication Sector Broadcasting Service(T elevision) 709) standard, DCI-P3 (Digital Cinema Projection) igital Cinema Initiatives P3) standard, UHDTV (Ul tra High Definition Television, Super Hi-Vision ITU-R BT.2020 (REC.2020 (Recommendation) It is possible to reproduce color gamuts such as the HDMI 2.0 (Endation 2020) standard.

[0086] In addition, if the pixels 120 are arranged in a 1920 x 1080 matrix, a so-called full high-definition Resolution of vision (also called "2K resolution", "2K1K", or "2K") It is possible to realize a display device 100 capable of full color display at 3000 x 1000 pixels. When 120 pixels are arranged in a 3840 x 2160 matrix, it becomes what is called Ultra High Vision. (also called "4K resolution", "4K2K", or "4K") In addition, for example, the pixel 120 can be used as the display device 100 capable of displaying multiple colors. When these are arranged in a 7680 x 4320 matrix, it becomes what is known as Super Hi-Vision ( It is also called "8K resolution," "8K4K," or "8K." By increasing the number of pixels 120, a display device 100 capable of displaying 16 pixels can be realized. It is also possible to realize a display device 100 capable of full-color display at a resolution of 32K or 32K. .

[0087] According to one aspect of the present invention, a transistor for driving a display element is made of, for example, amorphous silicon. Even when transistors are used, the screen size is 30 inches or more diagonally, and even 60 inches. According to one embodiment of the present invention, a display device having a high display quality of 1.0 inches or more can be provided. When an amorphous silicon transistor is used as a transistor for driving a display element, Even if the display is not 4K or higher, it is possible to provide a display device with good display quality at resolutions of 4K or higher, and even 8K or higher. Can be provided.

[0088] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0089] (Embodiment 2) In this embodiment, an example of a circuit configuration that can be used for the pixel 110 will be described with reference to FIG. The pixel 110 includes a pixel circuit 438 and a display element 432.

[0090] [An example of a pixel circuit for a light-emitting display device] FIG. 9(A) shows an example of a circuit configuration that can be used for the pixel 110. The pixel circuit 438 shown in A) includes a transistor 436, a capacitor 433, and a transistor The pixel circuit 438 includes a display element 432 and a transistor 434. The light-emitting element 4513 functions as a light-emitting element.

[0091] One of the source electrode and the drain electrode of the transistor 436 is connected to a pixel to which an image signal is applied. The gate electrode of the transistor 436 is electrically connected to the line SL_j. The signal is electrically connected to a wiring GL_i to which a signal is given.

[0092] The transistor 436 has a function of controlling writing of an image signal to the node 435 .

[0093] One of a pair of electrodes of the capacitor 433 is electrically connected to the node 435, and the other is The source and drain electrodes of the transistor 436 are electrically connected to the gate 437. The other of the electrodes is electrically connected to node 435 .

[0094] The capacitor 433 functions as a storage capacitor that stores data written to the node 435. has.

[0095] One of the source electrode and the drain electrode of the transistor 251 is connected to the potential supply line VL_a. The other end is electrically connected to node 437. The gate electrode of one is electrically connected to a node 435 .

[0096] One of the source electrode and the drain electrode of the transistor 434 is electrically connected to the potential supply line V0. and the other is electrically connected to a node 437. The gate electrode is electrically connected to the wiring GL_i.

[0097] One of the anode and the cathode of the light emitting element 4513 is electrically connected to the potential supply line VL_b. and the other is electrically connected to node 437.

[0098] The light emitting element 4513 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 4513 is not limited to this, and examples thereof include For example, an inorganic EL element made of an inorganic material may be used.

[0099] As the power supply potential, for example, a potential on the relatively high potential side or a potential on the relatively low potential side is used. The power supply potential on the high potential side is called the high power supply potential (also called "VDD"), and the power supply potential on the low potential side is called the The power supply potential on the side of the power supply is called the low power supply potential (also called "VSS"). Or it can be used as a low power supply potential. For example, when the high power supply potential is the ground potential, The low power supply potential is a potential lower than the ground potential. When the low power supply potential is the ground potential, the high power supply potential is The potential is higher than the ground potential.

[0100] For example, a high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0101] In the display device having the pixel circuit 438 of FIG. 9A, the scanning line driver circuit 102 and / or The pixel circuits 438 in each row are sequentially selected by the scanning line driving circuit 103, and the transistors 43 6, and a transistor 434 is turned on to write an image signal to a node 435.

[0102] The pixel circuit 438 in which data is written to the node 435 is connected to a transistor 436 and a transistor The transistor 434 is turned off, which results in a holding state. A current flows between the source and drain electrodes of the transistor 251 according to the potential of the input data. The amount of current flowing through the light emitting element 4513 is controlled, and the light emitting element 4513 emits light with a luminance according to the amount of current flowing through the light emitting element 4513. By performing this process row by row, an image can be displayed.

[0103] The transistor 436 is preferably a transistor with low off-state current. By using a transistor with low off-state current for the transistor 436, the potential of the node 435 can be stabilized. In addition, the transistor 434 also has an off-state current It is preferable to use transistors with low current.

[0104] [An example of a pixel circuit for a liquid crystal display device] The pixel circuit 438 shown in FIG. 9B includes a transistor 436 and a capacitor 433. The pixel circuit 438 is electrically connected to the liquid crystal element 180 that functions as the display element 432. Connected.

[0105] The potential of one of the pair of electrodes of the liquid crystal element 180 is appropriately set according to the specifications of the pixel circuit 438. The alignment state of the liquid crystal element 180 is set by the data written to the node 435. Note that one of a pair of electrodes of the liquid crystal element 180 included in each of the pixel circuits 438 A common potential may be applied to the liquid crystal pixels of each row of pixel circuits 438. A different potential may be applied to one of the pair of electrodes of the element 180 .

[0106] The liquid crystal element 180 may be, for example, a vertical alignment (VA) liquid crystal element. A liquid crystal element in which the MV t) mode is applied can be used. A (Multi-Domain Vertical Alignment) mode, PV A(Patterned Vertical Alignment) mode, ASV(A Advanced Super View (AVC) mode can be used.

[0107] The liquid crystal element 180 can be a liquid crystal element to which various modes are applied. For example, In addition to the VA mode, TN (Twisted Nematic) mode and IPS (In- Plane-Switching) mode, VA-IPS mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetr ic aligned Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr ionic Liquid Crystal) mode, guest-host mode, etc. A liquid crystal element to which the above is applied can be used.

[0108] A liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of liquid crystals. The optical modulation of liquid crystals is caused by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field or oblique electric field). The liquid crystal used in the liquid crystal element is thermotropic. Low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC) ispersed liquid crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. These liquid crystal materials can be used in the cholesteric phase, smectic phase, etc., depending on the conditions. These phases include cubic phase, chiral nematic phase, isotropic phase, etc.

[0109] The liquid crystal material may be either a positive type liquid crystal or a negative type liquid crystal. The optimum liquid crystal material should be selected according to the mode and design.

[0110] An alignment film can be provided to control the alignment of the liquid crystal. In this case, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing a chiral agent of several percent by weight or more is used. A liquid crystal composition containing a liquid crystal exhibiting the above formula and a chiral agent has a short response time and is optically isotropic. In addition, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require an alignment treatment, The viewing angle dependency is small. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. Therefore, electrostatic damage caused by the rubbing process can be prevented, and This makes it possible to reduce defects and damage to the liquid crystal display device.

[0111] In addition, by using a liquid crystal material that operates in a guest-host mode for the liquid crystal element 180, Functional members such as a light diffusing layer and a polarizing plate can be omitted. This improves the productivity of the display device. In addition, since no functional members such as a polarizing plate are provided, the liquid crystal element The reflected brightness of 180 can be increased. Therefore, the visibility of the display device can be improved. do.

[0112] In addition, the switching between the on and off states (bright state) of a reflective liquid crystal display device using a circular polarizer The switching between the dark and light states is achieved by aligning the long axes of the liquid crystal molecules in a direction roughly perpendicular to the substrate or roughly parallel to the substrate. This is done by aligning the display in a horizontal direction. Generally, this is done in the horizontal electric field method such as IPS mode. In liquid crystal elements that operate at 1000 Hz, the long axes of the liquid crystal molecules are approximately parallel to the substrate in both the on and off states. Since the reflections are aligned in the same direction, it is difficult to use this method in a reflective liquid crystal display device.

[0113] The liquid crystal element that operates in VA-IPS mode operates in a horizontal electric field manner and has an on / off state. The state can be switched by aligning the long axis of the liquid crystal molecules in a direction approximately perpendicular to the substrate or approximately parallel to the substrate. For this reason, the in-plane switching method is used for reflective LCD devices. When using a liquid crystal element that operates in VA-IPS mode, use a liquid crystal element that operates in VA-IPS mode. is preferred.

[0114] As described later, other than the light-emitting element 4513 and the liquid crystal element 180, A display element can also be applied.

[0115] In the pixel circuit 438 in the i-th row and the j-th column, One of the electrodes is electrically connected to the wiring SL_j, and the other is electrically connected to a node 435. A gate electrode of the transistor 436 is electrically connected to the wiring GL_i. The register 436 has a function of controlling writing of an image signal to the node 435 .

[0116] One of a pair of electrodes of the capacitor 433 is connected to a wiring to which a specific potential is supplied (hereinafter, a capacitor line CL ) and the other is electrically connected to node 435. The other of the pair of electrodes of 80 is electrically connected to a node 435. The value of is set appropriately according to the specifications of the pixel circuit 438. 5 serves as a storage capacitor for storing data written therein.

[0117] For example, in a display device having a pixel circuit 438 shown in FIG. The pixel circuits 438 in each row are sequentially selected by the scanning line driver circuit 103 and / or the transistors A starter 436 is turned on to write an image signal to a node 435 .

[0118] In the pixel circuit 438 in which an image signal is written to the node 435, the transistor 436 is in an off state. By performing this process for each row, the image is displayed in the display area 235. You can display the image.

[0119] The transistor 436 is preferably a transistor with low off-state current. By using a transistor with low off-state current for the transistor 436, the potential of the node 435 can be stabilized. This makes it possible to improve the display quality of the display device.

[0120] [Display element] The display device according to one embodiment of the present invention may have various forms or various display elements. The display element can be, for example, an LED (white LED, red LED, green LED, blue LED, etc.). EL (electroluminescence) elements (organic and inorganic) including color LEDs EL elements, organic EL elements, inorganic EL elements), transistors (emitting light according to the electric current) Transistors), plasma display panels (PDPs), electron emission elements, liquid crystal elements, Electrophoretic elements, grating light valves (GLVs) and digital micromirror devices (DMD), DMS (Digital Micro Shutter) element, MIRASOL (registered trademark) Display, IMOD (Interferometric Modulation) element, pressure MEMS (Micro-Electro-Mechanical Systems) such as electro-ceramic displays In addition, display elements using fluororesin and electrowetting elements are also included. However, the contrast, brightness, reflectance, transmittance, etc., change due to electrical or magnetic effects. The display medium may be a quantum dot.

[0121] An example of a display device using an EL element is an EL display. An example of a display device using this method is a field emission display (FED). is a flat panel display using the SED method (SED: Surface-conduction E LCD displays are used in the following applications: An example of the device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). play, reflective LCD, direct-view LCD, projection LCD) An example of a display device using an electrophoretic element is electronic paper. An example of a display device using quantum dots is a quantum dot display.

[0122] In order to realize a semi-transmissive or reflective LCD, the pixel voltage must be A part or the whole of the electrode may function as a reflective electrode. For example, A part or the whole of the pixel electrode may be made of aluminum, silver, or the like. In this case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode. This further reduces power consumption.

[0123] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0124] (Embodiment 3) In this embodiment mode, a transistor that can be used for the display device or the like shown in the above embodiment mode will be described. An example of the star will be described with reference to the drawings.

[0125] The display device 100 according to one embodiment of the present invention includes a bottom-gate transistor and a top-gate transistor. The transistors can be manufactured using various types of transistors, such as Planar type transistors or staggered type transistors may be used. Therefore, the semiconductor layer material and transistor structure used can be easily adjusted to fit existing production lines. can be easily replaced.

[0126] [Bottom-gate transistor] FIG. 10(A1) shows a channel-protected transistor, which is a type of bottom-gate transistor. 10A is a cross-sectional view of a transistor 410. In FIG. The transistor 410 is formed on a substrate 271 with an insulating layer 272 interposed therebetween. The semiconductor layer 242 is formed on the electrode 246 via the insulating layer 226. The electrode 246 can function as a gate electrode. The insulating layer 226 can function as a gate insulating layer. It can function.

[0127] In addition, an insulating layer 241 is provided on a channel formation region of the semiconductor layer 242. 42, the electrode 244a and the electrode 244b are provided on the insulating layer 226. Electrode 244a can function as either a source electrode or a drain electrode. A part of the electrode 244a and the electrode 244b can function as the other of the source electrode and the drain electrode. A portion of the pole 244 b is formed on the insulating layer 241 .

[0128] The insulating layer 241 can function as a channel protection layer. By providing the electrode 244a and the electrode 244b, the exposure of the semiconductor layer 242 that occurs during the formation of the electrode 244a and the electrode 244b is prevented. Therefore, when the electrodes 244a and 244b are formed, the semiconductor layer This can prevent the channel formation region 242 from being etched. According to this, a transistor having good electrical characteristics can be realized.

[0129] The transistor 410 is provided with an insulating layer 241 on the electrodes 244a and 244b. A layer 228 is provided, and an insulating layer 229 is provided on the insulating layer 228 .

[0130] When a semiconductor such as silicon is used for the semiconductor layer 242, the semiconductor layer 242 and the electrode 244a and between the semiconductor layer 242 and the electrode 244b, as an n-type semiconductor or a p-type semiconductor. It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. It can function as a source or drain region of a transistor.

[0131] The insulating layer 229 has a function of preventing or reducing the diffusion of impurities from the outside into the transistor. It is preferable to form the insulating layer 229 using a material having the above structure. It is also possible.

[0132] The transistor 411 shown in FIG. 10A2 has an insulating layer 229 over which a back gate electrode is formed. The transistor 410 differs from the transistor 410 in that it has a functioning electrode 223. It can be formed from the same materials and by the same method as 246.

[0133] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can function in the same manner as the gate electrode. Alternatively, the potential may be set to ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the potential of the back electrode, the transistor threshold The voltage can be varied.

[0134] Both the electrode 246 and the electrode 223 can function as a gate electrode. The insulating layer 226, the insulating layer 228, and the insulating layer 229 each serve as a gate insulating layer. The electrode 223 is provided between the insulating layer 228 and the insulating layer 229. This is also fine.

[0135] When one of the electrodes 246 and 223 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 411, the electrode 223 is called a "gate electrode." When the term "electrode" is used, the electrode 246 is referred to as the "back gate electrode." When the transistor 411 is used as a "top gate electrode," the transistor 411 is a top-gate type transistor. In addition, either the electrode 246 or the electrode 223 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0136] By providing the electrode 246 and the electrode 223 with the semiconductor layer 242 interposed therebetween, 6 and the electrode 223 are set to the same potential, the region in which carriers flow in the semiconductor layer 242 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 411 increases, the field effect mobility increases.

[0137] Therefore, the transistor 411 is a transistor having a large on-current relative to its area. That is, the area occupied by the transistor 411 is set to the required on-current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0138] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they can be electrically connected to the outside of the transistor. The function of preventing the electric field generated from acting on the semiconductor layer in which the channel is formed (especially static electricity The back gate electrode is larger than the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0139] The gate electrode and the back gate electrode each have the function of shielding an electric field from the outside. Therefore, the charges of charged particles generated above and below the transistor form a channel in the semiconductor layer. As a result, stress tests (e.g., applying a negative voltage to the gate) BT (Negative Gate Bias-Temperature) stress test (also called "NBT" or "NBTS") deterioration is suppressed. The back gate electrode blocks the electric field generated by the drain electrode from acting on the semiconductor layer. Therefore, the on-current rise voltage caused by the drain voltage fluctuation can be This effect can be achieved by controlling the gate electrode and the back gate electrode. This is particularly noticeable when a potential is applied.

[0140] In addition, a transistor having a back gate electrode is a PGBT in which a positive voltage is applied to the gate. (Positive Gate Bias-Temperature) Stress Test (" The variation in threshold voltage before and after the PBT or PBTS process is also due to backgain. It is smaller than a transistor that does not have a gate electrode.

[0141] Note that NGBT and PGBT stress tests are a type of accelerated test, and are used for a long period of time. This allows the evaluation of changes in transistor characteristics (aging) that occur during use in a short period of time. In particular, the amount of change in the threshold voltage of a transistor before and after the BT stress test is This is an important index for investigating the reliability of the device. The smaller the amount of variation, the more reliable the transistor is.

[0142] In addition, by providing a gate electrode and a back gate electrode and setting both to the same potential, This reduces the amount of variation in the low-value voltage. At the same time, the fluctuation is reduced.

[0143] In addition, when light is incident from the back gate electrode side, the back gate electrode is made of a material having a light blocking property. By forming the semiconductor layer from a conductive film, light is prevented from entering the semiconductor layer from the back gate electrode side. This prevents the semiconductor layer from being photodegraded and the threshold voltage of the transistor is shifted. This can prevent deterioration of electrical characteristics such as the occurrence of

[0144] According to one embodiment of the present invention, a transistor with high reliability can be provided. A highly reliable semiconductor device can be realized.

[0145] FIG. 10(B1) shows a channel-protection transistor, which is a type of bottom-gate transistor. 4 shows a cross-sectional view of transistor 420. Transistor 420 has a similar structure to transistor 410. The difference is that an insulating layer 241 covers a semiconductor layer 242. In an opening formed by selectively removing a portion of the insulating layer 241 overlapping the conductor layer 242, The semiconductor layer 242 and the electrode 244a are electrically connected to each other. In another opening formed by selectively removing a part of the insulating layer 241, the semiconductor layer 242 and The electrode 244b is electrically connected to the insulating layer 241. can function as a channel protection layer.

[0146] The transistor 421 illustrated in FIG. 10B2 has a back gate electrode over the insulating layer 229. It differs from transistor 420 in that it has a functioning electrode 223 .

[0147] By providing the insulating layer 241, the semiconductor generated during the formation of the electrodes 244a and 244b is Therefore, when the electrodes 244a and 244b are formed, the layer 242 can be prevented from being exposed. In addition, it is possible to prevent the semiconductor layer 242 from becoming thin.

[0148] In addition, the transistors 420 and 421 are the same as the transistors 410 and The distance between the electrodes 244a and 246 and the distance between the electrodes 244b and 246 are larger than the distance between the electrodes 244a and 246 and the distance between the electrodes 244b and 246 and the distance between the electrodes 244b and 246 and the distance between the electrodes 244a and 246 and the distance between the electrodes 244b ... Therefore, the distance between the electrodes 244a and 246 is increased. In addition, the parasitic capacitance between the electrode 244b and the electrode 246 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Cut.

[0149] The transistor 425 illustrated in FIG. 10C1 is a bottom-gate transistor. The transistor 425 is a channel etching type transistor having an insulating layer 241. Therefore, the electrodes 244a and 244b are formed without using the When the electrode 244b is formed, a part of the semiconductor layer 242 that is exposed may be etched. On the other hand, since the insulating layer 241 is not provided, productivity of the transistor can be increased.

[0150] The transistor 426 shown in FIG. 10C2 has an insulating layer 229 over which a backgate electrode is formed. It differs from transistor 425 in that it has a functioning electrode 223 .

[0151] [Top-gate transistor] FIG. 11A1 shows a cross-sectional view of a transistor 430, which is a type of top-gate transistor. The transistor 430 has a semiconductor layer 242 over an insulating layer 272. an electrode 244a on the layer 242 and the insulating layer 272, the electrode 244a being in contact with a portion of the semiconductor layer 242; The semiconductor layer 242 has an electrode 244b in contact with a part of the semiconductor layer 242. An insulating layer 226 is provided on the electrode 244b, and an electrode 246 is provided on the insulating layer 226.

[0152] The transistor 430 is connected to the electrodes 246 and 244a, and the electrodes 246 and Since the electrodes 246 and 244b do not overlap, the parasitic capacitance between the electrodes 246 and 244a and In addition, the parasitic capacitance occurring between the electrode 246 and the electrode 244b can be reduced. After the electrode 246 is formed, the electrode 246 is used as a mask to introduce the impurity 255 into the semiconductor. By introducing the ions into the semiconductor layer 242, the ions are self-aligned in the semiconductor layer 242. A pure region can be formed (see FIG. 11(A3)). Therefore, a transistor having good thermal characteristics can be realized.

[0153] The introduction of the impurity 255 can be performed by an ion implantation device, an ion doping device, or a plasma treatment device. This can be done using a processing device.

[0154] The impurity 255 may be, for example, at least one of Group 13 elements or Group 15 elements. When an oxide semiconductor is used for the semiconductor layer 242, As impurities 255, at least one element selected from rare gases, hydrogen, and nitrogen is used. It is also possible that

[0155] The transistor 431 shown in FIG. 11A2 has an electrode 223 and an insulating layer 227. The transistor 431 is formed on the insulating layer 272. The electrode 223 has an insulating layer 227 formed on the electrode 223. The electrode 223 is Therefore, the insulating layer 227 can function as a gate insulating layer. The insulating layer 227 can function as a barrier layer. It can be formed.

[0156] Like the transistor 411, the transistor 431 has a large on-state current relative to its area. That is, for the required on-current, the transistor 4 According to one aspect of the present invention, the area occupied by the transistor 31 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. It is possible to realize a body device.

[0157] The transistor 440 illustrated in FIG. 11B1 is a top-gate transistor. The transistor 440 is a semiconductor device after forming the electrodes 244a and 244b. The transistor 430 differs from the transistor 430 in that the layer 242 is formed. The transistor 441 has an electrode 223 and an insulating layer 227. In the transistor 440 and the transistor 441, the semiconductor layer 242 A part of the semiconductor layer 242 is formed on the electrode 244a, and another part of the semiconductor layer 242 is formed on the electrode 244b. will be done.

[0158] Like the transistor 411, the transistor 441 has a large on-state current relative to the area it occupies. That is, for the required on-current, the transistor 4 According to one aspect of the present invention, the area occupied by the transistor 41 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. It is possible to realize a body device.

[0159] The transistor 442 illustrated in FIG. 12A1 is a top-gate transistor. The transistor 442 is formed by forming the insulating layer 229, and then forming the electrode 244a and the electrode 244b. The transistor 430 and the transistor 440 are different in that the electrode 244a is formed. The electrode 244b is a semiconductor layer formed in an opening in the insulating layer 228 and the insulating layer 229. The insulating layer 242 is electrically connected to the insulating layer 242 .

[0160] In addition, a part of the insulating layer 226 that does not overlap the electrode 246 is removed, and the electrode 246 and the remaining insulating layer 226 as a mask to introduce impurities 255 into the semiconductor layer 242, In the semiconductor device shown in FIG. 242, an impurity region can be formed in a self-aligned manner (see FIG. 12(A3)). The transistor 442 is configured such that the insulating layer 226 extends beyond the edge of the electrode 246. When the impurity 255 is introduced into the semiconductor layer 242, the semiconductor layer 242 The impurity concentration in the region where the impurity 255 is introduced through the insulating layer 226 is The region where the impurity 255 is introduced without any intervening layer is smaller than the region where the impurity 255 is introduced without any intervening layer. The LDD (Lightly Doped Drain) region exists in the area that does not overlap with pole 246. is formed.

[0161] The transistor 443 shown in FIG. 12A2 has an electrode 223. 2. The transistor 443 has an electrode 223 formed on a substrate 271 and an insulating The electrode 223 overlaps the semiconductor layer 242 via the edge layer 272. The electrode 223 functions as a back gate electrode. It can be done.

[0162] In addition, the transistor 444 shown in FIG. 12B1 and the transistor As in the case of the area 445, the insulating layer 226 in the area not overlapping the electrode 246 may be entirely removed. In addition, the transistor 446 shown in FIG. 12C1 and the transistor shown in FIG. The insulating layer 226 may be left as is, for example, at 447.

[0163] After forming the electrode 246, the transistors 442 to 447 are also As a result, the semiconductor layer 242 is doped with impurities 255 using the mask. According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner. According to one aspect of the present invention, a transistor having good integration properties can be realized. Therefore, a highly reliable semiconductor device can be realized.

[0164] [substrate] There are no major limitations on the material used for the substrate. Depending on the purpose, the substrate may be transparent or non-transparent, or may be able to withstand heat treatment. The material can be selected taking into consideration the degree of heat resistance, etc. For example, barium borosilicate glass or aluminum Glass substrates such as borosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. In addition, semiconductor substrates, flexible substrates, and bonding substrates can be used. A laminating film, a base film, etc. may also be used.

[0165] The semiconductor substrate is, for example, a semiconductor made of silicon or germanium. Substrate, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, There are also compound semiconductor substrates made of zinc oxide or gallium oxide. The solid substrate may be a single crystal semiconductor or a polycrystalline semiconductor.

[0166] In addition, the substrates are, for example, 6th generation (1500mm x 1850mm), 7th generation (18 70mm×2200mm), 8th generation (2200mm×2400mm), 9th generation (24 00mm x 2800mm), 10th generation (2950mm x 3400mm), etc. This allows the use of a glass substrate having a large size. This makes it possible to manufacture a large-sized display device. In addition, larger substrates allow more display devices to be produced from a single substrate, Production costs can be reduced.

[0167] In order to increase the flexibility of the display device 100, a flexible substrate (flexible substrate) is used as the substrate. ), lamination films, base films, etc. may also be used.

[0168] Examples of materials for the flexible substrate, lamination film, and base film include polyethylene. Polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN) Resin, polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate Resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, Polyamide resins (nylon, aramid, etc.), polysiloxane resins, cycloolefin resins, Polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, Polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) Resin, ABS resin, cellulose nanofiber, etc. can be used.

[0169] By using the above-mentioned materials for the substrate, a lightweight display device can be provided. By using the above-mentioned material for the substrate, a display device that is resistant to impact can be provided. In addition, by using the above-mentioned material for the substrate, it is possible to provide a display device that is less susceptible to damage. can be done.

[0170] The flexible substrate used is preferably one having a lower linear expansion coefficient since deformation due to the environment is suppressed. The flexible substrate used for the substrate has a linear expansion coefficient of, for example, 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 In particular, aramid is a material with a wire Its low expansion coefficient makes it suitable for use as a flexible substrate.

[0171] [Conductive layer] In addition to the gate, source and drain of the transistor, various wiring and Conductive materials that can be used for the conductive layers such as electrodes include aluminum, chromium, Copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium Hf, vanadium (V), niobium (Nb), manganese, magnesium, zirconium A metal element selected from aluminum, beryllium, etc., an alloy containing the above-mentioned metal element, or The above-mentioned metal elements can be combined to form an alloy. Semiconductors, such as polycrystalline silicon containing silicon, and silicides, such as nickel silicide The method for forming the conductive material is not particularly limited, and may be a deposition method, a CVD method, a sputtering method, or the like. Various methods such as a deposition method and a spin coating method can be used.

[0172] Examples of conductive materials that can be used for the conductive layer include indium tin oxide and tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Conductive materials containing oxygen, such as indium tin oxide doped with silicon oxide, are used. In addition, nitrides containing nitrogen such as titanium nitride, tantalum nitride, and tungsten nitride can be used. Conductive materials containing oxygen and conductive materials containing nitrogen can also be used. Alternatively, a laminated structure may be formed by appropriately combining the materials containing the above-mentioned metal elements.

[0173] The conductive material that can be used for the conductive layer may have a single layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum layer containing silicon, a titanium layer on an aluminum layer, A two-layer structure in which a titanium layer is laminated on a titanium nitride layer, a two-layer structure in which a titanium layer is laminated on a titanium nitride layer, Two-layer structure with a tungsten layer laminated, two-layer structure with a tungsten layer laminated on a tantalum nitride layer The structure is a titanium layer, an aluminum layer on top of the titanium layer, and a titanium layer on top of that. In addition, titanium, tantalum, tungsten, etc. are used as conductive materials. One or more elements selected from tenn, molybdenum, chromium, neodymium, and scandium Alternatively, an aluminum alloy containing such a material may be used.

[0174] [Insulation layer] Each insulating layer is made of aluminum nitride, aluminum oxide, aluminum nitride oxide, or aluminum oxide nitride. Aluminum, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, oxide Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate Materials selected from the group consisting of oxides, nitrides, etc. are used in a single layer or in a laminated form. A mixture of a plurality of materials selected from the group consisting of a nitride material, an oxide-nitride material, and a nitride oxide material may be used. .

[0175] In this specification, the term "nitride oxide" refers to a compound that contains more nitrogen than oxygen. In addition, oxynitrides refer to compounds that contain more oxygen than nitrogen. The content of is, for example, measured by Rutherford Backscattering (RBS) spectroscopy. Measurements can be made using techniques such as kScattering Spectrometry. .

[0176] In particular, the insulating layer 272 and the insulating layer 229 are formed using an insulating material that is difficult for impurities to permeate. For example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, etc. minium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, A single layer of insulating material containing zirconium, lanthanum, neodymium, hafnium or tantalum An example of an insulating material that is difficult for impurities to penetrate is oxidized aluminum. Aluminum, aluminum nitride, aluminum oxide nitride, aluminum oxide nitride, gas oxide Sodium oxide, Germanium oxide, Yttrium oxide, Zirconium oxide, Lanthanum oxide, Examples of the oxide include neodymium, hafnium oxide, tantalum oxide, and silicon nitride.

[0177] By using an insulating material that is difficult for impurities to penetrate for the insulating layer 272, impurities from the substrate 271 side are prevented from being The diffusion of impurities can be suppressed, and the reliability of the transistor can be improved. By using an insulating material that is difficult for objects to penetrate, the diffusion of impurities from above the insulating layer 229 is prevented. This suppresses diffusion and improves the reliability of the transistor.

[0178] In addition, an insulating layer that can function as a planarizing layer may be used as the insulating layer. Examples of insulating layers that can be used include polyimide, acrylic resin, benzocyclobutene resin, and polyamide. Organic materials having heat resistance, such as amide and epoxy resins, can be used. In addition to the materials, low-k materials, siloxane resins, and PSG (phosphor glass) are also available. , BPSG (borophosphorus glass), etc. can be used. A plurality of insulating layers may be laminated.

[0179] The siloxane resin is a Si-O compound formed using a material containing siloxane as a starting material. The siloxane resin corresponds to a resin containing -Si bonds. Alternatively, the organic group may have a fluoro group. It's fine if you're there.

[0180] In addition, a CMP process may be performed on the surface of an insulating layer or the like. This reduces the unevenness of the sample surface and improves the coverage of the insulating and conductive layers that will be formed later. do.

[0181] [Semiconductor layer] The semiconductor material used for the semiconductor layer of the transistor is an amorphous semiconductor, a crystalline semiconductor, or a Conductors (microcrystalline semiconductors, polycrystalline semiconductors, single crystal semiconductors, or semiconductors with partially crystalline regions) Either the body or the

[0182] For example, silicon and germanium are used as semiconductor materials for the semiconductor layer of a transistor. Also usable are silicon carbide, gallium arsenide, metal oxides, nitrides, etc. Compound semiconductors such as semiconductors containing fluorine or organic semiconductors can be used.

[0183] For example, amorphous silicon (amorphous silicon) is used as a semiconductor material for transistors. In particular, amorphous silicon is excellent for mass production and can be used for large-area substrates. Generally, the amorphous silicon used in transistors is hydrogenated. For this reason, amorphous silicon that contains a lot of hydrogen is called "hydrogenated amorphous silicon." Amorphous silicon is also called polycrystalline silicon. Since it can be formed at a lower temperature than silicon, the maximum temperature during the fabrication process can be reduced. Therefore, materials with low heat resistance can be used for the substrate, conductive layer, insulating layer, and the like.

[0184] In addition, the semiconductor materials used for transistors include microcrystalline silicon, polycrystalline silicon, and single crystal silicon. Silicon having crystallinity, such as crystalline silicon, can also be used. In particular, polycrystalline silicon It can be formed at a lower temperature than single crystal silicon and has a higher electrical conductivity than amorphous silicon. It has high field effect mobility and high reliability.

[0185] In addition, an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor material for the transistor. Typically, an oxide semiconductor containing indium can be used. Oxide semiconductors have higher field-effect mobility and higher reliability than amorphous silicon. In addition, oxide semiconductors are easy to mass-produce and can be easily applied to large-area substrates. It is.

[0186] In addition, oxide semiconductors, a type of metal oxide, have a wider band gap than silicon. Since the carrier density is low, it is preferable to use it for the semiconductor layer of a transistor. When an oxide semiconductor is used for the semiconductor layer, the source and drain of the transistor in the off state This is preferable because it can reduce the current flowing between the electrodes.

[0187] Oxide semiconductors, a type of metal oxide, have an energy gap of 2 eV or more. It is preferable that the potential is 2.5 eV or more, more preferable that the potential is 3 eV or more. In this way, by using an oxide semiconductor with a wide energy gap, The off-current of the transistor can be reduced.

[0188] The oxide semiconductor, which is a type of metal oxide, is, for example, at least indium, zinc, and M( Aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum In-M-Zn oxide containing metals such as cerium, tin, neodymium or hafnium In addition, a transistor using the oxide semiconductor is preferably formed using the material shown in FIG. It is preferable to include a stabilizer therewith to reduce variations in the electrical properties of the stomach.

[0189] The stabilizer includes the metals listed under M above, such as gallium, tin, hafnium, etc. Other stabilizers include tungsten, aluminum, or zirconium. The lanthanides are lanthanum, cerium, praseodymium, neodymium, samarium, and yttrium. Uropium, gadolinium, terbium, dysprosium, holmium, erbium, Examples include tungsten, ytterbium, and lutetium.

[0190] Examples of metal oxides constituting the semiconductor layer include In-Ga-Zn oxides and In-Al -Zn oxide, In-Sn-Zn oxide, In-Hf-Zn oxide, In-La- Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Z n-type oxides, In-Sm-Zn-type oxides, In-Eu-Zn-type oxides, In-Gd-Zn In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide Oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide oxides, In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, In-Hf-Ga -Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide and In-Hf-Al-Zn oxide can be used. do.

[0191] In this case, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as main components. It means oxide, and the ratio of In, Ga, and Zn does not matter. Also, In, Ga, and Zn Metal elements other than those may be included.

[0192] Regarding the metal oxide that can be used for the semiconductor layer of the transistor, The details will be explained in the form.

[0193] [How each layer is formed] Insulating layers, semiconductor layers, and conductive layers for forming electrodes and wiring are formed by sputtering, chemical Chemical Vapor Deposition (CVD) method, vacuum evaporation deposition method, pulsed laser deposition (PLD) method , atomic layer deposition (ALD) method, etc. The CVD method can be plasma enhanced chemical vapor deposition (PECVD). Alternatively, a thermal CVD method may be used. An example of the thermal CVD method is metal organic chemical vapor deposition (MOCVD). Metal Organic CVD method may also be used.

[0194] In addition, the insulating layer, semiconductor layer, conductive layer for forming electrodes and wiring, etc., which constitute the display device, , spin coat, dip, spray coating, inkjet, dispense, screen Printing, offset printing, slit coating, roll coating, curtain coating, knife coating It may be formed by the above method.

[0195] The PECVD method can produce high-quality films at relatively low temperatures. When a deposition method that does not use plasma, such as thermal CVD, is used, damage is caused to the deposition surface. For example, wiring, electrodes, and elements (transistors, capacitors, etc.) included in semiconductor devices Some elements (such as a photodiode) may become charged up by receiving electric charge from the plasma. At this time, the accumulated charge can destroy the wiring, electrodes, elements, etc., contained in the semiconductor device. On the other hand, in the case of a film formation method that does not use plasma, such plasma damage may occur. Since no defects occur, the yield of the semiconductor device can be increased. Since no Zuma damage occurs, a film with few defects can be obtained.

[0196] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is not easily affected by the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of films with high aspect ratios. However, the ALD method has a relatively low deposition rate. Because the deposition rate is slow, it can be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this is preferable.

[0197] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0198] When processing the layers (thin films) that make up the display device, photolithography and other methods are used. Alternatively, an island-shaped layer may be formed by a film formation method using a shielding mask. Alternatively, layers can be added by nanoimprinting, sandblasting, lift-off, etc. In the photolithography method, a resist mask is applied to the layer (thin film) to be processed. A resist mask is formed, and a part of the layer (thin film) is selectively removed using the resist mask as a mask. a method in which a photosensitive layer is formed and then the resist mask is removed; and a method of processing the layer into a desired shape by applying light and developing.

[0199] When light is used in the photolithography method, the light used for exposure is, for example, i-line (wavelength 3 65nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these In addition, ultraviolet light, KrF laser light, or ArF laser light can be used. Also, exposure may be performed by immersion exposure technology. The light used is extreme ultraviolet (EUV) Alternatively, an electron beam may be used in place of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams enable extremely fine processing. It is preferable to perform exposure by scanning a beam such as an electron beam. No photomask is required.

[0200] There are several methods for removing (etching) layers (thin films): dry etching, wet etching, and A combination of these etching methods can also be used. It may also be used.

[0201] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0202] (Embodiment 4) In this embodiment, a metal oxide that can be used for a semiconductor layer of a transistor will be described. Reveal.

[0203] <Metal oxide composition> In this section, a semiconductor device such as a transistor disclosed in one embodiment of the present invention will be described. CAC-OS (Cloud-Aligned Computing-Operated System), which is one of the metal oxides that can be used osite-Oxide Semiconductor, or CAC (Cloud- The composition of Aligned Composite (metal oxide) is explained. do.

[0204] In this specification, CAC and CAAC (c-axis aligned c In this case, CAC is a function or a part of the composition of the material. represents an example, and CAAC represents an example of the structure.

[0205] CAC-OS or CAC-metal oxide is a material that has the function of electrical conductivity. A part of the material has an insulating function, and the whole material has a semiconductor function. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a material, the function of conductivity is to allow the flow of electrons (or holes) that serve as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the functions of the two work in a complementary manner, the switching function (On / Off) The function of allowing the CAC-OS or CAC-metal oxide to In CAC-OS or CAC-metal oxide, the respective functions are By separating the two, the functions of both can be maximized.

[0206] Therefore, CAC-OS or CAC-metal oxide is a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a gap in the material. In addition, the conductive regions are observed as connected clouds with blurred edges. This may be the case.

[0207] In addition, in the CAC-OS or CAC-metal oxide, the conductive region and the insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be present in the material:

[0208] In addition, CAC-OS or CAC-metal oxide has different band gaps. For example, CAC-OS or CAC-metal oxi de is a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In the case of this configuration, when a carrier flows, In the narrow gap component, carriers mainly flow. The component having a narrow gap acts complementary to the component having a wide gap. Carriers also flow to the wide gap component in conjunction with the component with a large gap. AC-OS or CAC-metal oxide is placed in the channel formation region of the transistor. When used, the transistor has a high current driving force in the on-state, i.e., a large on-current. And high field effect mobility can be obtained.

[0209] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called a composite matrix.

[0210] <Metal oxide structure> In this section, a semiconductor device such as a transistor disclosed in one embodiment of the present invention will be described. This paper explains the structure of metal oxides that can be used.

[0211] The metal oxides include metal oxides made of single crystal materials, metal oxides made of non-single crystal materials, and Single crystal materials have a single crystal structure, while non-single crystal materials have an amorphous structure. , microcrystalline, or polycrystalline structure.

[0212] Semi-crystalline materials are also one type of non-single crystal material. Semicrystalline materials are materials that have both a single crystal structure and non-crystalline structures. It has an intermediate structure between the crystalline structure and the amorphous structure.

[0213] A single crystal of a metal oxide is a polyhedron of oxygen with a metal atom at the center, arranged in a specific order. Specifically, the InGaZnO4 single crystal has an In atom at the center. The oxygen octahedron and the oxygen trigonal bipyramid with Ga or Zn at the center are arranged in a specific order. The molecules are linked together in a layered crystal structure.

[0214] On the other hand, semi-crystalline materials have multiple oxygen polyhedra with a metal atom in the center, Semicrystalline materials have a structure in which the crystals are connected to each other without any particular regularity. The polyhedrons in the single crystal structure are significantly broken, and these are polyhedra that are not observed in single crystals. However, some semi-crystalline materials have polyhedrons that are characteristic of single crystal structures, and There may also be regions that are connected with regularity.

[0215] Semicrystalline materials are made up of polyhedrons that are interconnected without any particular regularity, resulting in so-called non-crystalline structures. The structure is stable compared to amorphous materials.

[0216] For example, when the metal oxide is an oxide semiconductor, a single crystal oxide semiconductor and other non-crystalline oxide semiconductors are used. As a non-single-crystal oxide semiconductor, for example, CAA C-OS(c-axis aligned crystalline oxide se miconductor, polycrystalline oxide semiconductor, nc-OS (nanocrystal line oxide semiconductor, pseudo-amorphous oxide semiconductor (a- like OS:amorphous-like oxide semiconductor or), and amorphous oxide semiconductors.

[0217] For example, the semi-crystalline oxide semiconductor has a CAAC structure and a CAC configuration ( Hereinafter, there is an oxide semiconductor that is a CAAC / CAC.

[0218] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The oxide semiconductor has a CAAC structure with distortion. In the region where the crystals are connected, there are a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement, This refers to the point where the orientation of the lattice array changes between

[0219] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may be non-regular hexagons. In addition, the distortion may have a lattice arrangement such as a pentagon or a heptagon. In addition, in the CAAC-OS, clear grain boundaries (grain boundaries) are not observed even in the vicinity of the strain. In other words, the grain boundaries are not observed due to the distortion of the lattice arrangement. This is because the CAAC-OS has a high lattice constant in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms changes due to the substitution of metal elements. This is believed to be because distortion can be tolerated by, for example, converting the signal into a signal having a high resolution.

[0220] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter, the In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are stacked. Indium and element M tend to have a layered structure. It is possible, and when part of the element M in the (M,Zn) layer is replaced with indium, (In,M, In addition, when part of the indium in the In layer is replaced with element M, , (In,M) layer.

[0221] CAAC-OS is a highly crystalline oxide semiconductor. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries is unlikely to occur. In addition, the crystallinity of oxide semiconductors can be degraded by the inclusion of impurities or the generation of defects. Therefore, CAAC-OS is an oxide with few impurities and defects (such as oxygen vacancies). It can be said to be a semiconductor. Therefore, the physical properties of CAAC-OS are stable. AC-OS is heat resistant and highly reliable.

[0222] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). It is an oxide semiconductor with a periodic atomic arrangement in the region of 100 nm or less. In addition, the nc-OS does not show any regularity in the crystal orientation between different nanocrystals. Therefore, nc-OS is not a-lik e In some cases, it may be difficult to distinguish from OS or amorphous oxide semiconductors.

[0223] The a-like OS is an oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has porosity or low density areas. The OS has a lower crystallinity compared to the nc-OS and CAAC-OS.

[0224] Oxide semiconductors have a variety of structures, each of which has different characteristics. Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and nc The compound may have two or more of -OS, CAAC-OS, and CAAC-OS.

[0225] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0226] (Embodiment 5) In this embodiment mode, a transistor that can be used for the display device or the like shown in the above embodiment mode will be described. An example of the star will be described with reference to the drawings.

[0227] <Transistor configuration example 1> First, as an example of the structure of a transistor, a transistor 3200a will be described with reference to FIG. 13A is a top view of a transistor 3200a. FIG. 13B is a cross-sectional view taken along the dashed line X1-X2 in FIG. FIG. 13C is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. In FIG. 13(A), in order to avoid complication, Some of the components of the transistor 3200a (such as an insulating layer that functions as a gate insulating layer) are omitted. In the following description, the direction of the dashed dotted line X1-X2 is the channel length direction, The direction of the dashed line Y1-Y2 may be referred to as the channel width direction. In the top view, some of the components are omitted as in FIG. 13 and in the subsequent drawings. may be indicated.

[0228] The transistor 3200a includes a conductive layer 3221 on an insulating layer 3224, and an insulating layer 3224 and An insulating layer 3211 on the conductive layer 3221, a metal oxide layer 3231 on the insulating layer 3211, and a gold A conductive layer 3222a on the metal oxide layer 3231 and a conductive layer 3222 on the metal oxide layer 3231 b, and the insulating layer 32 on the metal oxide layer 3231, the conductive layer 3222a, and the conductive layer 3222b. 12, a conductive layer 3223 on the insulating layer 3212, and a and an insulating layer 3213.

[0229] The insulating layer 3211 and the insulating layer 3212 each have an opening 3235. is electrically connected to the conductive layer 3221 through the opening 3235.

[0230] Here, the insulating layer 3211 functions as a first gate insulating layer of the transistor 3200a. The insulating layer 3212 serves as a second gate insulating layer of the transistor 3200a. The insulating layer 3213 functions as a protective insulating layer for the transistor 3200a. In the transistor 3200a, the conductive layer 3221 functions as a first gate. The conductive layer 3222a functions as either a source or a drain, and The layer 3222b functions as the other of the source and drain. In the gate 3200a, the conductive layer 3223 functions as a second gate.

[0231] The transistor 3200a is a so-called channel etch type transistor. It is a rugate structure.

[0232] The transistor 3200a may not include the conductive layer 3223. In this case, the transistor 3200a is a so-called channel etch type transistor, This is a Tom Gate structure.

[0233] As shown in FIG. 13B and FIG. 13C, the metal oxide layer 3231 is a conductive layer 3221 and a conductive It is located opposite the layer 3223 and is sandwiched between two conductive layers having the function of a gate. The length of the conductive layer 3223 in the channel length direction and the length of the conductive layer 3223 in the channel width direction is the length of the metal oxide layer 3231 in the channel length direction and the The metal oxide layer 3231 is formed on the insulating layer 3212. It is covered with a conductive layer 3223 through which the insulating layer 3222 is formed.

[0234] In other words, the conductive layer 3221 and the conductive layer 3223 are the insulating layer 3211 and the insulating layer 3212. 3231 and 3232. The metal oxide layer 3231 is connected to the opening 3235 provided in the also has an area located on the outside.

[0235] With such a structure, the metal oxide layer 323 included in the transistor 3200a 1 can be electrically surrounded by the electric field of the conductive layer 3221 and the conductive layer 3223. As in the transistor 3200a, the electric field of the first gate and the second gate causes a channel The device structure of the transistor that electrically surrounds the metal oxide layer in which the hole formation region is formed is called S This can be called a surrounded channel (S-channel) structure.

[0236] Since the transistor 3200a has an S-channel structure, the function of the first gate The conductive layer 3221 having a metal oxide Since the voltage can be applied to the layer 3231, the current driving capability of the transistor 3200a is improved. This makes it possible to obtain high on-current characteristics. Therefore, it is possible to miniaturize the transistor 3200a. 3200a shows a structure in which a metal oxide layer 3231 is formed on a conductive layer 3221 having a function of a first gate and Since the transistor has a structure surrounded by the conductive layer 3223 having the function of the second gate, This can increase the mechanical strength of the transistor 3200a.

[0237] For example, the metal oxide layer 3231 may be made of In and M (M is gallium, aluminum, silicon, etc.). Boron, Yttrium, Tin, Copper, Vanadium, Beryllium, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium It is preferable that the alloy contains at least one of aluminum, tantalum, tungsten, or magnesium, and Zn.

[0238] In addition, the metal oxide layer 3231 has a region in which the atomic ratio of In is greater than the atomic ratio of M. As an example, the ratio of the number of atoms of In, M, and Zn in the metal oxide layer 3231 is preferably It is preferable that In:M:Zn=4:2:3 or so. Here, "nearby" means that In is 4. , M is 1.5 or more and 2.5 or less, and Zn is 2 or more and 4 or less. Or, metal oxide The atomic ratio of In, M, and Zn in the semiconductor layer 3231 is set to about In:M:Zn=5:1:6. This would be preferable.

[0239] The metal oxide layer 3231 is CAC-OS or CAC-metal oxide. It is preferable that the metal oxide layer 3231 has an area in which the atomic ratio of In is greater than the atomic ratio of M. The CAC-OS or CAC-metal oxide has a ternary structure. This can increase the field effect mobility of the transistor 3200a.

[0240] In addition, the transistor 3200a, which has an s-channel structure, has a high field effect mobility. Since the driving capability is high, the transistor 3200a is connected to a driving circuit, typically a gate signal By using this in the gate driver that generates the MOS transistors, a display device with a narrow frame width (also called a narrow frame) can be provided. In addition, the transistor 3200a can be provided as a source driver of the display device. (especially, the demultiplexer connected to the output terminal of the shift register of the source driver) By using the display device in a display device having a small number of wirings, can be done.

[0241] In addition, since the transistors 3200a are each a transistor having a channel etch structure, In comparison with transistors using low-temperature polysilicon, the number of manufacturing steps is smaller. The transistor 3200a uses a metal oxide layer for the channel, so it does not require low-temperature polysilicon. Unlike the transistors that use this method, the laser crystallization process is not required. Even in the case of a display device using a substrate, it is possible to reduce the manufacturing cost. Tora Hi-Vision ("4K resolution", "4K2K", "4K"), Super Hi-Vision ("8K resolution", "8K4K", "8K") and large display devices In the device, a transistor with high field effect mobility such as the transistor 3200a is driven. By using it in the circuit and display, writing can be done in a short time, reducing display defects. This is possible and preferable.

[0242] The insulating layer 3211 and the insulating layer 3212 in contact with the metal oxide layer 3231 are made of oxide insulating material. It is preferable that the film is a film, and the film has a region containing oxygen in excess of the stoichiometric composition (excess oxygen region). In other words, the insulating layer 3211 and the insulating layer 3212 preferably have a The insulating layer 3211 and the insulating layer 3212 are insulating films capable of releasing oxygen. To provide the excess oxygen region, for example, the insulating layer 3211 and the insulating layer 321 are heated in an oxygen atmosphere. 2 is formed, or the insulating layer 3211 and the insulating layer 3212 after film formation are heated in an oxygen atmosphere. Just process it.

[0243] The metal oxide layer 3231 can be made of an oxide semiconductor, which is a type of metal oxide. Cut.

[0244] When the metal oxide layer 3231 is an In-M-Zn oxide, the In-M-Zn oxide is deposited. The atomic ratio of the metal elements in the sputtering target used for this purpose must satisfy the following relationship: In>M The atomic ratio of the metal elements in such a sputtering target is preferably In: M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1 , In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1 :8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc.

[0245] In addition, when the metal oxide layer 3231 is formed of In-M-Zn oxide, sputtering As the target, it is preferable to use a target containing polycrystalline In-M-Zn oxide. By using a target containing polycrystalline In-M-Zn oxide, it is possible to obtain a crystalline It is easy to form the metal oxide layer 3231. The atomic ratio is the plus or minus of the atomic ratio of the metal elements contained in the sputtering target. For example, the sputtering target used for the metal oxide layer 3231 When the composition of the chip is In:Ga:Zn=4:2:4.1 [atomic ratio], the metal oxide film formed is The composition of the compound layer 3231 is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. There is.

[0246] The metal oxide layer 3231 has an energy gap of 2 eV or more, preferably 2.5 e V or more. In this way, by using oxide semiconductors with a wide energy gap, The off-current of the transistor can be reduced.

[0247] In addition, it is preferable that the metal oxide layer 3231 has a non-single crystal structure. For example, CAAC (C Axis Aligned Crystalline), polycrystalline structure , microcrystalline, or amorphous structures. In non-single crystal structures, the amorphous structure is the most defect-free. The defect level density is high in CAAC, while the defect level density is the lowest in CAAC.

[0248] The metal oxide layer 3231 is a metal oxide film having a low impurity concentration and a low defect level density. By using this, a transistor having excellent electrical characteristics can be manufactured. Here, the low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic The impurities in the metal oxide film are typically In the present specification, the term "reducing water and hydrogen in a metal oxide film" refers to reducing water and hydrogen. The removal or elimination of the metal oxide film may be referred to as dehydration or dehydrogenation. The addition of oxygen to an oxide insulating film may be referred to as oxygen addition. The state in which there is more oxygen than the stoichiometric composition is sometimes referred to as an overoxygenated state.

[0249] High-purity intrinsic or substantially high-purity intrinsic metal oxide films have fewer carrier sources and therefore Therefore, the carrier density can be reduced. The transistor in which this is formed has electrical characteristics in which the threshold voltage is negative (normally on In addition, high-purity genuine or substantially high-purity genuine gold is rarely used. Metal oxide films have a low defect state density, and therefore may also have a low trap state density. Metal oxide films that are highly intrinsic or substantially highly intrinsic have significantly smaller off-state currents. , with a channel width of 1×10 6 Even if the device has a channel length L of 10 μm, the source electrode When the voltage between the drain electrode and the gate electrode (drain voltage) is in the range of 1V to 10V, the off-state current is , below the measurement limit of the semiconductor parameter analyzer, i.e., 1 × 10 -13 The special feature of A or below You can get sexuality.

[0250] The insulating layer 3213 contains either hydrogen or nitrogen or both. The insulating layer 3213 contains nitrogen and silicon. The insulating layer 3213 contains oxygen, hydrogen, water, and aluminum. It has the function of blocking potassium metals, alkaline earth metals, etc. By this, the diffusion of oxygen from the metal oxide layer 3231 to the outside and the diffusion of oxygen contained in the insulating layer 3212 are prevented. The diffusion of oxygen to the outside and the penetration of hydrogen, water, etc. into the metal oxide layer 3231 from the outside are prevented. It can be prevented.

[0251] The insulating layer 3213 may be, for example, a nitride insulating film. Examples include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. etc.

[0252] <Transistor configuration example 2> Next, as an example of the structure of a transistor, a transistor 3200b will be described with reference to FIG. 14A is a top view of a transistor 3200b. FIG. 14B is a cross-sectional view taken along the dashed line X1-X2 in FIG. FIG. 14C is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. This corresponds to a cross-sectional view.

[0253] The transistor 3200b includes a metal oxide layer 3231, a conductive layer 3222a, and a conductive layer 3222. The transistor 3200 differs from the transistor 3200a in that the insulating layer 3212 has a stacked structure. do.

[0254] The insulating layer 3212 is formed on the metal oxide layer 3231, the conductive layer 3222a, and the conductive layer 3222b. The insulating layer 3212a is a first insulating layer 3212b, and the insulating layer 3212b is a second insulating layer 3212b. 12 has a function of supplying oxygen to the metal oxide layer 3231. That is, the insulating layer 321 The insulating layer 3212a is an insulating layer that can transmit oxygen. The insulating layer 3212a is formed by removing the metal when the insulating layer 3212b is formed later. It also functions as a film for reducing damage to the oxide layer 3231 .

[0255] The insulating layer 3212a has a thickness of 5 nm to 150 nm, preferably 5 nm to 500 nm. Silicon oxide, silicon oxynitride, etc. having a thickness of 0 nm or less can be used.

[0256] In addition, it is preferable that the insulating layer 3212a has a small amount of defects. Therefore, the spin density of the signal at g=2.001 originating from the silicon dangling bond is Degree is 3 x 10 17 spins / cm 3 This is because the insulating layer 321 If the density of defects in 2a is high, oxygen will bond to the defects, and the insulating layer 3212a will This reduces the oxygen permeability.

[0257] In addition, in the insulating layer 3212a, all of the oxygen that has entered the insulating layer 3212a from the outside is Some oxygen does not move outside the insulating layer 3212a and remains in the insulating layer 3212a. As oxygen enters the insulating layer 3212a, the oxygen contained in the insulating layer 3212a The migration to the outside may also cause migration of oxygen in the insulating layer 3212a. When an oxide insulating layer capable of transmitting oxygen is formed as the layer 3212a, the insulating layer 32 The oxygen desorbed from the insulating layer 3212b provided on the insulating layer 3212a is absorbed through the insulating layer 3212a. The metal oxide layer 3231 can be transported by the metal oxide.

[0258] The insulating layer 3212a is formed using an oxide insulating layer having a low density of states due to nitrogen oxide. The density of states caused by the nitrogen oxides can be determined by the valence of the metal oxide film. The energy of the upper edge of the electronic band (Ev_os) and the energy of the lower edge of the conduction band of the metal oxide film ( The oxide insulating layer may be formed between the SiO_O_2 and the SiC_O_4. Silicon oxynitride film with low emission or aluminum oxynitride film with low emission of nitrogen oxides A film such as a gypsum film can be used.

[0259] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectrometry (TDS). In Thermal Desorption Spectroscopy, nitrogen This is a film that releases more ammonia than oxide, and typically releases ammonia is 1×10 18 / cm 3 5×10 or more 19 / cm 3 The following is the release of ammonia. The amount is adjusted so that the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This is the amount released due to heat treatment.

[0260] Nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO2 or NO forms a level in the insulating layer 3212a. The nitrogen oxide is located in the energy gap of the insulating layer 32. When the ions diffuse to the interface between the insulating layer 3212a and the metal oxide layer 3231, the level increases toward the insulating layer 3212a. As a result, the trapped electrons may be trapped in the insulating layer 321. 2a and the metal oxide layer 3231, the threshold voltage of the transistor is increased. This causes the wheel to shift in the negative direction.

[0261] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in a is converted to the ammonia contained in the insulating layer 3212b by the heat treatment. This reacts with the insulating layer 3212a, reducing the amount of nitrogen oxide contained in the insulating layer 3212a. At the interface between layer 3212a and metal oxide layer 3231, electrons are less likely to be trapped.

[0262] By using the oxide insulating layer as the insulating layer 3212a, the threshold voltage of the transistor can be reduced. It is possible to reduce the voltage shift and thus reduce the fluctuation in the electrical characteristics of the transistor. can be done.

[0263] The oxide insulating layer has a nitrogen concentration of 6×10 20 atoms / cm 3 The following is the result.

[0264] PECV using silane and nitrous oxide with a substrate temperature of 220°C to 350°C By forming the oxide insulating layer using the D method, a dense and hard film is formed. It can be achieved.

[0265] The insulating layer 3212b is an oxide insulating layer containing more oxygen than the oxygen required for the stoichiometric composition. When the oxide insulating layer is heated, some of the oxygen is released. The oxide insulating layer has an oxygen release rate of 1.0×10 19 atoms / cm 3 That's all, Preferably 3.0 x 10 20 atoms / cm 3 The above oxygen range is also included. The amount of release is greater when the heat treatment temperature in TDS is 50°C or more and 650°C or less, or when the heat treatment temperature is 50°C or more and 650°C or less. The amount of oxygen released is the total amount in the range of 550°C or less. This is the total amount converted into elementary atoms.

[0266] The insulating layer 3212b has a thickness of 30 nm to 500 nm, preferably 50 nm or less. Silicon oxide, silicon oxynitride, etc., having a thickness of 400 nm or less can be used.

[0267] In addition, it is preferable that the insulating layer 3212b has a small amount of defects. Therefore, the spin density of the signal at g=2.001 originating from the silicon dangling bond is Degree is 1.5 x 10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 It is preferable that the insulating layer 3212b has a thickness of 100 nm or less compared to the insulating layer 3212a. Since it is far from the metal oxide layer 3231, the defect density is at most lower than that of the insulating layer 3212a. good.

[0268] In addition, since the insulating layer 3212 can be made of an insulating layer of the same material, the insulating layer 321 In some cases, the interface between the insulating layer 3212a and the insulating layer 3212b may not be clearly visible. In the diagram, the interface between insulating layer 3212a and insulating layer 3212b is illustrated by a dashed line. In this embodiment, the two-layer structure of the insulating layer 3212a and the insulating layer 3212b is However, the present invention is not limited to this. For example, the insulating layer 3212a may have a single layer structure or a three layer structure. The above laminated structure may also be used.

[0269] In the transistor 3200b, the metal oxide layer 3231 is a metal oxide layer on the insulating layer 3211. a metal oxide layer 3231_1 and a metal oxide layer 3231_2 on the metal oxide layer 3231_1, The metal oxide layer 3231_1 and the metal oxide layer 3231_2 have the same structure. For example, the metal oxide layer 3231_1 and the metal oxide layer 3231_2 have the same elements. It is preferable that the metal oxide layer 3231 independently contains the elements described above.

[0270] In addition, the metal oxide layer 3231_1 and the metal oxide layer 3231_2 are each independently It is preferable to have a region in which the atomic ratio of n is greater than the atomic ratio of M. As an example, The ratio of the number of In, M, and Zn atoms in the metal oxide layer 3231_1 and the metal oxide layer 3231_2 is It is preferable that In:M:Zn=4:2:3 or so. Here, "nearby" means that In is 4. , M is 1.5 or more and 2.5 or less, and Zn is 2 or more and 4 or less. Or, metal oxide The ratio of the number of In, M, and Zn atoms in the metal oxide layer 3231_1 and the metal oxide layer 3231_2 is It is preferable that the ratio of In:M:Zn is about 5:1:6. By making the metal oxide layer 3231 and the metal oxide layer 3231 have approximately the same composition, the same sputtering temperature can be used. Since the target can be used for the formation, the manufacturing cost can be reduced. When using a sputtering target, metal oxide can be continuously performed in a vacuum in the same chamber. Since the metal oxide layer 3231_1 and the metal oxide layer 3231_2 can be formed, Suppresses the incorporation of impurities into the interface between the material layer 3231_1 and the metal oxide layer 3231_2. It is possible.

[0271] Here, the metal oxide layer 3231_1 has a region with lower crystallinity than the metal oxide layer 3231_2. In addition, the metal oxide layer 3231_1 and the metal oxide layer 3231_2 may have a region. The crystallinity of the material can be measured, for example, by X-ray diffraction (XRD). or by using a transmission electron microscope (TEM). The analysis can be performed using a TEM (High Electron Microscope).

[0272] The low-crystallinity region of the metal oxide layer 3231_1 serves as a diffusion path for excess oxygen, and the metal oxide Excess oxygen is diffused into the metal oxide layer 3231_2, which has higher crystallinity than the layer 3231_1. In this way, a laminated structure of metal oxide layers with different crystal structures can be used to achieve low crystallinity. By using the thin region as a diffusion path for excess oxygen, it is possible to provide a highly reliable transistor. can.

[0273] In addition, the metal oxide layer 3231_2 has a region having higher crystallinity than the metal oxide layer 3231_1. By having such a structure, impurities that may be mixed into the metal oxide layer 3231 can be suppressed. In particular, by increasing the crystallinity of the metal oxide layer 3231_2, the conductive layer 3222a and the conductive layer The damage caused when processing the metal oxide layer 3231 can be suppressed. The surface of the metal oxide layer 3231_2 is a conductive layer 3222a and a conductive layer 3222b. b) is exposed to an etchant or etching gas during processing of the metal oxide. When the metal oxide layer 3231_2 has a region with high crystallinity, the metal oxide layer 323 The metal oxide layer 3231_2 has a higher etching resistance than the metal oxide layer 3231_1. It functions as an etching stopper.

[0274] In addition, the metal oxide layer 3231_1 has a region with lower crystallinity than the metal oxide layer 3231_2. By having such a structure, the carrier density may be increased.

[0275] In addition, when the carrier density of the metal oxide layer 3231_1 is increased, the metal oxide layer 3231_ The Fermi level may be relatively high with respect to the conduction band of 1. This results in The lower end of the conduction band of the metal oxide layer 3231_1 becomes lower, and the lower end of the conduction band of the metal oxide layer 3231_1 becomes The energy of the trap level that may be formed in the gate insulating film (the insulating layer 3211 in this example) is When the energy difference becomes large, the gate insulating film This reduces the amount of charge trapped in the transistor, which reduces the variation in the threshold voltage of the transistor. In addition, when the carrier density of the metal oxide layer 3231_1 becomes high, the metal oxide The field effect mobility of the material layer 3231 can be increased.

[0276] In the transistor 3200b, the metal oxide layer 3231 has a two-layer structure. However, the present invention is not limited to this example, and a configuration in which three or more layers are laminated may also be used.

[0277] The conductive layer 3222a of the transistor 3200b includes a conductive layer 3222a_1 and a conductive layer A conductive layer 3222a_2 on the conductive layer 3222a_1 and a conductive layer 3222 on the conductive layer 3222a_2 The conductive layer 3222b of the transistor 3200b has a conductive layer 3222b_1, a conductive layer 3222b_2 on the conductive layer 3222b_1, and a conductive layer 322 and a conductive layer 3222b_3 on 2b_2.

[0278] For example, the conductive layer 3222a_1, the conductive layer 3222b_1, the conductive layer 3222a_3, and the conductive The conductive layer 3222b_3 may be made of titanium, tungsten, tantalum, molybdenum, indium, or the like. It is preferable that the material contains one or more of aluminum, gallium, tin, and zinc. The conductive layer 3222a_2 and the conductive layer 3222b_2 may be made of copper, aluminum, or the like. It is preferable that the conductive material contains one or more selected from the group consisting of zinc and silver.

[0279] More specifically, the conductive layer 3222a_1, the conductive layer 3222b_1, the conductive layer 3222a_3 , and the conductive layer 3222b_3 is made of In-Sn oxide or In-Zn oxide, Copper can be used for 3222a_2 and the conductive layer 3222b_2.

[0280] In addition, the end of the conductive layer 3222a_1 is located outside the end of the conductive layer 3222a_2. The conductive layer 3222a_3 covers the upper surface and side surfaces of the conductive layer 3222a_2. The conductive layer 3222b_1 has an area in contact with the conductive layer 3222a_1. , the conductive layer 3222b_3 has a region located outside the end of the conductive layer 3222b_2. The area covers the upper and side surfaces of the conductive layer 3222b_2 and is in contact with the conductive layer 3222b_1. It has a range.

[0281] With the above structure, the wiring resistance of the conductive layer 3222a and the conductive layer 3222b is reduced, and This is also preferable because it can suppress the diffusion of copper into the metal oxide layer 3231 .

[0282] <Transistor configuration example 3> Next, as an example of the structure of a transistor, a transistor 3200c will be described with reference to FIG. 15A is a top view of a transistor 3200c. FIG. 15(B) is a cross-sectional view taken along the dashed line X1-X2 shown in FIG. FIG. 15C is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. This corresponds to a cross-sectional view.

[0283] The transistor 3200c shown in FIGS. 15(A), (B), and (C) includes a conductive layer 3224 on an insulating layer 3224. 3221, an insulating layer 3211 on the conductive layer 3221, and a metal oxide layer 3 on the insulating layer 3211. 231, an insulating layer 3212 on the metal oxide layer 3231, and a conductive layer 32 on the insulating layer 3212. 23, an insulating layer 3211, a metal oxide layer 3231, and an insulating layer 321 on a conductive layer 3223 The metal oxide layer 3231 has a channel forming portion overlapping with the conductive layer 3223. A region 3231i, a source region 3231s in contact with the insulating layer 3213, and the insulating layer 3213 and a drain region 3231d adjacent thereto.

[0284] The insulating layer 3213 contains nitrogen or hydrogen. 31s and the drain region 3231d are in contact with each other, and thus, nitrogen or Hydrogen is added to the source region 3231s and the drain region 3231d. The drain region 3231d and the drain region 3231s are doped with nitrogen or hydrogen to form a carrier The density increases.

[0285] The transistor 3200c includes an insulating layer 3215 over the insulating layer 3213 and an insulating layer 321 3 and an opening 3236a provided in the insulating layer 3215, A conductive layer 3222a electrically connected to the insulating layer 3213 and the insulating layer 3215 is provided A conductive layer 3236 is electrically connected to the drain region 3231d through the opening 3236b. 22b.

[0286] An oxide insulating film can be used as the insulating layer 3215. For example, a stacked film of an oxide insulating film and a nitride insulating film can be used. 5 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. Examples of the material that may be used include aluminum, hafnium oxide, gallium oxide, and Ga-Zn oxide. The insulating layer 3215 is a film that functions as a barrier film against hydrogen, water, etc. from the outside. is preferred.

[0287] The insulating layer 3211 functions as a first gate insulating film, and the insulating layer 3212 functions as a second gate insulating film. The insulating layer 3213 and the insulating layer 3215 function as a gate insulating film. It functions as a veneer.

[0288] The insulating layer 3212 also has an excess oxygen region. By this, excess oxygen is provided in the channel formation region 3231i of the metal oxide layer 3231. Therefore, oxygen vacancies that may be formed in the channel formation region 3231i can be eliminated. Since the excess oxygen can be used to compensate, a highly reliable semiconductor device can be provided. do.

[0289] In order to supply excess oxygen into the metal oxide layer 3231, Excess oxygen may be supplied to the insulating layer 3211 formed below the insulating layer 32. The excess oxygen contained in the metal oxide layer 3231 is used to form the source region 3231s and the The source region 3231s and the drain region 3231d may also be supplied with the When excess oxygen is supplied to the source region 3231s and the drain region 3231d, 31d resistance may be high.

[0290] On the other hand, the insulating layer 3212 formed above the metal oxide layer 3231 has an excess of oxygen. By forming the semiconductor layer 3231 in this manner, it is possible to selectively supply excess oxygen only to the channel formation region 3231i. Alternatively, the channel forming region 3231i, the source region 3231s, and the drain region 3231s may be formed. After supplying excess oxygen to the drain region 3231d, the source region 3231s and the drain By selectively increasing the carrier density in the region 3231d, the source region 3231s and the This can prevent the resistance of the rain region 3231d from increasing.

[0291] The metal oxide layer 3231 has a source region 3231s and a drain region 3231d. Each of them preferably has an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. Representative elements that form oxygen vacancies or that bond with oxygen vacancies include are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, rare gases, etc. Representative examples of rare gas elements include helium, neon, argon, krypton, and The above oxygen vacancy-forming elements are present in the insulating layer 3213 in one or more. If several are included, the source region 3231s and the drain region 3231 are formed from the insulating layer 3213. d and / or by doping the source region 3231s and the drain region 3232. The dopant is added to the dopant region 3231d.

[0292] When an impurity element is added to an oxide semiconductor film, a metal element in the oxide semiconductor film is bonded to oxygen. Alternatively, an impurity element is added to the oxide semiconductor film. Then, oxygen that has been bonded to a metal element in the oxide semiconductor film is bonded to an impurity element, and the oxygen is converted from the metal element to an impurity element. As a result, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The rear density increases and the conductivity becomes higher.

[0293] The conductive layer 3221 functions as a first gate electrode, and the conductive layer 3223 functions as a second gate electrode. The conductive layer 3222a functions as a gate electrode of the second semiconductor device, and the conductive layer 3222b functions as a source electrode. The conductive layer 3222b functions as a drain electrode.

[0294] As shown in FIG. 15C, the insulating layer 3211 and the insulating layer 3212 have an opening 323. 7 is provided. The conductive layer 3221 is connected to the conductive layer 3223 through the opening 3237. Therefore, the conductive layer 3221 and the conductive layer 3223 are given the same potential. Note that the conductive layer 3221 and the conductive layer 3223 are not provided with the opening 3237, and different Alternatively, the opening 3237 may not be provided, and the conductive layer 3221 may be a light-shielding film. For example, the conductive layer 3221 may be formed of a light-shielding material. This can suppress light from below irradiating the channel formation region 3231i.

[0295] As shown in FIG. 15B and FIG. 15C, the metal oxide layer 3231 serves as a first gate electrode. and a conductive layer 3223 functioning as a second gate electrode. They are positioned opposite each other and are sandwiched between two conductive films that function as gate electrodes.

[0296] In addition, the transistor 3200c is also connected to the transistors 3200a and 3200b. Similarly, it has an S-channel structure. By having such a configuration, transistor 3 The metal oxide layer 3231 included in 200c is covered with a conductive layer 3 functioning as a first gate electrode. The gate electrode 221 and the conductive layer 3223 functioning as the second gate electrode are electrically connected by the electric field. Can be surrounded.

[0297] Since the transistor 3200c has an S-channel structure, the conductive layer 3221 The electric field for inducing a channel through the conductive layer 3223 is effectively applied to the metal oxide layer 32. 31, the current driving capability of the transistor 3200c is improved, and It is possible to obtain a high on-current characteristic. Therefore, it is possible to miniaturize the transistor 3200c. 0c shows that the metal oxide layer 3231 is surrounded by the conductive layer 3221 and the conductive layer 3223. The integrated structure can increase the mechanical strength of the transistor 3200c.

[0298] The transistor 3200c is disposed at a position of the conductive layer 3223 relative to the metal oxide layer 3231. TGSA (Top Gate Self-Al It may also be called an ignition type FET.

[0299] In addition, in the transistor 3200c, a metal oxide The layer 3231 may be configured to have two or more layers stacked.

[0300] In addition, in the transistor 3200c, a portion where the insulating layer 3212 overlaps with the conductive layer 3223 However, the present invention is not limited to this, and the insulating layer 3212 is provided only on the metal oxide layer 32 Alternatively, the conductive layer 3221 may be omitted. can.

[0301] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0302] (Embodiment 6) In this embodiment, a configuration example of a display device using a liquid crystal element and a configuration example of a display device using an EL element are described. A configuration example will be described. In FIG. 16A, a surface provided on a first substrate 4001 A sealant 4005 is provided so as to surround the display unit 101. 005 and is sealed by a second substrate 4006 .

[0303] In FIG. 16A, a scanning line driving circuit 102, a scanning line driving circuit 103, and a signal line driving circuit 10 4 and the signal line driver circuit 105 are integrated on a printed circuit board 4041. The integrated circuit 4042 is made of a single crystal semiconductor or a polycrystalline semiconductor. has been formed.

[0304] The integrated circuit 4042 included in the scanning line driver circuit 102 and the scanning line driver circuit 103 is The signal line driver circuit 104 and the signal line driver circuit 101 have a function of supplying a selection signal. The integrated circuit 4042 included in the LCD panel 105 has a function of supplying image signals to the display portion 101 . The integrated circuit 4042 is manufactured by the TAB (Tape Automated Bonding) method. Therefore, the area different from the area surrounded by the sealant 4005 on the first substrate 4001 is It is implemented in.

[0305] A scanning line driving circuit 102, a scanning line driving circuit 103, a signal line driving circuit 104, and a signal line driving circuit Various signals and potentials are applied to the operating circuit 105 through an FPC4018 (FPC: Flexible Printed Circuit) The digital input is supplied from the BLE printed circuit.

[0306] The method of connecting the integrated circuit 4042 is not particularly limited, and may be wire bonding. COG (Chip On Glass) method, TCP (Tape Carrier Package method, COF (Chip On Film) method, etc. can be used. .

[0307] FIG. 16B shows an integrated circuit included in the signal line driver circuit 104 and the signal line driver circuit 105. 4042 is mounted by the COG method. A part or the whole of the driving circuit is formed integrally on the same substrate as the display unit 101 using a transistor. A system on panel can be formed by using the above-mentioned techniques.

[0308] In FIG. 16B, the scanning line driver circuit 102 and the scanning line driver circuit 103 are disposed in a display unit 101. In this example, the driving circuit is formed on the same substrate as the pixel circuit in the display unit 101. By forming the die, the number of parts can be reduced, and the productivity can be improved. do.

[0309] In FIG. 16B, the display portion 101 and the scanning line driver 4002 are provided on the first substrate 4001. A sealant 4005 is provided so as to surround the driving circuit 102 and the scanning line driving circuit 103. In addition, the display unit 101, the scanning line driving circuit 102, and the scanning line driving circuit 103 are A second substrate 4006 is provided on the display unit 101. 2, and the scanning line driver circuit 103 are formed by a first substrate 4001, a sealant 4005, and a second substrate 4002. The display element is sealed with a plate 4006 .

[0310] In FIG. 16B, the signal line driver circuit 104 and the signal line driver circuit 105 are formed separately. 10, the scanning lens 4001 is mounted on the first substrate 4001, but the present invention is not limited to this configuration. A signal line driver circuit may be formed separately and mounted, or a part of a signal line driver circuit or a scanning line driver circuit may be mounted. A part of the path may be formed separately and implemented.

[0311] The display device includes a panel in which a display element is sealed, and a controller for the panel. The term "IC" may also refer to a module in which an IC or the like including the above is mounted.

[0312] The display portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment may be used as the transistor. can be done.

[0313] The transistors in the peripheral driver circuits and the transistors in the pixel circuits in the display area are the same. The transistors in the peripheral driver circuit may have the same structure or a different structure. may all have the same structure, or two or more types of structures may be used in combination. Similarly, the transistors in the pixel circuit may all have the same structure, or may have two or more types. The above structures may be used in combination.

[0314] 17(A) and 17(B) show the structure of the region indicated by the dashed line N1-N2 in FIG. 16(B). The display device shown in FIG. 17(A) and FIG. 17(B) has an electrode 4015. The electrode 4015 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive layer 4019. 17(A) and 17(B), the electrode 4015 is Wiring is provided in openings formed in the insulating layers 4112, 4111, and 4110. It is electrically connected to 4014.

[0315] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The conductive layer is made of the same material.

[0316] The display portion 101 and the scanning line driver circuit 102 provided on the first substrate 4001 are In FIG. 17(A) and FIG. 17(B), the display unit 101 includes a A transistor 4010 included in the scanning line driver circuit 102 and a transistor 40 11 is illustrated. In addition, in FIG. 17(A) and FIG. 17(B), the transistor 401 0 and a bottom-gate transistor is illustrated as an example of the transistor 4011.

[0317] In FIG. 17(A) and FIG. 17(B), a transistor 4010 and a transistor 401 17B, ​​an insulating layer 4112 is provided on the insulating layer 4112. A partition wall 4510 is formed.

[0318] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 4111. The semiconductor device has an electrode 4017 formed thereon. The electrode 4017 functions as a back gate electrode. It is possible.

[0319] The transistors 4010 and 4011 are the same as those described in the above embodiment modes. A star can be used.

[0320] 17A and 17B further includes a capacitor 4020. The display device shown in FIG. The capacitor 4020 has an electrode 4 formed in the same process as the gate electrode of the transistor 4010. 021, and electrodes formed in the same process as the source electrode and the drain electrode. The electrodes overlap with each other with an insulating layer 4103 interposed therebetween.

[0321] In general, the capacitance of a capacitor provided in a pixel portion of a display device is determined by the capacitance of a transistor disposed in the pixel portion. The capacitance is set so that the charge can be held for a predetermined period of time, taking into consideration the leakage current of the capacitor. The capacitance of the capacitance element may be set in consideration of the off-state current of the transistor and the like.

[0322] The transistor 4010 provided in the display portion 101 is electrically connected to a display element. FIG. 17(A) is an example of a liquid crystal display device using a liquid crystal element as a display element. In the liquid crystal display device, a liquid crystal element 4013 serving as a display element includes a first electrode layer 4030 and a second electrode layer 40 31, and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between the alignment films 31 and 32. The second electrode layer 4031 is provided with an insulating layer 4032 and an insulating layer 4033 which function as a A first electrode layer 4030 and a second electrode layer 4031 are provided on the second substrate 4006 side. Overlapping via layer 4008.

[0323] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer. and the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0324] If necessary, a black matrix (light-shielding layer), a colored layer (color filter), a polarizing Optical members (optical substrates) such as a member, a phase difference member, and an anti-reflection member may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Crites, sidelights, etc. may also be used.

[0325] In the display device shown in FIG. 17A, a light-shielding layer is provided between the substrate 4006 and the second electrode layer 4031. 4132, a coloring layer 4131, and an insulating layer 4133 are provided.

[0326] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, etc. Examples of the material for the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film of an inorganic material such as a metal. In addition, a laminated film of a film containing the material of the colored layer may be used for the light-shielding layer. A film containing a material for a colored layer that transmits light of a certain color and a material for a colored layer that transmits light of a different color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0327] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, or dyes. The method for forming the light-shielding layer and the colored layer is the same as the method for forming each layer described above. For example, the ink jet method may be used.

[0328] In addition, the display device shown in FIG. 17(A) and FIG. 17(B) includes an insulating layer 4111 and an insulating layer 41 The insulating layer 4111 and the insulating layer 4104 are made of insulating material that is difficult for impurity elements to penetrate. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, It is possible to prevent impurities from entering from the outside.

[0329] In addition, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. An EL element is a light-emitting diode (EL element) that is disposed between a pair of electrodes. The EL element has a layer containing a light-emitting compound (also called an "EL layer"). When a potential difference larger than the threshold voltage is generated, holes are injected into the EL layer from the anode side, and the cathode Electrons are injected from the electrode side. The injected electrons and holes recombine in the EL layer, forming a The contained luminescent material emits light.

[0330] EL elements are also classified according to whether the luminescent material is an organic compound or an inorganic compound. In general, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0331] When a voltage is applied to an organic EL element, electrons are emitted from one electrode and holes are emitted from the other electrode. are injected into the EL layer. Then, the carriers (electrons and holes) recombine. This causes the light-emitting organic compound to form an excited state, which then returns to the ground state. Due to this mechanism, this type of light-emitting element is called a current-excited light-emitting element. is called a child.

[0332] In addition to the light-emitting compound, the EL layer may be formed by using a material having a high hole-injecting property and a material having a high hole-transporting property. , hole blocking material, material with high electron transporting ability, material with high electron injecting ability, or bipolar The insulating layer may include a material having high electron-transporting and hole-transporting properties.

[0333] The EL layer can be formed by a variety of methods, including deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0334] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0335] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes must be transparent. A transistor and a light emitting element are formed on the substrate, and light is emitted from the opposite side of the substrate. Top emission structure, which emits light from the top surface of the substrate, and bottom emission structure, which emits light from the bottom surface of the substrate. (bottom emission) structure and dual emission (double emission) structure that emits light from both sides There are light emitting elements having a light-emitting (emission) structure, and light emitting elements having any of the emission structures can be applied.

[0336] FIG. 17(B) shows a light-emitting display device (also called an "EL display device") that uses light-emitting elements as display elements. The light-emitting element 4513, which is a display element, is provided in the display portion 101. The light-emitting element 4513 is electrically connected to the transistor 4010. This is a laminated structure of an electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031. The light emitting element 4513 may be arranged in accordance with the direction of light to be extracted from the light emitting element 4513. The configuration of 13 can be changed as appropriate.

[0337] The partition 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is continuous. It is preferable to form the inclined surface so as to have a curvature.

[0338] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers may be laminated. Either way is fine.

[0339] The color of light emitted by the light-emitting element 4513 can be white, red, green, or blue depending on the material that constitutes the light-emitting layer 4511. , cyan, magenta, or yellow, etc.

[0340] As a method for realizing color display, a light-emitting element 4513 that emits white light is combined with a colored layer. There are two methods: one is to combine the two and the other is to provide a light-emitting element 4513 with a different light-emitting color for each pixel. The first method has higher productivity than the latter method. On the other hand, the latter method requires a light-emitting layer 4511 for each pixel. However, the latter method is less productive than the former method because it requires separate production of In addition to the latter method, it is possible to obtain a luminescent color with higher color purity than the former method. By adding a microcavity structure to element 4513, color purity can be further improved. can be done.

[0341] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. The child dots can be used in a light-emitting layer to function as a light-emitting material.

[0342] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513, the second electrode layer A protective layer may be formed on the insulating layer 4031 and the partition wall 4510. The protective layer may be silicon nitride. Silicon oxide nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealant 4 The space sealed by 005 is sealed with a filler 4514. In addition, a protective film (lamination film) that is highly airtight and has little outgassing is used to prevent exposure to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. I wish.

[0343] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, poly Imide, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (ethylene vinyl acetate) or the like can be used. Agents may also be included.

[0344] The sealing material 4005 is made of glass materials such as glass frit, or two-liquid mixed resin. Resin materials such as heat-curable resin, photocurable resin, and thermosetting resin can be used. Also, the sealant 4005 may contain a desiccant.

[0345] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) is placed on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. can be installed as needed. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0346] In addition, by making the light-emitting element a microcavity structure, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces congestion and improves visibility of the displayed image.

[0347] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmitting property or the reflecting property can be selected depending on the pattern structure of the electrode layer.

[0348] The first electrode layer 4030 and the second electrode layer 4031 are made of indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide In addition, a conductive material having light transmitting properties, such as indium tin oxide doped with silicon oxide, is used. This can be done.

[0349] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) or molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b) Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or an alloy thereof, or a metal nitride thereof. .

[0350] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer of two or more of aniline, pyrrole and thiophene, Its derivatives are also included.

[0351] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the driver circuit is also required. It is preferable that the protection circuit is configured using a non-linear element.

[0352] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0353] (Embodiment 7) In this embodiment, a display module will be described. A display module 60 shown in FIG. 00 is connected to the FPC 6003 between the upper cover 6001 and the lower cover 6002. A touch sensor 6004, a display panel 6006 connected to an FPC 6005, and a backlight A light source unit 6007, a frame 6009, a printed circuit board 6010, and a battery 6011 are included. In addition, the backlight unit 6007, the battery 6011, the touch sensor 6004 etc. may not be provided.

[0354] The semiconductor device of one embodiment of the present invention includes, for example, a touch sensor 6004, a display panel 6006, It can be used for an integrated circuit mounted on a printed circuit board 6010. For example, The display device described above can be used for the panel 6006.

[0355] The upper cover 6001 and the lower cover 6002 are connected to the touch sensor 6004 and the display panel 6 The shape and dimensions can be changed appropriately to suit sizes such as 006.

[0356] The touch sensor 6004 is a resistive or capacitive touch sensor connected to the display panel 6 The display panel 6006 can be used by being superimposed on the display panel 6006. For example, a touch sensor electrode can be provided in each pixel of the display panel 6006. It is also possible to add a capacitive touch panel function. By providing an optical sensor in each pixel of the panel 6006, the function of an optical touch sensor can be added. Also, when there is no need to provide the touch sensor 6004, Sensor 6004 can be omitted.

[0357] The backlight unit 6007 includes a light source 6008. The unit 6007 may be provided at its end and configured to use a light diffusion plate. When a light-emitting display device or the like is used for 6006, the backlight unit 6007 is omitted. It is possible.

[0358] The frame 6009 has a function of protecting the display panel 6006 and also a function of preventing the display panel 6006 from being damaged. It also functions as an electromagnetic shield to block electromagnetic waves generated. 009 may have a function as a heat sink.

[0359] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. A battery 6011 is used as a power source for supplying power to the power supply circuit. If a commercial power source is used as the power source, , the battery 6011 can be omitted.

[0360] In addition, components such as polarizing plates, retardation plates, and prism sheets are added to the display module 6000. It may also be provided as such.

[0361] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0362] (Embodiment 8) In this embodiment, electronic devices to which the display device of one embodiment of the present invention can be applied will be described with reference to FIGS. This will be explained with reference to FIG.

[0363] An example of an electronic device will be described with reference to Fig. 19 and Fig. 20. According to one embodiment of the present invention, Even with a large-sized and / or high-definition display device, good display quality and high visibility are achieved. Therefore, it is possible to realize a wide range of applications, such as television equipment, digital signage, and portable electronic devices. The present invention can be suitably used in electronic devices such as wearable devices and electronic book terminals. In addition, it is possible to use VR (Virtual Reality) devices and AR (Augmented Reality) devices. The present invention can also be suitably used in devices such as 3D reality (VR) devices.

[0364] The electronic device of one embodiment of the present invention may include a secondary battery, and may be configured to transmit power in a non-contact manner. It is preferable to be able to charge the secondary battery.

[0365] As the secondary battery, for example, a lithium polymer battery (lithium ion battery) using a gel electrolyte is used. Lithium-ion secondary batteries such as lithium-ion polymer batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic These include nickel-zinc batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries. .

[0366] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. In the case where the power supply has a secondary battery, the antenna may be used for contactless power transmission.

[0367] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, etc.) ,distance, light, liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays) It is okay to do so.

[0368] The electronic device according to one embodiment of the present invention can have various functions. Still images, videos, text images, etc.) on the display, touch panel function, calendar Functions such as displaying date, time, etc., and running various software (programs) function, wireless communication function, and function to read out programs or data recorded on a recording medium. They may have the following abilities:

[0369] Furthermore, in an electronic device having a plurality of display units, one of the display units is used mainly for displaying image information. The function of displaying a single image on one display unit and displaying text information primarily on another display unit, or displaying multiple displays By displaying an image that takes the difference into consideration, it is possible to have a function for displaying a three-dimensional image, etc. Furthermore, in electronic devices having an image receiving unit, the function of taking still or moving images, The function of automatically or manually correcting the captured image, and the function of storing the captured image on a recording medium (external or electronic) The camera can have functions such as storing the captured image in a digital camera (built into the camera) and displaying the captured image on the display unit. Note that the functions of the electronic device of one embodiment of the present invention are not limited to those described above, and various functions can be provided. It is possible to have.

[0370] FIG. 19A shows a television device 1810. The television device 1810 displays The device includes a display unit 1811, a housing 1812, a speaker 1813, and the like. Keys (including power switches and operation switches), connection terminals, various sensors, microphones It is possible to have a .on etc.

[0371] The television device 1810 can be operated by a remote control 1814. do.

[0372] The television device 1810 can receive broadcast waves from terrestrial or satellite. In addition, broadcasting waves include analog broadcasting and digital broadcasting. There are also broadcasts of video and audio, or audio only. For example, the UHF band (approximately 30 0MHz~3GHz) or a specific frequency in the VHF band (30MHz~300MHz) It is possible to receive broadcast radio waves transmitted in several frequency bands. By using multiple received data, the transfer rate can be increased and more information can be This allows you to display images with resolutions that exceed full HD. For example, 4K, 8K, 16K, or more can be displayed on the display unit 1831. It is possible to display an image having a resolution of 100 .mu.m.

[0373] In addition, the Internet, LAN (Local Area Network), and Wi-Fi (registered trademark) or other data transmission technology transmitted over a computer network. The image to be displayed on the display unit 1831 may be generated using broadcast data. In this case, the television device 1810 does not need to have a tuner.

[0374] FIG. 19(B) shows a digital signage 1820 attached to a cylindrical pole 1822. The digital signage 1820 includes a display unit 1821.

[0375] The larger the display unit 1821, the more information can be provided at one time. The wider the part 1821, the more noticeable it is, and for example, the more effective the advertising can be. Cut.

[0376] By applying a touch panel to the display unit 1821, images or videos can be displayed on the display unit 1821. It is also preferable because it not only shows the route information but also allows the user to operate it intuitively. When used to provide information such as traffic information, the device must be intuitively operated. Usability can be improved.

[0377] FIG. 19C shows a notebook type personal computer 1830. The computer 1830 includes a display unit 1831, a housing 1832, a touch pad 1833, a connection port, It has Route 1834, etc.

[0378] The touch pad 1833 can be used as a pointing device, a pen tablet, or other input means. It functions as a touch screen and can be operated with a finger or a stylus.

[0379] In addition, a display element is incorporated in the touch pad 1833. As shown in FIG. By displaying input keys 1835 on the surface of the touchpad 1833, 833 can be used as a keyboard. In this case, when the input key 1835 is touched, A vibration module is built into the touchpad 1833 to provide a tactile sensation through vibration. It may be included.

[0380] An example of a portable information terminal is shown in FIG. 19(D). The portable information terminal 1840 shown in FIG. , a housing 1841, a display unit 1842, an operation button 1843, an external connection port 1844, The device has a speaker 1845, a microphone 1846, a camera 1847, etc.

[0381] The display portion 1842 is provided with the display device of one embodiment of the present invention.

[0382] The mobile information terminal 1840 has a touch sensor on the display unit 1842. Any operation such as inputting characters is performed by touching the display unit 1842 with a finger or a stylus. This can be done by:

[0383] In addition, by operating the operation button 1843, the power can be turned on and off, and the display unit 1842 can be displayed. You can change the type of image displayed. For example, from the email composition screen, You can switch to the menu screen.

[0384] In addition, a detection device such as a gyro sensor or an acceleration sensor is installed inside the mobile information terminal 1840. By providing the display unit 1842, the orientation of the portable information terminal 1840 (vertical or horizontal) can be determined. You can also set the screen orientation to automatically switch. The switching can be performed by touching the display unit 1842, by operating the operation button 1843, or by using the microphone. This can also be done by voice input using 1846.

[0385] The portable information terminal 1840 is, for example, one selected from a telephone, a notebook, an information viewing device, etc. Or it has multiple functions. Specifically, it can be used as a smartphone. The portable information terminal 1840 can be used for, for example, mobile phone calls, e-mails, document browsing and creation, and music playback. , video playback, Internet communication, games, and other applications. can be done.

[0386] 19(E) and (F) show an example of a portable information terminal 1850. The portable information terminal 1850 is , a housing 1851, a housing 1852, a display unit 1853, a display unit 1854, and a hinge unit 18 55 etc.

[0387] The housing 1851 and the housing 1852 are connected by a hinge portion 1855. 50 is folded as shown in FIG. 19(E) to the housing as shown in FIG. 19(F). 1851 and housing 1852 can be opened.

[0388] For example, document information can be displayed on the display unit 1853 and the display unit 1854. It can also be used as an electronic book terminal. It is also possible to display still images and moving images.

[0389] In this way, the portable information terminal 1850 can be folded when carried around, making it a versatile device. Excellent usability.

[0390] The housings 1851 and 1852 are provided with a power button, an operation button, and an external connection port. , a speaker, a microphone, etc.

[0391] FIG. 20(A) shows the appearance of a camera 1860 with a viewfinder 1861 attached. vinegar.

[0392] The camera 1860 includes a housing 1869, a display unit 1862, operation buttons 1863, and a shutter button. The camera 1860 has a removable lens 1865. It is being done.

[0393] Here, as the camera 1860, the lens 1865 is removed from the housing 1869 and replaced. However, the lens 1865 and the housing may be integrated together.

[0394] The camera 1860 can capture an image by pressing the shutter button 1864. The display unit 1862 also functions as a touch panel. It is also possible to capture an image by

[0395] The housing 1869 of the camera 1860 has a mount with electrodes, and a viewfinder 1861 In addition, a strobe device, etc. can be connected.

[0396] The viewfinder 1861 has a housing 1866, a display unit 1867, a button 1868, and the like.

[0397] The housing 1866 has a mount that mates with the mount of the camera 1860 and is The mount can be attached to the camera 1860. The mount can also include electrodes. and displays on a display unit 1867 an image or the like received from a camera 1860 via the electrode. It is possible.

[0398] The button 1868 functions as a power button. The display of 867 can be switched on and off.

[0399] The display unit 1862 of the camera 1860 and the display unit 1867 of the finder 1861 are The display device according to the present embodiment can be applied.

[0400] In FIG. 20A, the camera 1860 and the finder 1861 are separate electronic devices. These are configured to be detachable, but the housing 1869 of the camera 1860 is The camera may have a built-in viewfinder equipped with a display device such as the one shown in FIG.

[0401] FIG. 20B shows the appearance of the head mounted display 1870.

[0402] The head mounted display 1870 includes a mounting part 1871, a lens 1872, and a main body 187 3, a display unit 1874, a cable 1875, etc. It has a built-in Teri 1876.

[0403] A cable 1875 supplies power from a battery 1876 to the main body 1873. The reference numeral 3 is provided with a wireless receiver and displays image information such as received image data on a display unit 1874. In addition, the camera installed in the main body 1873 can record the movements of the user's eyeballs and eyelids. The system captures the user's viewpoint and calculates the coordinates of the user's viewpoint based on that information. It can be used as a force means.

[0404] Furthermore, the mounting section 1871 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 1873 detects the current flowing through the electrodes in response to the movement of the user's eyeball, The device may have a function of recognizing the user's gaze. Also, the device may have a function of detecting the current flowing through the electrode. In addition, the mounting unit 1871 may have a function of monitoring the pulse of the user. The sensor may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 1874 may have a function of displaying the user's biological information. The image displayed on the display unit 1874 can be changed according to the movement of the object. good.

[0405] The display device of one embodiment of the present invention can be applied to the display portion 1874.

[0406] 20(C) and (D) show the appearance of the head mounted display 1880.

[0407] The head mounted display 1880 includes a housing 1881, two display units 1882, and an operation button. It has a tongue 1883 and a band-like fastener 1884.

[0408] The head mounted display 1880 is In addition to the functionality, it has two displays.

[0409] By having two displays 1882, the user can see one display per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax. The display unit 1882 can display an image in an arc shape with the user's eye as the approximate center. This ensures that the distance from the user's eyes to the display surface of the display unit is constant. This allows users to see more natural images. In addition, the brightness and chromaticity of the light coming from the display unit are Even if the image changes depending on the viewing angle, it should be used in the normal direction to the display surface. Because the user's eyes are located at the site, the effect can be virtually ignored, resulting in a more realistic appearance. A certain image can be displayed.

[0410] The operation button 1883 has functions such as a power button. It may have a button.

[0411] As shown in FIG. 20(E), a lens is provided between the display unit 1882 and the position of the user's eyes. The lens 1885 allows the user to magnify the display 1882. This increases the sense of realism. It may also have a dial 1886 for changing the position of the lenses for diopter adjustment.

[0412] The display device of one embodiment of the present invention can be applied to the display portion 1882. The display device has extremely high resolution, so it is possible to use a lens 1885 as shown in Figure 20(E). Even when enlarged, the pixels are not visible to the user, providing a more realistic image. It is possible.

[0413] FIG. 20F shows an example of a television device. A television device 1890 includes a housing 18 A display unit 1892 is built into the housing 1891. This shows the configuration that supported 91.

[0414] The display device of one embodiment of the present invention can be applied to the display portion 1892.

[0415] The television device 1890 shown in FIG. 20(F) is operated using an operation switch provided in a housing 1891. This can be done by a touch panel or a separate remote control 1894. 2 may be provided with a touch sensor, and the operation may be performed by touching the display unit 1892 with a finger or the like. The remote control unit 1894 displays information output from the remote control unit 1894. The remote control 1894 may have an operation key or a touch panel. The panel allows the user to operate the channel and volume, and the display 1892 shows You can control the images displayed.

[0416] The television device 1890 is configured to include a receiver and a modem. It is also possible to receive general television broadcasts via wired or wireless connection via a modem. By connecting to a wired communication network, it can be one-way (sender to receiver) or two-way It is also possible to communicate information in both directions (between sender and receiver, or between receivers). do.

[0417] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0418] (Embodiment 9) In this embodiment, a method for crystallizing polycrystalline silicon used in a semiconductor layer of a transistor and An example of a laser crystallization apparatus will be described.

[0419] To form a polycrystalline silicon layer with good crystallinity, an amorphous silicon layer is provided on a substrate. It is preferable to crystallize the amorphous silicon layer by irradiating it with laser light. For example, The substrate is moved while irradiating the amorphous silicon layer with the linear beam. In this way, a polycrystalline silicon layer can be formed in a desired region on the substrate.

[0420] The line beam method has a relatively good throughput. On the other hand, This is a method in which the laser light is irradiated multiple times while moving relatively. The beam profile is easily affected by the beam vibration and the resulting changes in the crystallinity. For example, the semiconductor layer crystallized by this method can be used as a transistor in a pixel of a display device. When the liquid crystal is heated, random stripes caused by variations in crystallinity may be visible on the display.

[0421] In addition, the length of the linear beam is ideally equal to or greater than the length of one side of the substrate. The length of the system is limited by the output of the laser oscillator and the configuration of the optical system. In substrate processing, it is practical to irradiate the laser in a folded manner within the substrate surface. The crystallinity of the overlapping regions is different from that of the other regions. Since the crystallinity is easily different, display unevenness may occur in this region.

[0422] In order to prevent the above problems, a laser is locally applied to an amorphous silicon layer formed on a substrate. The crystallization may be achieved by irradiating the material with a laser. A polycrystalline silicon layer can be easily formed.

[0423] FIG. 21(A) shows a method of locally irradiating an amorphous silicon layer formed on a substrate with a laser. FIG.

[0424] A laser beam 826 emitted from the optical system unit 821 is reflected by a mirror 822 and The laser light 826 enters the microlens array 823. The light is focused to form multiple laser beams 827 .

[0425] A substrate 830 on which an amorphous silicon layer 840 is formed is fixed to the stage 815. By irradiating the polycrystalline silicon layer 840 with a plurality of laser beams 827, a plurality of polycrystalline silicon The insulating layer 841 can be formed at the same time.

[0426] The individual microlenses of the microlens array 823 are arranged at the same pitch as the pixels of the display device. It is preferable to provide them at the same interval. Alternatively, they may be provided at intervals that are an integral multiple of the pixel pitch. Even in the case of deviation, the laser irradiation and the movement of the stage 815 in the X or Y direction are repeated. By doing so, it is possible to form a polycrystalline silicon layer in the regions corresponding to all the pixels.

[0427] For example, if the microlens array 823 has a pixel pitch of M rows and N columns (M and N are natural numbers), When the lens is attached to the substrate, a laser beam is first irradiated at a predetermined starting position to form a polycrystalline silicon having M rows and N columns. Then, the recon layer 841 can be formed by moving the layer in the row direction by a distance of N columns. Laser light is irradiated to form polycrystalline silicon layers 841 of M rows and N columns. It is possible to form N columns of polycrystalline silicon layers 841. By repeating this process, A plurality of polycrystalline silicon layers 841 can be formed in a desired area. When performing the laser irradiation process, the laser is irradiated by moving the distance of N columns in the row direction. Furthermore, the movement in the column direction by a distance of M rows and the irradiation of the laser light may be repeated.

[0428] In addition, if the oscillation frequency of the laser light and the moving speed of the stage 815 are appropriately adjusted, Even if the laser is irradiated while moving the 815 in one direction, the polycrystalline silicon A thin film layer can be formed.

[0429] The size of the laser beam 827 is set to, for example, an entire semiconductor layer of one transistor. Alternatively, the entire channel formation region of one transistor can be formed in an area of ​​about Alternatively, the area of ​​the channel forming region of one transistor may be set to be within the range of 100 nm to 150 nm. These can be made to have an area that includes a part of the required transistor. The appropriate one can be used according to the electrical characteristics of the device.

[0430] In addition, in the case of a display device having a plurality of transistors in one pixel, The area of ​​the matrix 827 is set to be large enough to include the entire semiconductor layer of each transistor in one pixel. In addition, the laser beam 827 can be incident on the semiconductor of the transistors included in the plurality of pixels. The area may be large enough to include the entire layer.

[0431] As shown in FIG. 22A, between the mirror 822 and the microlens array 823, A mask 824 may be provided. The mask 824 has a number of apertures corresponding to each microlens. The shape of the opening can be reflected in the shape of the laser beam 827. In the case where the mask 824 has a circular opening as shown in FIG. 22(A), a circular laser beam is In addition, when the mask 824 has a rectangular opening, a rectangular A laser beam 827 having a shape of a transistor can be obtained. This is effective when it is desired to crystallize only the channel forming region. As shown in FIG. 22B, it may be provided between the optical system unit 821 and the mirror 822 .

[0432] FIG. 21(B) shows a laser crystal that can be used in the local laser irradiation process described above. FIG. 1 is a perspective view illustrating the main configuration of a laser crystallization apparatus. The components include a moving mechanism 812, a moving mechanism 813, and a stage 815. A laser oscillator 820 for shaping a laser beam 827, an optical system unit 821, a mirror The optical fiber 821 has a microlens array 822 and a microlens array 823.

[0433] The moving mechanism 812 and the moving mechanism 813 have a function of performing reciprocating linear motion in the horizontal direction. The mechanism for powering the moving mechanism 812 and the moving mechanism 813 may be, for example, a motor-driven mechanism. A ball screw mechanism 816 that moves the moving mechanism 812 can be used. Since the directions of movement of each of the stages 813 are perpendicular to each other, the stages fixed to the moving mechanism 813 The 815 can be freely moved in the X and Y directions.

[0434] The stage 815 has a fixing mechanism such as a vacuum suction mechanism, and can fix a substrate 830 and the like. In addition, the stage 815 may have a heating mechanism as necessary. Although not shown, the stage 815 has a pusher pin and a mechanism for raising and lowering the pin. When the substrate 830 is carried in or out, the substrate 830 can be moved up and down.

[0435] The laser oscillator 820 is required only to output light of a wavelength and intensity suitable for the purpose of processing. A 351-353n laser is preferred, but a CW laser may also be used. Using an excimer laser capable of irradiating ultraviolet light such as 308 nm (XeF) and 308 nm (XeCl), Or, it can be used as a double wave of a solid-state laser (YAG laser, fiber laser, etc.). (515nm, 532nm, etc.) or triple waves (343nm, 355nm, etc.) Also, the laser oscillator 820 may be multiple.

[0436] The optical system unit 821 includes, for example, a mirror, a beam expander, a beam homogenizer, etc. The laser oscillator 820 outputs a laser beam 825 having a uniform energy distribution in a plane. It is possible to unify and expand the material.

[0437] The mirror 822 may be, for example, a dielectric multilayer mirror. The microlens array 823 is arranged so that the angle is approximately 45°. The shape may be such that a plurality of convex lenses are provided on the top surface or on the upper and lower surfaces.

[0438] By using the above-mentioned laser crystallization apparatus, polycrystalline silicon with little variation in crystallinity can be obtained. A layer can be formed.

[0439] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible. EXAMPLES

[0440] In this embodiment, an 8K4K liquid crystal display having a pixel area (display section) with a screen size of 65 inches diagonally is used. This section explains the results of an estimate of the data writing time for the display module. do.

[0441] The resolution of an 8K4K display is 7680 horizontally and 4320 vertically. , which is an extremely high resolution. In addition, the ITU -R BT.2020. In this standard, the driving method is the progressive method. The frame frequency is set to a maximum of 120Hz.

[0442] In this embodiment, a selection signal is supplied to each gate line, and pixels are selected one by one. In addition, the selection signal is supplied to two or four gate lines at the same time, and up to two adjacent gate lines in the column direction are selected. We considered a configuration in which two or four pixels are selected simultaneously. Each pixel is connected to a different source line, i.e., two or four sources per column. In this embodiment, the pixel layout in this configuration is used to We estimated the data writing time.

[0443] In this embodiment, amorphous silicon is used for the semiconductor layer of the transistor. In this study, the case of using metal oxides was examined.

[0444] When amorphous silicon is used for the semiconductor layer, it is fabricated using microcrystalline silicon. From the actual measured values ​​of the transistor, we have created a pseudo-transistor with varying field-effect mobility, which is a design parameter. It was estimated using parameters.

[0445] Regarding the semiconductor layer using metal oxide, the following two types of structures were considered. The first type is an In-Ga-Zn oxide with atoms of In, Ga, and Zn. When a single layer of metal oxide with a numerical ratio of In:Ga:Zn=1:1:1 is used as the semiconductor layer, The second type has an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2. 3: In the case where a metal oxide in the vicinity of the first metal is used as a semiconductor layer in a laminated state. CAC-OS (Cloud-Aligned Composite ox The second metal oxide layer is a CAAC-O S(c-axis-aligned crystalline oxide semic The case where a conductive film is used is assumed.

[0446] The parameters of each layer used in this example are shown in Table 1. These are the parameters of the semiconductor layer made of metal oxide. These parameters are based on the assumption that the transistor is made of amorphous silicon. Similar parameters were used for the semiconductor layer.

[0447] [Table 1]

[0448] <When pixels are selected one by one> FIG. 23A is a block diagram showing the configuration of a display module used in this embodiment. In this configuration, a selection signal is supplied to each gate line, and each pixel is selected. The gate driver and source driver are both external. The same signal is supplied from the source driver IC to the source line. The signal is supplied from the pixel area. The pixel area is not divided. The size of the pixel area is 65 inches diagonally. The number of effective pixels is 7680 x RGB(H) x 4320(V).

[0449] FIG. 23B shows a circuit diagram of pixel PIX(i,j). The gate of the transistor M1 is connected to a capacitance element C1 and a liquid crystal element LC. is connected to the gate line GDL(i). One of these is connected to the source line SDL(j), and the other is connected to one electrode of the capacitance element C1. The other electrode of the capacitance element C1 is connected to the wiring The other electrode of the liquid crystal element LC is connected to the wiring TCOM. There are.

[0450] 24(A) and (B) show the image of a display module when pixels are selected one by one. FIG. 24(A) shows the stacked structure from the gate line GDL(i) to the pixel electrode. FIG. 24(B) is a top view of the structure of the pixel electrode as viewed from the pixel electrode side. FIG.

[0451] The pixel size is 62.5 μm × 187.5 μm. Transistor M1 is a bottom gate The transistor M1 is a channel-etched type transistor with a top contact structure. The channel length L is 4 μm, the channel width W is 8 μm, and the LDD region overlapping the gate (hereafter, the over -Lap LDD area L ov The width of the gate line GDL(i) is 10 μm, and the The width of the line CSCOM is 3.5 μm. The width of the source line SDL(j) is 10 μm. , and 4 μm at the crossing with other wiring (gate line GDL(i) and wiring CSCOM). The aperture ratio is 45.6%.

[0452] First, using FIG. 25, the data write time when metal oxide is used for the semiconductor layer is roughly calculated. This article explains:

[0453] The parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 24(A) and the mobility parameters are By changing the amount of charge, the charging time of the gate line of the pixel and the charging time of the source line and pixel can be roughly In this embodiment, the data write time is calculated based on the gate line charging time and the In this embodiment, the charging time of the gate line corresponds to the total charging time of the gate line and the pixel. The charge time is the time it takes for the gate line potential to reach 75% of the maximum input voltage. The charging time for the source line and pixel is until the potential of the source line reaches 99% of the maximum input voltage. It's time.

[0454] In addition, the atomic ratio of In, Ga, and Zn is approximately In:Ga:Zn=4:2:3. The field effect mobility when a metal oxide is used as a semiconductor layer is normalized to 1. The value (normalized mobility) was used. The size of the transistor was not changed. The load is as follows: The parasitic resistance Rgl of the gate line is 3.60 kΩ, The parasitic capacitance Cgl of the source line is 255 pF, the parasitic resistance Rsl of the source line is 5.80 kΩ, The parasitic capacitance Csl is 147 pF, and the pixel parasitic capacitance Cpix is ​​216.6 fF. In this embodiment, the parasitic capacitance Cpix of the pixel is a sum of the storage capacitance of the capacitive element, the capacitance of the liquid crystal element, and the parasitic capacitance of node A. In this embodiment, node A is the In the above, a source or drain of a transistor, one electrode of a capacitor, and a One electrode is a connected node.

[0455] In FIG. 25, the normalized mobility is 1 when the atomic ratio of In, Ga, and Zn is In This corresponds to the case where a metal oxide having a ratio of about Ga:Zn=4:2:3 is used as the semiconductor layer. (In Figure 25, this is shown as "CAC\CAAC"). In this case, the data write time is 3.5 5μs, which is shorter than the horizontal period of 3.85μs at 60Hz. It was estimated that the data writing time was 120 Hz. It is estimated that it will be difficult to operate at 120Hz because the horizontal period is longer than 1.93μs. Ta.

[0456] In FIG. 25, the normalized mobility is 0.5 when the atomic ratio of In, Ga, and Zn is When a single layer of metal oxide with a ratio of In:Ga:Zn=1:1:1 is used as the semiconductor layer, (In Figure 25, this is shown as "IGZO(111)"). At this time, the data writing time is This is 4.17μs, which is longer than the horizontal period of 3.85μs at 60Hz. It was estimated that not only would it be difficult to drive it, but it would also be difficult to operate it at 60Hz.

[0457] Next, referring to FIG. 26, data writing when amorphous silicon is used for the semiconductor layer will be described. Explain time estimates.

[0458] The parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 24(A) and a microcrystalline silicon is used. The field-effect mobility, which is a design parameter, was changed based on the actual measured values ​​of the transistors fabricated by this method. By this, the charging time of the gate line of the pixel and the charging time of the source line and pixel were roughly calculated. The size of the transistor and the size of the storage capacitance have not been changed. When using a semiconductor layer, a larger transistor size and storage capacitance are required. Therefore, the data writing time needs to be longer than that in the present embodiment. The load of the gate line is as follows: The parasitic resistance Rgl of the gate line is 3.60 kΩ, The parasitic capacitance Cgl of the line is 255 pF, the parasitic resistance Rsl of the source line is 5.80 kΩ, and the source line The parasitic capacitance Csl of the pixel is 147 pF, and the parasitic capacitance Cpix of the pixel is 216.6 fF.

[0459] In FIG. 26, the field effect mobility is 0.6, 0.7, and 0.8 [cm 2 / V s The result of This corresponds to the case where amorphous silicon is used for the semiconductor layer. The intervals are 19.66μs, 16.19μs, and 13.81μs, respectively, and are 120Hz drive. 1 horizontal period at 60Hz is longer than 1.93μs and 3.85μs at 60Hz. It was estimated that it would be difficult to operate the device not only at 120Hz, but also at 60Hz.

[0460] <When two pixels are selected at the same time> FIG. 27A is a block diagram showing the configuration of a display module used in this embodiment. In this configuration, a selection signal is supplied to two gate lines at the same time, and adjacent pixels in the column direction are selected. are selected simultaneously. Both the gate driver and the source driver are external. The same signal is supplied to the gate lines from two gate driver ICs. Gate line GDL0 (i) is electrically connected to the gate line GDL(i) and the gate line GDL(i+1). The i-th row and the (i+1)-th row are driven simultaneously. The signal is supplied from the driver IC. The pixel area is not divided. The size of the pixel area is diagonal It is 65 inches and has an effective pixel count of 7680 x RGB (H) x 4320 (V).

[0461] FIG. 27B shows a circuit diagram of pixel PIX(i,j) and pixel PIX(i+1,j). .

[0462] First, the configuration of pixel PIX(i,j) will be described. The transistor M1 has a capacitance element C1, and a liquid crystal element LC. The gate of the transistor M1 is , connected to the gate line GDL(i). One of them is connected to the source line SDL1(j), and the other is connected to one electrode of the capacitance element C1. The other electrode of the capacitance element C1 is connected to the wiring The other electrode of the liquid crystal element LC is connected to the wiring TCOM. There are.

[0463] Next, the configuration of pixel PIX(i+1,j) will be described. , a transistor M2, a capacitance element C2, and a liquid crystal element LC. The gate is connected to the gate line GDL(i+1). One of the drains is connected to the source line SDL2(j), and the other is connected to the The other electrode of the capacitance element C2 is connected to one of the electrodes of the liquid crystal element LC. The electrode is connected to the wiring CSCOM. The other electrode of the liquid crystal element LC is connected to the wiring TCOM. and is connected.

[0464] FIG. 28(A) and (B) show the display module when two pixels are selected at the same time. The pixel layout is shown in FIG. 28(A). FIG. 28(B) is a top view of the structure seen from the pixel electrode side. FIG.

[0465] The pixel size is 62.5 μm × 187.5 μm. Transistor M1 is a bottom gate The transistor M1 is a channel-etched type transistor with a top contact structure. The channel length L is 4 μm, the channel width W is 8 μm, and the overlap LDD region L ov is 2μm The width of the gate line GDL(i) is 10 μm, and the width of the wiring CSCOM is 3.5 μm. The width of the source line SDL1(j) and the source line SDL2(j) is both 10 μm. However, at the crossing with the gate line, the gap is 4μm for both. The aperture ratio is 37.3%. .

[0466] First, using FIG. 29, we will roughly estimate the data write time when metal oxide is used for the semiconductor layer. This article explains:

[0467] The parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 28(A) and the mobility parameters are By changing the amount of charge, the charging time of the gate line of the pixel and the charging time of the source line and pixel can be roughly Here, the atomic ratio of In, Ga, and Zn was In:Ga:Zn=4:2:3. The field effect mobility is normalized to 1 when a nearby metal oxide is used as the semiconductor layer. The value (normalized mobility) was used. The size of the transistor was not changed. Entire pixel area The load of the gate line is as follows: The parasitic resistance Rgl of the gate line is 3.60 kΩ, The parasitic capacitance Cgl of the line is 364 pF, the parasitic resistance Rsl of the source line is 4.83 kΩ, and the source line The parasitic capacitance Csl of the pixel is 182 pF, and the parasitic capacitance Cpix of the pixel is 191 fF.

[0468] In FIG. 29, the normalized mobility is 1 when the atomic ratio of In, Ga, and Zn is In This corresponds to the case where a metal oxide having a ratio of about Ga:Zn=4:2:3 is used as the semiconductor layer. (In Figure 29, this is shown as "CAC\CAAC"). In this case, the data write time is 3.4 9μs, which is shorter than the horizontal period of 3.83μs at 120Hz. It was estimated that it would be possible to operate at

[0469] In FIG. 29, the normalized mobility is 0.5 when the atomic ratio of In, Ga, and Zn is When a single layer of metal oxide with a ratio of In:Ga:Zn=1:1:1 is used as the semiconductor layer, (In Figure 29, this is shown as "IGZO(111)"). At this time, the data writing time is This is 4.02μs, which is shorter than the horizontal period of 7.66μs when driven at 60Hz. It was estimated that the data writing time would be 120Hz. It is estimated that it will be difficult to operate at 120Hz because the horizontal period is longer than 3.83μs. It was stolen.

[0470] In FIG. 29, the same selection signal is supplied to two gate lines, so the length of one horizontal period is 25, which is twice as large as the conventional MOS transistor. This makes it easier to operate high resolution displays.

[0471] From the results of FIG. 25 and FIG. 29, when CAC\CAAC is used in the semiconductor layer, The 120Hz drive operation, which was difficult with a configuration that writes to two pixels at the same time, is now possible. It was shown that this can be achieved by configuring it to be written.

[0472] In addition, from the results of Figures 25 and 29, when IGZO(111) is used for the semiconductor layer, The 60Hz operation, which was difficult with a configuration that writes to two pixels one by one, can now be achieved with It was shown that this can be achieved by configuring simultaneous writing.

[0473] Next, referring to FIG. 30, data writing when amorphous silicon is used for the semiconductor layer will be described. Explain time estimates.

[0474] The parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 28(A) and a microcrystalline silicon is used. The field-effect mobility, which is a design parameter, was changed based on the actual measured values ​​of the transistors fabricated by this method. By this, the charging time of the gate line of the pixel and the charging time of the source line and pixel were roughly calculated. The size of the transistor and the size of the storage capacitor have not been changed. The parasitic resistance Rgl of the gate line is 3.60 kΩ, and the parasitic capacitance C gl is 364pF, the parasitic resistance of the source line Rsl is 4.83kΩ, and the parasitic capacitance of the source line Cs l is 182pF, and the pixel parasitic capacitance Cpix is ​​191fF.

[0475] In FIG. 30, the field effect mobility is 0.6, 0.7, and 0.8 [cm 2 / V s The result of This corresponds to the case where amorphous silicon is used for the semiconductor layer. The intervals are 17.98μs, 14.89μs, and 12.78μs, respectively, and the 120Hz drive 3.83μs for one horizontal period at 60Hz and 7.66μs for one horizontal period at 60Hz. It was estimated that it would be difficult to operate the device not only at 120Hz, but also at 60Hz.

[0476] From the results in Figure 30, when amorphous silicon is used as a semiconductor, it is better to use a metal oxide as a semiconductor. Unlike the case where the MOS transistor is used for a single layer (see the results in Figure 29), two pixels are written simultaneously. However, it was estimated that it would be difficult to operate at 60Hz.

[0477] <When four pixels are selected at the same time> FIG. 31(A) is a block diagram showing the configuration of a display module used in this embodiment. In this configuration, a selection signal is simultaneously supplied to four gate lines, and adjacent pixels in the column direction are Four gate drivers and source drivers are selected simultaneously. The same signal is supplied to the gate line from two gate driver ICs. i) is the gate line GDL(i), the gate line GDL(i+1), the gate line GDL(i+2) , and the gate line GDL(i+3) is electrically connected to the i-th row to the (i+3)-th row. Up to four rows are driven simultaneously. A signal is supplied to the source line from one source driver IC. The pixel area is not divided. The size of the pixel area is 65 inches diagonally, and the effective image is The prime number is 7680 x RGB(H) x 4320(V).

[0478] In FIG. 31B, pixels PIX(i,j), PIX(i+1,j), and PIX(i+ 2,j) and pixel PIX(i+3,j).

[0479] First, the configuration of pixel PIX(i,j) will be described. The transistor M1 has a gate connected to a capacitor C1 and a liquid crystal element LC. The source and drain of the transistor M1 are connected to the gate line GDL(i). One of the electrodes is connected to the source line SDL1(j), and the other is connected to one of the electrodes of the capacitance element C1. The other electrode of the capacitance element C1 is connected to the wiring CSC. The other electrode of the liquid crystal element LC is connected to the wiring TCOM.

[0480] Next, the configuration of pixel PIX(i+1,j) will be described. The gate of the transistor M2 is connected to the capacitance element C2 and the liquid crystal element LC. The source and drain of the transistor M2 are connected to the gate line GDL(i+1). One of the drains is connected to the source line SDL2(j), and the other is connected to one of the capacitance elements C2. The other electrode of the capacitance element C2 is connected to the electrode of the capacitance element C1 and one of the electrodes of the liquid crystal element LC. The other electrode of the liquid crystal element LC is connected to the wiring TCOM. It has been done.

[0481] Next, the configuration of pixel PIX(i+2,j) will be described. The gate of the transistor M3 is connected to a capacitor C3 and a liquid crystal element LC. The source and drain of the transistor M3 are connected to the gate line GDL(i+2). One of the drains is connected to the source line SDL3(j), and the other is connected to one of the capacitance elements C3. The other electrode of the capacitance element C3 is connected to the electrode of the capacitance element C4 and one electrode of the liquid crystal element LC. The other electrode of the liquid crystal element LC is connected to the wiring TCOM. It has been done.

[0482] Next, the configuration of pixel PIX(i+3,j) will be described. The gate of the transistor M4 is connected to the capacitance element C4 and the liquid crystal element LC. The source and drain of the transistor M4 are connected to the gate line GDL(i+3). One of the drains is connected to the source line SDL4(j), and the other is connected to one of the capacitance elements C4. The other electrode of the capacitance element C4 is connected to the electrode of the capacitance element C5 and one of the electrodes of the liquid crystal element LC. The other electrode of the liquid crystal element LC is connected to the wiring TCOM. It has been done.

[0483] Figure 32 shows the pixel layout of a display module when four pixels are selected simultaneously. FIG. 32 is a top view of the stacked structure from the gate line to the pixel electrode, as viewed from the pixel electrode side. In FIG. 32, the pixels PIX(i+2,j) and PIX(i+3,j) The layout of pixels PIX(i,j) and PIX(i+1,j) is as follows: It can be said to be a mirror image of Figure 32.

[0484] The pixel size is 62.5 μm × 187.5 μm. Transistor M3 and Transistor M4 is a bottom-gate top-contact channel-etched transistor. The size of the two transistors is similar. Specifically, the channel length L of the two transistors is 4 μm. m, the channel width W is 8 μm, and the overlap LDD region Lov is 3 μm. The width of the gate line GDL(i+2) and the gate line GDL(i+3) are both 10 μm. The width of each SCOM is 5 μm. ), source line SDL3(j), and source line SDL4(j) each have a width of 4 μm. The aperture ratio is 29%.

[0485] First, using FIG. 33, the data write time when metal oxide is used for the semiconductor layer is roughly calculated. This article explains:

[0486] The parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 32, and only the mobility parameters are changed. By simulating the above, the charging time of the gate line of the pixel and the charging time of the source line and pixel were estimated. Here, the atomic ratio of In, Ga, and Zn is about In:Ga:Zn=4:2:3. A value normalized to a field effect mobility of 1 when a certain metal oxide is used as a semiconductor layer in a laminated structure. (Normalized mobility) was used. The size of the transistor was not changed. The load of the entire pixel area The parasitic resistance of the gate line Rgl is 3.53 kΩ. The parasitic capacitance Cgl is 518 pF, the parasitic resistance Rsl of the source line is 10.28 kΩ, and the parasitic capacitance The raw capacitance Csl is 170 pF, and the parasitic capacitance Cpix of the pixel is 99.7 fF.

[0487] In FIG. 33, the normalized mobility is 1 when the atomic ratio of In, Ga, and Zn is In This corresponds to the case where a metal oxide having a ratio of about Ga:Zn=4:2:3 is used as the semiconductor layer. (In Figure 33, this is shown as "CAC\CAAC"). At this time, the data write time is 5.0 5μs, which is shorter than the horizontal period of 7.61μs at 120Hz. It was estimated that it would be possible to operate at

[0488] In FIG. 33, the normalized mobility is 0.5 when the atomic ratio of In, Ga, and Zn is When a single layer of metal oxide with a ratio of In:Ga:Zn=1:1:1 is used as the semiconductor layer, (In Figure 33, this is shown as "IGZO(111)". In this case, the data writing time is This is 5.22μs, which is shorter than the horizontal period of 7.61μs at 120Hz. It was estimated that it would be possible to operate with z-drive.

[0489] In FIG. 33, the same selection signal is supplied to four gate lines, so the length of one horizontal period is 25, which is four times higher than that of the conventional transistor. This makes it easier to operate high resolution displays.

[0490] From the results in Figure 33, by configuring four pixels to be written simultaneously, it is possible to achieve a higher resolution than CAC\CAAC. Even when IGZO(111), which has a lower mobility than IGZO, is used as the semiconductor layer, the It was shown that drive operation is possible.

[0491] Next, referring to FIG. 34, data writing when amorphous silicon is used for the semiconductor layer will be described. Explain time estimates.

[0492] Parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 30 and fabricated using microcrystalline silicon. By changing the field effect mobility, which is a design parameter, from the actual measured value of the transistor, The charging time of the gate line of the pixel and the charging time of the source line and pixel were estimated. The size of the capacitor and the storage capacitance have not been changed. The load on the entire pixel area is as follows: The parasitic resistance Rgl of the gate line is 3.53 kΩ, and the parasitic capacitance Cgl of the gate line is 518pF, the parasitic resistance Rsl of the source line is 10.28kΩ, and the parasitic capacitance Csl of the source line is 170pF, and the pixel parasitic capacitance Cpix is ​​99.7fF.

[0493] In FIG. 34, the field effect mobility is 0.6, 0.7, and 0.8 [cm 2 / V s The result of This corresponds to the case where amorphous silicon is used for the semiconductor layer. The time between the pulses is 11.66μs, 10.06μs, and 9.01μs, respectively, when driven at 60Hz. It is estimated that this is shorter than the horizontal period of 15.3 μs and that it can be operated at 60 Hz. The data write time was 7.61μs per horizontal period at 120Hz. It was estimated that it would be difficult to operate at 120Hz for a long time.

[0494] From the results of FIG. 26, FIG. 30, and FIG. 34, when amorphous silicon is used for the semiconductor layer, In this case, a 60Hz drive operation can be achieved by applying a configuration in which four pixels are written simultaneously. It was shown that this was possible.

[0495] As described above, by applying one embodiment of the present invention, it is possible to form an amorphous semiconductor layer in a transistor. Even if silicon is used, a large screen with a diagonal of 65 inches and a resolution of 8K4K is required. It was estimated that a high-resolution display could be driven by 1000mW.

[0496] The above rough calculation results are summarized in Table 2. In Table 2, the conditions under which operation is possible are marked with a circle, and those under which operation is difficult are marked with a circle. The new conditions are indicated by crosses. In addition, the conditions under which the operation becomes possible when the insulating layer is made thicker are shown in three figures. Indicated by a square mark.

[0497] [Table 2]

[0498] In addition, the data writing time when the size of the pixel area (screen size) is changed is roughly Based on the pixel layout used in the above rough calculation, the pixel area is proportional to the size of the pixel area. A rough estimate was made assuming that the parasitic resistance and capacitance change depending on the

[0499] The approximate data write time when pixels are selected one by one is shown in FIG. The approximate data write time when two elements are selected at the same time is shown in FIG. FIG. 37 shows an estimate of the data write time when four elements are selected simultaneously.

[0500] Moreover, the relationship between the size of the pixel area and the frame frequency is shown in FIG.

[0501] FIG. 38(A) shows the relationship between the size of the pixel area and the frame frequency when two pixels are selected at the same time. FIG.

[0502] For CAC\CAAC, up to 100 inches at 60Hz, up to 65 inches at 120Hz It may work. IGZO(111) supports up to 90 inches at 60Hz, 120 It can operate up to 60 inches at 30 Hz. a-Si:H can operate up to 40 inches at 30 Hz. It may work from ch to 60 inches.

[0503] FIG. 38(B) shows the size of the pixel area and the frame frequency when four pixels are selected simultaneously. When four pixels are selected at the same time, the pixel Layout is possible.

[0504] For CAC\CAAC, up to 100 inches at 60Hz and up to 85 inches at 120Hz It may work. IGZO(111) can handle up to 100 inches at 60Hz, 12 It can operate up to 60 inches at 60 Hz. a-Si:H can operate up to 75 inches at 60 Hz. It may work up to nch.

[0505] In FIG. 38(C), for CAC\CAAC and IGZO(111), two pixels are simultaneously For a-Si:H, when four pixels are selected at the same time, FIG. 13 is a diagram showing the relationship between the size of an area and the frame frequency. [Explanation of symbols]

[0506] 100 display device 101 Display section 102 Scanning line driving circuit 103 Scanning line driving circuit 104 Signal line driver circuit 105 Signal line driver circuit 108 Border 109 Border 110 pixels 120 pixels 180 Liquid crystal element 223 Electrode 226 Insulating Layer 227 Insulating Layer 228 Insulating Layer 229 Insulating Layer 235 Display area 241 Insulating Layer 242 Semiconductor layer 246 Electrode 251 Transistor 255 Impurities 271 Substrate 272 Insulating Layer

Claims

[Claim 1] A display device including a display unit including a plurality of pixels, a plurality of scanning lines, a plurality of first signal lines, and a plurality of second signal lines, At least one of the plurality of pixels includes a display element and a transistor; the first signal lines and the second signal lines extend in a scanning direction; the first signal lines are provided on the upstream side in a scanning direction, the second signal lines are provided downstream in a scanning direction; The plurality of pixels include a first pixel electrically connected to any one of the plurality of first signal lines; a second pixel electrically connected to any one of the plurality of second signal lines; The plurality of scanning lines include a first scan line, a second scan line, and a third scan line; The first scan line is a region of the plurality of first signal lines and the plurality of second signal lines that overlaps only the plurality of first signal lines; The second scan line is a region that overlaps only the second signal lines among the first signal lines and the second signal lines, The third scan line is a region overlapping at least one of the first signal lines and a region overlapping at least one of the second signal lines; A display device comprising:

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