Semiconductor device

Abstract

To provide a semiconductor device capable of inspecting a bonding wire.SOLUTION: A semiconductor device includes a base 11, one or a plurality of chips which are provided on the base and include semiconductor chips 20, a first bonding wire 32 connected to at least one chip out of the one or plurality of chips, second bonding wires 41 to 44 extending in a direction crossing an extension direction of the first bonding wire when viewed from a thickness direction of the base, and a resin layer which is provided on the base, and seals the one or plurality of chips, the first bonding wire and the second bonding wire, wherein the first bonding wire and the second bonding wire are not brought into contact with each other, and when the first bonding wire is inclined to the second bonding wire side, the first bonding wire can be brought into contact with the second bonding wire.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] It is known to mount a chip on a conductive base and connect a bonding wire to the chip (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-113284 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the chip and bonding wire are encapsulated in resin, if the shape of the bonding wire changes, the characteristics will change. If an X-ray inspection device is used to inspect the shape of the bonding wire inside the encapsulation resin, the manufacturing process will increase.

[0005] The present disclosure has been made in consideration of the above problems, and has an object to enable inspection of bonding wires. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising a base, one or more chips including a semiconductor chip provided on the base, a first bonding wire connected to at least one of the one or more chips, a second bonding wire extending in a direction intersecting an extension direction of the first bonding wire when viewed from the thickness direction of the base, a resin layer provided on the base and sealing the one or more chips, the first bonding wire, and the second bonding wire, the first bonding wire and the second bonding wire are not in contact with each other, and the first bonding wire is capable of contacting the second bonding wire when the first bonding wire is tilted toward the second bonding wire. Effect of the Invention

[0007] According to the present disclosure, it is possible to inspect bonding wires. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA of FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line BB of FIG. [Figure 4] FIG. 4 is a circuit diagram of one set in the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view of a semiconductor device according to a first comparative example. [Figure 7] FIG. 7 is a cross-sectional view taken along line AA in FIG. [Figure 8] FIG. 8 is a cross-sectional view of the semiconductor device in accordance with the first embodiment. [Figure 9] FIG. 9 is a side view of the bonding wire in the first embodiment as viewed from the Y direction. [Figure 10]FIG. 10 is a side view of the bonding wire in the first embodiment as viewed from the X direction. [Figure 11] FIG. 11 is a plan view of the bonding wire in the first embodiment. [Figure 12] FIG. 12 is a plan view of the bonding wire in the first embodiment. [Figure 13] FIG. 13 is a plan view of a semiconductor device in accordance with a second embodiment. [Figure 14] FIG. 14 is a cross-sectional view taken along line AA of FIG. [Figure 15] FIG. 15 is a circuit diagram of one set in the semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a plan view of a semiconductor device in accordance with a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device including a base, one or more chips including a semiconductor chip provided on the base, a first bonding wire connected to at least one of the one or more chips, a second bonding wire extending in a direction intersecting an extension direction of the first bonding wire as viewed from a thickness direction of the base, a resin layer provided on the base and sealing the one or more chips, the first bonding wire, and the second bonding wire, the first bonding wire and the second bonding wire are not in contact with each other, and the first bonding wire can be in contact with the second bonding wire when the first bonding wire is tilted toward the second bonding wire, thereby making it possible to detect the tilt of the first bonding wire. (2) In the above (1), a first terminal is connected to the first bonding wire in a DC manner, and a second terminal is connected to the second bonding wire in a DC manner, and the first terminal and the second terminal do not have to be connected in a DC manner. This makes it possible to detect the inclination of the first bonding wire. (3) In the above (1) or (2), the first bonding wire may be capable of contacting the second bonding wire when the first bonding wire is inclined toward the second bonding wire by 45° or more from the thickness direction of the base, thereby making it possible to detect the inclination of the first bonding wire. (4) In any of the above (1) to (3), when the second bonding wire is divided into three parts as viewed in the thickness direction of the base, the point of the second bonding wire farthest from the base may be located at the part of the third part that is closest to the first bonding wire, thereby making it possible to detect the inclination of the first bonding wire. (5) In any of the above (1) to (4), the angle between the direction in which the first bonding wire extends and the direction in which the second bonding wire extends may be 45° or more when viewed from the thickness direction of the base, thereby making it possible to reduce the effect of the second bonding wire on the characteristics of the first bonding wire. (6) In any one of (1) to (5) above, at least two of the second bonding wires may be provided so as to sandwich the first bonding wire therebetween, thereby making it possible to detect the inclination of the first bonding wire in any direction. (7) In any one of the above (1) to (6), both ends of the second bonding wire may be bonded to the base, thereby making it possible to set the second bonding wire at a reference potential. (8) In any of the above (1) to (7), both ends of the first bonding wire may be bonded onto one of the one or more chips, and a first end of both ends of the second bonding wire that is closer to the first bonding wire may be bonded onto the one chip, thereby making it possible to detect the inclination of the first bonding wire bonded onto the chip. (9) In any one of the above (1) to (8), the first bonding wire may be the longest of all the bonding wires that transmit signals, thereby making it possible to detect the tilt of the first bonding wire, which is prone to tilt. (10) In any one of (1) to (9) above, the first bonding wire may transmit a high-frequency signal, thereby making it possible to detect a change in high-frequency characteristics of the first bonding wire. (11) In the above (10), the one or more chips may include the semiconductor chip and a passive element chip, and the first bonding wire may electrically connect the semiconductor chip and the passive element chip. This makes it possible to detect the inclination of the first bonding wire, which is difficult to adjust.

[0010] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] Fig. 1 is a plan view of a semiconductor device according to a first embodiment. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. Fig. 3 is a cross-sectional view taken along line BB in Fig. 1. Note that Figs. 2 and 3 also show bonding wires 31 to 33 and 41 to 44 in the vicinity of the cross-sectional lines. The thickness direction of base 11 is the Z direction, the extension direction of a straight line connecting terminals 13 and 12 is the X direction, and the direction perpendicular to the X direction and the Z direction is the Y direction.

[0012] As shown in Figures 1 to 3, the semiconductor device 100 of the first embodiment has a structure in which a semiconductor chip 20 and a passive element chip 25 mounted on a base 11 of a conductive lead frame 10 are sealed with a resin layer 14. The lead frame 10 has a base 11, and terminals 12 and 13. The base 11, the terminals 12 and 13 are not in contact with each other. The base 11 is a die pad, and the terminals 12 and 13 are leads. A connection bar that connects the base 11, the terminals 12 and the terminals 13 before cutting is omitted from the illustration. The lower surfaces of the base 11 and the terminals 12 and 13 are exposed from the lower surface of the resin layer 14.

[0013] The terminals 12, the semiconductor chip 20, the passive element chip 25, and the terminals 13 are arranged in order in the negative direction of the X direction. Two sets 16a and 16b of the terminals 12, the semiconductor chip 20, the passive element chip 25, and the terminals 13 are provided, and the two sets 16a and 16b are arranged in the Y direction. The number of sets 16a and 16b may be one, or three or more.

[0014] A semiconductor chip 20 and a passive element chip 25 are mounted on a base 11. The semiconductor chip 20 includes a substrate 21 and electrodes 22 to 24. The substrate 21 is, for example, a semiconductor substrate. The electrodes 22 and 23 are provided on the upper surface of the substrate 21. The electrode 24 is provided on the lower surface of the substrate 21. The passive element chip 25 includes a substrate 26 and electrodes 27 and 28. The substrate 26 is, for example, a dielectric substrate. The electrode 27 is provided on the upper surface of the substrate 26, and the electrode 28 is provided on the lower surface of the substrate 26. A conductive bonding layer 36 bonds the base 11 to the electrodes 24 and 28. The electrodes 24 and 28 are electrically connected to the base 11 and short-circuited. The bonding wire 31 electrically connects the terminal 12 to the electrode 23. The bonding wire 32 electrically connects the electrode 22 to the electrode 27. The bonding wire 33 electrically connects the electrode 27 to the terminal 13.

[0015] Bonding wires 41 to 44 are provided on the base 11. The bonding wire 41 is provided adjacent to the bonding wires 31 to 33 of the set 16a between the bonding wires 31 to 33 of the set 16a and the side of the base 11 located in the + direction in the Y direction. The bonding wire 42 is provided adjacent to the bonding wires 31 to 33 of the set 16a between the bonding wires 31 to 33 of the set 16a and the set 16b. The bonding wire 43 is provided adjacent to the bonding wires 31 to 33 of the set 16b between the bonding wires 31 to 33 of the set 16b and the set 16a. The bonding wire 44 is provided adjacent to the bonding wires 31 to 33 of the set 16b between the bonding wires 31 to 33 of the set 16b and the side of the base 11 located in the - direction in the Y direction.

[0016] FIG. 4 is a circuit diagram of one set in the semiconductor device according to the first embodiment. As shown in FIG. 4, the sets 16a and 16b include terminals 12 and 13, a transistor Q, inductors L1 to L3, and a capacitor C1. The transistor Q is, for example, a FET (Field Effect Transistor), and has a source S, a gate G, and a drain D. The inductors L3 and L2 are connected in series between the terminal 13 and the gate G. The capacitor C1 is shunt-connected to a node between the inductors L3 and L2. The source S is grounded. The inductor L1 is connected between the drain D and the terminal 12. The inductors L3, L2, and the capacitor C1 are an LCL type circuit, and form a matching circuit 18. The matching circuit 18 matches the impedance seen from the terminal 13 to the matching circuit 18 and the impedance seen from the matching circuit 18 to the transistor Q.

[0017] The transistor Q is provided on a semiconductor chip 20. The source S, gate G and drain D correspond to electrodes 24, 22 and 23, respectively. The electrode 22 is an input electrode to which a high frequency signal is input, and the electrode 23 is an output electrode to which a high frequency signal is output. The capacitor C1 is provided on a passive element chip 25, and corresponds to a substrate 26 and electrodes 27 and 28 that sandwich the substrate 26. The inductors L1, L2 and L3 correspond to bonding wires 31, 32 and 33, respectively.

[0018] The high frequency signal input to terminal 13 passes through matching circuit 18 and is input to gate G. The high frequency signal amplified by transistor Q passes through inductor L1 from drain D and is output to terminal 12. Inductor L1 may form a part of the matching circuit. When semiconductor device 100 is used in an amplifier circuit for a mobile communication base station, the frequency of the high frequency signal is, for example, 0.5 GHz to 10 GHz. The frequency of the high frequency signal may be 10 GHz or higher.

[0019] The transistor Q is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). When the transistor Q has a GaN HEMT, the substrate 21 is, for example, a silicon carbide substrate or a gallium nitride substrate. The electrodes 22 to 24 are, for example, metal layers such as gold layers.

[0020] When the passive element chip 25 has a capacitor C1, the substrate 26 is, for example, a dielectric substrate, such as an alumina (aluminum oxide) substrate, a high dielectric ceramic substrate having a higher dielectric constant than an alumina substrate, a silicon substrate, or a gallium arsenide substrate. The electrodes 27 and 28 are, for example, metal layers such as gold layers.

[0021] Fig. 5 is a flowchart showing a method for manufacturing the semiconductor device according to the embodiment 1. As shown in Fig. 5, a frame in which a plurality of lead frames 10 are connected by connection bars is prepared (step S10). In step S10, the semiconductor chip 20 and the passive element chip 25 are mounted on the base 11, and bonding wires 31 to 33 and 41 to 44 are joined.

[0022] Next, the frame is resin-sealed (step S12). In step S12, the frame is placed in a mold, and a resin that will become the resin layer 14 is injected into the mold using a transfer molding method. Next, the resin layer 14 and the frame are cut (step S14). This completes the semiconductor device 100 shown in FIGS. 1 to 3.

[0023] Next, the semiconductor device 100 is electrically inspected (step S16). In step S16, for example, an electrical short between the terminal 12 and the base 11 and an electrical short between the terminal 13 and the base 11 are inspected using a DC measuring device. Next, based on the inspection result in step S16, the semiconductor device 100 is judged as pass or fail (step S18). In step S18, for example, if the terminal 12 and the base 11 are electrically short-circuited or the terminal 13 and the base 11 are electrically short-circuited, the semiconductor device 100 is judged as failing, and if the terminal 12 and the base 11 are not electrically short-circuited and the terminal 13 and the base 11 are not electrically short-circuited, the semiconductor device 100 is judged as pass.

[0024] Next, in step S18, the semiconductor device 100 that has been determined to be acceptable is designated as an acceptable product (step S20). In step S20, if the semiconductor device 100 is deemed to be an acceptable product, for example, a mark is stamped on the semiconductor device 100.

[0025] [Comparative Example 1] FIG. 6 is a cross-sectional view of the semiconductor device according to Comparative Example 1. FIG. 7 is a cross-sectional view taken along the line AA in FIG. 6. As shown in FIGS. 6 and 7, the semiconductor device 110 of Comparative Example 1 does not have the bonding wires 41 to 44. The resin layer 14 is formed by, for example, a transfer molding method. In step S12, among the multiple lead frames, there is a lead frame into which the resin is injected from the negative direction in the Y direction, as indicated by the arrow 50 in FIGS. 6 and 7. In this lead frame 10, the bonding wires 31 to 33 are tilted due to the flow of the resin. In the case where the resin layer 14 is provided by a method other than the transfer molding method, for example, a potting method, the bonding wires 31 to 33 may be tilted when the resin flows.

[0026] 7, the bonding wire 32a is shown before the resin is injected, and the bonding wire 32 is shown after the resin is injected. The bonding wire 32 is inclined at an angle θ1. When the bonding wire 32 is inclined, the high frequency characteristics of the bonding wire 32 change. Also, if the angle θ1 is too large, there is a possibility of shorting with other components. Therefore, if it is attempted to inspect the inclination of the bonding wire 32, an expensive device such as an X-ray inspection device will be used.

[0027] [Description of Example 1] FIG. 8 is a cross-sectional view of the semiconductor device according to the first embodiment. As shown in FIG. 8, when the bonding wire 32 is tilted, the bonding wire 32 comes into contact with the bonding wires 41 and 43. This causes an electrical short circuit between the terminal 13 and the base 11. Therefore, in step S16 of FIG. 5, an electrical short circuit between the terminal 13 and the base 11 is inspected. In step S18, if the terminal 13 and the base 11 are electrically shorted, the semiconductor device is determined to be unsuccessful. In this manner, the tilt of the bonding wire 32 can be inspected.

[0028] According to the first embodiment, as shown in Figs. 1 to 3, the terminal 12 (first terminal) is connected to the bonding wire 31 (first bonding wire) in a DC manner, and the terminal 13 (first terminal) is connected to the bonding wires 32 and 33 (first bonding wires) in a DC manner. The base 11 (second terminal) is connected to the bonding wires 41 to 44 (second bonding wires) in a DC manner. The base 11 is not connected to the terminals 12 and 13 in a DC manner. As a result, by detecting a DC short circuit between the terminals 12 and 13 and the base 11 in step S16, the inclination of the bonding wires 31 to 33 can be detected in step S18.

[0029] FIG. 9 is a side view of the bonding wire in the first embodiment as viewed from the Y direction. FIG. 10 is a side view of the bonding wire in the first embodiment as viewed from the X direction. FIG. 11 is a plan view of the bonding wire in the first embodiment. In FIG. 9 to FIG. 11, the bonding wire 30 corresponds to the bonding wires 31 to 33, and the bonding wire 40 corresponds to the bonding wires 41 to 44. The apexes of the bonding wires 30 and 40 are P3 and P4, respectively. The heights of the bonding wires 30 and 40 are H3 and H4, respectively. The apexes P3 and P4 of the bonding wires 30 and 40 are the farthest points from the base 11 of the bonding wires 30 or 40 to be treated. The height of the bonding wires 30 and 40 is the height in the Z direction between the lower one of both ends of the bonding wires 30 or 40 to be treated (the one closer to the base 11) and the apex P3 or P4.

[0030] 10, bonding wires 30 and 40 are not in contact with each other, and when bonding wire 30 is tilted toward bonding wire 40, bonding wire 30 can come into contact with bonding wire 40. This allows the tilt of bonding wire 30 to be detected by detecting the electrical contact between bonding wires 30 and 40.

[0031] When the bonding wire 30 is inclined from the Z direction toward the bonding wire 40 at an angle θ1, the bonding wire 30 can contact the bonding wire 40. The angle θ1 can be, for example, 45° or less, 30° or less, or 15° or less. When the angle θ1 is large, the high-frequency characteristics of the bonding wire 30 change significantly. Therefore, by making the angle θ1 small, the change in the high-frequency characteristics of the bonding wire 30 can be detected with high accuracy. When the angle θ1 is too small, the bonding wires 30 and 40 will come into contact with each other even if the inclination of the bonding wire 30 is within the manufacturing error range. From this viewpoint, the angle θ1 can be 5° or more.

[0032] The shortest distance between the bonding wires 30 and 40 is set as distance D1. In Fig. 9 to Fig. 11, the distance between vertices P3 and P4 is assumed to be the shortest distance D1. By making distance D1 smaller than height H3, the bonding wires 30 and 40 are more likely to come into contact with each other when the bonding wire 30 tilts. Distance D1 can be set to 1 time or less of height H3, 3 / 4 or less, or 1 / 2 or less.

[0033] In order to make it possible to contact the bonding wire 40 when the bonding wire 30 is tilted, the bonding wire 40 is made asymmetric. When the length of the bonding wire 40 as viewed from the Z direction is D2, the position of 1 / 3×D2 from the end closer to the bonding wire 30 among both ends of the bonding wire 40 as viewed from the Z direction is Q3, the position of 1 / 4×D2 is Q4, and the position of 1 / 5×D2 is Q5. As viewed from the Z direction, the apex P4 is located closer to the bonding wire 30 than the position Q3. That is, when the bonding wire 40 is divided into three parts as viewed from the Z direction, the apex P4 is located at the part closest to the bonding wire 30 among the three divided parts. The apex P4 may be located closer to the bonding wire 30 than the position Q4, or may be located closer to the bonding wire 30 than the position Q5. In this way, by making the bonding wire 40 asymmetric, the shortest distance D1 can be made smaller.

[0034] If the height H4 is too low, even if the bonding wire 30 is tilted, it will not come into contact with the bonding wire 40. From this viewpoint, the height H4 can be set to 0.5 times or more, and can be set to 0.8 times or more, the height H3.

[0035] 12 is a plan view of the bonding wire in Example 1. When viewed from the Z direction, the angle between the extension direction of the bonding wire 30 and the extension direction of the bonding wire 40 is θ2. The angle θ2 does not have to be 90°. It is sufficient that the extension direction of the bonding wire 30 and the extension direction of the bonding wire 40 intersect. From the viewpoint of reducing the influence of the bonding wire 40 on the high-frequency characteristics of the bonding wire 30, the angle θ2 can be set to 45° or more, 60° or more, or 80° or more.

[0036] 8, at least two bonding wires 41 and 42 are provided to sandwich the bonding wire 32. This makes it possible to detect the inclination of the bonding wire 32 regardless of whether the bonding wire 32 is inclined in the + direction or the - direction in the Y direction.

[0037] Both ends of the bonding wires 41 to 44 are bonded to the base 11. This allows the bonding wires 41 to 44 to be at a reference potential. This allows the tilt of the bonding wires 31 to 33 to be detected by detecting an electrical short between the base 11 and the terminal 12 or 13.

[0038] When the bonding wires 31 to 33 transmit high-frequency signals, tilting the bonding wires 31 to 33 changes the high-frequency characteristics of the bonding wires 31 to 33. Therefore, by providing bonding wires 41 to 44 adjacent to the bonding wires 31 to 33, the change in the high-frequency characteristics of the bonding wires 31 to 33 can be detected.

[0039] If the high frequency characteristics of the bonding wire 32 electrically connecting the semiconductor chip 20 and the passive element chip 25 change, it is not possible to adjust the characteristics of the matching circuit 18 from outside the semiconductor device 100. Therefore, it is important to detect the inclination of the bonding wire 32. Therefore, bonding wires 41 and 42 adjacent to the bonding wire 32 are provided.

[0040] [Example 2] FIG. 13 is a plan view of the semiconductor device according to the second embodiment. FIG. 14 is a cross-sectional view taken along the line AA of FIG. 13. As shown in FIGS. 13 and 14, in the semiconductor device 102 according to the second embodiment, electrodes 27a and 27b are provided on the upper surface of the passive element chip 25. The bonding wire 34 electrically connects the electrodes 27a and 27b. The bonding wire 32 electrically connects the electrodes 22 and 27a. The bonding wire 33 electrically connects the electrode 27b and the terminal 13. The electrode 29 is provided on the substrate 26 so as to sandwich the bonding wire 34 in the Y direction. The bonding wire 45 is bonded onto the electrode 29. The via 29a penetrates the substrate 26, electrically connects the electrodes 28 and 29, and shorts them. As a result, the bonding wire 45 has the same potential as the base 11.

[0041] FIG. 15 is a circuit diagram of one set in the semiconductor device according to the second embodiment. As shown in FIG. 15, an inductor L4 is connected in series between inductors L2 and L3. A capacitor C1 is shunt-connected between inductors L2 and L4. A capacitor C2 is shunt-connected between inductors L4 and L3. The inductors L2 to L4 and the capacitors C1 and C2 form a matching circuit 18. The capacitors C1 and C2 are provided on a passive element chip 25. The inductor L4 corresponds to a bonding wire 34 that electrically connects the electrodes 27a and 27b. The capacitor C1 corresponds to the substrate 26 and the electrodes 27a and 28 that sandwich the substrate 26. The capacitor C2 corresponds to the substrate 26 and the electrodes 27b and 28 that sandwich the substrate 26. The other configurations are the same as those of the first embodiment, and will not be described.

[0042] When both ends of the bonding wire 34 are bonded onto one passive element chip 25 as in the second embodiment, it is difficult to provide a bonding wire adjacent to the bonding wire 34 on the base 11. Therefore, of both ends of the bonding wire 45, a first end closer to the bonding wire 34 is bonded onto the passive element chip 25. This makes it possible to detect the inclination of the bonding wire 34.

[0043] [Example 3] FIG. 16 is a plan view of a semiconductor device according to a third embodiment. As shown in FIG. 16, in a semiconductor device 104 of the third embodiment, a semiconductor chip 20 and a passive element chip 25 are mounted on a base 11. A conductive layer 48 is provided on the base 11 with an insulating layer sandwiched therebetween. Terminals 12 and 13 are provided on the conductive layer 48 in electrical contact with each other. The bonding wires 31 to 33 are connected in the same manner as in the first embodiment. A passive element chip 25a is provided on the base 11. The passive element chip 25a includes a substrate 26 and an electrode 27. The electrode 27 and the conductive layer 48 are electrically connected by a bonding wire 35. Bonding wires 46 are provided on the base 11 so as to sandwich the bonding wire 35 in the Y direction.

[0044] The bonding wire 35 and the passive element chip 25a form a VBW (Video Band Width) circuit 19. The VBW circuit 19 passes signals of frequencies lower than the operating band among the high-frequency signals flowing through the terminal 12 to the ground, and does not pass signals in the operating band to the ground. For this reason, the passive element chip 25a has a large capacitance to pass low-frequency signals. The bonding wire 35 has a large inductance to prevent high-frequency signals in the operating band from passing. For this reason, the bonding wire 35 becomes long and is easily tilted when the resin is injected. Therefore, the tilt of the bonding wire 35 can be detected by providing bonding wires 46 so as to sandwich the bonding wire 35 in the Y direction. The other configurations are the same as those in the first embodiment, and the description will be omitted.

[0045] In the third embodiment, the bonding wire 35 is the longest of the bonding wires 31 to 33 and 35 that transmit signals. In this case, a bonding wire 46 is provided adjacent to the bonding wire 35. This makes it possible to detect the inclination of the bonding wire 35.

[0046] Of the bonding wires 31 to 33 and 35 that transmit signals, the shortest bonding wire 31 is less likely to tilt. Therefore, there is no need to provide a bonding wire adjacent to the bonding wire 31. In this way, at least one of the bonding wires 31 to 33 that transmit signals other than the longest bonding wire 35 does not have an adjacent bonding wire 41 to 44. This allows for miniaturization.

[0047] In the first to third embodiments, examples have been described in which high-frequency signals are transmitted to the bonding wires 31 to 35, but the bonding wires 31 to 35 may transmit signals other than high-frequency signals, or may be supplied with a reference potential. When the bonding wires 31 to 35 transmit high-frequency signals, the high-frequency signals of the bonding wires 31 to 35 are likely to change if the bonding wires 31 to 35 are tilted. Therefore, bonding wires 41 to 46 are provided adjacent to the bonding wires 31 to 35 through which high-frequency signals flow.

[0048] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0049] 10 Lead frame 11. Base 12, 13 Terminals 14 Resin layer Set 16a, 16b 18 Matching circuit 19 VBW circuit 20. Semiconductor Chips 21, 26 Board 22, 23, 24, 27, 27a, 27b, 28, 29 electrode 25, 25a Passive element chip 29a Via 30, 31, 32, 33, 34, 35, 40, 41, 42, 43, 44, 45, 46 Bonding wire 36 Bonding layer 48 Conductive Layer 50 Arrow 100, 102, 104, 110 Semiconductor device

Claims

1. With the base, one or more chips including a semiconductor chip disposed on the base; a first bonding wire connected to at least one of the one or more chips; a second bonding wire extending in a direction intersecting the extending direction of the first bonding wire as viewed from a thickness direction of the base; a resin layer provided on the base and sealing the one or more chips, the first bonding wires, and the second bonding wires; A semiconductor device in which the first bonding wire and the second bonding wire are not in contact with each other, and when the first bonding wire is tilted toward the second bonding wire, the first bonding wire can come into contact with the second bonding wire.

2. a first terminal connected to the first bonding wire in a DC manner; a second terminal connected to the second bonding wire in a DC manner; Equipped with 2. The semiconductor device according to claim 1, wherein the first terminal and the second terminal are not connected in a DC manner.

3. 3. The semiconductor device according to claim 1, wherein the first bonding wire is capable of contacting the second bonding wire when the first bonding wire is inclined by 45 degrees or more from the thickness direction of the base toward the second bonding wire.

4. A semiconductor device as described in claim 1 or claim 2, wherein the point of the second bonding wire farthest from the base is located at the part of the second bonding wire closest to the first bonding wire when the second bonding wire is divided into three parts when viewed in the thickness direction of the base.

5. 3. The semiconductor device according to claim 1, wherein an angle between an extending direction of the first bonding wire and an extending direction of the second bonding wire is 45 degrees or more when viewed from a thickness direction of the base.

6. 3. The semiconductor device according to claim 1, wherein at least two of the second bonding wires are provided so as to sandwich the first bonding wire therebetween.

7. 3. The semiconductor device according to claim 1, wherein both ends of the second bonding wire are bonded to the base.

8. both ends of the first bonding wire are bonded onto one of the one or more chips; 3. The semiconductor device according to claim 1, wherein a first end of said second bonding wire, which is closer to said first bonding wire, is bonded onto said one chip.

9. 3. The semiconductor device according to claim 1, wherein the first bonding wire is the longest of all the bonding wires that transmit signals.

10. 3. The semiconductor device according to claim 1, wherein the first bonding wire transmits a high frequency signal.

11. the one or more chips include the semiconductor chip and a passive element chip, The semiconductor device according to claim 10 , wherein the first bonding wire electrically connects the semiconductor chip and the passive element chip.

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