Delay control circuit, optical transmitter, and delay control method

Abstract

To provide a delay control technique for suppressing the timing deviation between different data signals input to a plurality of electrode segments provided in an optical modulator during operation.SOLUTION: A delay control circuit includes a delay circuit that imparts a predetermined delay to a signal input to a plurality of electrode segments provided in series along one or both of two waveguides of a Mach-Zehnder interferometer of an optical modulator, a monitor that monitors the power of a baud rate frequency component including a frequency of the same value as a baud rate or a beat frequency of the baud rate frequency component, from output light of the optical modulator, and a control circuit that controls the amount of delay of the delay circuit so that the monitored power of the baud rate frequency or the beat frequency is maximized.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present disclosure relates to a delay control circuit, an optical transmitter, and a delay control method. [Background technology]

[0002] A configuration has been considered in which a signal electrode divided into multiple segments is provided along one or both of the two waveguides that make up the Mach-Zehnder interferometer (MZI) of the optical modulator, and each electrode segment is driven independently for each bit that makes up a symbol. This driving method is called an "optical DAC" because a digital signal representing the value of each bit is input to the corresponding electrode segment of the MZI, and an analog signal is generated in the optical domain. A configuration has been proposed that adjusts the timing of the electrical signal provided to each electrode segment of the optical DAC modulator (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-24347 A Summary of the Invention [Problem to be solved by the invention]

[0004] In an optical DAC type optical modulator, the signal input timing between electrode segments is adjusted when shipped from the factory or when set up on site. In general, a test signal is input to the electrode segment to be adjusted, and the delay amount of each bit is manually adjusted while observing the eye pattern. During operation of the optical modulator, there is no means for monitoring the timing deviation of the signal input between the electrode segments. If the signal input timing is shifted between the electrode segments due to temperature changes in the usage environment, the signal waveform will deteriorate. The present disclosure provides a delay control technology that suppresses the timing deviation between different data signals input to multiple electrode segments provided in the optical modulator during operation. [Means for solving the problem]

[0005] In one embodiment, the delay control circuit comprises: a delay circuit that gives a predetermined delay to a signal input to a plurality of electrode segments that are provided in series along one or both of two waveguides of a Mach-Zehnder interferometer of the optical modulator; a monitor for monitoring the power of a baud rate frequency component including a frequency equal to or an integral multiple of the baud rate, or a beat frequency component of the baud rate frequency component, from the output light of the optical modulator; a control circuit for controlling the delay amount of the delay circuit so that the monitor power of the baud rate frequency component or the beat frequency component is maximized; Equipped with. Effect of the Invention

[0006] A delay control technique is realized that reduces the timing misalignment between different data signals input to multiple electrode segments on an optical modulator during operation. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic diagram of an optical transmitter including a delay control circuit according to a first embodiment. [Diagram 2] FIG. 13 is a diagram showing a baud rate frequency component included in the output of a photodetector. [Diagram 3] FIG. 13 is a diagram showing a data signal input to an electrode segment of an IQ modulator and a monitor output of a photodetector. [Figure 4] FIG. 2 is a constellation diagram on a complex plane. [Diagram 5] FIG. 13 is a diagram showing data signals input to two electrode segments of an I-phase MZI and an I-phase monitor output. [Figure 6] FIG. 13 is a diagram showing the significance of monitoring a frequency component having the same value as the baud rate. [Figure 7A] FIG. 13 is a diagram showing monitor outputs when there is no deviation in signal input timing between electrode segments. [Figure 7B]FIG. 13 is a diagram showing monitor outputs when there is a signal input timing difference between electrode segments. [Figure 8] FIG. 13 is a diagram showing frequency components extracted by a baud rate frequency filter. [Figure 9] FIG. 13 is a diagram showing the relationship between the timing difference between electrode segments and the intensity of the baud rate frequency component. [Figure 10] 1 is a flowchart of a delay control method. [Figure 11] FIG. 4 is a diagram illustrating an effect of delay control in the first embodiment. [Figure 12] FIG. 11 is a diagram illustrating a monitoring principle of the second embodiment. [Figure 13] FIG. 13 is a schematic diagram of an optical transmitter including a delay control circuit according to a second embodiment. [Figure 14] 13A to 13C are diagrams illustrating a monitoring principle of a third embodiment. [Figure 15] FIG. 13 is a schematic diagram of an optical transmitter including a delay control circuit according to a third embodiment. [Figure 16] FIG. 13 is a diagram showing components whose power is monitored in the third embodiment. [Figure 17] FIG. 13 is a diagram showing the relationship between the timing difference between electrode segments and the intensity of the beat frequency component. [Figure 18] FIG. 13 is a schematic diagram of an optical transmitter including a delay control circuit according to a fourth embodiment. [Figure 19] FIG. 13 is a diagram showing the relationship between the timing difference between electrode segments and the intensity of the baud rate frequency component. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In an embodiment, during operation of the optical transmitter, the input timing of different data signals, i.e., signals of different bits, input to multiple electrode segments of the optical modulator is adjusted. To achieve this, a frequency component with the same value as the baud rate or its beat frequency is monitored, and the delay amount of each data signal is controlled so that the monitored power is maximized. For example, when the baud rate, i.e., the modulation speed, is 64 Gbaud, the 64 GHz frequency component of the output light of the optical modulator or its beat frequency is monitored, and the timing of the input data is adjusted based on the monitoring result.

[0009] The specific configuration and method of delay control of the embodiment will be described below with reference to the drawings. The embodiment shown below is an example for embodying the technical idea of ​​the present disclosure, and does not limit the disclosed contents. The size, positional relationship, etc. of the components shown in each drawing may be exaggerated to facilitate understanding of the invention. The same components or functions may be given the same names or symbols, and duplicate explanations may be omitted.

[0010] (First embodiment) FIG. 1 is a schematic diagram of an optical transmitter 1 including a delay control circuit 10 of the first embodiment. The optical transmitter 1 includes a digital signal processor (DSP) 5, an optical modulator 7, a delay control circuit 10 that controls the delay amount of a data signal input to the optical modulator 7, and a photodetector 9 that detects a part of the output light of the optical modulator 7. Digital drivers 6-1 and 6-2 are arranged between the delay control circuit 10 and the optical modulator 7, and output a digital drive signal that drives the optical modulator 7 based on the data signal delayed and adjusted by the delay control circuit 10. The DSP 5, the delay control circuit 10, and the digital drivers 6-1 and 6-2 are included in an electronic circuit. Meanwhile, the optical modulator 7 formed of an optical waveguide and a photodetector 130 that detects a part of the output light of the optical modulator 7 are included in an optical circuit. The photodetector 9 includes, for example, a photodiode (PD) and a transimpedance amplifier (TIA), and outputs a voltage signal.

[0011] The optical modulator 7 is an MZI type modulator formed of two optical waveguides 71 and 72. At least one of the optical waveguides 71 and 72 is provided with electrode segments corresponding to the data signal output from the DSP 5. In the example of FIG. 1, the DSP 5 outputs a bit 0 signal and a bit 1 signal. Bit 0 represents the lower bit, and bit 1 represents the upper bit. These signals are delayed and adjusted by the delay control circuit 10, and then input to the two electrode segments provided in the optical modulator 7.

[0012] The optical waveguide 71 of the optical modulator 7 is provided with electrode segments 711 and 712, and the optical waveguide 72 is provided with electrode segments 721 and 722. The electrode segments 711 and 712 and the electrode segments 721 and 722 function as phase shifters that change the refractive index of the optical waveguides 71 and 72 according to an input bit signal, thereby changing the phase of light passing through the optical waveguides 71 and 72. The length of the electrode segments 712 and 722 (denoted as "seg.2" in the figure) is set to twice the length of the electrode segments 711 and 721 (denoted as "seg.1" in the figure). As a result, the amount of phase change in seg.2 is twice the amount of phase change in seg.1.

[0013] Electrode segments 711 and 721 are push-pull driven by receiving positive and negative phase signals generated by digital driver 6-1, respectively. Electrode segments 712 and 722 are push-pull driven by receiving positive and negative phase signals generated by digital driver 6-2, respectively. When the push-pull driving method is not used, seg.1 and seg.2 may be provided on only one of optical waveguides 71 and 72.

[0014] 1 employs an "optical DAC" in which an electrical digital signal is input to each of the electrode segments seg.1 and seg.2 of the optical modulator 7, and an optical analog signal is generated by the optical modulator 7. However, the "optical DAC" is merely one application example of the delay control of the embodiment, and the delay control technology of the present disclosure is also applicable to optical transmitters other than those using the optical DAC system.

[0015] The delay amount of the bit 0 signal and the bit 1 signal is controlled so that bit 0 is input to seg.1 at the timing when the light incident on the optical modulator 7 passes through seg.1, and bit 1 is input to seg.2 at the timing when the light passes through seg.2. This signal input timing adjustment is performed by monitoring part of the output light of the optical modulator 7 with a photodetector 9 and using the monitoring result by a delay control circuit 10.

[0016] The delay control circuit 10 has a delay circuit 11, a baud rate frequency filter 12, a power monitor 13, and a control circuit 15. The delay circuit 11 has delay adjusters 111 and 112 that individually adjust the delay amount of each bit signal output from the DSP 5. The baud rate frequency filter 12 extracts a frequency having the same value as the baud rate or an integer multiple of the baud rate (these frequency components are called "baud rate frequency components") from the output of the photodetector 9. The power monitor 13 monitors the power of the electrical signal having the baud rate frequency. The control circuit 125 controls the delay amounts of the delay adjusters 111 and 112 so that the power of the baud rate frequency component monitored by the power monitor 13 is maximized.

[0017] As will be described later, the power of the baud rate frequency component correlates with the amount of deviation in the input timing of the data signal given to the electrode segments seg.1 and seg.2 of the optical modulator 7. Therefore, by monitoring the baud rate frequency component from the output light of the optical modulator 7 during operation and adjusting the amount of delay so that the power of the baud rate frequency component is maximized, the input timing between different data can be optimized.

[0018] FIG. 2 is a diagram showing the baud rate frequency components included in the output of the photodetector 9. The power spectrum of the electrical signal output from the photodetector 9 is extinguished at regular frequency intervals, i.e., at a regular cycle. A sharp peak appears at or near the frequency of extinction. The peaks in the power spectrum that appear after the extinction are harmonic components. For example, when the baud rate is 64 Gbaud, the power spectrum has a peak at 64 GHz, and peaks appear at 128 GHz and 192 GHz at 64 GHz intervals. The peaks that appear every 64 GHz correspond to the cycle of switching between bits when the light phase-modulated by the optical modulator 7 is detected as electrical power by the photodetector 9. This will be explained in more detail with reference to FIG. 3 to FIG. 6.

[0019] Figure 3 shows the IQ modulator 7 IQ The data signal input to the electrode segments and the monitor output of the photodetector are shown in Fig. 7. IQ is a nested optical modulator in which an I-phase MZ modulator 7I and a Q-phase MZ modulator 7Q are connected in parallel to form a parent MZ modulator 7M. A part of the output light from the I-phase MZ modulator 7I is branched and enters a photodetector 9I as monitor light. The result of the detection of the monitor light by the photodetector 9I is input to an I-phase delay control circuit 10 (see FIG. 1) and used for I-phase delay control. A part of the output light from the Q-phase MZ modulator 7Q is branched and enters a photodetector 9Q as monitor light. The result of the detection of the monitor light by the photodetector 9Q is used for Q-phase delay control.

[0020] Electric fields of two different intensities are applied to each of the I-phase MZ modulator 7I and the Q-phase MZ modulator 7Q, generating four types of signals (2 intensities x 2 phases) with two phases (0 radians and π radians). A phase difference of 90° (π / 2) is given between the light passing through the I-phase MZ modulator 7I and the light passing through the Q-phase MZ modulator 7Q, and the lights are combined to generate a QAM (quadrature amplitude modulation) optical signal, which is output to the IQ modulator 7 IQ is output from

[0021] FIG. 4 is a constellation diagram on a complex plane. A 2-intensity × 2-phase signal generated by the I-phase MZ modulator 7I can be expressed on the I-axis as, for example, 3π / 16, π / 16, -π / 16, and -3π / 16. In FIG. 4, "π / 16" is omitted, and values ​​representing the signal state are simply written as 3, 1, -1, and -3. A 2-intensity × 2-phase signal generated by the Q-phase MZ modulator 7Q and given a phase difference of π / 2 is expressed as 3j, 1j, -1j, and -3j on the Q-axis. 16 signal points are identified on the complex plane by the combination of the four types of I-phase signals and the four types of Q-phase signals.

[0022] Figure 5 shows two data signals input to two electrode segments of the I-phase MZ modulator 7I, and the I-phase monitor output. Figure 5 (a) shows the signal waveform of data I1 input to the electrode segment (seg.1) for the lower bits, (b) shows the signal waveform of data I2 input to the electrode segment (seg.2) for the higher bits, and (c) shows the output waveform of the I-phase photodetector 9I. Data I1 is an NRZ signal, and its intensity is represented, for example, by "1" and "-1". Data I2 is an NRZ signal, and its intensity is represented, for example, by "2" and "-2".

[0023] The amplitude of the modulated light output from the I-phase MZ modulator 7I takes on any one of the following values, depending on the combination of data I1 and data I2: 3, 1, -1, or 1. However, as shown in (c) of Fig. 5, photodetector 9I detects the "power" (the square of the amplitude) of the modulated light, so whether the amplitude of the modulated light is -3 or 3, it is detected as the same power.

[0024] FIG. 6 is a diagram showing the significance of monitoring the baud rate frequency component having the same value as the baud rate. When the output light of the MZ modulator 7I is monitored by the photodetector 9I including the PD, the optical power is detected and the phase information of the optical signal is lost. With the 2-bit data input, the modulated light of the I phase can take four values, 3, 1, -1, and -3, but the monitor result at the photodetector 9I is two values, "1" or "3". Focusing on the relationship between "-3" and "3", when the same modulation value, for example, "3" or "-3", occurs consecutively, the monitor power does not return to zero but maintains the peak level. On the other hand, when the modulated light transitions between "-3" and "3", the signal of "-3" is inverted to "3" in the optical power detection, but the actual modulated light passes through "0". Therefore, in the region of interest enclosed by the thick dashed line in Figure 6, when the signal value transitions from "-3" to "3" or from "3" to "-3", a dip occurs between the peaks where the monitor power becomes zero. The interval t (or pulse width) of the dips represents the period of the pulse that changes from "zero power → peak → zero power" within one bit, and corresponds to the modulation speed. For example, when a transmission speed of 128 bps is achieved with 2 bits, the modulation speed is 64 Gbaud. The interval of the dips, i.e., the pulse width that switches in one cycle per bit, is 15.625 picoseconds, and in the frequency domain, the peaks are at 64 GHz and its integer multiples. The baud rate frequency and its integer multiples are collectively called the "baud rate frequency components."

[0025] If the input timing of the signal given to each electrode segment is shifted, the signal inversion, i.e., the bit switching state, changes in the power detection by the photodetector 9, and the intensity of the peak that appears at the baud rate frequency (64 GHz in this example) or its integer multiple changes. Therefore, by observing the change in the power of the baud rate frequency component, the signal input timing between the electrode segments can be adjusted.

[0026] Figure 7A shows the monitor output when there is no (or minimal) deviation in the signal input timing between the electrode segments. Figure 7B shows the monitor output when there is a deviation in the signal input timing between the electrode segments. When there is no or minimal deviation in the signal input timing between the electrode segments as in Figure 7A, the peak of the pulse that occurs with the same period as the interval between dips will be maximum. In contrast, when the signal input timing to the electrode segments is deviated by 8 picoseconds, the intensity of the pulse that changes from dip to peak to dip within one bit will decrease. As a result, the power of the baud rate frequency component in the power spectrum will decrease.

[0027] Fig. 8 shows the frequency components extracted by the baud rate frequency filter 12. Fig. 9 shows the relationship between the timing difference between the electrode segments and the strength of the baud rate frequency component. As described above, the monitoring strength of the baud rate frequency component depends on the timing deviation of the input signal. When signals with different bits are input between the electrode segments, such as in QAM modulation, the timing deviation between the electrode segments can be detected by monitoring the power of the baud rate frequency component, and the delay can be controlled in the direction of reducing the timing deviation.

[0028] When the modulation speed is 64 Gbaud, the baud rate frequency filter 12 extracts, for example, a frequency component of 64 GHz±1 GHz. The delay control circuit 10 controls the delay amount of each input signal so that the power of this frequency component is maximized. If the timing at which the signal of bit 0 is input to seg.1 and the timing at which the signal of bit 1 is input to seg.2 are relatively synchronized, the signal of bit 0 is input at the timing at which the incident light to the optical modulator 7 passes through seg.1, and the signal of bit 1 is input at the timing at which the incident light passes through seg.2. In this case, the power of the monitored 64 GHz frequency component is maximized. If the timing of one signal input is earlier or later than the timing of the other signal input, the intensity of the 64 GHz frequency component decreases. This is because the accuracy of the dip->peak->dip switching due to signal inversion decreases due to a timing shift in the signal input.

[0029] The delay control circuit 10 monitors the power of the baud rate frequency component (64 GHz±1 GHz in this example) from the electrical output of the photodetector 9, and adjusts the delay amount of the delay adjusters 111 and 112 of the delay circuit 11 so that the monitored power is maximized.

[0030] (Delay control method) 10 is a flowchart of a delay control method executed by the delay control circuit 10. First, among two or more bits input to the optical modulator 7, a bit to be adjusted is selected, and the delay amounts of the other bits are fixed (S1). For example, the most significant bit that contributes most to modulation is selected first. Delay adjustment is then started with the selected bit (S2).

[0031] The delay amount of the delay adjuster corresponding to the bit to be controlled is set in a direction to increase or decrease (S3), and the delay amount is changed in the set direction by a predetermined step size (S4). Baud rate frequency filter 12 extracts the baud rate frequency component from the output of photodetector 9, and power monitor 13 monitors the power of the baud rate frequency component. Control circuit 15 determines whether the amount of change in the monitored value exceeds threshold value Th (S5).

[0032] If the amount of change in the monitored value is greater than the threshold value Th (YES in S5), it is determined whether the direction of change is an increase or decrease (S6). If the direction of change is a decrease, i.e., if the power of the monitored baud rate frequency component is decreasing, the direction of control is incorrect, so the process returns to step S3 and switches the delay amount adjustment direction to the opposite direction. If the direction of change is an increase, the direction of control is correct, so the process returns to step S4 and changes the delay amount in the set direction. If the amount of change in the monitored value has converged to within the threshold value Th (NO in S5), the delay amount is fixed to the setting at that time (S7), and setting of the delay amount for the current bit is completed (S8).

[0033] Next, it is determined whether the selected bit is the least significant bit (S9). If the selected bit is not the least significant bit (NO in S9), the next lower bit is selected (S10), and the processing from step S2 onwards is repeated. If the selected bit is the least significant bit (YES in S9), the process returns to step S1, and the processing from S1 to S10 is repeated during operation. By repeating steps S2 to S10, an adjustment cycle is completed for all bits constituting the data signal, and this is counted as one cycle of timing adjustment for all bits, and this adjustment cycle is repeated during operation.

[0034] In the delay control method of the embodiment, when adjusting the input timing between different bits, it is not necessary to stop the actual operation of the optical transmitter 1 and input a test signal. Since the input timing between different bits can be repeatedly adjusted using actual data in the background while the optical transmitter 1 is in operation, the signal quality of the multilevel optical signal can be maintained even if the environment such as temperature changes.

[0035] Fig. 11 is a diagram showing the effect of delay control in the first embodiment. Fig. 11(A) shows an eye pattern when there is a shift in input timing between different bits, i.e., between data signals input to different electrode segments. A PAM4 (Pulse Amplitude Modulation 4) signal for 16QAM transmission shown in Fig. 4 is generated using two bits, bit 0 and bit 1. When there is a shift in input timing between bit 0 and bit 1, the rise time of the signal is delayed, the eye opening changes, and the waveform deteriorates.

[0036] The delay control of FIG. 10 provides a good eye pattern as shown in FIG. 11B. By controlling the power of the monitored baud rate frequency component to be maximized, the delay amount for each signal of bit 0 and bit 1 is set correctly, and an almost uniform eye opening is obtained among the four levels. Even if the delay amount is set correctly at the time of shipment, the timing at which the signals of bit 0 and bit 1 are applied to the light passing directly under the electrode segments seg.1 and seg.2 may shift during operation due to variations in environmental temperature and process variations. Even in such a case, the delay control circuit 10 of the embodiment repeatedly performs delay control during operation, thereby maintaining good signal quality regardless of variations in the manufacturing process and installation environment.

[0037] Second embodiment FIG. 12 is a diagram showing the monitoring principle of the second embodiment. In the first embodiment, an electrical signal of the baud rate frequency (for example, 64 GHz) is extracted from the output of the photodetector 9 using the baud rate frequency filter 12, and its power is monitored. To monitor the power of a high-speed electrical signal of 64 GHz, a high-speed, high-precision frequency filter is required. In the second embodiment, an optical frequency component corresponding to the baud rate is extracted at the optical spectrum stage. For example, when the baud rate is 64 Gbaud, an optical frequency component that is 64 GHz away from the center frequency of the carrier wave on the plus or minus side is separated from the output light of the optical modulator. The separated optical frequency component is detected by the photodetector 9, and the power of the baud rate frequency component is monitored from the electrical output of the photodetector 9.

[0038] In FIG. 12, two-bit signals, data I1 and data I2, are input to two electrode segments provided on each arm of an MZ modulator (for example, the I-phase MZ modulator 7I in FIG. 3). The symbol rate, i.e., the modulation speed, is set to 64 GBaud. PD1 is connected to the signal output side of the MZ modulator 7I, and PD2 is connected to the monitor side, and the optical spectrum and electrical spectrum are compared on the signal output side and the monitor side. The 64 GHz component appears in the electrical spectrum of the signal light detected by PD1, but in the spectrum of the optical signal incident on PD1, the sharp peak is buried in the signal light power and cannot be observed. On the other hand, in the optical spectrum incident on PD2 on the monitor side, sharp peaks are observed at positions 64 GHz away from the center frequency (193.4 THz) of the carrier wave on both the positive and negative sides. By extracting this peak at the optical spectrum stage, it becomes easy to monitor the power of the 64 GHz component in the electrical signal.

[0039] FIG. 13 is a schematic diagram of an optical transmitter 1A including a delay control circuit 10A of the second embodiment. The optical transmitter 1A includes a DSP 5, a delay control circuit 10A, an optical modulator 7, an optical filter 8 that extracts a predetermined frequency component from the output light of the optical modulator 7, and a photodetector 9. Digital drivers 6-1 and 6-2 are arranged between the delay control circuit 10A and the optical modulator 7. The optical filter 8 arranged on the output side of the optical modulator 7 may have any configuration as long as it can extract a specific frequency component of light. For example, an optical filter in which asymmetric MZIs (AMZ: Asymmetric Mach-Zehnder interferometers) formed of silicon photonics waveguides are connected in series, or an optical filter having an AMZ triplet in which three AMZs are tree-connected as a unit structure can be used. In these optical filters, it is possible to transmit only light of a desired wavelength (i.e., frequency) by controlling the effective optical path length difference between the two waveguides of the AMZ.

[0040] The spectrum of the output light from the optical filter 8 includes peaks that appear at positions spaced apart from the center frequency of the carrier wave by the baud rate frequency on both sides. These peaks are optical signal components modulated by the digital signal input to the optical modulator 7. The photodetector 9 detects the light that has passed through the optical filter 8 and outputs an electrical signal. The electrical signal output from the photodetector 9 is input to the delay control circuit 10A, and the power is measured by the power monitor 13. The control circuit 15 controls the delay amounts of the delay adjusters 111 and 112 of the delay circuit 11 so that the power monitored by the power monitor 13 is maximized.

[0041] In the configuration of the second embodiment, the amount of delay between different bit signals input to the optical modulator 7 can be optimized by monitoring the power of the baud rate frequency component from the transmitted component of the optical filter 8 without using a high-performance electrical frequency filter.

[0042] Third embodiment FIG. 14 is a diagram showing the monitoring principle of the third embodiment. As described above, since separation of high-frequency electrical signals requires a high-precision frequency filter, in the third embodiment, the baud rate frequency component is converted to a low-frequency signal and the power is monitored. As described with reference to FIG. 6, the time waveform of the signal detected by the photodetector 9 has a dip where the power becomes zero at the point where the data value is inverted. The time interval of the dip, i.e., the pulse width, corresponds to the modulation period of 1 bit and 1 period. In the case of 64 GBaud, a peak appears at 64 GHz and its integer multiple in the electrical spectrum output from the photodetector 9. By interfering with another signal with a slightly different frequency with this 64 GHz frequency component, a beat frequency equal to the difference between the two frequencies can be extracted.

[0043] For example, multiplying a 64 GHz peak by a 60 GHz sine wave will give a 4 GHz beat frequency. By monitoring the power of this beat frequency, the delay between data I1 and data I2 can be controlled correctly.

[0044] 15 is a schematic diagram of an optical transmitter 1B including a delay control circuit 10B of the third embodiment. The optical transmitter 1B has a DSP 5, a delay control circuit 10B, an optical modulator 7, and a photodetector 9 that detects a part of the output light of the optical modulator 7. Digital drivers 6-1 and 6-2 are disposed between the delay control circuit 10B and the optical modulator 7. An electrical signal output from the photodetector 9 is input to the delay control circuit 10B.

[0045] The delay control circuit 10B includes a delay circuit 11, a power monitor 13, a control circuit 15, a multiplier 17, and a frequency generator 18. The frequency generator 18 generates a frequency slightly different from the baud rate frequency. For example, when the baud rate frequency is 64 GHz, the frequency generator 18 generates a frequency of 60 GHz. This 60 GHz frequency is used as a clock frequency for mixing. The multiplier 17 multiplies the electrical signal input from the photodetector 9 by the clock frequency of 60 GHz. As a result of this multiplication, a beat signal, which is the difference frequency between the 64 GHz component included in the output of the photodetector 9 and the clock frequency, is output from the multiplier 17.

[0046] The output of the multiplier 17 is supplied to the power monitor 13. The power monitor 13 monitors the power of the beat frequency. A frequency filter may be inserted between the multiplier 17 and the power monitor 13 to extract the 4 GHz frequency component. Compared to a 64 GHz electrical signal, it is easier to separate the 4 GHz electrical signal, making it easier to monitor the power for delay control.

[0047] 16 shows the components whose power is monitored in the third embodiment. The spectrum of the electrical signal output from the photodetector 9 contains a peak that stands out at the baud rate frequency (64 GHz in this example). By multiplying this electrical signal by a clock frequency of 60 GHz, a sharp peak appears at 4 GHz, which is the difference frequency. This low-frequency beat frequency is easier to separate than the baud rate frequency of 64 GHz, making it easy to monitor the power.

[0048] Figure 17 shows the relationship between the timing difference between the electrode segments and the intensity of the beat frequency component. If the input timing of data I2 to seg.2 is taken as the reference, when the input timing of data I1 to seg.1 matches the reference timing, the timing difference between the electrode segments is 0 ps. At this time, the power monitor intensity of the 4 GHz component is at its maximum. When the timing difference between the segments becomes large, that is, when the timing at which data I1 acts on the light passing through seg.1 becomes earlier or later than the input timing of data I2 to seg.2, the monitor power of the 4 GHz component decreases.

[0049] Control circuit 15 controls the delay amounts of delay adjusters 111 and 112 in delay circuit 11 so as to maximize the power of the beat frequency to be monitored. The configuration of the third embodiment makes it easy to monitor the power of the baud rate frequency component by extracting the beat frequency component.

[0050] (Fourth embodiment) 18 is a schematic diagram of an optical transmitter 1C including a delay control circuit 10C of the fourth embodiment. The number of bits input to the optical modulator is not limited to 2 bits, and a signal of 3 or more bits may be input to the optical modulator. In the fourth embodiment, the input timing between the data signals input to the three electrode segments is adjusted.

[0051] The optical transmitter 1C includes a DSP 5, an optical modulator 7C, a delay control circuit 10C that controls the amount of delay of a data signal input to the optical modulator 7C, and a photodetector 9 that detects a part of the output light of the optical modulator 7C. Digital drivers 6-1, 6-2, and 6-3 are disposed between the delay control circuit 10C and the optical modulator 7C, and drive the optical modulator 7C based on the data signal whose delay has been adjusted by the delay control circuit 10C.

[0052] The optical modulator 7C is an MZ modulator in which two optical waveguides 71 and 72 are connected between couplers 714 and 715. The optical waveguide 71 is provided with electrode segments 711, 712, and 713 for inputting the signals of bit 0, bit 1, and bit 2 output from the DSP 5. The optical waveguide 72 is provided with electrode segments 721, 722, and 723 for inputting the signals of bit 0, bit 1, and bit 2. In this example, both the two optical waveguides 71 and 72 are provided with electrode segments corresponding to the bit signals and are driven in a push-pull manner, but electrode segments may be provided on only one of the optical waveguides.

[0053] If the length of electrode segments 711 and 721 to which bit 0 is input is L, the length of electrode segments 712 and 722 to which bit 1 is input is set to 2L, and the length of electrode segments 713 and 723 to which bit 2 is input is set to 4L. The amount of phase change in electrode segments 712 and 722 is twice the amount of phase change in electrode segments 711 and 721, and the amount of phase change in electrode segments 713 and 723 is four times the amount of phase change in electrode segments 711 and 721.

[0054] The delay amount of the bit 0 signal is controlled so that the bit 0 signal is input to electrode segments 711 and 721 at the timing when the light incident on optical modulator 7C passes through electrode segments 711 and 721. The delay amount of the bit 1 signal is controlled so that the bit 1 signal is input to electrode segments 712 and 722 at the timing when the light passes through electrode segments 712 and 722. The delay amount of the bit 2 signal is controlled so that the bit 2 signal is input to electrode segments 713 and 723 at the timing when the light passes through electrode segments 713 and 723. Such adjustment of the signal input timing is performed by delay control circuit 10C based on the detection result by detecting a part of the output light from optical modulator 7C with photodetector 9.

[0055] The delay control circuit 10C has a delay circuit 11C, a baud rate frequency filter 12, a power monitor 13, and a control circuit 15. The delay circuit 11C has delay adjusters 111, 112, and 113 that individually adjust the delay amount of each bit signal output from the DSP 5. The baud rate frequency filter 12 extracts a baud rate frequency component, which is a frequency having the same value as the baud rate, from the output of the photodetector 9. The power monitor 13 monitors the power of the baud rate frequency component. The control circuit 15 controls the delay amounts of the delay adjusters 111, 112, and 113 so that the power of the baud rate frequency component monitored by the power monitor 13 is maximized.

[0056] The delay control circuit 10C performs the same delay control as the delay control circuit 10 of the first embodiment, except that it controls the delay amount of three bits. The baud rate is 64 Gbaud, the same as in the first embodiment. Since a three-bit signal is used here, the transmission rate is 192 Gbps. The 64 GHz component contained in the power spectrum of the output of the photodetector 9 is monitored, and the delay amounts of bit 0, bit 1, and bit 2 are adjusted so that the power is maximized. As described with reference to FIG. 10, the influence of bit 2, which has the largest modulation amount, is dominant, so it is preferable to adjust the timing starting from the delay amount of bit 2.

[0057] When a 3-bit signal is input, the configuration of the delay control circuit 10A of the second embodiment or the delay control circuit 10B of the third embodiment may be adopted. When the delay control circuit 10A of the second embodiment is used, an optical filter 8 is inserted between the coupler 715 and the photodetector 9, and the baud rate frequency component is extracted from the optical spectrum. When the delay control circuit 10B of the third embodiment is used, the electrical output of the photodetector 9 is multiplied by the clock frequency for mixing, and the power of the beat frequency component is monitored. In either case, a good signal waveform can be maintained during operation by controlling the delay amount so that the monitored power is maximized.

[0058] 19 shows the relationship between the timing difference between the electrode segments in the fourth embodiment and the intensity of the monitor light. The most significant bit 2 is data I2, the least significant bit 0 is data I0, and the middle bit 1 is data I1. The horizontal axis is the timing difference between the most significant two bits, data I2 and data I1. The vertical axis is the monitor light intensity at the baud rate frequency.

[0059] The solid line in the graph shows the timing difference dependency of the monitor light intensity when the timing difference between bit 2 and bit 0, i.e., data I2 and data I0, is 0 ps. The dashed line shows the timing difference dependency of the monitor light intensity when the timing difference between data I2 and data I0 is 2 ps. The dashed line shows the timing difference dependency of the monitor light intensity when the timing difference between data I2 and data I0 is 4 ps.

[0060] First, the delay amount is relatively controlled so that the timing difference between data I2 and data I1 approaches zero. With the timing difference between data I2 and data I1 adjusted to 0 ps or close to it, the delay amount is then controlled so that the timing difference between data I2 and data I0 approaches zero.

[0061] For example, if the timing difference between the top two data, I2 and I1, is 4 ps, and the timing difference between data I2 and I0 is 4 ps, it appears as if the timing between the three bits is aligned. However, if we focus on the input timing between data I2 and I1, the power of the monitored 64 GHz component is low. By changing the delay amount of data I2, the 64 GHz monitor optical power can be brought closer to its maximum. With the timing of data I2 and data I1 aligned, the delay is adjusted between data I2 and I0 so that the 64 GHz power is maximized. This aligns the signal input timing between the three bits.

[0062] Although the delay control focusing on the baud rate frequency based on a specific configuration example has been described above, the present disclosure is not limited to the above configuration. The baud rate is not limited to 64 Gbaud. When the baud rate is 32 Gbaud, the power of the 32 GHz component is monitored, and when the baud rate is 128 Gbaud, the power of the 128 GHz component is monitored. When the baud rate is high, the configurations of the second and third embodiments are advantageous. In the embodiment, an input signal of 2 or more bits is used, but this is not limited thereto, and it is also applicable to 1-bit binary phase modulation. In this case, the signal electrode may be divided into multiple electrode segments, and the same signal string may be applied to each electrode segment. By dividing the signal electrode into short electrode segments, the driving power of the optical modulator can be reduced, and the power consumption of the optical transmitter can be reduced. By repeatedly controlling the delay amount of the same bit signal applied to each divided power segment during operation, the signal waveform can be maintained good regardless of environmental fluctuations and process variations.

[0063] The method of the embodiment is a method of monitoring bit switching such as from "-3" to "3" and from "-1" to "1". As shown in Fig. 2, instead of a baud rate frequency with the same value as the baud rate, the power of an integer multiple of the baud rate frequency may be monitored. This is because the power of a frequency that is an integer multiple of the baud rate also depends on the timing difference between bits. In this case, the configurations of the second and third embodiments are advantageous because they can monitor the power without using a high-precision frequency filter.

[0064] In response to the above disclosure, the following remarks are presented: (Appendix 1) a delay circuit that gives a predetermined delay to a signal input to a plurality of electrode segments that are provided in series along one or both of two waveguides of a Mach-Zehnder interferometer of the optical modulator; a monitor for monitoring the power of a baud rate frequency component including a frequency equal to or an integral multiple of the baud rate, or a beat frequency component of the baud rate frequency component, from the output light of the optical modulator; a control circuit for controlling the delay amount of the delay circuit so that the monitor power of the baud rate frequency component or the beat frequency component is maximized; A delay control circuit comprising: (Appendix 2) a baud rate frequency filter that extracts the baud rate frequency component from an electrical output of a photodetector that detects a portion of the output light of the optical modulator; wherein the monitor monitors the power of the baud rate frequency component that has passed through the baud rate frequency filter. 2. The delay control circuit of claim 1. (Appendix 3) the delay control circuit receives as an input a detection result of an optical frequency component that is separated from a center frequency of a carrier wave included in the optical spectrum of the output light of the optical modulator by the baud rate frequency component; The monitor monitors the power of an electrical signal representing the detection result. 2. The delay control circuit of claim 1. (Appendix 4) a frequency generator for generating a clock frequency different from the baud rate frequency component; a multiplier for multiplying the baud rate frequency component by the clock frequency; the monitor monitors the power of the beat frequency component output from the multiplier. 2. The delay control circuit of claim 1. (Appendix 5) A digital signal processor; an optical modulator driven by a bit signal output from the digital signal processor; a delay control circuit for controlling a delay amount of the bit signal input to the optical modulator; a photodetector that detects a portion of the output light of the optical modulator and outputs the detection result to the delay control circuit; and the delay control circuit controls the delay amount of the bit signal so that a baud rate frequency component including a frequency having the same value as the baud rate or an integer multiple thereof, or a beat frequency component of the baud rate frequency component, contained in the detection result of the photodetector, is maximized. Optical transmitter. (Appendix 6) The delay control circuit includes a baud rate frequency filter that extracts the baud rate frequency component from the detection result of the photodetector, and a power monitor that monitors the power of the baud rate frequency component that has passed through the baud rate frequency filter. 6. The optical transmitter of claim 5. (Appendix 7) an optical filter that extracts an optical frequency component that is shifted from a center frequency of a carrier wave by a baud rate frequency component from the output light of the optical modulator; the photodetector detects the optical frequency component transmitted through the optical filter; the delay control circuit controls the delay amount of the bit signal so that the power of the baud rate frequency component included in the detection result of the photodetector is maximized. 6. The optical transmitter of claim 5. (Appendix 8) the delay control circuit has a frequency generator which generates a clock frequency different from the baud rate frequency component, and a multiplier which multiplies the baud rate frequency component by the clock frequency, and controls the delay amount of the bit signal so that the power of the beat frequency component output from the multiplier is maximized. 6. The optical transmitter of claim 5. (Appendix 9) The optical modulator includes a plurality of electrode segments arranged in series along one or both of two waveguides that constitute a Mach-Zehnder interferometer; the delay control circuit controls the delay amount of each of the plurality of bits output from the digital signal processor. 9. The optical transmitter according to any one of appendix 5 to 8. (Appendix 10) A delay amount of a signal input to a plurality of electrode segments arranged in series along one or both of two waveguides of a Mach-Zehnder interferometer of an optical modulator is changed, monitoring the power of a baud rate frequency component including a frequency equal to the baud rate or an integral multiple thereof, or a beat frequency component of the baud rate frequency component, from the output light of the optical modulator; setting the delay amount to a value that maximizes the power of the monitored baud rate frequency component or the monitored beat frequency component; Delay control method. (Appendix 11) detecting a portion of the output light of the optical modulator with a photodetector; extracting the baud rate frequency component from the electrical output of the photodetector; 11. The delay control method according to claim 10. (Appendix 12) extracting an optical frequency component that is separated from a center frequency of a carrier wave included in the optical spectrum of the output light of the optical modulator by the baud rate frequency component using an optical filter; Detecting the optical frequency component transmitted through the optical filter with a photodetector; monitoring the power of an electrical signal representing the optical frequency component from the detection result of the optical detector; 11. The delay control method according to claim 10. (Appendix 13) generating a clock frequency different from the baud rate frequency component; multiplying the clock frequency by the baud rate frequency component to extract the beat frequency component; monitoring the power of the beat frequency components; 11. The delay control method according to claim 10. [Explanation of symbols]

[0065] 1, 1A, 1B, 1C Optical Transmitter 5 DSP 6-1, 6-2, 6-3 Binary Driver 7, 7C Optical Modulator 7I I-phase MZ modulator 7Q Q-phase MZ modulator 7M Parent MZ Modulator 711, 712, 713, 721, 722, 723 Electrode Segments 8 Optical Filters 9. Photodetector 10, 10A, 10B, 10C Delay control circuit 11, 11C Delay circuit 111, 112, 113 Delay adjuster 12 Baud rate frequency filter 13 Power Monitor 15 Control circuit 17 Multiplier 18 Frequency Generator

Claims

1. a delay circuit for applying a predetermined delay to a signal input to a plurality of electrode segments provided in series along one or both of two waveguides of a Mach-Zehnder interferometer of the optical modulator; a monitor for monitoring the power of a baud rate frequency component including a frequency equal to or an integral multiple of the baud rate, or a beat frequency component of the baud rate frequency component, from the output light of the optical modulator; a control circuit for controlling the delay amount of the delay circuit so that the monitor power of the baud rate frequency component or the beat frequency component is maximized; A delay control circuit comprising:

2. a baud rate frequency filter that extracts the baud rate frequency component from an electrical output of a photodetector that detects a portion of the output light of the optical modulator; wherein the monitor monitors the power of the baud rate frequency component that has passed through the baud rate frequency filter.

2. The delay control circuit of claim 1.

3. the delay control circuit receives as an input a detection result of an optical frequency component that is separated from a center frequency of a carrier wave included in the optical spectrum of the output light of the optical modulator by the baud rate frequency component; The monitor monitors the power of an electrical signal indicative of the detection result.

2. The delay control circuit of claim 1.

4. a frequency generator for generating a clock frequency different from the baud rate frequency component; a multiplier for multiplying the baud rate frequency component by the clock frequency; the monitor monitors the power of the beat frequency component output from the multiplier.

2. The delay control circuit of claim 1.

5. A digital signal processor; an optical modulator driven by a bit signal output from the digital signal processor; a delay control circuit for controlling a delay amount of the bit signal input to the optical modulator; a photodetector that detects a portion of the output light of the optical modulator and outputs the detection result to the delay control circuit; and the delay control circuit controls the delay amount of the bit signal so that a baud rate frequency component including a frequency having the same value as the baud rate or an integer multiple thereof, or a beat frequency component of the baud rate frequency component, contained in the detection result of the photodetector, is maximized. Optical transmitter.

6. The delay control circuit includes a baud rate frequency filter that extracts the baud rate frequency component from the detection result of the photodetector, and a power monitor that monitors the power of the baud rate frequency component that has passed through the baud rate frequency filter.

6. The optical transmitter according to claim 5.

7. an optical filter that extracts an optical frequency component that is shifted from a center frequency of a carrier wave by a baud rate frequency component from the output light of the optical modulator; the photodetector detects the optical frequency component transmitted through the optical filter; the delay control circuit controls the delay amount of the bit signal so that the power of the baud rate frequency component included in the detection result of the photodetector is maximized.

6. The optical transmitter according to claim 5.

8. the delay control circuit has a frequency generator which generates a clock frequency different from the baud rate frequency component, and a multiplier which multiplies the baud rate frequency component by the clock frequency, and controls the delay amount of the bit signal so that the power of the beat frequency component output from the multiplier is maximized.

6. The optical transmitter according to claim 5.

9. changing a delay amount of a signal input to a plurality of electrode segments provided in series along one or both of two waveguides of a Mach-Zehnder interferometer of an optical modulator; monitoring the power of a baud rate frequency component including a frequency equal to the baud rate or an integral multiple thereof, or a beat frequency component of the baud rate frequency component, from the output light of the optical modulator; setting the delay amount to a value that maximizes the power of the monitored baud rate frequency component or the monitored beat frequency component; Delay control method.

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