Semiconductor device

Abstract

To provide a semiconductor device that can ensure heat dissipation performance, reduce path impedance, and ensure isolation distance.SOLUTION: In a semiconductor device having a semiconductor element on a substrate with a conductive pattern, the semiconductor element has a plurality of electrodes on the first surface and electrodes on the second surface, and each of the plurality of electrodes on the first surface is bonded to the conductive pattern of the substrate via conductive spacers, and the electrodes on the second surface are bonded to the pad surface of conductive clip leads.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A typical semiconductor device is manufactured by electrically connecting a semiconductor element to a circuit board on which a metal pattern is formed or a lead frame with inner leads, and then sealing the semiconductor element with resin. In particular, power chips such as transistors and diodes that handle high power, which are typical semiconductor elements, are mainly soldered to the metal pattern in a reflow process. In addition, when there is a power chip and a control chip such as a control IC that does not handle as much power as the power chip, it is common to place them in different positions on the circuit board or in different areas of the lead frame. In addition, the control chip may be connected with a conductive adhesive instead of soldering.

[0003] It is expected that power chips (hereinafter referred to as semiconductor elements or simply chips) will handle increasingly large amounts of power as their applications expand, but at the same time, technology for increasing integration density and miniaturization is also advancing.

[0004] FCB (Flip Chip Bonding) technology has been disclosed for increasing the degree of integration. In FCB, the electrodes on the first surface of a power chip, which has electrodes on both sides, are mounted on a first substrate, then the chip is flipped 180 degrees and the electrodes on the second surface of the power chip are bonded to a second substrate (see Patent Document 1). FCB requires less space than conventional WB (Wire Bonding), and is known to have less inductance components and is suitable for high frequencies due to the shorter wiring length.

[0005] For miniaturization, a technology of Cu pillars (multiple arrangements of Cu pillar-shaped bumps (protrusions)) has been disclosed as an example of miniaturization of electrodes (see Patent Document 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-107506 A [Patent Document 2] JP 2012-151183 A Summary of the Invention [Problem to be solved by the invention]

[0007] When using semiconductor elements such as power chips that handle large amounts of power to further increase integration and miniaturize devices, the following three challenges arise.

[0008] The first is ensuring heat dissipation performance. Sufficient heat dissipation is required to prevent thermal destruction of semiconductor elements due to temperature rise caused by power loss.

[0009] The second is the reduction of the impedance of the path. When the power handled by a semiconductor element increases, the current (I) that flows also increases. Therefore, if the impedance (Z) of the path to which the semiconductor element is connected is large, the power loss (I 2 × |Z|) becomes large, which leads to heat generation and reduced efficiency. To avoid this, the impedance of the path must be low.

[0010] The third is ensuring the insulation distance. When the distance between the electrodes of a semiconductor element (for example, the first and second electrodes of a semiconductor element) becomes smaller due to increased integration and miniaturization, the mating electrode to which the first electrode is bonded (for example, the conductive pattern of a substrate) becomes close not only to the first electrode but also to the second electrode. If this happens, even a slight misalignment during bonding may make it impossible to ensure the insulation distance between the conductive pattern of the substrate to which the first electrode of the semiconductor element is bonded and the second electrode, which could result in a short circuit or damage to the semiconductor element. To avoid this, an insulation distance must be ensured.

[0011] The present invention has been made to solve the above problems, and has an object to provide a semiconductor device capable of ensuring heat dissipation performance, reducing impedance of a path, and ensuring an insulation distance. [Means for solving the problem]

[0012] In order to solve the above problems, the semiconductor device of the present invention is a semiconductor device having a semiconductor element on a substrate having a conductive pattern, the semiconductor element having a plurality of electrodes provided on a first surface and an electrode provided on a second surface, each of the plurality of electrodes provided on the first surface being joined to the conductive pattern of the substrate via a conductive spacer, and the electrode provided on the second surface being joined to a pad surface of a conductive clip lead.

[0013] In such a semiconductor device, the semiconductor element can dissipate heat by having each of the multiple electrodes on the first surface joined to the conductive pattern of the substrate via a conductive spacer, and the electrodes on the second surface joined to the pad surface of the conductive clip lead, so that heat can be dissipated through each electrode on both sides of the semiconductor element, ensuring sufficient heat dissipation performance.

[0014] In addition, the semiconductor element has multiple electrodes on a first surface that are each bonded to the conductive pattern of the substrate via a conductive spacer, and the electrodes on the second surface that are bonded to the pad surface of the conductive clip lead. The impedance of the path after bonding is determined by the shape of the conductive pattern of the substrate or the shape of the pad surface of the clip lead, and can be adjusted as desired depending on the shape. Specifically, since both are planar, it is possible to make it easier for more current to flow by increasing the area. In other words, it is possible to reduce the impedance of the path by increasing the area.

[0015] In addition, since each of the multiple electrodes provided on the first surface of the semiconductor element is bonded to the conductive pattern of the substrate via a conductive spacer, the distance between each of the multiple electrodes and the conductive pattern of the substrate can be increased by the thickness of the spacer, and the insulation distance can be easily ensured. Furthermore, when the spacer widens the gap surrounded by the multiple electrodes, the spacer, and the conductive pattern, it becomes possible to fill this gap with an insulating resin material, and filling the insulating resin material can further improve the insulation performance.

[0016] It is also preferable that the clip lead further comprises a terminal surface, the terminal surface being joined to the conductive pattern of the substrate.

[0017] With such a planar terminal surface, not only can the terminal surface itself dissipate heat, but by bonding to the conductive pattern through surface contact, heat can be efficiently transferred from the terminal surface to the conductive pattern for dissipation. Furthermore, since the planar configuration can be maintained from the pad surface through the terminal surface to the conductive pattern, the impedance of the path can be kept low without narrowing the area along the way.

[0018] It is also preferable that a wiring wire is joined to the surface of the clip lead opposite to the pad surface.

[0019] With this configuration, heat can be dissipated from the pad surface of the clip lead, and even if the connection destination is in a position that is difficult to connect to using the clip lead (for example, a distant position), the wire can be extended and wiring can be performed freely.

[0020] It is also preferable that an insulating resist is provided around the spacer on the conductive pattern of the substrate, and the semiconductor element and the conductive pattern are joined by soldering.

[0021] With this configuration, the solder melted on the conductive pattern is blocked by the insulating resist and does not spread outward, and in addition to bonding the opposing surfaces of the conductive pattern and the spacer, it creeps up the gap between the inside of the insulating resist and the periphery of the spacer and adheres to the side of the spacer, wrapping around the bottom and sides of the spacer to bond them together. This ensures that the semiconductor element and the conductive pattern are bonded together.

[0022] Moreover, the spacer is preferably a Cu pillar.

[0023] Such Cu pillars can reliably realize conductive spacers that connect multiple electrodes and conductive patterns. Effect of the Invention

[0024] As described above, according to the semiconductor device of the present invention, the semiconductor element can dissipate heat by having each of the multiple electrodes provided on the first surface joined to the conductive pattern of the substrate via a conductive spacer, and the electrodes provided on the second surface joined to the pad surface of the conductive clip lead, so that heat can be dissipated through various electrodes on both sides of the semiconductor element, ensuring sufficient heat dissipation performance.

[0025] In addition, the semiconductor element has multiple electrodes on a first surface that are each bonded to the conductive pattern of the substrate via a conductive spacer, and the electrodes on the second surface that are bonded to the pad surface of the conductive clip lead. The impedance of the path after bonding is determined by the shape of the conductive pattern of the substrate or the shape of the pad surface of the clip lead, and can be adjusted as desired depending on the shape. Specifically, since both are planar, it is possible to make it easier for more current to flow by widening the width of the surface. In other words, it is possible to reduce the impedance of the path by widening the width of the surface.

[0026] In addition, since each of the multiple electrodes provided on the first surface of the semiconductor element is bonded to the conductive pattern of the substrate via a conductive spacer, the distance between each of the multiple electrodes and the conductive pattern of the substrate can be increased by the thickness of the spacer, and the insulation distance can be easily ensured. Furthermore, when the spacer widens the gap surrounded by the multiple electrodes, the spacer, and the conductive pattern, it becomes possible to fill this gap with an insulating resin material, and filling the insulating resin material can further improve the insulation performance. [Brief description of the drawings]

[0027] [Figure 1] 1 is a schematic lateral cross-sectional view of a semiconductor device according to a first embodiment of the present invention; [Diagram 2] 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention; [Diagram 3] 1 is a schematic vertical cross-sectional view of a semiconductor device according to a second embodiment of the present invention; [Figure 4] FIG. 11 is a schematic plan view of a semiconductor device according to another embodiment of the present invention. [Diagram 5] FIG. 11 is a schematic vertical cross-sectional view of a semiconductor device according to another embodiment of the present invention. [Figure 6] FIG. 11 is a schematic plan view of a semiconductor device according to a third embodiment of the present invention. [Figure 7] FIG. 11 is a schematic lateral cross-sectional view of a semiconductor device according to a third embodiment of the present invention. [Figure 8] FIG. 11 is a schematic vertical cross-sectional view of a semiconductor device according to a third embodiment of the present invention. [Figure 9] FIG. 13 is a schematic plan view of a semiconductor device according to a fourth embodiment of the present invention. [Figure 10] FIG. 13 is a schematic lateral cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. [Figure 11] 13A and 13B are schematic diagrams of a semiconductor device and a semiconductor element according to a fifth embodiment of the present invention. [Figure 12] FIG. 13 is a schematic diagram of a Cu pillar in a fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The present invention will be described in detail below, but the present invention is not limited thereto.

[0029] As described above, in order to further increase the integration density and miniaturization using semiconductor elements that handle large amounts of power, there has been a demand for semiconductor devices that can ensure heat dissipation performance, reduce path impedance, and ensure insulation distance.

[0030] As a result of extensive research, the present inventors have found that the above problems can be solved by devising a junction structure for electrodes of a semiconductor element, and have completed the present invention.

[0031] That is, the present invention is a semiconductor device having a semiconductor element on a substrate having a conductive pattern, the semiconductor element having a plurality of electrodes provided on a first surface and an electrode provided on a second surface, each of the plurality of electrodes provided on the first surface being joined to the conductive pattern of the substrate via a conductive spacer, and the electrode provided on the second surface being joined to a pad surface of a conductive clip lead.

[0032] The following description will be given with reference to the drawings.

[0033] Here, the substrate is not particularly limited as long as a conductive pattern is formed on the front surface, and may be a substrate having a metal pattern formed on the back surface as well, or may be a multi-layer substrate. For example, a DBC (Direct Bonding Cupper) substrate may be used.

[0034] The conductive pattern is not particularly limited as long as it can be joined with solder, and may be a copper pattern.

[0035] The solder is not particularly limited as long as it can fix the semiconductor element. For example, a lead-free solder can be used.

[0036] The solder is not particularly limited, but may be printed in advance and joined by heating and melting in a reflow process.

[0037] The semiconductor element is not particularly limited, but may be a power chip such as a diode or a transistor. Also, an IGBT or a power MOSFET may be used.

[0038] The electrodes are not particularly limited as long as they are conductive and can be joined by soldering, and may be made of Cu or Al.

[0039] The conductive spacer is not particularly limited as long as it is conductive and can be soldered, but it may be made of Cu or may be a Cu pillar. It may also be plated, and in the case of plating, it may be plated with Sn or the like.

[0040] The conductive clip lead is not particularly limited as long as it is conductive and can be joined by soldering, but may be a metal plate such as Cu, Al, SUS, Fe, or other alloys.

[0041] [First embodiment] A first embodiment of the present invention will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a schematic lateral cross-sectional view of a semiconductor device, and Fig. 2 is a schematic plan view. In order to clearly show the components, Fig. 2 shows Fig. 2(a) to Fig. 2(d) based on the steps of manufacturing the semiconductor device. Here, Fig. 1 is a cross-sectional view of part AA in Fig. 2(c).

[0042] As shown in FIG. 1, the semiconductor device in this embodiment is a semiconductor device including semiconductor elements 5, 6 on a substrate 1 having a conductive pattern. In particular, the semiconductor element 5 includes a plurality of electrodes 7a, 7b provided on a first surface and an electrode 7c provided on a second surface, with the plurality of electrodes 7a, 7b provided on the first surface being joined to the conductive patterns 3a, 3b of the substrate 1 via conductive spacers 4a, 4b, respectively, and the electrode 7c provided on the second surface being joined to a pad surface 11 of a conductive clip lead 10.

[0043] In such a semiconductor device, the semiconductor element 5 has multiple electrodes 7a, 7b on the first surface which are joined to the conductive patterns 3a, 3b of the substrate 1 via conductive spacers 4a, 4b, respectively, enabling heat dissipation through the entire substrate 1. In addition, the electrode 7c on the second surface is joined to the pad surface 11 of the conductive clip lead 10, enabling heat dissipation through the entire clip lead 10. Therefore, heat can be dissipated over a wide area through the electrodes 7a to 7c on both surfaces of the semiconductor element 5, ensuring sufficient heat dissipation performance.

[0044] In addition, the semiconductor element 5 has a plurality of electrodes 7a, 7b provided on the first surface thereof bonded to the conductive patterns 3a, 3b of the substrate 1 via the conductive spacers 4a, 4b, respectively, and the electrode 7c provided on the second surface thereof bonded to the pad surface 11 of the conductive clip lead 10. The impedance of the path after bonding is determined by the shape of the conductive patterns 3a, 3b of the substrate 1 or the shape of the pad surface 11 of the clip lead 10, and can be adjusted arbitrarily depending on the shape. Specifically, since both are planar, it is possible to make it easier for more current to flow by increasing the area. In particular, the conductive pattern 3a and the pad surface 11 of the clip lead 10 have a larger area than the semiconductor element 5, as is clear from FIGS. 1 to 3. In this way, it is possible to make it easier for more current to flow by increasing the area, and it is possible to reduce the impedance of the path.

[0045] 1, the semiconductor element 5 has a plurality of electrodes 7a, 7b provided on the first surface, which are bonded to the conductive patterns 3a, 3b of the substrate via the conductive spacers 4a, 4b, respectively. Therefore, the distance between the plurality of electrodes 7a, 7b and the conductive patterns 3a, 3b of the substrate can be increased by the thickness of the spacers 4a, 4b, and the insulation distance (particularly, the insulation distance between the electrode 7a and the conductive pattern 3b, which should not be bonded, and the insulation distance between the electrode 7b and the conductive pattern 3a) can be easily ensured. For example, when the semiconductor element 5 is mounted on the substrate 1, even if the semiconductor element 5 is slightly shifted in the left-right direction of FIG. 1 with respect to the substrate 1, the insulation distance can be ensured because there is a distance in the up-down direction (thickness direction of the spacers 4a, 4b). Furthermore, the spacers 4a, 4b widen the gap 15 surrounded by the plurality of electrodes 7a, 7b, the spacers 4a, 4b, and the conductive patterns 3a, 3b. Even if the electrodes 7a, 7b are close to each other due to increased integration and miniaturization, by widening the gap 15, it becomes possible to fill the gap 15 with an insulating resin material, and filling the gap with an insulating resin material can further improve the insulating performance.

[0046] Next, the steps of manufacturing a semiconductor device will be described with reference to Fig. 2. First, Fig. 2(a) is a diagram of the step of preparing a substrate, in which substrate 1 has conductive patterns 3a-3d and the like on the upper surface of ceramic base material 2. There are also many conductive patterns to the right of conductive patterns 3a-3d, but they are omitted here since it would be very difficult to understand if all of them were labeled. In addition, substrate 1 also has conductive pattern 3e on its lower surface (see Figs. 1 and 3).

[0047] Next, FIG. 2(b) is a diagram of a step of mounting power chips (semiconductor elements) 5 and 6 on the substrate 1 via conductive spacers 4a to 4c (see FIGS. 1 and 3). There are five sets of power chips on the right side of the power chips 5 and 6, but their reference numbers are omitted. In addition, although the underlying patterns are normally not visible when elements are arranged on the pattern, the entire configuration is shown here to clarify the positional relationship (this also applies to FIGS. 2(c) and 2(d)). Here, the power chip 5 is an IGBT, and has two electrodes 7a and 7b on the first surface (the surface facing the substrate 1), the wider one being the source electrode 7a and the narrower one being the gate electrode 7b, which are respectively bonded to the conductive patterns 3a and 3b via the spacers 4a and 4b. The power chip 6 is a diode, and has one electrode 8a on the first surface (the surface facing the substrate 1), which is bonded to the conductive pattern 3a via the spacer 4c. Here, solders 9a to 9c are used for bonding.

[0048] Next, Fig. 2(c) is a diagram showing a step of mounting a conductive clip lead 10. As shown in Fig. 3, the pad surface 11 of the clip lead 10 is joined to the electrodes 7c and 8b provided on the second surfaces of the power chips 5 and 6 with solder 9d and 9e. The clip lead 10 further includes a terminal surface 12, and the terminal surface 12 is joined to the conductive pattern 3d of the substrate with solder 9f.

[0049] 2(d) shows the step of completing the semiconductor device by integrating the substrate 1 and the lead frame 13. A control chip 14 is mounted on the lead frame 13, and since the control chip 14 does not handle a large amount of power, wiring between the control chip 14 and the substrate 1 is performed by WB (wire bonding).

[0050] [Second embodiment] Fig. 3 is a schematic vertical cross-sectional view, which is a cross-sectional view of the portion BB in Fig. 2(c). Other parts are the same as those of the above embodiment, but as shown in Fig. 3, the clip lead 10 further includes a terminal surface 12, and the terminal surface 12 and the conductive pattern 3d of the substrate are joined with solder 9f.

[0051] With the clip lead 10 having such a planar terminal surface 12, not only can the terminal surface 12 itself dissipate heat, but also, by joining to the conductive pattern 3d by surface contact, heat can be efficiently transferred from the terminal surface 12 to the conductive pattern 3d and dissipated. Furthermore, since a wide planar configuration can be maintained from the pad surface 11 through the terminal surface 12 to the conductive pattern 3d, there is no need to narrow the area by, for example, passing a wire with a narrow cross-sectional area along the way, and the impedance of the path can be kept low.

[0052] In this embodiment, the semiconductor elements 5 and 6 are assumed to be of a general silicon type and are configured with two chips, an IGBT and a diode, but the present invention is not limited to this.

[0053] In another embodiment, for example, a SiC type IGBT may be configured with only one chip. An example of one chip will be described with reference to Figures 4 and 5. Figure 4 is a plan view, and Figure 5 is a vertical cross-sectional view.

[0054] The semiconductor element 16 is a single chip, and is a SiC type IGBT. Compared to the two chips (semiconductor elements 5 and 6 in FIG. 2(b)), the single chip in FIG. 4 has a shape that extends in the vertical direction of the paper. In addition, in the vertical cross section, the shape of the electrode 17a on the first surface (surface facing the substrate 1) of the semiconductor element 16, the electrode 17b on the second surface, the spacer 4d, the solder 9g, and 9h, etc. are different in the single chip in FIG. 5 compared to the two chips in FIG. 3. Here, the horizontal cross section is omitted because it is the same as FIG. 2, but even if it is a single chip, it still has two electrodes on the first surface (surface facing the substrate 1) to be bonded to the conductive patterns 3a and 3b, so there are the same problems as in the case of two chips, and they can be solved by the same means as in the case of two chips.

[0055] [Third embodiment] A third embodiment of the present invention will be described with reference to Fig. 6 to Fig. 8. Fig. 6 is a schematic plan view. Fig. 7 is a schematic horizontal cross-sectional view, which is a cross-sectional view of part EE in Fig. 6. Fig. 8 is a schematic vertical cross-sectional view, which is a cross-sectional view of part FF in Fig. 6.

[0056] The third embodiment differs from the second embodiment in that the clip lead 18 has a flat shape when viewed from the side, has no terminal surface, and has a wire 19.

[0057] Specifically, one end of a wiring wire 19 is joined with solder 9i to the surface of the clip lead 18 opposite to the pad surface 20, and the other end of the wire 19 is joined with solder 9j to the conductive pattern 3d. The wire 19 can also be made of a thick wire such as aluminum by ultrasonic wire bonding without using the solders 9i and 9j.

[0058] With this configuration, heat can be dissipated through the pad surface 20 of the clip lead 18, and even if the connection destination is in a location that is difficult to connect to using a clip lead (for example, a distant location), the other end of the wire 19 can be extended and wired freely.

[0059] [Fourth embodiment] A fourth embodiment of the present invention will be described with reference to Figures 9 and 10. Figure 9 is a plan view, and Figure 10 is a lateral cross-sectional view.

[0060] The fourth embodiment differs from the first embodiment in that it has an insulating resist. Fig. 9(a) is an enlarged view of the substrate 1, which is an enlarged view of the lower left portion of Fig. 2(a) of the first embodiment. Fig. 9(b) shows, unlike the first embodiment, insulating resists 21 and 22 are applied to surround a portion of the conductive patterns 3a and 3b, and spacers 4a and 4b are arranged within the region surrounded by the insulating resists 21 and 22 and joined by solders 9k and 9l.

[0061] In other words, insulating resists 21, 22 are provided around spacers 4a, 4b on conductive patterns 3a, 3b of substrate 1, and semiconductor element 5 and conductive patterns 3a, 3b are joined by solders 9k, 9l.

[0062] With this configuration, the solder 9k, 9l melted on the conductive patterns 3a, 3b is blocked by the insulating resists 21, 22 and does not spread outward, and in addition to bonding the opposing surfaces of the conductive patterns 3a, 3b and the spacers 4a, 4b, it creeps up the gap between the inside of the insulating resists 21, 22 and the periphery of the spacers 4a, 4b and adheres to the side surfaces of the spacers 4a, 4b, resulting in bonding that wraps around the bottom and side surfaces of the spacers 4a, 4b. This ensures bonding of the semiconductor element 5 and the conductive patterns 3a, 3b.

[0063] It goes without saying that the fourth embodiment can be applied to the second and third embodiments.

[0064] [Fifth embodiment] A fifth embodiment of the present invention will be described with reference to Figures 11 and 12. Figure 11 is a schematic diagram of a semiconductor device and a semiconductor element, and Figure 12 is a schematic diagram of a typical Cu pillar.

[0065] The fifth embodiment differs from the first embodiment in that Cu pillars are used as spacers. FIG. 11(a) is an enlarged view of the substrate 1, which is an enlarged view of the lower left portion of FIG. 2(b) of the first embodiment. FIG. 11(b) is a schematic diagram of the semiconductor element 5 of the first embodiment described above, with the upper view being a view in which the semiconductor element 5 of FIG. 11(a) is inverted in the left-right direction, and the lower view being a CC cross-sectional view of the upper view. On the electrodes 7a and 7b of the semiconductor element 5, spacers 4a and 4b, each having a bottom shape substantially the same as that of the electrodes 7a and 7b, are configured one on each electrode. In this case, the number of electrodes and the number of spacers are the same (two in each case). Meanwhile, FIG. 11(c) is a configuration diagram of the semiconductor element 5 using the Cu pillars of this embodiment, and the lower view is a DD cross-sectional view of the upper view. Compared to FIG. 11(b), FIG. 11(c) shows that the semiconductor element 5 and the electrodes 7a and 7b have the same configuration, but the spacers 4e and 4f are configured with far more Cu pillars than the number of electrodes. Specifically, the spacer 4e on the electrode 7a has 159 Cu pillars, and the spacer 4f on the electrode 7b has 12 Cu pillars.

[0066] As described above, the spacers 4e and 4f in this embodiment are Cu pillars.

[0067] Such a Cu pillar can reliably realize the conductive spacers 4e, 4f that connect the multiple electrodes 7a, 7b and the conductive patterns 3a, 3b.

[0068] In particular, when the electrodes 7a, 7b and the conductive patterns 3a, 3b are joined by soldering, the solder can penetrate into the gaps between the Cu pillars of the spacers 4e, 4f, thereby making the joining stronger.

[0069] Figure 12 is a schematic diagram showing typical shapes of Cu pillars. Figure 12(a) shows a trapezoidal shape, Figure 12(b) shows a dome shape, and Figure 12(c) shows a Cu pillar 23 formed by Cu plating with a Sn plating 24 applied to the top for surface protection. The Sn plating 24 has the effect of preventing oxidation of Cu and the effect of making it easier for the Cu to blend with solder.

[0070] It goes without saying that the fifth embodiment can be applied to the second, third, and fourth embodiments.

[0071] The present invention includes the following aspects. [1]: The semiconductor element has a plurality of electrodes provided on a first surface and an electrode provided on a second surface, each of the plurality of electrodes provided on the first surface being joined to the conductive pattern of the substrate via a conductive spacer, and the electrode provided on the second surface being joined to a pad surface of a conductive clip lead. [2]: The semiconductor device according to [1] above, wherein the clip lead further comprises a terminal surface, the terminal surface being joined to the conductive pattern of the substrate. [3]: The semiconductor device according to [1] above, characterized in that a wiring wire is bonded to the surface of the clip lead opposite to the pad surface. [4]: The semiconductor device according to any one of [1] to [3] above, characterized in that an insulating resist is provided around the spacer on the conductive pattern of the substrate, and the semiconductor element and the conductive pattern are joined by solder. [5]: The semiconductor device according to any one of the above [1] to [4], wherein the spacer is a Cu pillar.

[0072] The present invention is not limited to the above-described embodiment. The above-described embodiment is merely an example, and anything that has substantially the same configuration as the technical idea described in the claims of the present invention and exhibits similar effects is included in the technical scope of the present invention. [Explanation of symbols]

[0073] REFERENCE SIGNS LIST 1...substrate, 2...ceramic base material, 3a, 3b, 3c, 3d, 3e...conductive pattern, 4a, 4b, 4c, 4d, 4e, 4f...spacer, 5, 6, 16...power chip (semiconductor element), 7a, 7b, 7c, 8a, 8b, 17a, 17b...electrode, 9a, 9b, 9c, 9d, 9e, 9f, 9g, 9h, 9i, 9j, 9k, 9l...solder, 10, 18...clip lead, 11, 20...pad surface, 12...terminal surface, 13...lead frame, 14...control chip, 15...gap, 19...wire, 21, 22...insulating resist, 23...Cu pillar, 24...Sn plating.

Claims

1. A semiconductor device including a semiconductor element on a substrate having a conductive pattern, The semiconductor element has a plurality of electrodes provided on a first surface and an electrode provided on a second surface, each of the plurality of electrodes provided on the first surface being joined to the conductive pattern of the substrate via a conductive spacer, and the electrode provided on the second surface being joined to a pad surface of a conductive clip lead.

2. 2. The semiconductor device according to claim 1, wherein the clip lead further comprises a terminal surface, the terminal surface being joined to the conductive pattern of the substrate.

3. 2. The semiconductor device according to claim 1, wherein a wiring wire is bonded to a surface of said clip lead opposite to said pad surface.

4. 4. The semiconductor device according to claim 1, further comprising an insulating resist provided around the spacer on the conductive pattern of the substrate, and the semiconductor element and the conductive pattern are joined by solder.

5. 4. The semiconductor device according to claim 1, wherein the spacer is a Cu pillar.

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