Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a technique of improving the adhesion of a barrier metal film.SOLUTION: A semiconductor device includes a floating region formed between a trench gate electrode and a trench emitter electrode, a multilayer film formed on the floating region, an interlayer insulating film formed on the multilayer film, a plug penetrating the interlayer insulating film and reaching the multilayer film, a barrier metal film formed covering the interlayer insulating fil and the plug, and a metal film formed on the barrier metal film.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and is applicable to, for example, an IE type trench gate IGBT. [Background technology]

[0002] In an IGBT (Insulated Gate Bipolar Transistor), which is a type of power semiconductor, the emitter wiring is composed of a barrier metal film and a conductor film, and is sometimes electrically connected to the emitter region and base region formed in the semiconductor substrate through a via formed in the insulating film (for example, JP 2023-35453 A). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-35453 A Summary of the Invention [Problem to be solved by the invention]

[0004] As described above, when an emitter wiring (emitter electrode) is formed on an insulating film (interlayer insulating film) and a via (plug), the adhesion at the interface between the barrier metal film and the interlayer insulating film may be low.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A brief overview of representative aspects of this disclosure is as follows. That is, the semiconductor device has a floating region formed between a trench gate electrode and a trench emitter electrode, a laminated film formed on the floating region, an interlayer insulating film formed on the laminated film, a plug penetrating the interlayer insulating film and reaching the laminated film, a barrier metal film formed to cover the interlayer insulating film and the plug, and a metal film formed on the barrier metal film. Effect of the Invention

[0007] According to the semiconductor device, the adhesion of the barrier metal film is improved. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a configuration of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is an enlarged plan view of a main portion showing a part of the cell formation region of the semiconductor device shown in FIG. [Diagram 3] 3 is a cross-sectional view of a main part of the semiconductor device shown in FIG. 2 taken along line A1-A2. [Figure 4] 4A to 4C are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment. [Diagram 5] FIG. 5 is a cross-sectional view showing a manufacturing process following FIG. [Figure 6] FIG. 6 is a cross-sectional view showing a manufacturing process following FIG. [Figure 7] FIG. 7 is a cross-sectional view showing a manufacturing process following FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a manufacturing process following FIG. [Figure 9] FIG. 9 is a cross-sectional view showing a manufacturing process following FIG. [Figure 10] FIG. 10 is a cross-sectional view showing a manufacturing process following FIG. [Figure 11] FIG. 11 is a cross-sectional view showing a manufacturing process following FIG. [Figure 12] FIG. 12 is a cross-sectional view showing a manufacturing process following FIG. [Figure 13]FIG. 13 is a cross-sectional view showing a manufacturing process following FIG. [Figure 14] FIG. 14 is a cross-sectional view showing a manufacturing process following FIG. [Figure 15] FIG. 15 is a cross-sectional view showing a manufacturing process following FIG. [Figure 16] FIG. 16 is a plan view of a main part of a semiconductor device in a comparative example. [Figure 17] FIG. 17 is a cross-sectional view taken along line A1-A2 of the semiconductor device shown in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing the configuration of a semiconductor device in the first modified example. [Figure 19] FIG. 19 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the second modification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described with reference to the drawings. However, in order to clarify the description, the following description and drawings are omitted and simplified as appropriate. Furthermore, the width, thickness, shape, etc. of each part may be shown in a schematic manner compared to the actual embodiment. Furthermore, the same components may be given the same reference numerals, and repeated description may be omitted.

[0010] The configuration of a semiconductor device according to an embodiment will be described with reference to FIGS. 1, 2 and 3. FIG.

[0011] As shown in FIG. 1, two directions that intersect, preferably perpendicular to each other, on the surface of a semiconductor substrate (hereinafter simply referred to as "substrate") S are defined as the X direction as a first direction and the Y direction as a second direction, and the direction perpendicular to the surface of the substrate S, i.e., the up-down direction, is defined as the Z direction.

[0012] In this specification, "in a plan view" means a view from a direction perpendicular to the surface of the substrate S. In addition, in this specification, the conductivity type of a semiconductor is P-type means that only holes are charge carriers, or both electrons and holes may be charge carriers, but the concentration of holes is higher than the concentration of electrons, and holes are the main charge carriers. In this specification, the conductivity type of a semiconductor is N-type means that only electrons are charge carriers, or both electrons and holes may be charge carriers, but the concentration of electrons is higher than the concentration of holes, and electrons are the main charge carriers.

[0013] As shown in FIG. 1, a semiconductor chip 2 as a semiconductor device has a substrate S. The substrate S has a front surface as one main surface and a back surface opposite the front surface as the other main surface. The substrate S also has a cell formation region RCL as a partial region of the front surface, a cell peripheral connection region RC0, and a chip peripheral portion PER. The cell formation region RCL is provided in an approximately central region of the semiconductor chip 2. The cell peripheral connection region RC0 is provided so as to surround the periphery of the cell formation region RCL. The chip peripheral portion PER is provided in the chip peripheral region so as to surround the periphery of the cell peripheral connection region RC0.

[0014] An emitter electrode EE, an emitter pad EP, and a gate wiring (not shown) are provided on the upper side of the cell formation region RCL so as to cover the entire cell formation region RCL. In this example, the cell peripheral connection region RC0 is provided with a gate pad GP, a gate electrode GE, and an internal gate resistor (resistance element) Rg connected between the gate wiring and the gate electrode GE. An annular guard ring (not shown) is provided on the upper surface of the chip peripheral portion PER, and several (single or multiple) annular field plates connected to an annular floating field ring or the like are provided inside the guard ring.

[0015] In the cell formation region RCL, cells of an IE (Injection Enhancement) type trench gate IGBT are formed. As shown in FIG. 2, the cell formation region RCL has a trench gate electrode TG1 consisting of a trench connected to a gate potential between the active cell region LCa and the inactive cell region LCi. The cell formation region RCL replaces every other active cell region LCa with a hole collector cell region LCc, and has a trench emitter electrode TG2 consisting of a trench connected to an emitter potential between the hole collector cell region LCc and the inactive cell region LCi. In this specification, this IGBT is called a GGEE type IGBT.

[0016] In the cell formation region RCL, unit cell regions are periodically arranged in the X direction. Each unit cell region is composed of a first unit cell region LC1 and a second unit cell region LC2, and in this embodiment, the width (length in the X direction) of the second unit cell region LC2 is formed to be narrower than the width of the first unit cell region LC1.

[0017] Each of the first unit cell regions LC1 is composed of a central active cell region LCa and a pair of inactive cell regions LCi each having a half width sandwiching the central active cell region LCa on both sides in the X direction.

[0018] In each active cell region LCa, two trench gate electrodes TG1 are formed along the Y direction, spaced apart from each other in the X direction. Therefore, the trench gate electrode TG1 is between the active cell region LCa and the inactive cell region LCi. The trench gate electrode TG1 is electrically connected to the gate electrode (gate electrode GE shown in FIG. 1). In other words, the trench gate electrode TG1 is a trench gate electrode formed of a trench connected to a gate potential.

[0019] Each active cell region LCa is provided with a region where an emitter region NE is formed and a region where the emitter region NE is not formed in a plan view. A body region PB is provided in the region where the emitter region NE is not formed. The body region PB is also called a channel region, a base region, or a base diffusion layer.

[0020] On the other hand, each second unit cell region LC2 is composed of a central hole collector cell region LCc and a pair of inactive cell regions LCi each having a half width sandwiching the central hole collector cell region LCc on both sides in the X direction.

[0021] In each hole collector cell region LCc, a trench emitter electrode TG2 is formed along the Y direction at a distance from each other in the X direction. Therefore, the trench emitter electrode TG2 is present between the hole collector cell region LCc and the inactive cell region LCi. The trench emitter electrode TG2 is electrically connected to the emitter electrode EE via a first plug PL1 described later. In other words, the trench emitter electrode TG2 is a trench emitter electrode formed of a trench connected to an emitter potential. The trench gate electrode TG1 and the trench emitter electrode TG2 are adjacent to each other in the X direction in a plan view.

[0022] The width in the X direction of the active cell region LCa and the width in the X direction of the hole collector cell region LCc are formed narrower than the width in the X direction of the inactive cell region LCi. The active cell region LCa or the hole collector cell region LCc and the inactive cell region LCi are alternately arranged to form a unit cell region.

[0023] A contact groove CT extending along the Y direction is provided in the center of each of the active cell region LCa and the hole collector cell region LCc, and the lower end of the contact groove CT reaches a body contact region PBC (see FIG. 3) formed in the substrate S. A first plug PL1 (see FIG. 3), which will be described later, is formed in the contact groove CT. In other words, the first plug PL1 extends in the Y direction in a plan view.

[0024] The interval between the trench emitter electrodes TG2 formed in the hole collector cell region LCc and adjacent to each other in the X direction is smaller than the interval between the trench gate electrodes TG1 formed in the active cell region LCa and adjacent to each other in the X direction. The hole collector cell region LCc has the function of discharging holes injected into the floating region PF.

[0025] On the other hand, the width in the X direction of the contact groove CT in the hole collector cell region LCc is larger than the width in the X direction of the contact groove CT in the active cell region LCa. The contact groove CT in the hole collector cell region LCc is formed in contact with the trench emitter electrode TG2. In FIG. 2 and FIG. 3, the contact groove CT is in contact with both of the pair of trench emitter electrodes TG2, but it is sufficient that the contact groove CT is in contact with either one of the trench emitter electrodes TG2. In other words, the contact groove CT is formed so as to straddle between the trench emitter electrode TG2 and the emitter region NE.

[0026] In this embodiment, the width of the hole collector cell region LCc is narrower than the width of the active cell region LCa, but this is not essential, and the width of the hole collector cell region LCc and the width of the active cell region LCa may be the same or substantially the same. By making them the same or substantially the same, there is an advantage that the hole distribution becomes uniform.

[0027] A floating region PF is provided in the inactive cell region LCi. Furthermore, contact grooves CT are provided in the center of the inactive cell region LCi, spaced apart from each other and extending along the Y direction, and the lower ends of the contact grooves CT reach a conductive film G2 formed on the substrate S. A second plug PL2 (see FIG. 3), which will be described later, is formed in the contact groove CT. In this embodiment, an example having three contact grooves CT is shown, but it is sufficient to have at least one contact groove CT.

[0028] In FIG. 3, the floating region PF is deeper than the lower ends of the first trench T1 and the second trench T2, and is structured to cover the lower ends. This has the advantage that the withstand voltage can be easily maintained even if the width of the inactive cell region LCi is made larger than the width of the active cell region LCa. Such a structure is not essential, in other words, the floating region PF may have a structure that does not cover the lower ends of the first trench T1 and the second trench T2. For example, the structures shown in FIG. 15, FIG. 18, and FIG. 20 may be used. In this embodiment, the width of the active cell region LCa is made narrower than the width of the inactive cell region LCi to enhance the IE effect.

[0029] Next, the cross-sectional structure taken along line A1-A2 in Fig. 2 will be described with reference to Fig. 3. Figs. 1 and 2 will also be referred to as appropriate.

[0030] 3, the main portion of the substrate S is occupied by a drift layer ND, and a field stop region Ns and a collector region PC are provided, from the side closer to the drift layer ND, on the back surface (second main surface, lower surface) Sb side of the substrate S. Furthermore, a collector electrode CE is provided on the back surface Sb of the substrate S, which is electrically connected to the collector region PC.

[0031] On the other hand, on the surface (first main surface, upper surface) Sa side of the substrate S, a floating region PF or a body region PB is provided over almost the entire surface of the cell formation region RCL.

[0032] In the active cell region LCa, a first trench T1 is provided on the surface Sa side of the substrate S, and a trench gate electrode TG1 is provided therein via a gate insulating film GF. The gate insulating film GF is located at the interface between the trench gate electrode TG1 and the substrate S. The trench gate electrode TG1 is electrically connected to a gate electrode (gate electrode GE shown in FIG. 1). The trench gate electrode TG1 is embedded from the lower end to the upper part of the trench T1 formed in the substrate S.

[0033] On the other hand, in the hole collector cell region LCc, a second trench T2 is provided on the surface Sa side of the substrate S, and a trench emitter electrode TG2 is provided therein via a gate insulating film GF. The gate insulating film GF is located at the interface between the trench emitter electrode TG2 and the substrate S. The trench emitter electrode TG2 is electrically connected to the emitter electrode EE via a first plug PL1 and a barrier metal film BM. The trench emitter electrode TG2 is embedded from the lower end to the upper part of the second trench T2 formed in the substrate S.

[0034] In the active cell region LCa, an emitter region NE is provided on the surface Sa side of the substrate S. The lower end of the first plug PL1 formed in the contact groove CT (see FIG. 2) reaches the body region PB. In other words, the first plug PL1 penetrates the interlayer insulating film IL and reaches the body region PB. The body contact region PBC is provided in the substrate S in contact with the lower end of the first plug PL1 formed in the contact groove CT (see FIG. 2). A hole barrier region NHB is provided below the body region PB. A latch-up prevention region may be provided below the body contact region PBC.

[0035] In the hole collector cell region LCc, the impurity doped structure is almost the same as that in the active cell region LCa, except that the emitter region NE is not provided. However, the lower end of the first plug PL1 formed in the contact trench CT (see FIG. 2) reaches the trench emitter electrode TG2 in addition to the body region PB. In other words, the first plug PL1 penetrates the interlayer insulating film IL and reaches the body region PB. The body contact region PBC is provided in the substrate S to which the lower end of the contact trench CT (see FIG. 2) reaches.

[0036] The hole collector cell region LCc is also provided with a hole barrier region NHB, as in the active cell region LCa, but this is not essential. However, by providing the hole barrier region NHB, the overall balance of the flow of holes can be maintained.

[0037] In the inactive cell region LCi, on the surface Sa side of the substrate S, a floating region PF is provided below the surface Sa and the body region PB of the substrate S, the floating region PF being deeper than the first trench T1 and the second trench T2. A second insulating film HLD and a conductive film G2 are provided on the gate insulating film GF as a first insulating film formed on the floating region PF. The gate insulating film GF, the second insulating film HLD, and the conductive film G2 form a laminated film. Note that there is no body region PB below the laminated film. The laminated film has an end on the floating region PF in a plan view, and a step is generated by this end. This step is, for example, 50 nm or more. Three second plugs PL2 are formed by biting into the laminated film. In other words, the second plugs PL2 penetrate the interlayer insulating film IL and reach the laminated film. The second plugs PL2 are dummy plugs that are not electrically connected to the substrate S on which the floating region PF is formed. In this embodiment, an example having three second plugs PL2 is shown, but it is sufficient to have at least one second plug PL2.

[0038] An interlayer insulating film IL is formed on almost the entire surface Sa of the substrate S. A barrier metal film BM is formed on the interlayer insulating film IL. In other words, the barrier metal film BM is in contact with the interlayer insulating film IL. A metal film (metal film) MT is formed on the barrier metal film BM. The barrier metal film BM and the metal film MT constitute an emitter electrode EE.

[0039] In the active cell region LCa, the emitter electrode EE is connected to the emitter region NE, the body region PB, and the body contact region PBC via the first plug PL1 embedded in the contact groove CT. In the hole collector cell region LCc, the emitter electrode EE is connected to the body region PB and the body contact region PBC via the first plug PL1 embedded in the contact groove CT. In other words, the first plug PL1 is electrically connected to the body region PB. The barrier metal film BM is in contact with the first plug PL1.

[0040] In the inactive cell region LCi, the emitter electrode EE is connected to the conductive film G2 via the second plug PL2 embedded in the contact groove CT. In other words, the second plug PL2 is not electrically connected to the floating region PF and the body region PB. The barrier metal film BM is in contact with the second plug PL2.

[0041] An insulating film FPF is further formed on the emitter electrode EE as a passivation film. Although not shown, a conductive film called OPM (Over Pad Metal) is formed on the emitter electrode EE included in the emitter pad EP and on the gate electrode GE included in the gate pad GP.

[0042] (Method of manufacturing a semiconductor device) Next, a manufacturing method of a semiconductor device according to an embodiment will be described with reference to Fig. 4 to Fig. 15. Fig. 4 to Fig. 15 show a cell formation region RCL on the left side and a cell periphery connection region RC0 in which a resistive element Rg is formed on the right side. Fig. 3 will be referred to as appropriate. In Fig. 3, three second plugs PL2 are formed on one floating region PF, but Fig. 4 to Fig. 15 show an example in which four second plugs PL2 are formed.

[0043] First, a semiconductor wafer 1 is prepared, which includes a silicon single crystal substrate S doped with an N-type impurity as a first conductivity type, such as phosphorus. Hereinafter, the semiconductor wafer 1 is simply referred to as the wafer 1. The wafer 1 has a front surface as a first main surface, and a back surface as a second main surface opposite to the front surface.

[0044] The term "wafer" used in this specification may mean the wafer itself or a laminate of the wafer and a predetermined layer or film formed on the wafer. The term "surface of the wafer" used in this specification may mean the surface of the wafer itself or the surface of a predetermined layer or the like formed on the wafer.

[0045] 4, an N-type well region NW is formed by introducing an N-type impurity into the substrate S on the front side of the wafer 1 by ion implantation using a resist pattern as a mask. The N-type well region NW is formed in the active cell region LCa and the hole collector cell region LCc.

[0046] Next, a P-type well region PW is formed by introducing a P-type impurity as a second conductivity type into the substrate S on the front side of the wafer 1 by ion implantation using a resist pattern as a mask. The P-type well region PW is formed in the inactive cell region LCi. When forming the P-type well region PW in the cell formation region RCL, the P-type well region PW is also formed in the cell peripheral connection region RC0.

[0047] Next, a silicon oxide (SiO2) film is formed on the surface of the wafer 1 by, for example, a CVD method to form an insulating film HL.

[0048] 5, the insulating film HL is patterned by, for example, dry etching using the resist pattern as a mask. Then, the insulating film HL is used as a hard mask to form a first trench T1 and a second trench T2 by, for example, anisotropic dry etching. Then, the insulating film HL is removed by, for example, dry etching.

[0049] Next, as shown in Fig. 6, the extension diffusion is performed on the P-type well region PW and the N-type well region NW. At this time, the extension diffusion is performed so that the end of the P-type well region PW on the back side of the wafer 1 is located at the end of the first trench T1 and the second trench T2 on the back side of the wafer 1 in the Z-axis direction. Next, for example, a film of SiO2 is formed on the front surface of the wafer 1 and on the inner walls of the first trench T1 and the second trench T2 by, for example, a thermal oxidation method to form a gate insulating film GF. As a result, the gate insulating film GF (first insulating film) on the floating region PF is formed in the same layer as the gate insulating film GF of the trench gate electrode TG1 and the trench emitter electrode TG2.

[0050] The extending diffusion forms a P-type well region PW between the first trench T1 and the adjacent second trench T2. Preferably, the P-type well region PW is in contact with the gate insulating film GF formed on the inner wall of the first trench T1 and the gate insulating film GF formed on the inner wall of the second trench T2.

[0051] Furthermore, an N-type well region NW is formed between the first trench T1 and the first trench T1 and between the second trench T2 and the second trench T2. Preferably, the N-type well region NW formed between the first trench T1 and the first trench T1 contacts the gate insulating film GF formed on the inner wall of the first trench T1. Preferably, the N-type well region NW formed between the second trench T2 and the second trench T2 contacts the gate insulating film GF formed on the inner wall of the second trench T2.

[0052] During the above-mentioned extension diffusion, the region of the N-type wafer 1 where the P-type well region PW and the N-type well region NW are not formed becomes the drift layer ND shown in FIG. 3. The P-type well region PW in the cell formation region RCL becomes the floating region PF shown in FIG. 3. The N-type well region NW becomes the hole barrier region NHB shown in FIG. 3. The drift layer ND is also called an N-type drift layer. The floating region PF is also called a P-type floating region. The hole barrier region NHB is also called an N-type hole barrier region. FIG. 6 shows a structure in which the floating region PF does not cover the lower ends of the first trench T1 and the second trench T2.

[0053] Between the first trenches T1 and T1, the N-type impurity concentration of the hole barrier region NHB is higher than the N-type impurity concentration in the drift layer ND and is lower than the N-type impurity concentration of the emitter region NE described later.

[0054] Next, as shown in FIG. 7, a conductive film G1 is formed by depositing phosphorus-doped polycrystalline silicon (Doped Poly-Silicon) on the surface of the wafer 1 and inside the first trench T1 and the second trench T2, for example, by a CVD (Chemical Vapor Deposition) method.

[0055] Next, the conductive film G1 is etched back by, for example, a dry etching method. This forms a trench gate electrode TG1 including the conductive film G1 embedded in the first trench T1 via the gate insulating film GF. Also, a trench emitter electrode TG2 including the conductive film G1 embedded in the second trench T2 via the gate insulating film GF is formed.

[0056] 8, a second insulating film HLD is formed by depositing SiO2 on the surface of the wafer 1, for example, by the CVD method. Then, a conductive film G2 is formed by depositing polycrystalline silicon not doped with impurities on the surface of the wafer 1, for example, by the CVD method.

[0057] 9, the gate insulating film GF, the second insulating film HLD, and the conductive film G2 are patterned by, for example, dry etching using the resist pattern PR1 as a mask to form a laminated film. Here, the conductive film G2 is thicker than the second insulating film HLD, and the second insulating film HLD is thicker than the gate insulating film GF. Next, a body region PB is formed by introducing P-type impurities into the entire surface of the cell formation region RCL and other necessary parts by ion implantation using the resist pattern PR1 as a mask. The body region PB is also called a P-type body region.

[0058] Specifically, a body region PB is formed between the first trenches T1 and T1 and between the second trenches T2 and T2, in contact with the gate insulating film GF formed on the inner wall of the first trench T1 and the gate insulating film GF formed on the inner wall of the second trench T2. The body region PB is formed on the hole barrier region NHB. In the inactive cell region LCi, the body region PB is formed in a place on the floating region PF where the second insulating film HLD and the conductive film G2 are not present.

[0059] Furthermore, as shown in FIG. 10, an emitter region NE is formed by introducing an N-type impurity into the upper layer of the body region PB in the active session of the active cell region LCa by ion implantation using the resist pattern PR2 as a mask. The emitter region NE is also called an N+ type emitter region. In addition, a resistive film RS is formed by introducing an N-type impurity into the conductive film G2 in the cell peripheral connection region RC0. The trench gate electrode TG1 penetrates the emitter region NE and the body region PB and reaches the drift layer ND. The trench emitter electrode TG2 penetrates the body region PB and reaches the drift layer ND.

[0060] Next, as shown in FIG. 11, a silicon oxide film is formed on the surface of the wafer 1 by, for example, a CVD method to form an interlayer insulating film IL. More specifically, for example, PSG (Phosphosilicate Glass) is formed as the silicon oxide film to form the interlayer insulating film IL. The interlayer insulating film IL is formed so as to cover the emitter region NE and the body region PB in the active cell region LCa, and the body region PB in the hole collector region LCc. The interlayer insulating film IL is formed so as to cover the body region PB and the stacked film composed of the gate insulating film GF, the second insulating film HLD, and the conductive film G2 in the inactive cell region LCi. The interlayer insulating film IL is formed so as to cover the resistive film RS in the cell peripheral connection region RC0. In addition to the PSG film, the material of the interlayer insulating film IL may be, for example, a borophosphosilicate glass (BPSG) film, a non-doped silicate glass (NSG) film, a spin-on-glass (SOG) film, or a composite film thereof.

[0061] Next, as shown in Fig. 12, a contact trench CT is formed in the interlayer insulating film IL by anisotropic dry etching using a resist pattern as a mask. Then, a P-type impurity is introduced into the upper layer of the body region PB in the inactive session of the active cell region LCa and the hole collector cell region LCc through the contact trench CT by ion implantation to form a body contact region PBC. The body contact region PBC is also called a P+ type body contact region.

[0062] Next, as shown in FIG. 13, a film of titanium (Ti) and titanium nitride (TiN) is formed on the surface of the wafer 1, for example, by a sputtering method, and a film of tungsten (W) is formed thereon, for example, by a CVD method, to form a conductive film PCF.

[0063] Next, the conductive film PCF is etched back by, for example, a dry etching method to remove the conductive film PCF except in the contact trench CT. As a result, a first plug PL1 is formed in the active cell region LCa and the hole collector cell region LCc, and a second plug PL2 is formed in the inactive cell region LCi. Also, a third plug PL3 is formed in the cell peripheral connection region RC0. At this time, the first plug PL1, the second plug PL2, and the third plug PL3 are formed such that the center of the first plug PL1, the center of the second plug PL2, and the center of the third plug PL3 are recessed (concave) in a plan view.

[0064] Next, the emitter electrode EE and the gate electrode GE are formed. Specifically, for example, the following procedure is performed. First, as shown in Fig. 14, for example, an alloy mainly composed of tungsten (W) or titanium tungsten (TiW) is deposited on the surface of the wafer 1 by sputtering to form a barrier metal film BM.

[0065] Subsequently, an aluminum (Al) based metal is deposited on the entire surface of the barrier metal film BM on the surface of the wafer 1 by, for example, a sputtering method to form a metal film MT.

[0066] 15, the emitter electrode EE, the gate wiring GL, and the gate electrode GE, each including the metal film MT and the barrier metal film BM, are formed by a dry etching method using a resist pattern as a mask. As a result, the emitter electrode EE, the gate wiring GL, and the gate electrode GE are formed on the interlayer insulating film IL.

[0067] Moreover, the emitter electrode EE is electrically connected to the plurality of emitter regions NE, the plurality of body contact regions PBC, and the trench emitter electrode TG2 formed in the active cell region LCa. The emitter electrode EE is electrically connected to the trench emitter electrode TG2 and the body contact region PBC formed in the hole collector cell region LCc. The gate wiring GL is electrically connected to the trench gate electrode TG1. Moreover, the gate wiring GL is electrically connected to one end of the resistive film RS. The gate electrode GE is electrically connected to the other end of the resistive film RS.

[0068] 3, and the P-type well region PW in RP0 is a region at the emitter potential. The floating region PF is also called a P-type floating region.

[0069] Next, an insulating film FPF is formed by depositing an organic material containing, for example, polyimide as a main component on the surface of the wafer 1. Next, the insulating film FPF is patterned by a dry etching method using a resist pattern as a mask to form openings that penetrate the insulating film FPF and reach the emitter electrode EE and the gate electrode GE.

[0070] Next, for example, by using an electroless plating method, a film of, for example, nickel (Ni) and gold (Au) is formed on the emitter electrode EE and the gate electrode GE exposed in the opening to form an OPM, and an emitter pad EP and a gate pad GP are formed.

[0071] Next, the back surface of the wafer 1 is thinned by performing a backgrinding process. If necessary, chemical etching or the like is also performed to remove damage to the back surface of the wafer 1.

[0072] Next, a field stop region Ns is formed on the back surface of the wafer 1 by introducing N-type impurities by, for example, ion implantation. The field stop region Ns is also called an N-type field stop region. Thereafter, as necessary, laser annealing or the like is performed on the back surface Sb of the wafer 1 to activate the impurities.

[0073] Next, a collector region PC is formed on the back surface of the wafer 1 by introducing P-type impurities into the back surface of the wafer 1, for example, by ion implantation. The collector region PC is also called a P+ type collector region. Thereafter, if necessary, laser annealing or the like is performed on the back surface of the wafer 1 to activate the impurities.

[0074] Next, a metal film such as aluminum is formed by, for example, sputtering, to form a collector electrode CE electrically connected to the collector region PC on the rear surface of the wafer 1. As a result, as shown in Fig. 3, the collector region PC is provided in the semiconductor region on the rear surface of the semiconductor chip, and the collector electrode CE is provided on the front surface of the collector region PC. A field stop region Ns is provided between the drift layer ND constituting the main portion of the substrate S and the collector region PC. The emitter electrode EE, the gate electrode GE, and the collector electrode CE constitute an IGBT.

[0075] Thereafter, the wafer 1 is divided into chip regions of the substrate S by dicing or the like, and sealed in a package as necessary, thereby almost completing the semiconductor device of the embodiment.

[0076] The effects of the semiconductor device according to the embodiment will be described.

[0077] First, a technique (hereinafter, referred to as a comparative example) that the present disclosure examiners conducted prior to the present disclosure will be described with reference to Fig. 16 and Fig. 17. Fig. 16 is a plan view of a main part of a semiconductor device in the comparative example. Fig. 17 is a cross-sectional view taken along line A1-A2 of the semiconductor device shown in Fig. 16.

[0078] The semiconductor device in the comparative example has a structure in which the second insulating film HLD, the conductive film G2, and the second plug PL2 are not present in the inactive cell region LCi, unlike the semiconductor device in the embodiment shown in FIG.

[0079] The emitter pad EP is electrically connected to a clip, which is a plate-shaped conductor such as copper (Cu), via solder, for example. A peeling test (hereinafter referred to as a copper sheet peeling test) is performed to evaluate the OPM. In the copper sheet peeling test of the semiconductor device of the comparative example, peeling may occur not at the interface between the OPM and the emitter electrode EE but at the interface between the barrier metal film BM and the interlayer insulating film IL. In the copper sheet peeling test, peeling at the solder bulk is considered to be a good product. Here, the emitter electrode EE is formed of a metal film mainly composed of aluminum (Al), the barrier metal film BM is formed of a titanium tungsten (TiW) film, and the first plug PL1 is formed of tungsten (W).

[0080] The reason why peeling occurs at the interface between the barrier metal film BM and the interlayer insulating film IL in the semiconductor device of the comparative example will be described.

[0081] (Structural reason) Because of the plug contact structure, the barrier metal film BM (TiW film) is in contact with the top surface of the plug, but not with the inside of the contact groove CT. Therefore, the so-called anchor effect is considered to be small.

[0082] (Material reasons) A barrier metal film (herein referred to as a W-based barrier metal film) formed from a material containing tungsten (W) and tungsten (W) has good adhesion due to the miscibility of the two metals. A W-based barrier metal film is an alloy film whose main component is W, such as TiW. On the other hand, a W-based barrier metal film and a silicon oxide film have a certain degree of adhesion. In particular, in the case of TiW, the adhesion with the silicon oxide film is relatively good due to the action of Ti. However, since the Ti content of TiW is about 10%, the adhesion is lower than that with tungsten (W).

[0083] (Estimated mechanism) It is speculated that when the shear stress caused by peeling off the copper plate was applied to the interface between the barrier metal film BM and the interlayer insulating film IL, the interface peeled off because the anchor effect was small due to the structural reasons mentioned above. In particular, the IE type trench gate IGBT has a large area where the floating region PF is formed, so there are few plugs. Therefore, it is speculated that the peeling became even more likely due to the material reasons mentioned above.

[0084] In the comparative example, there is nothing on the floating region PF, and the barrier metal film BM and the interlayer insulating film IL are bonded to each other in a wide flat area. In contrast, in the embodiment, a plug structure is formed in the flat area on the floating region PF, and the contact area between the plug and the barrier metal film is increased, resulting in an anchor effect, which improves the adhesion between the barrier metal film BM and the interlayer insulating film IL compared to the comparative example.

[0085] In addition, materials with good compatibility between the metals of the barrier metal film BM and the plug are used, for example, an alloy film (e.g., TiW) whose main component is tungsten (W) is used for the barrier metal film BM, and tungsten (W) is used for the plug. This improves the adhesion between the barrier metal film BM and the interlayer insulating film IL by contacting TiW and tungsten (W) in the plug, compared to the TiW-silicon oxide film interface in a simple flat portion as in the comparative example.

[0086] <Modification> Below, some representative modified examples of the embodiment are exemplified. In the following description of the modified examples, the same reference numerals as those in the above-mentioned embodiment may be used for parts having the same configuration and function as those described in the above-mentioned embodiment. The description of such parts may be appropriately cited within the scope of technical inconsistency. Furthermore, a part of the above-mentioned embodiment and all or a part of the multiple modified examples may be appropriately applied in a composite manner within the scope of technical inconsistency.

[0087] (First Modification) FIG. 18 is a schematic cross-sectional view showing the configuration of a semiconductor device in the first modified example. In FIG. 18, only the main parts of the inside of the substrate S are shown.

[0088] In the embodiment, the conductive film PCF is etched back, so that the first plug PL1 and the second plug PL2 are formed such that the center of the first plug PL1 and the center of the second plug PL2 are recessed (concave) in plan view. In the first modified example, this recess is made even larger, and the upper surfaces of the first plug PL1 and the second plug PL2 are formed in a V shape, as shown in Fig. 18. This makes it possible to increase the contact area between the barrier metal film BM and the first plug PL1 and the second plug PL2 more than in the embodiment.

[0089] The V-shape of the upper surface of the plug in the contact trench CT described above is obtained by adjusting the amount of overetching when etching back the plug material.

[0090] In FIG. 3, the top surfaces of the first plug PL1, the second plug PL2, the barrier metal film BM, the emitter electrode EE, and the insulating film FPF are shown as being flat; however, as shown in FIG. 18, the presence of the second insulating film HLD, the conductive film G2, and the second plug PL2 results in steps.

[0091] 18, the top surfaces of the first plug PL1 and the second plug PL2 are V-shaped, causing a step. Therefore, above the first plug PL1, the barrier metal film BM, the emitter electrode EE, and the OPM as a conductive film have a cross section that follows the V-shape of the two plugs. Above the second plug PL2, the emitter electrode EE and the conductive film OPM are higher, and have a cross section that follows the V-shape of the second plug PL2.

[0092] (Second Modification) Fig. 19 is a schematic cross-sectional view showing the configuration of a semiconductor device in the second modified example. In Fig. 19, only the main parts of the inside of the substrate S are shown.

[0093] Instead of the gate insulating film GF, the second insulating film HLD, and the conductive film G2 in the embodiment, an isolation insulating film LCS including a silicon oxide film is formed on the upper part of the floating region PF by a LOCOS (Local Oxidation of Silicon) process. When a contact groove is formed in the isolation insulating film LCS on the floating region PF with a simple LOCOS process, there is a concern that the contact may be punched through. In that case, it is preferable to use a recessed LOCOS process. This makes it possible to avoid punch-through.

[0094] The disclosure made by the present inventor has been specifically described above based on the embodiments, but it goes without saying that the present disclosure is not limited to the above-described embodiments and can be modified in various ways.

[0095] In the embodiment, the GGEE type IGBT has been described, but the present invention is not limited thereto and can be applied to an IE type trench gate IGBT having a wide floating region. That is, the present invention can be applied to, for example, a GG type IGBT, an EGE-S type IGBT, and a GE-S type IGBT described in JP2019-29434A.

[0096] Here, the GG-type IGBT has a trench gate electrode between the active cell region and the inactive cell region, and a floating region is formed between the trench gate electrodes in the inactive cell region. The trench gate electrode extends from the front surface side of the substrate through the body region PB and the emitter region to the back surface side.

[0097] The EGE-S type IGBT has a trench emitter electrode between the active cell region and the inactive cell region, and a trench gate electrode between the trench emitter electrodes in the active cell region. A floating region is formed between the trench emitter electrodes. The trench emitter electrode extends from the front surface side of the substrate through the body region PB and the emitter region to the back surface side.

[0098] The GE-S type IGBT has a trench gate electrode or a trench emitter electrode between the active cell region and the inactive cell region, and the trench gate electrode and the trench emitter electrode are provided on either side of the inactive cell region. In other words, a floating region is formed between the trench gate electrode and the trench emitter electrode. The trench gate electrode penetrates the body region PB and the emitter region from the front side of the substrate and extends to the back side. The trench emitter electrode penetrates the body region PB and the emitter region from the front side of the substrate and extends to the back side. [Explanation of symbols]

[0099] S··· substrate (semiconductor substrate) ND...Drift layer PB: Body region NE···Emitter area TG1 Trench gate electrode TG2 Trench emitter electrode PF... Floating area IL: Interlayer insulating film PL1: First plug PL2: Second plug BM: Barrier metal film MT Metal film

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; A drift layer formed on the semiconductor substrate; a body region formed on the drift layer; an emitter region formed on the body region; a trench gate electrode extending from the first major surface through the body region and the emitter region toward the second major surface; a trench emitter electrode formed adjacent to the trench gate electrode, penetrating the body region and extending in a direction toward the second main surface in a plan view; a floating region formed between the trench gate electrode and the trench emitter electrode; a laminated film formed on the floating region; an interlayer insulating film formed on the laminated film and the body region; a first plug penetrating the interlayer insulating film and reaching the body region; a second plug penetrating the interlayer insulating film and reaching the stacked film; a barrier metal film formed so as to cover the interlayer insulating film, the first plug, and the second plug; and a metal film formed on the barrier metal film.

2. 2. The semiconductor device according to claim 1, wherein said barrier metal film is in contact with said interlayer insulating film, said first plug, and said second plug.

3. The semiconductor device according to claim 1 , wherein the second plug is formed in a plurality on the floating region.

4. 2. The semiconductor device according to claim 1, wherein said first plug and said second plug are formed such that a center portion of said first plug and a center portion of said second plug are recessed in a plan view.

5. 2. The semiconductor device according to claim 1, wherein the first plug is electrically connected to the body region, and the second plug is not electrically connected to the floating region or the body region.

6. 2. The semiconductor device according to claim 1, wherein the material of said barrier metal film is an alloy film containing tungsten as a main component.

7. 2. The semiconductor device according to claim 1, wherein the material of said barrier metal film is titanium tungsten.

8. 2. The semiconductor device according to claim 1, wherein the material of said first plug and said second plug is tungsten.

9. 2. The semiconductor device according to claim 1, wherein said interlayer insulating film is a silicon oxide film.

10. 2. The semiconductor device according to claim 1, wherein said laminated film has an end portion above said floating region in a plan view, said end portion creating a step.

11. The semiconductor device according to claim 10 , wherein the step is 50 nm or more.

12. the laminated film is a film in which a first insulating film, a second insulating film, and a conductive film are laminated in this order, a gate insulating film is further provided at an interface between the trench gate electrode and the semiconductor substrate and at an interface between the trench emitter electrode and the semiconductor substrate; 2. The semiconductor device according to claim 1, wherein said first insulating film is formed in the same layer as said gate insulating films of said trench gate electrode and said trench emitter electrode.

13. 2. The semiconductor device according to claim 1, wherein said first plug is formed so as to straddle between said trench emitter electrode and said emitter region.

14. the trench gate electrode and the trench emitter electrode are adjacent to each other in a first direction in a plan view, 2 . The semiconductor device according to claim 1 , wherein the trench gate electrode, the trench emitter electrode, the first plug, and the second plug extend in a second direction intersecting the first direction in a plan view.

15. the drift layer and the emitter region are of a first conductivity type; 2. The semiconductor device according to claim 1, wherein said body region and said floating region are of a second conductivity type opposite to said first conductivity type.

16. a gate electrode formed on the first main surface and electrically connected to the trench gate electrode; an emitter electrode formed on the first major surface and electrically connected to the trench emitter electrode; a collector electrode formed on the second major surface, 2. The semiconductor device according to claim 1, wherein said emitter electrode, said gate electrode and said collector electrode constitute an IGBT.

17. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; A drift layer formed on the semiconductor substrate; a body region formed on the drift layer; an emitter region formed on the body region; a trench gate electrode extending from the first major surface through the body region and the emitter region toward the second major surface; a trench emitter electrode formed adjacent to the trench gate electrode, penetrating the body region and extending in a direction toward the second main surface in a plan view; a floating region formed between the trench gate electrode and the trench emitter electrode; an isolation insulating film formed on the floating region; an interlayer insulating film formed on the isolation insulating film and the body region; a first plug penetrating the interlayer insulating film and reaching the body region; a second plug penetrating the interlayer insulating film and reaching the isolation insulating film; a barrier metal film formed so as to cover the interlayer insulating film, the first plug, and the second plug; and a metal film formed on the barrier metal film.

18. forming a drift layer on a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; forming a body region on the drift layer; forming an emitter region over the body region; forming a trench gate electrode penetrating the body region and the emitter region and extending in a direction toward the second main surface; forming a trench emitter electrode adjacent to the trench gate electrode, penetrating the body region, and extending in a direction toward the second main surface in a plan view; forming a floating region between the trench gate electrode and the trench emitter electrode; forming a laminated film having a first insulating film, a second insulating film, and a conductive film on the floating region; forming an interlayer insulating film on the stacked film and the body region; forming a first plug penetrating the interlayer insulating film and reaching the body region; forming a second plug penetrating the interlayer insulating film and reaching the stacked film; forming a barrier metal film so as to cover the interlayer insulating film, the first plug, and the second plug; forming a metal film on the barrier metal film; Including, the first insulating film is formed in the same layer as the gate insulating films of the trench gate electrode and the trench emitter electrode; The first plug and the second plug are formed simultaneously.

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