Semiconductor storage device

Abstract

To suppress the decrease in reliability of a semiconductor storage device.SOLUTION: A semiconductor storage device in an embodiment includes: a semiconductor substrate including a first region, a second region, and a third region, each of which is a source region or a drain region, arranged in this order apart from each other in a first direction in an element region; a first conductive layer having a first opening part; a second conductive layer having a second opening part and arranged apart from the first conductive layer in the first direction; a first contact connected to the first region and passing the first opening part; a second contact connected to the third region and passing the second opening part; and a third conductive layer and a fourth conductive layer provided between the first conductive layer and the second conductive layer and arranged in this order apart from each other in the first direction. The third conductive layer is disposed apart from the first conductive layer. The fourth conductive layer is disposed apart from the second conductive layer. The first conductive layer and the first contact are connected to each other so as to have the substantially same potential. The second conductive layer and the second contact are connected to each other so as to have the substantially same potential.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is a well-known semiconductor memory device capable of storing data nonvolatilely. Semiconductor memory devices such as NAND flash memory employ a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2014 / 0284713 Summary of the Invention [Problem to be solved by the invention]

[0004] This suppresses a decrease in the reliability of the semiconductor memory device. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment includes a semiconductor substrate including an element region, and a first region, a second region, and a third region, each of which is a source region or a drain region, arranged in this order in the element region and spaced apart from one another in a first direction; a first conductor layer provided above the element region and having a first opening; a second conductor layer provided above the element region and having a second opening, arranged adjacent to the first conductor layer in the first direction and spaced apart from the first conductor layer; a first contact connected to the first region and passing through the first opening; a second contact connected to the third region and passing through the second opening; The memory cell includes a first memory cell connected to a first contact, a second memory cell connected to a second contact, and a third conductive layer and a fourth conductive layer provided above an element region between the first conductive layer and the second conductive layer and arranged in this order and spaced apart from each other in a first direction, wherein the third conductive layer is arranged spaced apart from the first conductive layer and the fourth conductive layer is arranged spaced apart from the second conductive layer, the first conductive layer and the first contact are connected to each other so as to have approximately the same potential, and the second conductive layer and the second contact are connected to each other so as to have approximately the same potential. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment; [Figure 2] 1 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a semiconductor memory device according to an embodiment. [Figure 3] 1 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor memory device according to an embodiment. [Figure 4] FIG. 2 is a circuit diagram showing an example of the configuration of a row decoder module, a driver module, and a memory cell array of the semiconductor memory device according to the embodiment. [Figure 5] FIG. 2 is a circuit diagram showing an example of the configuration of a block decoder included in the semiconductor memory device according to the embodiment. [Figure 6] 1 is a plan view showing an example of a planar structure of a row decoder module of a semiconductor memory device according to an embodiment; [Figure 7]1 is a plan view showing an example of a planar structure of a transfer transistor included in a semiconductor memory device according to an embodiment; [Figure 8] 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7, showing an example of a cross-sectional structure of a transfer transistor included in the semiconductor memory device according to the embodiment. [Figure 9] 9 is a cross-sectional view taken along line IX-IX in FIG. 7, showing an example of a cross-sectional structure of a transfer transistor included in the semiconductor memory device according to the embodiment. [Figure 10] 10A and 10B are cross-sectional views showing an example of a structure during manufacturing of a transfer transistor included in the semiconductor memory device according to the embodiment. [Figure 11] 10A and 10B are cross-sectional views showing an example of a structure during manufacturing of a transfer transistor included in the semiconductor memory device according to the embodiment. [Figure 12] 10 is a plan view showing an example of a planar structure of a transfer transistor included in a semiconductor memory device according to a first modification. FIG. [Figure 13] 10 is a graph showing an example of a surface breakdown voltage of a transfer transistor according to a first modification. [Figure 14A] 14 is a cross-sectional view taken along line XIV-XIV in FIG. 12, showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a first modification. [Figure 14B] 14 is a cross-sectional view taken along line XIV-XIV in FIG. 12, showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a first modification. [Figure 14C] FIG. 14B is an enlarged cross-sectional view of the dashed-dotted line frame in FIG. 14A. [Figure 14D] FIG. 14C is an enlarged cross-sectional view of the dashed-dotted line frame in FIG. 14B. [Figure 15] 10 is a graph showing an example of an on-current of a transfer transistor according to a first modification. [Figure 16] 10 is a plan view showing an example of a planar structure of a transfer transistor included in a semiconductor memory device according to a second modification. FIG. [Figure 17] 17 is a cross-sectional view taken along line XVII-XVII in FIG. 16, showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a second modification. [Figure 18] 17 is a cross-sectional view taken along line XVIII-XVIII in FIG. 16, showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a second modification. [Figure 19] FIG. 11 is a plan view showing an example of a planar structure of a transfer transistor included in a semiconductor memory device according to a third modification. [Figure 20] 20 is a cross-sectional view taken along line XX-XX in FIG. 19, showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a third modification. [Figure 21] FIG. 11 is a plan view showing an example of a planar structure of a transfer transistor included in a semiconductor memory device according to a fourth modification. [Figure 22] 22 is a cross-sectional view taken along line XXII-XXII in FIG. 21, showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a fourth modification. [Figure 23] FIG. 11 is a plan view showing an example of a planar structure of a transfer transistor included in a semiconductor memory device according to a fifth modification. [Figure 24] 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 23, showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a fifth modification. [Figure 25] FIG. 13 is a plan view showing an example of a planar structure of a transfer transistor included in a semiconductor memory device according to a sixth modification. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and proportions of the drawings are not necessarily the same as those in reality.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. Embodiment 1.1 Configuration 1.1.1 Memory System FIG. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to the embodiment.

[0010] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2.

[0011] The memory system 3 may be, for example, an SD TM The memory system 3 is configured to be connected to an external host device (not shown).

[0012] The memory controller 2 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 controls the semiconductor memory device 1 based on a request from the host device. Specifically, for example, the memory controller 2 writes data requested to be written by the host device to the semiconductor memory device 1. The memory controller 2 also reads data requested to be read by the host device from the semiconductor memory device 1 and transmits the data to the host device.

[0013] The semiconductor memory device 1 is, for example, a NAND flash memory. The semiconductor memory device 1 stores data in a nonvolatile manner. The semiconductor memory device 1 is connected to a memory controller 2 via a NAND bus B.

[0014] The NAND bus B is, for example, a bus conforming to an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0015] 1.1.2 Semiconductor memory devices Continuing with the description of the internal configuration of the semiconductor memory device 1 according to the embodiment, with reference to the block diagram shown in Fig. 1, the semiconductor memory device 1 includes, for example, a memory cell array 10 and a peripheral circuit PERI. The peripheral circuit PERI includes a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0016] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). A block BLK is a collection of a plurality of memory cell transistors capable of storing data non-volatilely, and is used, for example, as a unit for erasing data. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. One memory cell transistor is associated with, for example, one bit line and one word line.

[0017] The command register 11 holds the command CMD that the semiconductor memory device 1 receives from the memory controller 2. The command CMD includes, for example, an instruction to make the sequencer 13 execute a read operation, a write operation, an erase operation, and the like.

[0018] The address register 12 holds address information ADD that the semiconductor memory device 1 receives from the memory controller 2. The address information ADD includes, for example, a page address PA, a block address BA, and a column address CA. For example, the page address PA, the block address BA, and the column address CA are used to select a word line, a block BLK, and a bit line, respectively.

[0019] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD held in the command register 11 to perform read operations, write operations, erase operations, etc.

[0020] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to a signal line corresponding to a selected word line based on, for example, a page address PA held in the address register 12.

[0021] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0022] The sense amplifier module 16 transfers data DAT between the memory controller 2 and the memory cell array 10. The data DAT includes write data and read data. More specifically, in a write operation, the sense amplifier module 16 transfers write data received from the memory controller 2 to the memory cell array 10. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell transistors based on the voltage of the bit line. Then, the sense amplifier module 16 transfers the result of this determination to the memory controller 2 as read data.

[0023] 1.1.3 Memory cell array circuit configuration Fig. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the semiconductor memory device according to the embodiment. Fig. 2 shows one block BLK among multiple blocks BLK included in the memory cell array 10. In the example shown in Fig. 2, the block BLK includes, for example, five string units SU0 to SU4.

[0024] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each of the memory cell transistors MT0 to MT7 includes a control gate and a charge storage layer, and stores data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select the string unit SU during various operations. In the following description, the memory cell transistors MT0 to MT7 are also referred to as memory cell transistors MT.

[0025] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. One end of the select transistor ST1 is connected to the associated bit line BL, and the other end of the select transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. One end of the select transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The other end of the select transistor ST2 is connected to a source line SL.

[0026] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistor ST1 in string units SU0 to SU4 are connected to select gate lines SGD0 to SGD4, respectively. In contrast, the gates of multiple select transistors ST2 are commonly connected to a select gate line SGS. However, this is not limited to this, and the gates of multiple select transistors ST2 may be connected to multiple select gate lines that are different for each string unit SU. In the following description, when the word lines WL0 to WL7 are not distinguished, they will simply be referred to as word lines WL. Furthermore, when the select gate lines SGD0 to SGD4 are not distinguished, they will simply be referred to as select gate lines SGD.

[0027] Each of the bit lines BL0 to BLm commonly connects one NAND string NS included in each string unit SU across multiple blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, across multiple blocks BLK.

[0028] A set of memory cell transistors MT connected to a common word line WL within one string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0029] The circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to the embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0030] 1.1.4 Cross-sectional structure of semiconductor memory device Next, the cross-sectional structure of the semiconductor memory device 1 according to the embodiment will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device according to the embodiment. Fig. 3 shows a cross-sectional structure including two of the five string units SU included in one block BLK.

[0031] In the drawings referred to below, the X direction corresponds to the extension direction of the word lines WL, the Y direction corresponds to the extension direction of the bit lines BL, and the Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate on which the semiconductor memory device 1 is formed.

[0032] The memory cell array 10 includes conductor layers 21, 22, 24, and 25, a plurality of conductor layers 23, and a plurality of memory pillars MP (only two are shown in FIG. 3 ) provided above a semiconductor substrate 20. In the following description, the direction in which the memory cell array 10 is provided relative to the semiconductor substrate 20 is referred to as the upward direction, and the opposite direction is referred to as the downward direction.

[0033] An insulating layer 30 is provided on the semiconductor substrate 20. The insulating layer 30 includes a peripheral circuit PERI corresponding to, for example, the row decoder module 15 and the like.

[0034] A conductor layer 21 is stacked on the insulating layer 30. The conductor layer 21 is formed, for example, in the shape of a plate extending along the XY plane. The conductor layer 21 is used as the source line SL. The conductor layer 21 is made of a conductive material, such as an N-type semiconductor doped with impurities, or a metal material such as titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), a laminated film of tantalum nitride (TaN) and tantalum (Ta), a laminated film of titanium (Ti), titanium nitride (TiN) and tungsten (W), or a laminated film of titanium nitride (TiN) and tungsten silicide (WSi). The conductor layer 21 may also have a laminated structure of a semiconductor and a metal material, such as a laminated film of titanium nitride (TiN), tungsten silicide (WSi), and poly-Si.

[0035] An insulator layer 31 is provided on the conductor layer 21. A conductor layer 22 is stacked on the insulator layer 31. The conductor layer 22 is formed, for example, in the shape of a plate extending along the XY plane. The conductor layer 22 is used as a select gate line SGS. The conductor layer 22 contains, for example, tungsten (W).

[0036] An insulator layer 32 is provided on the conductor layer 22. Eight conductor layers 23 and eight insulator layers 33 are stacked on the insulator layer 32 in the following order: conductor layer 23, insulator layer 33, ..., conductor layer 23, insulator layer 33. The conductor layer 23 is formed, for example, in the shape of a plate extending along the XY plane. The stacked eight conductor layers 23 are used as word lines WL0 to WL7, respectively, in order from the conductor layer 21 side. The conductor layer 23 contains, for example, tungsten (W).

[0037] A conductor layer 24 and an insulator layer 34 are stacked in this order on the uppermost insulator layer 33. The conductor layer 24 is formed, for example, in the shape of a plate extending along the XY plane. The stacked conductor layer 24 is used as a select gate line SGD. The conductor layer 24 contains, for example, tungsten (W). The conductor layer 24 is electrically separated for each string unit SU by, for example, a slit SHE.

[0038] An insulating layer 34 is provided on the conductive layer 24. A conductive layer 25 is provided on the insulating layer 34. The conductive layer 25 is formed in the shape of a line extending in the Y direction, for example, and functions as the bit line BL. The conductive layer 25 contains, for example, copper (Cu).

[0039] The multiple memory pillars MP are provided below the conductive layer 25, extending along the Z direction, and penetrate the conductive layers 22 and 24 and the multiple conductive layers 23. The bottom of each memory pillar MP is located below the insulating layer 31 and contacts the conductive layer 21.

[0040] Each of the memory pillars MP includes, for example, a core member 35, a semiconductor film 36, a tunnel insulating film 37, a charge storage film 38, a block insulating film 39, and a semiconductor portion 26.

[0041] The core member 35 is provided to extend, for example, along the Z direction. The upper end of the core member 35 is included in a layer above the conductive layer 24, and the lower end of the core member 35 is included in a layer below the conductive layer 22. The core member 35 includes, for example, silicon oxide (SiO2).

[0042] The semiconductor film 36 is provided so as to cover the side and bottom surfaces of the core member 35. The top end of the semiconductor film 36 reaches a position equivalent to the top end of the core member 35. The bottom end of the semiconductor film 36 contacts the conductor layer 21. The semiconductor film 36 includes, for example, polysilicon.

[0043] The tunnel insulating film 37 covers the side surface of the semiconductor film 36. The tunnel insulating film 37 includes, for example, silicon oxide (SiO2).

[0044] The charge storage film 38 covers the side surface of the tunnel insulating film 37. The charge storage film 38 includes, for example, an insulator capable of storing charges. The insulator is, for example, silicon nitride (SiN).

[0045] The block insulating film 39 covers the side surfaces of the charge storage film 38. The block insulating film 39 includes, for example, silicon oxide (SiO2).

[0046] The semiconductor portion 26 is provided so as to be in contact with the semiconductor film 36 and to cover the upper end of the core member 35. A conductor layer 27 functioning as a pillar-shaped contact CV is provided on the upper end of the semiconductor portion 26. The upper end of the conductor layer 27 is in contact with the conductor layer 25.

[0047] In the structure of the memory pillar MP described above, the portion where the memory pillar MP intersects with the conductive layer 22 functions as the select transistor ST2. Also, the portion where the memory pillar MP intersects with the conductive layer 23 functions as the memory cell transistor MT. Also, the portion where the memory pillar MP intersects with the conductive layer 24 functions as the select transistor ST1. Also, the semiconductor film 36 functions as the channels of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. Also, the charge storage film 38 functions as the charge storage layer of the memory cell transistor MT.

[0048] 1.1.5 Row Decoder Module Next, a configuration example of the row decoder module 15 included in the peripheral circuit PERI will be described.

[0049] 1.1.5.1 Overall Configuration The overall configuration of the row decoder module 15 will be described with reference to Fig. 4. Fig. 4 is a circuit diagram for explaining an example of the configuration of the row decoder module, the driver module, and the memory cell array of the semiconductor memory device according to the embodiment.

[0050] The row decoder module 15 includes row decoders RD0 to RDn, which are used to select blocks BLK and are associated with the blocks BLK0 to BLKn, respectively.

[0051] Each row decoder RD includes, for example, a block decoder BD and transfer transistors TW0 to TW7, TS, and TD0 to TD4. The transfer transistors TW0 to TW7, TS, and TD0 to TD4 are, for example, high-voltage N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). The transfer transistors TW0 to TW7 are associated with word lines WL0 to WL7, respectively. In the following description, when the transfer transistors TW0 to TW7 are not distinguished, they are simply referred to as transfer transistors TW. The transfer transistors TS and TD0 to TD4 are associated with select gate lines SGS and SGD0 to SGD4, respectively. In the following description, when the transfer transistors TD0 to TD4 are not distinguished, they are simply referred to as transfer transistors TD. A high-voltage MOSFET is a MOSFET whose gate insulating film has a physical thickness of 10 nm or more. The gate-source voltage of a high-voltage N-channel MOSFET can be, for example, 10 V or more.

[0052] The block decoder BD decodes the block address BA and applies a high (H) level voltage and a low (L) level voltage to the transfer gate line BLKSEL based on the result of the decoding, for example.

[0053] The transfer transistors TW0 to TW7, TS, and TD0 to TD4 connect the driver module 14 to the corresponding blocks BLK via signal lines CG0 to CG7, CGS, and CGD0 to CGD4, respectively. In the following description, when there is no need to distinguish between the signal lines CG0 to CG7, CGS, and CGD0 to CGD4, they will simply be referred to as signal lines CG.

[0054] More specifically, in each row decoder RD, the gate of the transfer transistor TD is connected to a transfer gate line BLKSEL. A first end of each transfer transistor TD is connected to the driver module 14 via a corresponding signal line CG among the signal lines CGD0 to CGD4. A second end of the transfer transistor TD is connected to a corresponding select gate line SGD among the select gate lines SGD0 to SGD4.

[0055] A gate of each transfer transistor TW is connected to a transfer gate line BLKSEL. A first end of each transfer transistor TW is connected to the driver module 14 via a corresponding signal line CG among the signal lines CG0 to CG7. A second end of each transfer transistor TW is connected to a corresponding word line WL among the word lines WL0 to WL7.

[0056] The gate of the transfer transistor TS is connected to a transfer gate line BLKSEL, a first terminal of the transfer transistor TS is connected to the driver module 14 via a signal line CGS, and a second terminal of the transfer transistor TS is connected to a select gate line SGS.

[0057] When a "H" level voltage is applied to the transfer gate line BLKSEL, the transfer transistors TW, TS, and TD are turned on. As a result, the voltages of the signal lines CG0 to CG7, CGS, and CGD0 to CGD4 are transferred to the word lines WL0 to WL7, select gate lines SGS, and select gate lines SGD0 to SGD4 via the transfer transistors TW0 to TW7, TS, and TD0 to TD4, respectively. When a "L" level voltage is applied to the transfer gate line BLKSEL, the transfer transistors TW, TS, and TD are turned off.

[0058] 1.1.5.2 Block Decoder The configuration of the block decoder BD included in each row decoder RD will be described with reference to Fig. 5. Fig. 5 is a circuit diagram for explaining an example of the configuration of the block decoder included in the semiconductor memory device according to the embodiment.

[0059] As shown in FIG. 5, the block decoder BD includes a logic circuit LC, an AND circuit AND, inverters INV1 and INV2, and transistors T1, T2, T3, and T4. The transistors T1, T2, and T4 are N-channel MOSFETs. The transistor T3 is a P-channel MOSFET. The transistors T2, T3, and T4 are high-voltage MOSFETs having a thicker physical thickness of the gate insulating film than the transistor T1. The physical thickness of the gate insulating film of each of the transistors T2, T3, and T4 is, for example, 10 nm or more. The gate-source voltage of each of the transistors T2, T3, and T4 can be, for example, 10 V or more. On the other hand, the physical thickness of the gate insulating film of the transistor T1 is, for example, less than 10 nm. The gate-source voltage of the transistor T1 is, for example, lower than 10 V.

[0060] A block address BA is input from the address register 12 to a first terminal of the logic circuit LC. For example, a power supply voltage VDD is applied to a second terminal of the logic circuit LC. The logic circuit LC is driven by the power supply voltage VDD. A signal based on the block address BA is output from a third terminal of the logic circuit LC. If the block address BA input to the logic circuit LC is the block address BA assigned to the block BLK corresponding to the logic circuit LC, a "H" level signal is output from the second terminal of the logic circuit LC. If the block address BA input to the logic circuit LC is not the block address BA assigned to the block BLK corresponding to the logic circuit LC, a "L" level signal is output from the second terminal of the logic circuit LC.

[0061] A first terminal of the AND circuit AND is connected to a third terminal of the logic circuit LC. A second terminal of the AND circuit AND is applied with, for example, a power supply voltage VDD. The AND circuit AND is driven by the power supply voltage VDD. A signal based on a logical AND operation of the signals output from the third terminal of the logic circuit LC is output from the third terminal of the AND circuit AND.

[0062] A first terminal of the inverter INV1 is connected to a third terminal of the AND circuit AND. A power supply voltage VDD, for example, is applied to a second terminal of the inverter INV1. The inverter INV1 is driven by the power supply voltage VDD. A third terminal of the inverter INV1 is connected to a node N1. An inverted signal of the signal output from the third terminal of the AND circuit AND is output from the third terminal of the inverter INV1.

[0063] A first terminal of the inverter INV2 is connected to the node N1. A second terminal of the inverter INV2 is applied with, for example, a power supply voltage VDD. The inverter INV2 is driven by the power supply voltage VDD. An inverted signal of the signal output from the third terminal of the inverter INV1 is output from a third terminal of the inverter INV2.

[0064] A first terminal of the transistor T1 is connected to a third terminal of the inverter INV2, a power supply voltage VDD is applied to a gate of the transistor T1, and a second terminal of the transistor T1 is connected to the transistor T2.

[0065] A first terminal of the transistor T2 is connected to the second terminal of the transistor T1, a power supply voltage VDD is applied to the gate of the transistor T2, and a second terminal of the transistor T2 is connected to the transfer gate line BLKSEL.

[0066] A first terminal of the transistor T3 is connected to the transfer gate line BLKSEL, a gate of the transistor T3 is connected to the node N1, and a second terminal of the transistor T3 is connected to the back gate of the transistor T3 and the transistor T4.

[0067] A first end of the transistor T4 is connected to a second end of the transistor T3 and a back gate of the transistor T3. A gate of the transistor T4 is connected to a transfer gate line BLKSEL. A second end of the transistor T4 is connected to a node VRDEC. A high voltage is applied to the node VRDEC, and is transferred to the transfer gate line BLKSEL via the transistors T3 and T4, so that the transfer transistors TW, TS, and TD can transfer the voltages supplied to the corresponding signal lines CG to the word line WL, select gate line SGS, and select gate line SGD, respectively.

[0068] With the above configuration, the block decoder BD outputs a "H" level signal to the transfer gate line BLKSEL when the corresponding block BLK is selected, and outputs a "L" level signal to the transfer gate line BLKSEL when the corresponding block BLK is not selected.

[0069] 1.1.5.3 Row Decoder Module Planar Configuration The planar structure of the row decoder module 15 of the semiconductor memory device 1 according to the embodiment will be described with reference to FIG. 6. FIG. 6 is a plan view showing an example of the planar structure of the row decoder module of the semiconductor memory device according to the embodiment. In the following description, the transfer transistors TW0 to TW7, TS, and TD0 to TD4 included in the row decoder RDi and the block decoder BD will also be referred to as transfer transistors TW0_i to TW7_i, TS_i, and TD0_i to TD4_i and block decoder BD_i, respectively. i is an integer between 0 and n.

[0070] The row decoder module 15 is provided on a semiconductor substrate 20 .

[0071] An N-type well region 40 is provided in the semiconductor substrate 20. The N-type well region 40 is a region containing N-type impurities. The N-type well region 40 is provided in, for example, a rectangular region.

[0072] A P-type well region 41 is provided in the N-type well region 40. The P-type well region 41 is a region that contains P-type impurities. The P-type well region 41 is provided in, for example, a rectangular region.

[0073] The pair of row decoders RD(2j) and RD(2j+1) is provided in, for example, a rectangular area, where j is an integer not less than 0 and not more than (n-1) / 2.

[0074] The set of row decoders RD0 and RD1, the set of row decoders RD2 and RD3, the set of row decoders RD4 and RD5, . . . are arranged in this order along the Y direction, for example.

[0075] In the pair of row decoders RD(2j) and RD(2j+1), transfer transistors TS_(2j) and TS_(2j+1), TW0_(2j) and TW0_(2j+1), ..., TW7_(2j) and TW7_(2j+1), TD0_(2j) and TD0_(2j+1), ..., and TD4_(2j) and TD4_(2j+1) are each provided, for example, in a P-type well region 41.

[0076] In the pair of row decoders RD(2j) and RD(2j+1), the block decoders BD_(2j) and BD_(2j+1) are provided outside the N-type well region 40, for example.

[0077] The set of multiple transfer transistors TW_(2j) and TW_(2j+1), the set of TS_(2j) and TS_(2j+1), and the set of TD_(2j) and TD_(2j+1) are arranged in a matrix, for example, aligned in the X and Y directions.

[0078] 1.1.5.4 Transfer Transistor The configurations of the transfer transistors TW, TS, and TD included in the semiconductor memory device 1 according to the embodiment will be described.

[0079] (Planar structure) The planar structure of the transfer transistors TW, TS, and TD will be described with reference to FIG. 7. FIG. 7 is a plan view showing an example of the planar structure of the transfer transistors included in the semiconductor memory device according to the embodiment. In the example shown in FIG. 7, a planar structure including the transfer transistors TW0_0 and TW0_1 of the configuration shown in FIG. 6 is mainly shown. FIG. 7 also shows a portion of the transfer transistor TW1_0, a portion of the transfer transistor TW1_1, a portion of the transfer transistor TW0_2, and a portion of the transfer transistor TW1_2. The structure of the pair of transfer transistors TW_(2j) and TW_(2j+1), the structure of the pair of TS_(2j) and TS_(2j+1), and the structure of the pair of TD_(2j) and TD_(2j+1) are substantially equivalent to each other. In the following, the structure of the transfer transistors TW0_0 and TW0_1 will be mainly described.

[0080] The P-type well region 41 (element region) is electrically divided into P-type well regions 41A and 41B by, for example, an insulator layer 50 that functions as an element isolation region. In a plan view, the insulator layer 50 surrounds the P-type well region 41B. The P-type well region 41B is the region surrounded by a dashed line in FIG. 7. The P-type well region 41A is provided outside the region surrounded by the insulator layer 50, in a region not shown. The insulator layer 50 is provided in a lattice pattern, for example, to separate sets of multiple transfer transistors TW, TS, and TD arranged in a matrix.

[0081] In the P-type well region 41B, the transfer transistors TW0_0 and TW0_1 are arranged in this order along the Y direction. In the following description, the end of the transfer transistors TW0_0 and TW0_1 where the transfer transistor TW0_0 is provided is referred to as one end. Also, the end of the transfer transistors TW0_0 and TW0_1 where the transfer transistor TW0_1 is provided is referred to as the other end.

[0082] The P-type well region 41B is - Impurity diffusion regions 42, 43, and 44 are provided in this order and spaced apart from one another in the Y direction. - The impurity diffusion regions 42, 43, and 44 are N-type impurity diffusion regions of phosphorus (P) or arsenic (As), for example.

[0083] N - An electrode 201 is provided on the impurity diffusion region 42. - An electrode 202 is provided on the impurity diffusion region 43. - An electrode 203 is provided in the impurity diffusion region 44. The region where the electrodes 201, 202, and 203 are provided is the region surrounded by the dashed line in FIG.

[0084] The electrode 201 functions as a first terminal of the transfer transistor TW0_0. The electrode 203 functions as a first terminal of the transfer transistor TW0_1. The electrode 202 functions as a second terminal of the transfer transistor TW0_0 and a second terminal of the transfer transistor TW0_1. In this way, the transfer transistors TW0_0 and TW0_1 share the electrode 202.

[0085] A contact 61 is connected to the electrode 201. The contact 61 is connected to the word line WL0 of the block BLK0. A contact 62 is connected to the electrode 202. The contact 62 is connected to the signal line CG0. A contact 63 is connected to the electrode 203. The contact 63 is connected to the word line WL0 of the block BLK1. Note that, although the example shown in FIG. 7 shows a case where the number of contacts provided to each of the electrodes 201, 202, and 203 is one, this is not limitative. The number of contacts provided to each of the electrodes 201, 202, and 203 may be two or more.

[0086] Above the P-type well region 41B, five electrodes 101, 105, 107, 106, and 102 are provided in this order from one end to the other end along the Y direction, with a gate insulating film interposed therebetween.

[0087] The electrode 101 has an opening that surrounds the contact 61. The opening corresponds to the region where the electrode 201 is provided. Sidewalls (not shown in FIG. 7) are provided on the outer peripheral side surface of the electrode 101 and on the inner peripheral side surface of the electrode 101 that corresponds to the opening.

[0088] Furthermore, the electrode 101 is connected to the contact 67. The contact 67 is electrically connected to the contact 61 via the conductive layer 66. As a result, the electrode 101 is connected to the contact 61 so as to have approximately the same potential as the contact 61.

[0089] The electrode 102 has an opening that opens to surround the contact 63. The opening corresponds to the region where the electrode 203 is provided. Sidewalls (not shown in FIG. 7) are provided on the outer peripheral side surface of the electrode 102 and on the inner peripheral side surface of the electrode 102 that corresponds to the opening.

[0090] Furthermore, the electrode 102 is connected to the contact 68. The contact 68 is electrically connected to the contact 63 via the conductive layer 66. As a result, the electrode 102 is connected to the contact 63 so as to have approximately the same potential as the contact 63.

[0091] The electrode 105 functions as the gate of the transfer transistor TW0_0. A sidewall (not shown in FIG. 7) is provided on the outer side surface of the electrode 105.

[0092] The electrode 106 functions as the gate of the transfer transistor TW0_1. A sidewall (not shown in FIG. 7) is provided on the outer circumferential side surface of the electrode 106.

[0093] The electrode 107 has an opening that opens to surround the contact 62. The opening corresponds to the region where the electrode 202 is provided. Sidewalls (not shown in FIG. 7) are provided on the outer peripheral side surface of the electrode 107 and on the inner peripheral side surface of the electrode 107 that corresponds to the opening.

[0094] Furthermore, the electrode 107 is connected to the contact 69. The contact 69 is electrically connected to the contact 62 via the conductive layer 66. As a result, the electrode 107 is connected to the contact 62 so that the electrode 107 and the contact 62 have approximately the same potential.

[0095] Adjacent two electrodes among the electrodes 101, 102, 105, 106, and 107 are spaced apart from each other so as to form slits.

[0096] The overlap distance L shown in FIG. 7 is the distance between the electrodes 105 and N when viewed from the Z direction. -The overlap distance L indicates the distance in the Y direction that the impurity diffusion regions 42 overlap each other. - The overlap distance L is also the distance in the Y direction over which the impurity diffusion regions 44 overlap each other. The overlap distance L is, for example, 0.2 μm to 0.6 μm. The overlap distance L may be any distance that ensures the withstand voltage required for cutoff during write and erase operations. The width Ws is the slit width in the Y direction between adjacent electrodes among the electrodes 101, 102, 105, 106, and 107, as viewed from the Z direction. The width Ws is, for example, 0.1 μm to 0.2 μm. The width Wg is the width in the Y direction from the inner periphery of the opening of the electrode 101 on the electrode 105 side to the outer periphery of the electrode 101 on the electrode 105 side, as viewed from the Z direction, or the width in the Y direction from the inner periphery of the opening of the electrode 102 on the electrode 106 side to the outer periphery of the electrode 102 on the electrode 106 side, as viewed from the Z direction. The width Wg is, for example, 0.1 μm to 0.3 μm.

[0097] With the above-described configuration of the electrodes 105 and 106, the electrodes 105 and 106 are arranged to sandwich the electrode 202 in the Y direction in plan view.

[0098] A contact 64 for applying a voltage to the electrode 105 is provided on the electrode 105. The contact 64 is connected to a transfer gate line BLKSEL of the block BLK0. A contact 65 for applying a voltage to the electrode 106 is provided on the electrode 106. The contact 65 is connected to a transfer gate line BLKSEL of the block BLK1. Note that, although the example shown in FIG. 7 shows a case where each of the electrodes 105 and 106 is provided with one contact, this is not limiting. The number of contacts provided on each of the electrodes 105 and 106 may be two or more.

[0099] Normally, a voltage equal to or higher than the ground voltage VSS (0 V) is applied to the electrodes 105 and 106 during various operations such as a write operation, a read operation, and an erase operation.

[0100] In the region where the insulator layer 50 is provided, a shield conductor layer 400 is provided on the insulator layer 50 so as to surround, for example, the P-type well region 41B. The shield conductor layer 400 includes, for example, polysilicon. The shield conductor layer 400 may be provided in a lattice shape, similar to the insulator layer 50. Sidewalls (not shown in FIG. 7) are provided on the inner and outer side surfaces of the shield conductor layer 400.

[0101] The shield conductor layer 400 is in a state where a ground voltage VSS is applied, in a floating state, or in a state where it has the same potential as the P-type well region 41 B. The shield conductor layer 400 suppresses the occurrence of leakage current between transfer transistors during various operations.

[0102] (Cross-sectional structure) The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 7, showing an example of the cross-sectional structure of the transfer transistor included in the semiconductor memory device according to the embodiment. The structure of the transfer transistor in the cross section shown in Fig. 8 will be described below.

[0103] The upper end of the insulator layer 50 is located above the upper end of the P-type well region 41 B. The lower end of the insulator layer 50 is located above the lower end of the N-type well region 40 and below the lower end of the P-type well region 41 B.

[0104] N - The lower ends of the impurity diffusion regions 42, 43, and 44 are provided at positions higher than the lower end of the P-type well region 41B.

[0105] The electrode 201 is N + It includes an impurity diffusion region 211 and a conductive layer 221. + The lower end of the impurity diffusion region 211 is N - It is provided at a position above the lower end of the impurity diffusion region 42. + The impurity diffusion region 211 is formed by diffusing N-type impurities such as phosphorus (P) or arsenic (As) into the N -The conductive layer 221 is an impurity diffusion region containing N + The conductive layer 221 is provided on the upper surface of the impurity diffusion region 211. The upper end of the conductive layer 221 is higher than the upper end of the N- impurity diffusion region 42. The conductive layer 221 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0106] The electrode 202 is N + It includes an impurity diffusion region 212 and a conductive layer 222. + The lower end of the impurity diffusion region 212 is N - It is provided at a position above the lower end of the impurity diffusion region 43. + The impurity diffusion region 212 is formed by diffusing N-type impurities such as phosphorus (P) or arsenic (As) into the N - The conductive layer 222 is an impurity diffusion region containing N + The conductive layer 222 is provided on the upper surface of the impurity diffusion region 212. The upper end of the conductive layer 222 is, for example, N - The conductive layer 222 is higher than the upper end of the impurity diffusion region 43. + The conductive layer 222 is provided on the upper surface of the impurity diffusion region 212. The conductive layer 222 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0107] The electrode 203 is N + It includes an impurity diffusion region 213 and a conductive layer 223. + The lower end of the impurity diffusion region 213 is N - It is provided at a position above the lower end of the impurity diffusion region 44. + The impurity diffusion region 213 is formed by diffusing N-type impurities such as phosphorus (P) or arsenic (As) into the N - The conductive layer 223 is an impurity diffusion region containing N + The conductive layer 223 is provided on the upper surface of the impurity diffusion region 213. The upper end of the conductive layer 223 is, for example, N - The conductive layer 223 is higher than the upper end of the impurity diffusion region 44. +The conductive layer 223 is provided on the upper surface of the impurity diffusion region 213. The conductive layer 223 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0108] A gate insulating film 51 is provided on the upper surface of the P-type well region 41B excluding the electrodes 201, 202, and 203. The upper end of the gate insulating film 51 is located lower than the upper end of the insulator layer 50.

[0109] The electrode 101 includes conductor layers 111 and 121. The upper end of the conductor layer 111 is located higher than the upper end of the insulator layer 50. The conductor layer 111 is located on the upper surface of a portion of the gate insulating film 51 located on the other end side of the electrode 201, on the upper surface of a portion of the gate insulating film 51 located on one end side of the electrode 201, and on the upper surface of a portion of the insulator layer 50 located on one end side of the P-type well region 41B on the other end side. The conductor layer 121 is located on the upper surface of the conductor layer 111. The conductor layer 111 includes, for example, polysilicon. The conductor layer 121 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0110] The electrode 102 includes conductor layers 112 and 122. The upper end of the conductor layer 112 is located higher than the upper end of the insulator layer 50. The conductor layer 112 is located on the upper surface of a portion of the gate insulating film 51 located closer to one end than the electrode 203, on the upper surface of a portion of the gate insulating film 51 located closer to the other end than the electrode 203, and on the upper surface of a portion of the insulator layer 50 located closer to one end than the P-type well region 41B. The conductor layer 122 is located on the upper surface of the conductor layer 112. The conductor layer 112 includes, for example, polysilicon. The conductor layer 122 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0111] The electrode 105 includes conductive layers 115 and 125. The upper end of the conductive layer 115 is located higher than the upper end of the insulator layer 50. The conductive layer 115 is located on the upper surface of a portion of the gate insulating film 51 located between the electrode 201 and the electrode 202. The conductive layer 125 is located on the upper surface of the conductive layer 115. The conductive layer 115 includes, for example, polysilicon. The conductive layer 125 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0112] The electrode 106 includes conductive layers 116 and 126. The upper end of the conductive layer 116 is located higher than the upper end of the insulator layer 50. The conductive layer 116 is located on the upper surface of a portion of the gate insulating film 51 located between the electrode 202 and the electrode 203. The conductive layer 126 is located on the upper surface of the conductive layer 116. The conductive layer 116 includes, for example, polysilicon. The conductive layer 126 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0113] The electrode 107 includes conductor layers 117 and 127. The upper end of the conductor layer 117 is located higher than the upper end of the insulator layer 50. The conductor layer 117 is located on the upper surface of portions of the gate insulating film 51 located on one end side and the other end side of the electrode 202. The conductor layer 127 is located on the upper surface of the conductor layer 117. The conductor layer 117 includes, for example, polysilicon. The conductor layer 127 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0114] The shield conductor layer 400 includes conductor layers 410 and 420. The conductor layer 410 is provided on the upper surface of a portion of the insulator layer 50 provided on one end side of the P-type well region 41B, and on the upper surface of a portion of the insulator layer 50 provided on the other end side of the P-type well region 41B. The conductor layer 420 is provided on the upper surface of the conductor layer 410. The conductor layer 410 includes, for example, polysilicon. The conductor layer 420 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0115] Sidewalls 52_1, 52_2, 52_3, and 52_4 are provided on the side surfaces of the electrodes 101 and 102, respectively. In the following description, when the sidewalls 52_1, 52_2, 52_3, and 52_4 are not to be distinguished from one another, they are simply referred to as sidewalls 52. The upper ends of the sidewalls 52 are located at a height equal to or lower than the upper ends of the electrodes 101 and 102.

[0116] The sidewall 52_1 includes a first portion and a second portion. The first portion of the sidewall 52_1 is provided on the upper surface of the insulator layer 50 so as to contact, in the Y direction, one end of a portion of the electrode 101 that is provided on one end side of the electrode 201. The second portion of the sidewall 52_1 is provided on the upper surface of the gate insulating film 51 so as to contact, in the Y direction, the other end of the portion of the electrode 101 that is provided on the other end side of the electrode 201.

[0117] The sidewall 52_2 includes a first portion and a second portion. The first portion of the sidewall 52_2 is provided on the upper surface of the gate insulating film 51 so as to contact in the Y direction one end of a portion of the electrode 101 that is provided on one end side of the electrode 201. The second portion of the sidewall 52_2 is provided on the upper surface of the gate insulating film 51 so as to contact in the Y direction one end of a portion of the electrode 101 that is provided on the other end side of the electrode 201. The first portion of the sidewall 52_2 and the second portion of the sidewall 52_2 are provided so as to be adjacent to the electrode 201 in the Y direction.

[0118] The sidewall 52_3 includes a first portion and a second portion. The first portion of the sidewall 52_3 is provided on the upper surface of the gate insulating film 51 so as to contact, in the Y direction, one end of a portion of the electrode 102 that is provided on one end side of the electrode 203. The second portion of the sidewall 52_3 is provided on the upper surface of the insulator layer 50 so as to contact, in the Y direction, the other end of the portion of the electrode 102 that is provided on the other end side of the electrode 203.

[0119] The sidewall 52_4 includes a first portion and a second portion. The first portion of the sidewall 52_4 is provided on the upper surface of the gate insulating film 51 so as to contact in the Y direction one end of a portion of the electrode 102 that is provided on one end side of the electrode 203. The second portion of the sidewall 52_4 is provided on the upper surface of the gate insulating film 51 so as to contact in the Y direction one end of a portion of the electrode 102 that is provided on the other end side of the electrode 203. The first portion of the sidewall 52_4 and the second portion of the sidewall 52_4 are provided so as to be adjacent to the electrode 203 in the Y direction.

[0120] Sidewalls 53_1 and 53_2 are provided on the side surfaces of the shield conductor layer 400. In the following description, when the sidewalls 53_1 and 53_2 are not distinguished from each other, they are simply referred to as sidewalls 53. The upper end of the sidewall 53 is located at a height equal to or lower than the upper end of the shield conductor layer 400.

[0121] The sidewall 53_1 includes a first portion and a second portion. The first portion of the sidewall 53_1 is provided on the upper surface of the insulator layer 50 so as to be in contact in the Y direction with the other end of a portion of the shield conductor layer 400 provided on one end side of the P-type well region 41B. The first portion of the sidewall 53_1 is provided so as to be adjacent to the first portion of the sidewall 52_1 along the Y direction. The second portion of the sidewall 53_1 is provided on the upper surface of the insulator layer 50 so as to be in contact in the Y direction with one end of the portion of the shield conductor layer 400 provided on the other end side of the P-type well region 41B. The second portion of the sidewall 53_1 is provided so as to be adjacent to the second portion of the sidewall 52_3 along the Y direction.

[0122] The sidewall 53_2 includes a first portion and a second portion. The first portion of the sidewall 53_2 is provided on the upper surface of the insulator layer 50 so as to contact, in the Y direction, one end of a portion of the shield conductor layer 400 provided on one end side of the P-type well region 41B. The second portion of the sidewall 53_2 is provided on the upper surface of the insulator layer 50 so as to contact, in the Y direction, the other end of the portion of the shield conductor layer 400 provided on the other end side of the P-type well region 41B. Note that, for example, the second portion of the sidewall 53_2 is provided in a region not shown so as to be adjacent to the sidewalls provided in the transfer transistors TW0_2 and TW0_3 along the Y direction.

[0123] Sidewalls 54_1, 54_2, 54_3, and 54_4 are provided on the side surfaces of the electrodes 105, 106, and 107, respectively. In the following description, when the sidewalls 54_1, 54_2, 54_3, and 54_4 are not to be distinguished from one another, they are simply referred to as sidewalls 54. The upper ends of the sidewalls 54 are positioned at a height equal to or lower than the upper ends of the electrodes 105, 106, and 107.

[0124] The sidewall 54_1 includes a first portion and a second portion. The first portion of the sidewall 54_1 is provided on the upper surface of the gate insulating film 51 so as to contact one end of the electrode 105 in the Y direction. The second portion of the sidewall 54_1 is provided on the upper surface of the gate insulating film 51 so as to contact the other end of the electrode 105 in the Y direction.

[0125] The sidewall 54_2 includes a first portion and a second portion. The first portion of the sidewall 54_2 is provided on the upper surface of the gate insulating film 51 so as to contact one end of the electrode 106 in the Y direction. The second portion of the sidewall 54_2 is provided on the upper surface of the gate insulating film 51 so as to contact the other end of the electrode 106 in the Y direction.

[0126] The sidewall 54_3 includes a first portion and a second portion. The first portion of the sidewall 54_3 is provided on the upper surface of the gate insulating film 51 so as to contact, in the Y direction, one end of a portion of the electrode 107 that is provided on one end side of the electrode 202. The second portion of the sidewall 54_3 is provided on the upper surface of the gate insulating film 51 so as to contact, in the Y direction, the other end of the portion of the electrode 107 that is provided on the other end side of the electrode 202.

[0127] The sidewall 54_4 includes a first portion and a second portion. The first portion of the sidewall 54_4 is provided on the upper surface of the gate insulating film 51 so as to contact in the Y direction one end of a portion of the electrode 107 that is provided closer to one end than the electrode 202. The second portion of the sidewall 54_4 is provided on the upper surface of the gate insulating film 51 so as to contact in the Y direction one end of a portion of the electrode 107 that is provided closer to the other end than the electrode 202. The first portion of the sidewall 54_4 and the second portion of the sidewall 54_4 are provided so as to be adjacent to the electrode 202 in the Y direction.

[0128] A plurality of conductor layers 66 are provided above the electrodes 101, 102, 105, 106, and 107. Each of the plurality of conductor layers 66 is connected to a corresponding wiring, for example, the select gate lines SGS and SGD0 to SGD4 of each of the plurality of blocks BLK, the word lines WL0 to WL7 of each of the plurality of blocks BLK, the transfer gate lines BLKSEL of each of the plurality of row decoders RD, and the signal lines CGS, CG0 to CG7, and CGD0 to CGD4, etc. Each of the plurality of conductor layers 66 is provided in a region not shown in the figure, in the form of a line extending, for example, along the X direction.

[0129] The lower end of the contact 61 is in contact with the conductive layer 221. The upper end of the contact 61 is connected to the word line WL0 of the block BLK0 via a corresponding one of the plurality of conductive layers 66.

[0130] The lower end of the contact 62 is in contact with the conductive layer 222. The upper end of the contact 62 is connected to the signal line CG0 via a corresponding one of the plurality of conductive layers 66.

[0131] The lower end of the contact 63 is in contact with the conductive layer 223. The upper end of the contact 63 is connected to the word line WL0 of the block BLK1 via a corresponding one of the plurality of conductive layers 66.

[0132] The lower end of the contact 64 is in contact with the conductive layer 125. The upper end of the contact 64 is connected to the transfer gate line BLKSEL of the block BLK0 via a corresponding one of the plurality of conductive layers 66.

[0133] The lower end of the contact 65 is in contact with the conductive layer 126. The upper end of the contact 65 is connected to the transfer gate line BLKSEL of the block BLK1 via a corresponding one of the plurality of conductive layers 66.

[0134] The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 will be further described with reference to Fig. 9. Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 7, showing an example of the cross-sectional structure of the transfer transistor included in the semiconductor memory device according to the embodiment. The structure of the transfer transistor in the cross section shown in Fig. 9 will be described below.

[0135] The gate insulating film 51 is provided on the P-type well region 41B in the entire region sandwiched between the insulating layers 50.

[0136] The conductor layer 111 is provided on the upper surface of one end of the gate insulating film 51 and on the upper surface of the other end of the portion of the insulator layer 50 provided on one end of the P-type well region 41B. The conductor layer 112 is provided on the upper surface of the other end of the gate insulating film 51 and on the upper surface of one end of the portion of the insulator layer 50 provided on the other end of the P-type well region 41B.

[0137] 9, the second portion of the sidewall 52_1 is provided to be in contact with the other end of the portion of the conductive layer 111 in the Y direction. The first portion of the sidewall 54_1 is provided to be in contact with one end of the portion of the conductive layer 115 in the Y direction. The second portion of the sidewall 52_1 and the first portion of the sidewall 54_1 are provided to be in contact with each other along the Y direction.

[0138] Similarly, the second portion of the sidewall 54_1 and the first portion of the sidewall 54_3 are provided to be in contact with each other along the Y direction. The second portion of the sidewall 54_3 and the first portion of the sidewall 54_2 are provided to be in contact with each other along the Y direction. The second portion of the sidewall 54_2 and the first portion of the sidewall 52_3 are provided to be in contact with each other along the Y direction.

[0139] 7 and 9, the upper end of the contact 67 is electrically connected to the contact 61 via the conductive layer 66. This connects the conductive layer 121 (electrode 101) to the contact 61 so that they are at approximately the same potential.

[0140] The lower end of the contact 68 is in contact with the conductive layer 122. The upper end of the contact 68 is electrically connected to the contact 63 via the conductive layer 66, as shown in Figures 7 and 9. This connects the conductive layer 122 (electrode 102) to the contact 63 so that they are at approximately the same potential.

[0141] 7 and 9, the upper end of the contact 69 is electrically connected to the contact 62 via the conductive layer 66. As a result, the conductive layer 127 (electrode 107) is connected to the contact 62 so as to have approximately the same potential.

[0142] 1.2 Transfer transistor manufacturing method 10 and 11 are cross-sectional views showing an example of a structure during the manufacturing process of the transfer transistor TW included in the semiconductor memory device 1 according to the embodiment. The cross-sectional views shown in Fig. 10 and 11 show the cross-sectional structure corresponding to Fig. 8. An example of a manufacturing method relating to the formation of the conductor layers 121, 122, 125, 126, 127, 420, 221, 222, and 223 will be mainly described below.

[0143] As shown in Figure 10, exposed N - N-type impurities are selectively ion-implanted into the impurity diffusion regions 42, 43, and 44, + Impurity diffusion regions 211, 212, and 213 are formed.

[0144] A salicide formation process is then performed, which results in the formation of electrodes 101, 102, 105, 106, 107, 201, 202, and 203, and shield conductor layer 400, as shown in FIG.

[0145] More specifically, N + A metal film is laminated on the structure after the impurity diffusion regions 211, 212, and 213 are formed. The metal film is a film containing, for example, nickel (Ni), nickel platinum (NiPt), and cobalt (Co). Then, by anisotropic etching using a pattern of a resist material, the portions of the metal film laminated outside the regions where the transfer transistors TW, TS, and TD are to be provided in plan view are removed. The anisotropic etching in this process is, for example, RIE (Reactive Ion Etching). Then, by heat treatment of the structure on which the metal film is formed, the conductor layers 111, 112, 115, 116, 117, and 410, as well as the N + Silicon contained in each of the impurity diffusion regions 211, 212, and 213 is reacted with the metal element contained in the metal film. By this treatment, the conductive layers 111, 112, 115, 116, 117, and 410, as well as the N +Silicide (conductive layers 121, 122, 125, 126, 127, 420, 221, 222, and 223) is formed on the upper surfaces of the impurity diffusion regions 211, 212, and 213, respectively. After the conductive layers 121, 122, 125, 126, 127, 420, 221, 222, and 223 are formed, the unreacted metal film is removed. By this salicide formation process, as shown in FIG. 11, the conductive layers 111, 112, 115, 116, 117, and 410, as well as the N + Conductor layers 121, 122, 125, 126, 127, 420, 221, 222, and 223 are formed on the upper surfaces of the impurity diffusion regions 211, 212, and 213, respectively.

[0146] 9, the region between the electrode 101 and the electrode 105 is blocked by the sidewalls 52_1 and 54_1. The region between the electrode 105 and the electrode 107 is blocked by the sidewalls 54_1 and 54_3. The region between the electrode 107 and the electrode 106 is blocked by the sidewalls 52_3 and 54_2. The region between the electrode 106 and the electrode 102 is blocked by the sidewalls 52_3 and 54_2. This is because the width Ws, which is the slit width in the Y direction between adjacent electrodes among the electrodes 101, 102, 105, 106, and 107, is relatively small. As a result, a full surface salicide process can be applied to the region shown in FIG.

[0147] 1.3 Effects of the embodiment According to the embodiment, it is possible to suppress a decrease in the reliability of the semiconductor memory device. The effects of the embodiment will be described below.

[0148] In the semiconductor memory device 1 according to the embodiment, the P-type well region 41B includes N-type wells arranged at a distance from each other in the Y direction in this order. - Impurity diffusion regions 42, 43, and 44 are provided. -Electrodes 201, 202, and 203 are provided in the impurity diffusion regions 42, 43, and 44, respectively. The electrode 201 functions as a first end of the transfer transistor TW0_0. The electrode 203 functions as a first end of the transfer transistor TW0_1. The electrode 202 functions as a second end of the transfer transistor TW0_0 and a second end of the transfer transistor TW0_1. The electrode 201 is connected to a word line WL0 of the block BLK corresponding to the transfer transistor TW0_0 via a contact 61. The electrode 202 is connected to a signal line CG0 via a contact 62. The electrode 203 is connected to a word line WL0 of the block BLK corresponding to the transfer transistor TW0_1 via a contact 63. An electrode 101 having an opening surrounding the contact 61 and an electrode 102 having an opening surrounding the contact 63 are provided above the P-type well region 41B. Moreover, above the P-type well region 41B, an electrode 105 functioning as the gate of the transfer transistor TW0_0, an electrode 106 functioning as the gate of the transfer transistor TW0_1, and an electrode 107 having an opening surrounding the contact 62 are provided. Such a structure of the electrodes 101, 102, 105, 106, and 107 can suppress changes in the characteristics of the transfer transistors TW0_0 and TW0_1 due to changes in the potential of each conductive layer 66 provided above the transfer transistors TW0_0 and TW0_1. Therefore, a decrease in the reliability of the semiconductor memory device 1 can be suppressed.

[0149] In addition, the conductive layer that functions as the gate is adjacent to the N - When it is provided only between the impurity diffusion regions, for example, N - The resistance of the impurity diffusion region is affected by the voltage change of the conductive layer (wiring) above the transistor. This effect is particularly noticeable in N - In a high-voltage transistor in which the resistance value of the impurity diffusion region is relatively high, there are cases where this cannot be ignored from the viewpoint of voltage resistance and reliability, and this is not preferable. - As a method for suppressing the change in the resistance value of the impurity diffusion region, the N -Although a method of providing wiring at a higher position than the impurity diffusion region is known, this method may increase the aspect ratio of the contact, which may make contact formation difficult and may degrade the performance of the semiconductor memory device.

[0150] According to the semiconductor memory device 1 of the embodiment, the electrode 101 is provided so as to surround the contact 61. The electrode 102 is provided so as to surround the contact 63. The electrodes 105 and 106 are provided so as to function as gates. The electrode 107 is provided so as to surround the contact 62. With such a configuration of the electrodes 101, 102, 105, 106, and 107, the electrodes 101 and 102 are N - The upper surfaces of the impurity diffusion regions 42, 43, and 44 can be entirely covered. Furthermore, during various operations such as a write operation, a read operation, and an erase operation, a voltage equal to or higher than the ground voltage VSS is applied to the electrodes 101, 102, 105, 106, and 107. As a result, the electrodes 101, 102, 105, 106, and 107 can shield the electric field formed by the conductive layer 66. Therefore, during various operations such as a write operation, a read operation, and an erase operation, the N - It is possible to suppress the change in the resistance value of the impurity diffusion regions 42, 43, and 44. - Even when the resistance value of the impurity diffusion region is relatively high, it is possible to prevent the aspect ratio of the contact from increasing, and also to prevent a decrease in the reliability of the transfer transistors TW0_0 and TW0_1 due to a change in the potential of each conductive layer 66.

[0151] Moreover, according to the embodiment, the transfer transistors TW0_0 and TW0_1 share the electrode 202. Such a configuration can suppress an increase in the area occupied by the transfer transistors TW0_0 and TW0_1 on the semiconductor substrate 20. Therefore, an increase in the size of the semiconductor memory device 1 can be suppressed.

[0152] Furthermore, according to the embodiment, the surface breakdown voltage is improved, thereby suppressing a decrease in the reliability of the semiconductor memory device. The surface breakdown voltage is a breakdown voltage that occurs at a pn junction between the source or drain and a well region (semiconductor substrate) near the gate when a high potential difference occurs between the gate and the source or drain with 0 V applied to the gate.

[0153] The electrodes 101, 102, and 107 are set to have approximately the same potential as the contacts 61, 63, and 62, respectively, and are not used as gates. This makes it possible to alleviate electric field concentration in the well region near the contacts 61, 62, and 63, even when 0 V is applied to the electrodes 105 and 106, which serve as gates. As a result, the surface breakdown voltage can be improved. Therefore, the surface breakdown voltage of the transfer transistors TW0_0 and TW0_1 can be improved while suppressing a decrease in the reliability of the transfer transistors TW0_0 and TW0_1 due to a change in the potential of the conductor layer 66.

[0154] 2. Variations The above-described embodiment can be modified in various ways.

[0155] A semiconductor memory device according to a modified example will be described below. The following describes the configuration and manufacturing method of the semiconductor memory device according to the modified example, focusing on differences from the semiconductor memory device 1 according to the embodiment. The semiconductor memory device according to the modified example also achieves the same effects as the embodiment.

[0156] 2.1 First Modification In the above embodiment, the position of the slit between the electrode 101 and the electrode 105 may be changed.

[0157] In the following description, the configuration of the transfer transistor according to the first modification example will be mainly described in terms of the configuration that differs from the configuration of the embodiment.

[0158] The planar structure of the transfer transistors TW0_0 and TW0_1 according to the first modification will be described with reference to Fig. 12. Fig. 12 is a plan view showing an example of the planar structure of the transfer transistors included in the semiconductor memory device according to the first modification.

[0159] In the example shown in FIG. - The impurity diffusion regions 42, 43, and 44 are also arranged around the P-type well region 41B (active region), for example. - The ends of the impurity diffusion region 42 are disposed outside the ends of the P-type well region 41B (active region) in the +X direction, the -X direction, and the +Y direction. - The ends of the impurity diffusion region 43 are disposed outside the ends of the P-type well region 41B (active region) in the +X direction and the −X direction. - The ends of the impurity diffusion region 44 are disposed outside the ends of the P-type well region 41B (active region) in the +X direction, −X direction, and −Y direction. That is, when viewed from the Z direction, the P-type well region 41B (active region) is - The impurity diffusion regions 42, 43, and 44 are arranged so as to extend over the impurity diffusion regions 42, 43, and 44. - The impurity diffusion region 42 may be arranged so as to be shared by the transfer transistors TW0_0 and TW1_0 adjacent to each other in the X direction. - The impurity diffusion region 43 may be arranged so as to be shared by the transfer transistors TW0_0 and TW1_0 adjacent to each other in the X direction, and also shared by the transfer transistors TW0_1 and TW1_1 adjacent to each other in the X direction. - The impurity diffusion region 44 may be arranged so as to be shared by the transfer transistors TW0_1 and TW1_1 adjacent to each other in the X direction.

[0160] The slit S between the electrode 101 and the electrode 105 is N - Impurity diffusion region 42 and N -The electrodes 101 and 105 are provided so as to be shifted in the opposite direction (+Y direction in FIG. 12) to the channel between the impurity diffusion region 43. That is, the slit S is shifted as shown in the direction of the arrow Ar.

[0161] 13 is a graph showing an example of the surface breakdown voltage of the transfer transistor according to the first modification. The horizontal axis represents the drain voltage. The vertical axis represents the drain current. The graph shows data for Case 1, Case 2, and Case 3. Case 1, Case 2, and Case 3 are data in which the shift in the position of the slit S increases in this order.

[0162] The surface breakdown voltage improves from Case 1 to Case 3, that is, as the shift in the position of the slit S increases.

[0163] The potential gradient and the surface breakdown voltage will be described with reference to FIG. 14. FIGS. 14A and 14B are cross-sectional views taken along line XIV-XIV in FIG. 12, showing an example of the cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a first modification. Note that FIGS. 14A and 14B are reversed in left and right compared to FIG. 8. FIG. 14A shows a case where the shift in the position of the slit S is small, as in Case 1. FIG. 14B shows a case where the shift in the position of the slit S is large, as in Case 3. Also, FIGS. 14C and 14D show enlarged views of the dashed-dotted frames shown in FIGS. 14A and 14B, respectively.

[0164] 14B and 14D, the shift in the position of the slit S is larger than that in FIGS. 14A and 14C. As a result, the width of the electrode 101 in the Y direction is smaller in FIGS. 14B and 14D than that in FIGS. 14A and 14C. That is, the width Wg is smaller in FIGS. 14B and 14D than that in FIGS. 14A and 14C. Also, in FIGS. 14B and 14D, the distance between the electrodes 105 and N is smaller than that in FIGS. 14A and 14C. - The overlap of the impurity diffusion regions 42 in the Y direction is large. That is, the overlap distance L is longer in Figures 14B and 14D than in Figures 14A and 14C.

[0165] 14A to 14D show an example of a data erase operation of the semiconductor memory device 1. For example, a voltage of 23.5 V is applied to the contact 61. A voltage of 0 V is applied to the contact 64 (cutoff). A voltage of 0.5 V is applied to the contact 62.

[0166] 14A to 14D schematically show equipotential lines relative to the electric lines of force from the contact points between the contacts 61 and the semiconductor substrate 20. In FIG.

[0167] 14A and 14C, the 0V electrode 105 creates a large potential difference near the electrode 105. In other words, the equipotential lines near the electrode 105 are dense. In areas where the equipotential lines are dense, a high electric field is generated, which may cause surface leakage. The surface leakage is indicated by the dashed arrow and is leakage to the P-type well region 41B of the 0V semiconductor substrate 20.

[0168] In FIG. 14B and FIG. 14D, the shift of the slit S causes the electrodes 105 and N - The overlap of the impurity diffusion region 42 is enlarged (the overlap distance L is extended). - As the impurity diffusion region 42 increases, the N - The voltage drop in the impurity diffusion region 42 increases. This reduces the potential difference at the junction between one end of the electrode 105 and the other end of the N-impurity diffusion region 42, thereby reducing surface leakage. In other words, the surface breakdown voltage can be improved.

[0169] 15 is a graph showing an example of the on-current of the transfer transistor according to the first modification. The horizontal axis represents the gate voltage. The vertical axis represents the drain current. The graph shows data for Case 1, Case 2, and Case 3. Case 1, Case 2, and Case 3 are data in which the shift in the position of the slit S increases in this order.

[0170] The on-current improves from Case 1 to Case 3, that is, as the shift in the position of the slit S increases. This is because the electrode 105 and N - This is because the greater the overlap of the impurity diffusion regions 42 in the Y direction, the greater the on-current.

[0171] The slit between the electrodes 102 and 106 is not limited to the electrodes 101 and 105. - Impurity diffusion region 43 and N - The electrodes 102 and 106 may be provided so as to be shifted in the opposite direction (-Y direction in FIG. 12) to the channel between the impurity diffusion region 44.

[0172] The transfer transistor configuration as described above also provides the same effects as those of the embodiment.

[0173] 2.2 Second variant In the above-described embodiment, portions of the electrodes 101 and 102 may be cut off.

[0174] In the following description, the configuration of the transfer transistor according to the second modification example will be mainly described in terms of the configuration that differs from the configuration of the embodiment.

[0175] The planar structure of the transfer transistors TW0_0 and TW0_1 according to the second modification will be described with reference to Fig. 16. Fig. 16 is a plan view showing an example of the planar structure of the transfer transistors included in the semiconductor memory device according to the second modification.

[0176] The electrode 101 has a slit S1 that extends from the end of the electrode 101 facing the electrode 105 to the opening. That is, the inner periphery of the electrode 101 is connected to the outer periphery of the electrode 101. The opening of the electrode 101 is connected to the slit between the electrode 101 and the electrode 105.

[0177] The electrode 102 has a slit S2 that extends from the end of the electrode 102 facing the electrode 106 to the opening. That is, the inner periphery of the electrode 102 is connected to the outer periphery of the electrode 102. The opening of the electrode 102 is connected to the slit between the electrode 102 and the electrode 106.

[0178] The opening of electrode 107 may be connected to the slit between electrode 107 and electrode 105. The opening of electrode 107 may be connected to the slit between electrode 107 and electrode .

[0179] The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 according to the second modification will be described with reference to Fig. 17. Fig. 17 is a cross-sectional view taken along line XVII-XVII in Fig. 16, showing an example of the cross-sectional structure of the transfer transistors included in the semiconductor memory device according to the second modification.

[0180] 17, in the second modification, the portion of electrode 101 that is provided on the other end side of electrode 201 is not provided, and the portion of electrode 102 that is provided on one end side of electrode 203 is not provided.

[0181] The transfer transistor configuration as described above also achieves the same effects as those of the embodiment and the first modification.

[0182] In the second modification, the surface breakdown voltage and on-current characteristics are almost the same as those of the embodiment.

[0183] Furthermore, in the second modification, electrode 101 has a slit S1. Electrode 102 has a slit S2. That is, the opening of electrode 101 is connected to the slit between electrodes 101 and 105, and the opening of electrode 102 is connected to the slit between electrodes 102 and 106. Therefore, in the second modification, the semiconductor memory device 1 is easier to manufacture than in the embodiment, even if the slit width Ws is smaller.

[0184] The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 according to the second modification will be described with reference to Fig. 18. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII in Fig. 16, showing an example of the cross-sectional structure of the transfer transistor included in the semiconductor memory device according to the second modification. Note that Fig. 18 omits configurations other than the gate insulating film 51, the electrode 101, and the sidewall 52_5.

[0185] 18, the region of the slit S1 may be closed by a sidewall 52_5 provided on the side surface in the X direction of the electrode 101. Similarly, the region of the slit S2 (not shown) may be closed by a sidewall provided on the side surface in the X direction of the electrode 102.

[0186] 2.3 Third variant In the above-described embodiment, an example in which the electrodes 107 and the contacts 69 are provided has been shown, but the present invention is not limited to this. The electrodes 107 and the contacts 69 do not necessarily have to be provided.

[0187] In the following description, the configuration of the transfer transistor according to the third modification example will be mainly described in terms of the configuration that differs from the configuration of the embodiment.

[0188] The planar structure of the transfer transistors TW0_0 and TW0_1 according to the third modification will be described with reference to Fig. 19. Fig. 19 is a plan view showing an example of the planar structure of the transfer transistors included in the semiconductor memory device according to the third modification.

[0189] As shown in FIG. 19 , in the third modification, the electrode 107 is not provided. Therefore, the structures are different on the drain side and the source side of the transfer transistor TW. That is, the structures are asymmetric on the drain side and the source side of the transfer transistor TW. The electrode 107 is not provided on the other end side of the transfer transistor TW0_0, i.e., the drain side. On the other hand, the electrode 101 is provided on one end side of the transfer transistor TW0_, i.e., the source side. The electrode 107 is not provided on one end side of the transfer transistor TW0_1, i.e., the drain side. On the other hand, the electrode 102 is provided on the other end side of the transfer transistor TW0_1, i.e., the source side.

[0190] When viewed from the Z direction, the electrodes 105 and N - The impurity diffusion regions 43 do not overlap each other. - The outer peripheral edge of the impurity diffusion region 43 is substantially flush. - The impurity diffusion regions 43 do not overlap each other. - The outer peripheral edge of the impurity diffusion region 43 is substantially flush, which can further improve the surface breakdown voltage.

[0191] The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 according to the third modification will be described with reference to Fig. 20. Fig. 20 is a cross-sectional view taken along line XX-XX in Fig. 19, showing an example of the cross-sectional structure of the transfer transistors included in the semiconductor memory device according to the third modification.

[0192] As shown in Figure 20, N - The impurity diffusion region 43 is not covered by the electrode 107 .

[0193] The transfer transistor configuration as described above also achieves the same effects as those of the embodiment, the first modification, and the second modification.

[0194] In addition, the third modification is, for example, N -The requirement for surface breakdown voltage is relatively low on the impurity diffusion region 42 side, and N - This can be applied to a location requiring high cutoff characteristics on the side of the impurity diffusion region 43. That is, although an example of the structure of the transfer transistor TW included in the row decoder RD has been described in Figures 19 and 20, the third modification example may also be applied to, for example, a peripheral circuit, a boost circuit, etc.

[0195] 2.4 Fourth Variant In the above-described embodiment, an example in which a silicide block film is not provided has been shown, but the present invention is not limited to this. A silicide block film may be provided.

[0196] In the following description, the configuration of the transfer transistor according to the fourth modification will be mainly described in terms of differences from the configuration of the third modification.

[0197] The planar structure of the transfer transistors TW0_0 and TW0_1 according to the fourth modification will be described with reference to Fig. 21. Fig. 21 is a plan view showing an example of the cross-sectional structure of the transfer transistors included in the semiconductor memory device according to the fourth modification.

[0198] As shown in FIG. 21, a silicide block film 500 that prevents silicidation is provided in a region near the electrode 202 when viewed from the Z direction so that the P-type well region 41B is not silicided.

[0199] The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 according to the fourth modification will be described with reference to Fig. 22. Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 21, showing an example of the cross-sectional structure of the transfer transistors included in the semiconductor memory device according to the fourth modification.

[0200] 22, the silicide block film 500 is provided on the upper surface of the P-type well region 41 B. A portion of the silicide block film 500 is provided on the upper surfaces of portions of the electrodes 105 and 106.

[0201] 2.5 Fifth Variant In the above-described embodiment, an example was shown in which the ends of the electrodes 101, 102, 105, 106, and 107 were provided outside the P-type well region 41B, but this is not limiting. The ends of the electrodes 101, 102, 105, 106, and 107 may also be provided inside the P-type well region 41B.

[0202] In the following description, the configuration of the transfer transistor according to the fifth modification example will be mainly described in terms of the configuration that differs from the configuration of the embodiment.

[0203] The planar structure of the transfer transistors TW0_0 and TW0_1 according to the fifth modification will be described with reference to Fig. 23. Fig. 23 is a plan view showing an example of the planar structure of the transfer transistors included in the semiconductor memory device according to the fifth modification.

[0204] When viewed from the Z direction, the electrodes 101, 102, 105, 106, and 107 are provided inside a P-type well region 41B (active region) provided in the semiconductor substrate 20.

[0205] The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 according to the fifth modification will be described with reference to Fig. 24. Fig. 24 is a cross-sectional view taken along line XXIV-XXIV in Fig. 23, showing an example of the cross-sectional structure of the transfer transistors included in the semiconductor memory device according to the fifth modification.

[0206] The electrodes 101 and 102 are provided so as not to reach the insulator layer 50 (so as not to come into contact with the insulator layer 50). That is, the electrode 101 is provided on the other end side of the insulator layer 50. The electrode 102 is provided on one end side of the insulator layer 50. This allows the electrodes of the transfer transistors TW0_0 and TW0_1 to be spaced farther from the electrodes of the transfer transistors TW1_0 and TW1_1. This makes it possible to suppress leakage between adjacent elements, such as field inversion leakage and punch-through leakage.

[0207] The transfer transistor configuration as described above also achieves the same effects as those of the embodiment, the first modified example, the second modified example, the third modified example, and the fourth modified example.

[0208] 2.6 Sixth Variant In the fifth modified example described above, the ends of the electrodes 101, 102, 105, 106, and 107 are provided inside the P-type well region 41B, but this is not limiting. Parts of the ends of the electrodes 105 and 106 may be provided outside the P-type well region 41B.

[0209] In the following description, the configuration of the transfer transistor according to the sixth modification will be mainly described in terms of differences from the configuration of the fifth modification.

[0210] The planar structure of the transfer transistors TW0_0 and TW0_1 according to the sixth modification will be described with reference to Fig. 25. Fig. 25 is a plan view showing an example of the planar structure of the transfer transistors included in the semiconductor memory device according to the sixth modification.

[0211] As viewed from the Z direction, the electrodes 101, 102, and 107 are provided inside a P-type well region 41B (active region) provided in the semiconductor substrate 20. As viewed from the Z direction, the electrodes 105 and 106 are provided so as to extend from the P-type well region 41B in the X direction. That is, in the X direction, a portion of the electrodes 105 and 106 is provided outside the P-type well region 41B. This increases the area where the electrodes 105 and 106 overlap with the P-type well region 41B as viewed from the Z direction, making it possible to suppress leakage from the P-type well region 41B to adjacent elements. This improves the stability of the characteristics of the transfer transistors TW_0 and TW0_1 when, for example, cutting off the current.

[0212] The transfer transistor configuration as described above also achieves the same effects as those of the embodiment, the first modified example, the second modified example, the third modified example, the fourth modified example, and the fifth modified example.

[0213] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0214] 1...semiconductor memory device, 2...memory controller, 3...memory system, 10...memory cell array, 11...command register, 12...address register, 13...sequencer, 14...driver module, 15...row decoder module, 16...sense amplifier module, 20...semiconductor substrate, 21-25, 103, 110-114, 121-124, 130-132, 221-223, 300, 301, 410, 420, 430...conductor layer, 400...shield conductor layer, 26...semiconductor section, 30-34, 50, 80, 90-93...insulator layer, 35...core section material, 36...semiconductor film, 37...tunnel insulating film, 38...charge storage film, 39...block insulating film, 51...gate insulating film, 52, 53...sidewall, 70-73...resist material, 101, 102, 104, 201-203...electrode, BLK...block, SU...string unit, NS...NAND string, MT...memory cell transistor, ST1, ST2...select transistor, BL...bit line, WL...word line, SGS, SGD...select gate line, TS, TW0-TW7, TD...transfer transistor, signal line...CGS, CG0-CG7, CGD0-CGD4.

Claims

1. a semiconductor substrate including an element region, and a first region, a second region, and a third region, each of which is a source region or a drain region, arranged in this order and spaced apart from one another in a first direction in the element region; a first conductor layer provided above the element region and having a first opening; a second conductive layer provided above the element region, having a second opening, and spaced apart from the first conductive layer in the first direction; a first contact connected to the first region and passing through the first opening; a second contact connected to the third region and passing through the second opening; a first memory cell connected to the first contact; a second memory cell connected to the second contact; a third conductive layer and a fourth conductive layer provided between the first conductive layer and the second conductive layer above the element region and arranged in this order and spaced apart from each other in the first direction; Equipped with the third conductive layer is disposed apart from the first conductive layer, the fourth conductive layer is disposed apart from the second conductive layer; the first conductive layer and the first contact are connected to each other so as to have substantially the same potential; The second conductive layer and the second contact are connected to each other so as to have substantially the same potential.

2. 2. The semiconductor memory device according to claim 1, further comprising a third contact connected to said second region and passing between said third conductive layer and said fourth conductive layer.

3. a fifth conductive layer provided between the third conductive layer and the fourth conductive layer above the element region, the fifth conductive layer having a third opening through which the third contact passes; the fifth conductive layer is disposed apart from the third conductive layer and the fourth conductive layer; 3. The semiconductor memory device according to claim 2, wherein said fifth conductive layer and said third contact are connected to each other so as to be at substantially the same potential.

4. the first conductive layer has a first slit extending from an end of the first conductive layer facing the third conductive layer to the first opening, 4. The semiconductor memory device according to claim 3, wherein said second conductive layer has a second slit extending from an end of said second conductive layer facing said fourth conductive layer to said second opening.

5. 4. The semiconductor memory device according to claim 3, wherein, when viewed from a direction substantially perpendicular to the semiconductor substrate, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer are arranged inside an active region provided in the semiconductor substrate.

6. When viewed from a direction substantially perpendicular to the semiconductor substrate, the first conductive layer, the second conductive layer, and the fifth conductive layer are provided inside an active region provided in the semiconductor substrate.

4. The semiconductor memory device according to claim 3, wherein, when viewed from a direction substantially perpendicular to the semiconductor substrate, the third conductive layer and the fourth conductive layer are provided so as to extend from the active region in a second direction substantially perpendicular to the first direction and substantially parallel to the semiconductor substrate.

7. When viewed from a direction substantially perpendicular to the semiconductor substrate, the third conductive layer and the second region do not overlap each other, 3. The semiconductor memory device according to claim 2, wherein said fourth conductive layer and said second region do not overlap each other when viewed in a direction substantially perpendicular to said semiconductor substrate.

8. 2. The semiconductor memory device according to claim 1, wherein the first region and the third conductive layer overlap each other when viewed in a direction substantially perpendicular to the semiconductor substrate.

9. 9. The semiconductor memory device according to claim 8, wherein the first region and the third conductive layer overlap each other within a range of 0.2 μm to 0.6 μm in the first direction when viewed from a direction substantially perpendicular to the semiconductor substrate.

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