Planar pin diode and method for manufacturing planar pin diode

Abstract

To provide a planar PIN diode with which it is possible to suppress a decrease in avalanche resistance, and a method for manufacturing the planar PIN diode.SOLUTION: In a planar PIN diode 100, an inner circumferential breakdown voltage holding region 32a1 located in the inner circumferential part 30c of a substrate 30 is composed of a plurality of subregions 40 that are formed by being aligned along the plane direction, and in each subregion 40, an impurity concentration is highest in a subregion center section p1 and the impurity concentration is lowest in an edge region 42a, with the edge regions 42a overlapping each other in an adjacent subregion 40. When the depth of subregion 40 in the depth direction orthogonal to the plane direction in a cross sectional view is defined as Xjp, an interval N between adjacent middle subregion edges P2 in an adjacent p+ type semiconductor region 41 is 0.60×2×Xjp≤N≤0.95×2×Xjp.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a planar PIN diode and a method for manufacturing a planar PIN diode. [Background technology]

[0002] In Patent Document 1, N + A semiconductor region of N - A semiconductor region of type P - A semiconductor region of type 1 and two P + The present invention discloses a planar PIN diode having a semiconductor region of a type, an oxide film, an anode electrode, and a cathode electrode. + N on the semiconductor region - A semiconductor region of N type is formed. - In the surface of the semiconductor region of P - A semiconductor region of type P is formed. + The semiconductor region is P - The oxide film is formed on the main surface side of the semiconductor region of the type so as to be separated from each other in a cross-sectional view. + The oxide film is disposed with an opening between the semiconductor regions of the P type. The anode electrode is disposed in the opening of the oxide film. - P - The cathode electrode is formed on the N-type semiconductor region and the oxide film. + A metal layer is formed on the back surface of the semiconductor region of the mold.

[0003] According to the configuration of Patent Document 1, when a reverse voltage is applied to a PN junction, - Type semiconductor region and N - Before avalanche breakdown occurs at the bend in the corner of the PN junction with the semiconductor region of the type + Between the P type semiconductor regions - Punch-through breakdown occurs in the semiconductor region of the PN junction. That is, punch-through breakdown occurs not in the bend of the PN junction but in the P - Type semiconductor region and N -This occurs between the planar semiconductor region and the gate electrode of the PIN diode. Therefore, the area where punch-through breakdown occurs is large, which makes it possible to suppress electric field concentration and to prevent destruction of the planar PIN diode due to avalanche breakdown.

[0004] In addition, Patent Document 1 states that - On the main surface side of the semiconductor region of the type, the above two P + Between the semiconductor regions of the same type, there are further multiple other P + The present invention discloses a structure in which a semiconductor region of a type is formed. + Between the semiconductor regions of the same type are multiple different P + Since the semiconductor regions are separated by P + The punch-through breakdown can be distributed among a plurality of the semiconductor regions of the type. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 7-221326 Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, the configuration of Patent Document 1 can suppress the destruction of the planar PIN diode due to avalanche breakdown to some extent. + In an embodiment in which punch-through breakdown occurs in a portion between two P + Electric field crowding can occur at any point between the semiconductor regions of the three or more P + This is because the electric field concentration is suppressed by the punch-through breakdown occurring between the semiconductor regions of the P-type. + In an embodiment in which punch-through breakdown occurs between two P +However, it is unclear to what extent the planar PIN diode can be prevented from being destroyed by avalanche breakdown. Therefore, a configuration capable of preventing a decrease in the avalanche resistance of the planar PIN diode is required.

[0007] SUMMARY OF THE PRESENT DISCLOSURE Therefore, a primary object of the present invention is to provide a planar PIN diode capable of suppressing a decrease in avalanche resistance and a method for manufacturing the planar PIN diode. [Means for solving the problem]

[0008] The planar PIN diode of the present invention is a planar PIN diode formed in a plate shape having a front surface and a back surface along a predetermined planar direction, and comprising a substrate having an outer peripheral portion and an inner peripheral portion surrounded by the outer peripheral portion in a planar view, a first electrode formed on the back surface of the substrate, and a second electrode formed on the inner peripheral portion of the front surface of the substrate and having a polarity opposite to that of the first electrode. The substrate has a first semiconductor region of a first conductivity type, the outer surface of which is formed as the back surface and on which a first electrode is disposed, and a second semiconductor region of a second conductivity type, which is formed inside the surface side of the first semiconductor region and is connected to a second electrode at its inner periphery. The inner periphery breakdown voltage holding region located on the inner periphery of the second semiconductor region is formed with a plurality of small regions of the second conductivity type aligned in the planar direction. In each small region, the second conductivity type impurity concentration is highest in the small region central portion, which is the center of the small region, and the second conductivity type impurity concentration is lowest in the edge region, which is the region at the edge of the small region among the outer regions relative to the central region including the small region central portion. Adjacent small regions have overlapping end regions. In the cross-sectional view, if the depth of the small region in the depth direction perpendicular to the plane direction is Xjp, The distance N between the ends of adjacent central regions is 0.60×2×Xjp≦N≦0.95×2×Xjp It is.

[0009] In the planar PIN diode according to the present invention, the provision of an inner peripheral withstand voltage maintaining region makes it possible to suppress a decrease in avalanche resistance.

[0010] The method for manufacturing a planar PIN diode according to the present invention is a method for manufacturing a planar PIN diode comprising: a substrate formed in a plate shape having a front surface and a back surface along a predetermined planar direction, and having an outer peripheral portion and an inner peripheral portion surrounded by the outer peripheral portion in a planar view; a first electrode formed on the back surface of the substrate; and a second electrode formed on the inner peripheral portion of the front surface of the substrate and having a polarity opposite to that of the first electrode. The method includes a step of forming a first semiconductor region of a first conductivity type, the outer surface of which is formed as a back surface and on which a first electrode is disposed, and a step of forming a second semiconductor region of a second conductivity type, which is formed inside the surface side of the first semiconductor region and is connected to a second electrode at its inner periphery. The process of forming the second semiconductor region is a process of depositing impurities of a second conductivity type into the first semiconductor region through the multiple openings using a mask having multiple openings in a portion located at the inner periphery, and the distance L between the opening ends of adjacent openings is 0.6×2×Xjp≦L≦0.95×2×Xjp. a process for forming an inner peripheral voltage-resistance retaining region located at the inner peripheral portion of the second semiconductor region by diffusing, through a heat treatment, impurities of the second conductivity type deposited through the openings, the inner peripheral portion being made up of a plurality of small regions of the second conductivity type arranged along a planar direction, wherein in each small region, the concentration of the second conductivity type impurities is highest at a small region central portion that is the center of the small region, and the concentration of the second conductivity type impurities is lowest at an end region that is an end region of the small region that is an outer region in the planar direction relative to a central region including the small region central portion; In adjacent small regions, the end regions overlap each other, The opening corresponds to the central region, In the cross-sectional view, the depth of the small region in the depth direction perpendicular to the planar direction is Xjp.

[0011] In the method for manufacturing a planar PIN diode according to the present invention, a planar PIN diode capable of suppressing a decrease in avalanche resistance can be obtained by providing an inner peripheral withstand voltage maintaining region. Effect of the Invention

[0012] According to the present invention, there is provided a planar PIN diode capable of suppressing a decrease in the avalanche resistance of the planar PIN diode, and a method for manufacturing the planar PIN diode.

[0013] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which refers to the drawings. [Brief description of the drawings]

[0014] [Figure 1] 1 is a plan view of a planar PIN diode according to an embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view taken along line II-II of FIG. 1. [Figure 3A] 2 is an enlarged view of a corner of the planar PIN diode of FIG. 1, and is a plan view of an inner peripheral withstand voltage maintaining region. [Figure 3B] 3B is an enlarged view of the inner peripheral pressure-resistant maintaining region of FIG. 3A. [Figure 4] 4 is a cross-sectional view of line IV-IV in FIG. 3A and FIG. 3B. [Diagram 5] FIG. 3 is a schematic diagram (1) showing the manufacturing process in the cross-sectional view of FIG. 2. [Figure 6] FIG. 3 is a schematic diagram (2) showing the manufacturing process in the cross-sectional view of FIG. [Figure 7] FIG. 3 is a schematic diagram (3) showing the manufacturing process in the cross-sectional view of FIG. [Figure 8] FIG. 4 is a schematic diagram (4) showing the manufacturing process in the cross-sectional view of FIG. [Figure 9] FIG. 5 is a schematic diagram (5) showing the manufacturing process in the cross-sectional view of FIG. [Figure 10]FIG. 6 is a schematic diagram (6) showing the manufacturing process in the cross-sectional view of FIG. [Figure 11] FIG. 11 is a plan view of an inner peripheral pressure-resistant retaining region of another embodiment 1. [Figure 12] FIG. 11 is a plan view of an inner peripheral pressure-resistant retaining region of another embodiment 2. [Figure 13] FIG. 11 is a plan view of an inner peripheral pressure-resistant retaining region of another embodiment 3. [Figure 14] FIG. 11 is a plan view of an inner peripheral pressure-resistant retaining region of another embodiment 4. [Figure 15] FIG. 13 is a plan view of an inner peripheral pressure-resistant retaining region according to another embodiment 5. [Figure 16] 13 is a plan view of an inner peripheral pressure-resistant retaining region of another embodiment 6. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] 1. Embodiment (1) Composition The structure of a planar PIN diode 100 according to an embodiment of the present invention will be described below with reference to the drawings. Fig. 1 is a plan view of a planar PIN diode according to an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3A is an enlarged view of a corner of the planar PIN diode of Fig. 1, and is a plan view of an inner peripheral withstand voltage maintaining region. Fig. 3B is an enlarged view of the inner peripheral withstand voltage maintaining region of Fig. 3A.

[0016] The planar PIN diode 100 is a diode formed in the shape of a flat plate and having a lightly doped, and therefore highly resistive, generally intrinsic semiconductor region between the PN junctions.

[0017] The planar PIN diode 100 includes a plate-shaped substrate 30 having a front surface 30a and a back surface 30b, a cathode electrode (an example of a first electrode) 10, and an anode electrode (an example of a second electrode) 20.

[0018] In Figures 1 and 2, one direction on a horizontal plane is the x-direction. The other direction perpendicular to the x-direction on the horizontal plane is the y-direction. The direction perpendicular to the x-direction and y-directions is the z-direction, and the upper side of the z-direction is sometimes called the top or front side, and the lower side is sometimes called the bottom or back side. Also, a plane parallel to the xy plane is sometimes called a horizontal plane.

[0019] The substrate 30 is formed in a plate shape along a horizontal plane (an example of a predetermined planar direction). The substrate 30 has a front surface 30a and a back surface 30b, and the front surface 30a and the back surface 30b are along a horizontal plane. A cathode electrode 10 is formed on the back surface 30b, and an anode electrode 20 is formed on the front surface 30a. The cathode electrode 10 and the anode electrode 20 have different polarities. A forward current flows when a voltage is applied between the cathode electrode 10 and the anode electrode 20. When this forward current changes, the resistance of the planar PIN diode 100 changes. Such a planar PIN diode 100 is formed by combining layers of an intrinsic semiconductor such as silicon with impurities added thereto.

[0020] Moreover, the substrate 30 has an inner peripheral portion 30c and an outer peripheral portion 30d in a plan view. The outer peripheral portion 30d is the outer periphery of the substrate 30 in a plan view. The inner peripheral portion 30c is a region surrounded by the outer peripheral portion 30d, and is a region to which the anode electrode 20 is connected on the front surface 30a of the substrate 30. In this embodiment, the inner peripheral portion 30c is a portion where the anode electrode 20 is in contact with the p-type semiconductor region 32 via the contact 21.

[0021] In addition, the substrate 30 has, in a cross-sectional view, an n-type semiconductor region (an example of a first semiconductor region) 31 on the back surface 30b side, a p-type semiconductor region (an example of a second semiconductor region) 32 on the front surface 30a side, and a stopper region 33. In this embodiment, for example, a region in which pentavalent elements such as phosphorus and arsenic are added as impurities to tetravalent silicon is defined as an n-type impurity region. n means that electrons are carriers. In addition, for example, a region in which trivalent elements such as boron and aluminum are added as impurities to tetravalent silicon is defined as a p-type impurity region. p means that holes are carriers. In the subscripts of n and p, - means that the impurity concentration is relatively low, and + means that the impurity concentration is relatively high.

[0022] The n-type semiconductor region 31 is + The n-type semiconductor region 31a - and n-type semiconductor region 31b. + The n-type semiconductor region 31a - The n-type semiconductor region 31b is located on the back surface 30b side, and the outer surface is formed as the back surface 30b. + A cathode electrode 10 is formed on the outer surface (back surface 30b) of the semiconductor region 31a. - The n-type semiconductor region 31b is, for example, + The n-type semiconductor region 31a can be formed by epitaxial growth or the like. + Type semiconductor regions 31a and n - The method for forming the n-type semiconductor region 31b is not limited to the above. For example, - The n-type semiconductor region 31b is formed. - The n-type semiconductor region 31b + By diffusing impurities into n-type semiconductors, + It is also possible to form a type semiconductor region 31a.

[0023] The p-type semiconductor region 32 is formed inside the surface 30a side of the n-type semiconductor region 31. Specifically, the p-type semiconductor region 32 is -The p-type semiconductor region 32 is formed inside the surface 30a side of the p-type semiconductor region 31b. The p-type semiconductor region 32 is connected to the anode electrode 20 at the inner periphery 30c. The p-type semiconductor region 32 has an anode region 32a and an outer periphery voltage-resistant region 32b. The anode region 32a has an inner periphery voltage-resistant region 32a1 which is a portion of the anode region 32a located at the inner periphery 30c. Specifically, the anode region 32a is in contact with the anode electrode 20 via a contact 21 which is an opening in the oxide film 60. In this embodiment, the region in contact with the anode electrode 20 at the inner periphery 30c via the contact 21 is referred to as the inner periphery voltage-resistant region 32a1. In this embodiment, at least the inner periphery voltage-resistant region 32a1 is formed as a high resistance region as a whole. The anode region 32a including the inner periphery voltage-resistant region 32a1 may also be formed as a high resistance region as a whole. The outer periphery voltage-resistant holding region 32b is an annular region located on the outer periphery 30d more outer periphery than the anode region 32a.

[0024] The outer peripheral breakdown voltage holding region 32b is a guard ring provided on the outer peripheral portion 30d for holding the breakdown voltage of the outer peripheral portion 30d, and is also called a FLR (Field Limiting Ring). In this embodiment, the outer peripheral breakdown voltage holding region 32b is formed of two p-type annular regions, an inner annular region and an outer annular region surrounding the inner annular region. +The planar PIN diode 100 is composed of a planar semiconductor region. When a reverse voltage is applied to the planar PIN diode 100, a depletion layer is formed to surround the anode region 32a. If the peripheral voltage-resistance holding region 32b is not provided, an electric field concentration occurs at the end of the anode region 32a, and avalanche breakdown is likely to occur. On the other hand, if the peripheral voltage-resistance holding region 32b is provided, the depletion layer 90 advances from the end of the anode region 32a toward the outer edge of the peripheral portion 30d, as shown in FIG. 2. That is, the depletion layer 90 extending from the end of the anode region 32a hits the peripheral voltage-resistance holding region 32b, and advances further outward from there. This can alleviate the electric field concentration at the end of the anode region 32a. In addition, the peripheral voltage-resistance holding region 32b is electrically independent from the anode region 32a, and each of the peripheral voltage-resistance holding regions 32b is electrically independent from each other. Therefore, a voltage drop occurs from the anode region 32a toward the outer peripheral voltage holding region 32b on the anode region 32a side, and a voltage drop occurs from the outer peripheral voltage holding region 32b on the anode region 32a side toward the outer peripheral voltage holding region 32b. Therefore, electric field concentration is unlikely to occur in the outer peripheral voltage holding region 32b. In this way, the avalanche resistance of the outer peripheral portion 30d is improved by the outer peripheral voltage holding region 32b.

[0025] The inner peripheral withstand voltage holding region 32a1 improves the avalanche withstand voltage in the inner peripheral portion 30c. Even if the outer peripheral withstand voltage holding region 32b can improve the avalanche withstand voltage in the outer peripheral portion 30d, the location of avalanche breakdown may shift from the outer peripheral portion 30d to the inner peripheral portion 30c. In this case, an avalanche current flows in the anode region 32a in the inner peripheral portion 30c, making avalanche breakdown more likely. If the anode region 32a is p +When the anode region 32a is formed of a planar semiconductor region and has low resistance, the voltage drop is small and the avalanche current is likely to flow in a concentrated manner. When it is difficult to completely uniform the impurity depth and impurity concentration of the anode region 32a, the anode region 32a has a place where avalanche breakdown is likely to occur and a place where avalanche breakdown is unlikely to occur. In this case, the avalanche current is likely to flow in the place where avalanche breakdown is likely to occur, causing electric field concentration. As a result, the planar PIN diode 100 is likely to be destroyed. In this embodiment, the inner peripheral withstand voltage holding region 32a1 is provided, so that the decrease in the avalanche withstand voltage in the anode region 32a can be suppressed. The configuration of the inner peripheral withstand voltage holding region 32a1 will be described in detail later.

[0026] The stopper region 33 is formed at the outermost edge of the outer periphery 30d. + The annular region is made of a type semiconductor region.

[0027] On the surface 30a side of the substrate 30, an anode electrode 20, an equipotential electrode 50, an oxide film 60, and a passivation film 70 are formed. As described above, the anode electrode 20 is formed on the surface 30a in correspondence with the anode region 32a, particularly in contact with the inner peripheral voltage-resistance holding region 32a1. The oxide film 60 is formed as an annular region on the surface 30a from the periphery of the anode region 32a to the stopper region 33. Specifically, the oxide film 60 is formed on the surface 30a from the edge of the contact 21 to the portion where the equipotential electrode 50 is connected to the stopper region 33. The equipotential electrode 50 is formed on the surface 30a in correspondence with the stopper region 33. The anode electrode 20 is formed so as to overlap the inner edge of the oxide film 60, and the annular equipotential electrode 50 is formed so as to overlap the outer edge of the oxide film 60. The passivation film 70 is formed on the oxide film 60 between the outer periphery of the anode electrode 20 and the inner periphery of the equipotential electrode 50 .

[0028] The inner peripheral voltage-resistant region 32a1 will be further described below. Fig. 4 is a cross-sectional view taken along line IV-IV in Figs. 3A and 3B.

[0029] As shown in Fig. 2, the inner circumference withstand voltage holding region 32a1 is formed with a plurality of small regions 40 aligned along a horizontal plane. In the example of Fig. 3A and Fig. 3B, the inner circumference withstand voltage holding region 32a1 has a plurality of small regions 40 arranged in a matrix in the x and y directions in a plan view. Each small region 40 is formed to have a high resistance overall.

[0030] Each small region 40 is p + A p-type semiconductor region (an example of a central region) 41 and - 3A and 3B, in plan view, the p + The p-type semiconductor region 41 is continuously formed, and a plurality of closed regions - The p-type semiconductor region 42 + In FIG. 3A and FIG. 3B, each p - The type semiconductor region 42 has a rectangular shape in a plan view.

[0031] In the cross-sectional view of the example of FIG. + In the direction away from the p-type semiconductor region 41 + The p-type semiconductor region 41 is - In other words, in the example of FIG. + In the radial direction from the semiconductor region 41, + The p-type semiconductor region 41 is - A p-type semiconductor region 42 is formed. + In the direction away from the type semiconductor region 41 in the horizontal direction (x direction), + The p-type semiconductor region 41 is - In addition, for example, a p + In the direction away from the semiconductor region 41 in the depth direction (z direction) perpendicular to the horizontal plane, + The p-type semiconductor region 41 is - In each of the small regions 40, a p + The p type semiconductor region 41 is adjacent to both sides in the horizontal direction. -In the adjacent small region 40, a p - End regions 42a, which are parts of the type semiconductor regions 42, overlap each other.

[0032] 4, the second small region 40b and the third small region 40c are arranged to face each other in the x direction with the first small region 40a at the center. + type semiconductor region 41 and p - The p-type semiconductor region 42 is - The type semiconductor region 42 includes an end region 42a. The end region 42a of the first small region 40a and the end region 42a of the second small region 40b overlap with each other. The end region 42a of the first small region 40a and the end region 42a of the third small region 40c overlap with each other.

[0033] Here, referring to FIG. 3B and FIG. 4, each point in the x direction is defined as follows as an example. The center of each small region 40 in the x direction is defined as a small region center P1x (an example of the small region center). + The type semiconductor region (an example of a central region) 41 is a region including a small region central portion P1x. - The p-type semiconductor region 42 is sandwiched between + It is also the center of the p-type semiconductor region 41 in the x direction. + The end of the p-type semiconductor region 41 in the x direction, i.e., + type semiconductor region 41 and p - The boundary portion with the type semiconductor region 42 is defined as a central region end P2x (an example of the central region end). - Of the p-type semiconductor region (an example of the outer region) 42 + The end region 42a is an end region of the small region 40 that is distant from the type semiconductor region 41. The center position of the end region 42a in the x direction is defined as an end region center position P3x (an example of an end region center position). The end position of each small region 40 in the x direction is defined as a small region end position P4x.

[0034] Next, referring to the plan view of FIG. 3B, if the small regions 40 are the first to fifth small regions 40a to 40e, the second to fifth small regions 40b to 40e are arranged adjacent to the first small region 40a. + type semiconductor region 41 and p - The semiconductor region 42 includes a p - They overlap at an end region 42a (FIG. 4), which is a part of the type semiconductor region 42. As an example, the first small region 40a can be defined as a region surrounded by points a, b, c, and d. The second small region 40b can be defined as a region surrounded by points e, f, g, and h. The third small region 40c can be defined as a region including points a and d in addition to points m and n. The fourth small region 40d can be defined as a region including points a and b in addition to points i and j. The fifth small region 40e can be defined as a region including points c and d in addition to points k and l. The first to third small regions 40a to 40c are shown in cross-sectional view in FIG. 4.

[0035] The cross-sectional view of FIG. 4 shows a concentration curve CV of the P-type impurity concentration. In the concentration curve CV, the higher the peak, the higher the impurity concentration. In each small region 40, the p-type impurity concentration is highest at the center P1x of the small region. - In the present embodiment, a predetermined impurity concentration is set as a reference concentration, and a region where the impurity concentration is equal to or higher than the reference concentration is a p-type impurity region. + The region where the impurity concentration is less than the reference concentration is a p - The p-type semiconductor region (an example of the outer region) 42. +In the p-type semiconductor region 41, the impurity concentration may be lower from the small region center P1x to the central region end P2x. In each small region 40, the p-type impurity concentration may be gradually lower from the central region end P2x to the end region 42a. Since the end regions 42a (including the end region center position P3x and the small region end position P4x) of adjacent small regions 40 overlap, in the example of FIG. 4, the impurity concentration of the end regions 42a adjacent in the x direction is low and flat as shown by the concentration curve CV. That is, the impurity concentration is flat in the end region 42a from the small region end position P4x of the adjacent first small region 40a to the small region end position P4x of the second small region 40b. Similarly, the impurity concentration is flat in the end region 42a from the small region end position P4x of the first small region 40a to the small region end position P4x of the third small region 40c.

[0036] 4, the first small region 40a and the second small region 40b overlap each other at their end regions 42a from the small region end position P4x of the first small region 40a to the small region end position P4x of the second small region 40b. The first small region 40a and the third small region 40c overlap each other at their end regions 42a from the small region end position P4x of the first small region 40a to the small region end position P4x of the third small region 40c.

[0037] In addition, in the cross-sectional view of FIG. 4, the surface 30a of the small region 40 in the depth direction is - The depth of the p-type semiconductor region 42 is Xjp. + The distance N1 (an example of the distance N) between central region ends P2x adjacent to each other in the x-direction in the type semiconductor region 41 is expressed by the following formula. 0.60×2×Xjp≦N1≦0.95×2×Xjp

[0038] 3A, 3B, and 4, p in the x direction on the horizontal plane +The width of the type semiconductor region 41 is width W1 (an example of width W). The distance K1 (an example of K) between the small region central portions P1x adjacent in the x direction is W1+N1. Alternatively, the distance M1 (an example of M) between the end region central positions P3x adjacent in the x direction is W1+N1. It is preferable that width W1≧0.5×Xjp. It is also preferable that 3.0×Xjp≧width W1.

[0039] In FIG. 3B, each point in the y direction is defined as an example as follows. The center of each small region 40 in the y direction is defined as a small region center P1y (an example of the small region center). + The type semiconductor region (an example of a central region) 41 is a region including a small region central portion P1y. - The p-type semiconductor region 42 is sandwiched between + It is also the center of the p-type semiconductor region 41 in the y direction. + The end of the p-type semiconductor region 41 in the y direction, i.e., + type semiconductor region 41 and p - The boundary portion with the type semiconductor region 42 is defined as a central region end P2y (an example of the central region end). - Of the p-type semiconductor region (an example of the outer region) 42 + The end region 42a (FIG. 4) is an end region of the small region 40 that is distant from the type semiconductor region 41. The center position of the end region 42a in the y direction is defined as an end region center position P3y (an example of the end region center position). The end position of each small region 40 in the y direction is defined as a small region end position P4y.

[0040] In each small region 40, the p-type impurity concentration is highest in the small region center P1y in the y direction as well as in the x direction. - In the end region 42a of the type semiconductor region 42 (including the end region center position P3y and the small region end position P4y), the p-type impurity concentration is the lowest.

[0041] Adjacent p in the y direction + The distance N2 (an example of the distance N) between the central region ends P2y adjacent to each other in the y direction in the type semiconductor region 41 is expressed by the following formula. 0.60×2×Xjp≦N2≦0.95×2×Xjp

[0042] In addition, in FIG. 3B, p in the y direction on the horizontal plane + The width of the type semiconductor region 41 is width W2 (an example of width W). The distance K2 between the small region central portions P1y adjacent in the y direction is W2+N2. Alternatively, the distance M2 between the end region central positions P3y adjacent in the y direction is W2+N2. It is preferable that width W2≧0.5×Xjp. It is also preferable that 3.0×Xjp≧width W2. Note that width W1 may be equal to width W2.

[0043] In the above, the intervals N1, K1, and M1 in the x direction are defined as above, and the intervals N2, K2, and M2 in the y direction are defined as above. However, the intervals N, K, M, etc. can also be defined in the same manner as above in directions other than the x and y directions so that the end regions 42a overlap between adjacent small regions 40 and the inner peripheral voltage-resistant holding region 32a1 as a whole is configured to have high resistance.

[0044] In the inner peripheral portion 30c of the planar PIN diode 100, by defining the distance N between the adjacent central region ends P2 as described above, it is possible to suppress a decrease in the avalanche resistance in the inner peripheral portion 30c of the planar PIN diode 100. This will be explained in detail as follows.

[0045] According to the above configuration, the inner peripheral breakdown voltage holding region 32a1 located in the inner peripheral portion 30c of the p-type semiconductor region (an example of the second semiconductor region) 32 is formed by gathering a plurality of small regions 40. In each small region 40, the p-type impurity concentration is highest in the small region center P1, whereas the p-type impurity concentration is lowest in the edge region 42a. Since each small region 40 is designed so that the interval N between adjacent center region edges P2 satisfies 0.60×2×Xjp≦N≦0.95×2×Xjp, the edge regions 42a of adjacent small regions 40 overlap each other. That is, the p-type semiconductor region 32 in the inner peripheral portion 30c is formed such that the small regions 40 with low p-type impurity concentrations overlap each other in the edge regions 42a. Therefore, the p-type semiconductor region 32 in the inner peripheral portion 30c is formed in a state in which the p-type impurity concentration is low overall, and in a high resistance state.

[0046] When a reverse voltage is applied to the planar PIN diode 100 due to a surge voltage, an inductive load, or the like, and an avalanche current flows at one or more first points in the inner circumferential portion 30c, exceeding the breakdown voltage of the planar PIN diode 100, a voltage drop occurs at the first point due to the avalanche current. Since the inner circumferential portion withstand voltage holding region 32a1 located at the inner circumferential portion 30c is formed to have a high resistance as a whole, the voltage drop at the first point due to the avalanche current is relatively large. Therefore, although an avalanche current flows at the beginning when a reverse voltage is applied at the first point, the avalanche current gradually stops flowing or becomes difficult to flow due to the large voltage drop. At other second points where no avalanche current flows or where the avalanche current flows only to a small extent, the voltage drop due to the avalanche current is small. The avalanche current tends to move to a location where the combined voltage of the breakdown voltage of the planar PIN diode 100 and the voltage drop due to the avalanche current is lower and easier to flow, so the point where the avalanche current flows moves from the first point to the second point. At the second point, the avalanche current flows initially as at the first point, but gradually becomes more difficult to flow. Therefore, the point where the avalanche current flows moves to another point. In this way, the points where the avalanche current flows in the inner circumferential portion 30c move from one point to another, so that the points where the avalanche current flows are dispersed. Therefore, the avalanche current can be prevented from continuously concentrating at one point in the inner circumferential portion 30c, and thus the avalanche current can be prevented from being destroyed due to the avalanche current concentrating at the inner circumferential portion 30c, and a decrease in the avalanche resistance of the planar PIN diode 100 can be prevented.

[0047] For example, in the case where the outer peripheral voltage holding region 32b is provided in the outer peripheral portion 30d to suppress the decrease in avalanche resistance in the planar PIN diode 100, it is considered that the phenomenon that the location of the avalanche breakdown moves from the outer peripheral portion 30d to the inner peripheral portion 30c is likely to occur. In the above configuration, since the inner peripheral voltage holding region 32a1 is provided, it is useful because it can suppress the decrease in the avalanche resistance of the inner peripheral portion 30c when the avalanche breakdown occurs in the inner peripheral portion 30c. And, in the case where both the outer peripheral voltage holding region 32b and the inner peripheral voltage holding region 32a1 are provided, it is possible to suppress the decrease in the avalanche resistance in the outer peripheral portion 30d and to suppress the decrease in the avalanche resistance in the inner peripheral portion 30c. It goes without saying that the configuration in which only the inner peripheral voltage holding region 32a1 is provided can be adopted in the planar PIN diode 100, and this can suppress the decrease in the avalanche resistance in the inner peripheral portion 30c.

[0048] In the above embodiment, the interval K is defined as W+N, and the interval M is defined as W+N. Here, the adjacent small regions 40 are the first small region 40a and the second small region 40b. In the adjacent first small region 40a and the second small region 40b, the interval K between the small region centers P1 is the distance (W / 2) from the small region center P1 of the first small region 40a to the center region end P2 of the first and second small regions 40a and 40b + the interval N between the center region ends P2 of the adjacent first and second small regions 40a and 40b + the distance (W / 2) from the small region center P1 of the second small region 40b to the center region end P2. That is, the interval K is W+N. In addition, in the adjacent first small region 40a and the second small region 40b, the interval M between the end region center positions P3 is the distance (N / 2) from the end region center position P3 of the first small region 40a to the center region end P2 of ... +The distance M is the width W of the first semiconductor region 41 plus the distance (N / 2) from the end region center position P3 of the second small region 40b to the central region end P2. That is, the interval M is W+N. By designing the small regions 40 in this way, the end regions 42a of adjacent small regions 40 overlap each other. As a result, as described above, the inner peripheral portion withstand voltage holding region 32a1 in the inner peripheral portion 30c is formed in a state in which the p-type impurity concentration is low overall and in a high resistance state. Therefore, it is possible to suppress the avalanche current from flowing continuously and concentrating at one point, and therefore it is possible to suppress the decrease in the avalanche withstand capability in the inner peripheral portion 30c of the planar PIN diode 100.

[0049] In the above embodiment, the width W of the central region is defined as 0.5×Xjp or more. + The range of the p-type semiconductor region 41 can be secured. Thus, while the p-type impurity concentration in the end region 42a is low, the p-type impurity concentration can be prevented from becoming too low, such as by not having any impurities in the end region 42a. By connecting each small region 40 to each other through the end region 42a having a low p-type impurity concentration, it is possible to prevent each small region 40 from being disconnected by a region without impurities. In other words, the high resistance region formed by the inner periphery withstand voltage holding region 32a1 can be formed without being disconnected. Therefore, even if an avalanche current flows at any point in the inner periphery withstand voltage holding region 32a1, the voltage drop due to the flow of the avalanche current can be made relatively large. This allows the point where the avalanche current flows to move from one point to another, and the decrease in the avalanche withstand capability in the inner periphery 30c of the planar PIN diode 100 can be prevented.

[0050] In the above embodiment, p + The width W of the semiconductor region 41 is defined as 3.0×Xjp or less. +Therefore, the p-type impurity concentration of the small regions 40 can be kept low as a whole. + The proportion of type semiconductor region 41 and its p - The ratio of the p-type semiconductor region 42 to the p-type impurity concentration of each small region 40 can be designed so that the p-type impurity concentration of each small region 40 is low and the resistance is high as a whole. This allows the inner periphery withstand voltage holding region 32a1 to be formed in a high resistance state as a whole, thereby suppressing a decrease in avalanche withstand capability in the inner periphery 30c of the planar PIN diode 100.

[0051] For example, the p-type impurity concentration is highest in the central portion P1 of the small region. + When the proportion of the p-type semiconductor region 41 in the small region 40 becomes large, the small region 40 as a whole may have a high p-type impurity concentration and low resistance. In this case, the voltage drop when an avalanche current flows at a certain point cannot be increased, and the avalanche current flows continuously and concentratedly at this point, which makes the planar PIN diode 100 prone to destruction.

[0052] (2) Manufacturing method 5 to 10 are schematic diagrams (1) to (6) showing the manufacturing steps in the cross-sectional view of FIG. 2, and sequentially show the manufacturing steps of the planar PIN diode 100 according to this embodiment.

[0053] As shown in FIG. 5, a substrate 30 is prepared by forming an n-type semiconductor region 31 on a silicon substrate. + The n-type semiconductor region 31a - and n-type semiconductor region 31b. + The n-type semiconductor region 31a is located at the bottom of a silicon substrate. + The n-type semiconductor region 31a is used as a base wafer. - The n-type semiconductor region 31b + It can be formed on the n-type semiconductor region 31a by epitaxial growth. -After forming the n-type semiconductor region 31b, - The n-type semiconductor region 31b + By diffusing impurities into n-type semiconductors, + It is also possible to form a type semiconductor region 31a. + The surface impurity concentration of the type semiconductor region 31a on the substrate 30b side is not limited, but is, for example, 1.0×10 19 cm -3 That's all. + The upper limit of the surface impurity concentration of the n-type semiconductor region 31a on the substrate 30b side is not limited, but may be, for example, + The thickness of the n-type semiconductor region 31a - The thickness of the n-type semiconductor region 31b + The impurity concentration required in the n-type semiconductor region 31a, - The impurity concentration can be appropriately set according to the impurity concentration required in the type semiconductor region 31b. + The thickness of the n-type semiconductor region 31a is not limited, but is, for example, 25 μm or more and 735 μm or less. - The impurity concentration of the type semiconductor region 31b is not limited, but is, for example, 3.0×10 13 cm -3 Above 1.0×10 15 cm -3 The following is true: - The thickness of the type semiconductor region 31b is not limited, but is, for example, not less than 12 μm and not more than 110 μm.

[0054] Next, as shown in Figure 6, + A plurality of masks 80 are formed on the surface 30a of the n-type semiconductor region 31a. In this embodiment, each mask 80 is made of an oxide film, and an opening 81 is formed between each mask 80. In other words, the plurality of masks 80 have a plurality of openings 81. + A plurality of masks 80 and a plurality of openings 81 are formed on the surface 30a of the n-type semiconductor region 31a. +The masks 80 and the openings 81 are arranged in a matrix, for example.

[0055] In the cross-sectional view of Fig. 8, the depth from the surface 30a of the small region 40 in the depth direction is designated as Xjp. In this case, in the inner peripheral portion 30c, the distance L1 (an example of the distance L) between the ends of the openings 81 adjacent to each other in the x direction shown in the cross-sectional view of Fig. 6 is expressed by the following formula. 0.60×2×Xjp≦L1≦0.95×2×Xjp The distance L1 between the ends of the openings 81 in the inner periphery 30c is substantially the same as the distance N1 between the ends P2x of the central regions adjacent in the x direction with one mask 80 therebetween.

[0056] 6, the center in the x direction of the opening 81 in the inner circumferential portion 30c corresponds to the small region center portion P1x described above. The end in the x direction of the opening 81 in the inner circumferential portion 30c, i.e., the approximate boundary portion between the mask 80 and the opening 81 in the x direction in the inner circumferential portion 30c, corresponds to the central region end portion P2x described above. The center in the x direction of the mask 80 in the inner circumferential portion 30c corresponds to the end region center position P3x described above. The width of the opening 81 in the x direction in the inner circumferential portion 30c corresponds to the small region center portion P1x described above. + 6, the spacing between the centers of adjacent openings 81 in the x direction is substantially the same as the spacing K1, and the spacing between the centers of adjacent masks 80 in the x direction is substantially the same as the spacing M1. + 41.

[0057] Although not shown, the center in the y direction of the opening 81 in the inner circumferential portion 30c corresponds to the small region center P1y described above. The end in the y direction of the opening 81 in the inner circumferential portion 30c, i.e., the approximate boundary portion in the y direction between the mask 80 and the opening 81 in the inner circumferential portion 30c, corresponds to the central region end P2y described above. The center in the y direction of the mask 80 in the inner circumferential portion 30c corresponds to the end region center position P3y described above. In the inner circumferential portion 30c, the distance L2 (an example of the distance L) between the ends of the openings 81 adjacent in the y direction is expressed by the following formula. 0.60×2×Xjp≦L2≦0.95×2×Xjp The distance L2 between the ends of the openings 81 in the inner periphery 30c is substantially the same as the distance N2 between the ends P2y of the central regions adjacent in the y direction with one mask 80 therebetween.

[0058] In the inner circumferential portion 30c, the width of the opening 81 in the y direction is p + The width of the mask 80 is substantially equal to the width W2 of the type semiconductor region 41. In addition, in the inner periphery 30c, the interval between the centers in the y direction of adjacent openings 81 is substantially equal to the interval K2, and the interval between the centers in the y direction of adjacent masks 80 is substantially equal to the interval M2.

[0059] In the above, the intervals L1, K1, M1, L2, K2, and M2 of the mask 80 and the openings 81 are specified in the x and y directions in the inner circumferential portion 30c. However, the intervals N, K, M, etc. of the mask 80 and the openings 81 can be defined in the same manner as above in directions other than the x and y directions so that the end regions 42a overlap between adjacent small regions 40 and the inner circumferential portion voltage-resistant holding region 32a1 as a whole is configured to have high resistance.

[0060] A mask 80 and openings 81 are also provided in the outer peripheral portion 30d, but these are for forming the outer peripheral voltage-resistant holding region 32b. The various intervals of the mask 80 and openings 81 in the outer peripheral portion 30d are defined to be different from those of the mask 80 and openings 81 in the inner peripheral portion 30c.

[0061] 7, p-type impurities are deposited from above the mask 80. The p-type impurities are introduced into the n-type semiconductor layer 81 through the openings 81. - That is, the n-type semiconductor region 31b is covered with the mask 80. - No p-type impurity is deposited on the surface 30a of the n-type semiconductor region 31b. - The surface impurity concentration of the impurity deposited on the surface 30a of the type semiconductor region 31b is not limited, but is, for example, 1.0×10 20 cm -3 The upper limit of the surface impurity concentration of the p-type impurity is, for example, P - The depth Xjp of the semiconductor region 42, P - It can be appropriately set according to the required impurity concentration at the point of depth Xjp of the type semiconductor region 42, etc.

[0062] Next, the substrate 30 with the p-type impurity deposited in the opening 81 is heat-treated. - The depth of the p-type semiconductor region 42 is Xjp. For example, when Xjp is 10 μm, the substrate 30 is heat-treated at 1100° C. or more and 1280° C. or less. The time for the heat treatment is not limited, but is set appropriately depending on, for example, the diffusion speed of the p-type impurity, the depth of Xjp, and the like. As a result, the p-type impurity becomes n-type as shown in FIG. - Specifically, in the inner periphery 30c, the p-type impurity is deposited through the opening 81, and the n-type impurity is diffused into the inner periphery 30b. - The inside of the type semiconductor region 31b is mainly P + The P type semiconductor region 41 is formed by heat treatment. + The p-type impurities are diffused from the p-type semiconductor region 41. + The P - The P type semiconductor regions 42 are formed. + type semiconductor region 41 and P - A small region 40 including a p-type semiconductor region 42 is formed. -Parts of the type semiconductor regions 42, that is, the end regions 42a, overlap with each other. As a result, a plurality of small regions 40 are continuously formed in the inner periphery withstand voltage holding region 32a1, as shown in FIGS.

[0063] 8, the inner peripheral voltage-withstanding region 32a1 is formed, and the outer peripheral voltage-withstanding region 32b is also formed. The outer peripheral voltage-withstanding region 32b is formed by depositing and diffusing a p-type impurity located in the outer peripheral portion 30d shown in FIG.

[0064] By the heat treatment after the p-type impurity is deposited, an oxide layer 61 is formed on the entire surface of the front surface 30a and the entire surface of the back surface 30b of the substrate 30 as shown in FIG. 8. The oxide layer 61 on the back surface 30b is removed, and the oxide layer 61 on the front surface 30a is selectively removed corresponding to the portion where the stopper region 33 is to be formed. In a state where the front surface 30a in the portion other than the stopper region 33 is covered with the oxide layer 61, n-type impurities are deposited. Then, by the heat treatment, the stopper region 33 is formed as shown in FIG. 9. By this heat treatment, an oxide film (not shown) is formed on the entire surface of the front surface 30a and the entire back surface 30b of the substrate 30. By selectively removing this oxide film, the oxide film is removed on the back surface 30b, and the oxide film on the portion where the anode electrode 20 and the equipotential electrode 50 are to be formed on the front surface 30a is removed. As a result, the oxide film 60 remains on the front surface 30a other than the portion where the anode electrode 20 and the equipotential electrode 50 are to be formed, as shown in FIG. 9.

[0065] 10, an anode electrode 20 is formed in the inner periphery 30c of the surface 30a of the substrate 30 so as to contact the exposed inner periphery voltage-resistant region 32a1 and overlap the inner edge of the oxide film 60. Furthermore, an equipotential electrode 50 is formed in the outer periphery 30d of the surface 30a of the substrate 30 so as to contact the stopper region 33 and overlap the outer edge of the oxide film 60.

[0066] Next, as shown in FIG. 2, the back surface 30b of the substrate 30 is +A cathode electrode 10 is formed in contact with the type semiconductor region 31a. A passivation film 70 is formed on the oxide film 60 between the anode electrode 20 and the equipotential electrode 50 on the front surface 30a side of the substrate 30.

[0067] By designing the interval L between the ends of the adjacent openings 81 of the mask 80 as described above by the above manufacturing method, the interval N between the ends P2 of the adjacent central regions can be set to 0.60×2×Xjp≦N≦0.95×2×Xjp. + Since the p-type semiconductor region 41 is deposited on the p-type semiconductor region 41, the distance L between the ends of the openings 81 and the distance N between the ends P2 of the central region are substantially the same. + P-type impurities are deposited in the type semiconductor region 41, and by diffusing the p-type impurities, the inner periphery withstand voltage holding region 32a1 is formed such that the small regions 40 overlap and are connected at the end region 42a where the p-type impurity concentration is low. Therefore, the inner periphery withstand voltage holding region 32a1 is formed in a state where the p-type impurity concentration is low overall and in a high resistance state. As a result, as in the above, it is possible to suppress the decrease in the avalanche resistance of the planar PIN diode 100. Therefore, it is possible to provide a manufacturing method for the planar PIN diode 100 that can suppress the decrease in the avalanche resistance.

[0068] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these are included in the present invention.

[0069] 2. Variations (A) Inner pressure-resistant area In the above, multiple rectangular p - The p-type semiconductor region 42 +In the above description, the inner periphery withstand voltage holding region 32a1 is arranged in a matrix shape in the type semiconductor region 41. However, as long as the inner periphery withstand voltage holding region 32a1 can improve the avalanche resistance in the inner periphery 30c, the form of the inner periphery withstand voltage holding region is not limited to the above embodiment. As an example, the inner periphery withstand voltage holding region can be configured in the following form.

[0070] (1) Another aspect 1 of the inner peripheral pressure-resistant retaining region An inner peripheral voltage-resistant region 32a11 of another embodiment 1 will be described. Fig. 11 is a plan view of the inner peripheral voltage-resistant region of another embodiment 1. In the inner peripheral voltage-resistant region 32a11 of another embodiment 1, similarly to the inner peripheral voltage-resistant region 32a1 of the above embodiment, each small region 40 is p + A p-type semiconductor region (an example of a central region) 41 and - However, in the inner peripheral breakdown voltage holding region 32a1 of the above embodiment, + The p-type semiconductor region 41 is continuously formed, and a plurality of p-type semiconductor regions each having a rectangular shape in plan view are formed as closed regions. - The p-type semiconductor region 42 + In contrast, in the inner peripheral breakdown voltage holding region 32a11 of the alternative embodiment 1, p - The p-type semiconductor region 42 is continuously formed, and a plurality of p-type semiconductor regions 42 are circular closed regions in a plan view. + The p-type semiconductor region 41 - The difference is that the p-type semiconductor region 42 is arranged in a matrix shape. + The semiconductor regions 41 are arranged at equal intervals.

[0071] In FIG. 11, each point in the x direction is defined as follows, for example: + The central portion of the x-direction of the type semiconductor region 41, that is, the circular p + The center point of the semiconductor region 41 is defined as a small region center P1 (an example of a small region center). - The end of the p-type semiconductor region 42 in the x direction, i.e., + type semiconductor region 41 and p- The boundary portion between the p-type semiconductor region 42 and the central region end P2 (an example of the central region end portion) is defined as the central region end P2 (an example of the central region end portion). + The center point between the end region semiconductor regions 41 is defined as an end region center position P3 (an example of the end region center position). A small region end position P4 is located adjacent to the end region center position P3.

[0072] 11 shows a cross-sectional view taken along line IV-IV in FIG. 4. As in FIG. 4 of the above embodiment, in each small region 40, p + The p-type semiconductor region 41 is continuously arranged in the radial direction. - A type semiconductor region 42 is formed. + The type semiconductor region (an example of a central region) 41 is a region that includes a small region central portion P1, which is also the central portion in the x direction of each small region 40. The end region 42a of the small region 40 is a region that includes an end region central position P3, and the end regions 42a of adjacent small regions 40 overlap each other. The end region central position P3 is also the central position in the x direction of the end region 42a.

[0073] The distance N between the end portions P2 of the central region adjacent to each other in the x direction across the center position P3 of the end portion + The distance K between the central portions P1 of the small regions in the semiconductor region 41 is + The distance M between the center positions P3 of the end regions between the semiconductor regions 41 is + The width W of the type semiconductor region 41 is as described in the above embodiment.

[0074] (2) Another aspect 2 of the inner peripheral pressure-resistant retaining region An inner peripheral voltage-resistant region 32a12 of another embodiment 2 will be described. Fig. 12 is a plan view of the inner peripheral voltage-resistant region of another embodiment 2. In the inner peripheral voltage-resistant region 32a12 of another embodiment 2, similarly to the inner peripheral voltage-resistant region 32a1 of the above embodiment, each small region 40 is p + A p-type semiconductor region (an example of a central region) 41 and -Similarly to the inner peripheral voltage-resistance maintaining region 32a1 of the above embodiment, the inner peripheral voltage-resistance maintaining region 32a12 of Alternative Mode 2 has a p + The p-type semiconductor region 41 is continuously formed and is a closed region. - The p-type semiconductor region 42 + The p-type semiconductor region 41 is arranged in a matrix shape. - The inner peripheral breakdown voltage holding region 32a12 of the second embodiment has a p - In the inner peripheral voltage-resistant region 32a12 of the second embodiment, a plurality of p - The semiconductor regions 42 are arranged at equal intervals.

[0075] In FIG. 12, for example, each point in the x direction is defined as follows: - The central portion of the p-type semiconductor region 42, i.e., the circular p - The center point of the end semiconductor region 42 is defined as the end region center position P3 (an example of the end region center position). - The end of the p-type semiconductor region 42 in the x direction, i.e., + type semiconductor region 41 and p - The boundary portion between the p-type semiconductor region 42 and the central region end P2 (an example of the central region end portion) is defined as the central region end P2 (an example of the central region end portion). - The center point between the type semiconductor regions 42 is defined as a small region center P1 (an example of a small region center). A small region end position P4 is located adjacent to the end region center position P3.

[0076] 12 shows a cross-sectional view taken along line IV-IV in FIG. 4. As in FIG. 4 of the above embodiment, in each small region 40, p + The p-type semiconductor region 41 is continuously arranged in the radial direction. - A type semiconductor region 42 is formed. +The type semiconductor region (an example of a central region) 41 is a region that includes a small region central portion P1, which is also the central portion in the x direction of each small region 40. The end region 42a of the small region 40 is a region that includes an end region central position P3, and the end regions 42a of adjacent small regions 40 overlap each other. The end region central position P3 is also the central position in the x direction of the end region 42a.

[0077] p - The distance N between the ends P2 of the central region adjacent to each other in the x direction with the type semiconductor region 42 in between is - The distance K between the central portions P1 of the small regions adjacent in the x direction with the type semiconductor region 42 in between, - The distance M between the center positions P3 of the end regions in the semiconductor region 42 is + The width W of the semiconductor region 41 (the adjacent - The width of the type semiconductor region 42 is as described in the above embodiment.

[0078] (3) Another aspect 3 of the inner peripheral pressure-resistant retaining region An inner peripheral voltage-resistant region 32a13 of another aspect 3 will be described. Fig. 13 is a plan view of the inner peripheral voltage-resistant region of another aspect 3. In the inner peripheral voltage-resistant region 32a13 of another aspect 3, similarly to the inner peripheral voltage-resistant region 32a1 of the above embodiment, each small region 40 is p + A p-type semiconductor region (an example of a central region) 41 and - However, in the inner peripheral breakdown voltage holding region 32a1 of the above embodiment, + The p-type semiconductor region 41 is continuously formed, and a plurality of closed regions each having a rectangular shape in a plan view are formed. - The p-type semiconductor region 42 + In contrast, in the inner peripheral breakdown voltage holding region 32a13 of the third embodiment, p - The p-type semiconductor region 42 is continuously formed, and a plurality of p-type semiconductor regions 42 are formed as closed regions each having a square shape in a plan view. + The p-type semiconductor region 41 - The difference is that the p-type semiconductor region 42 is arranged in a matrix shape.+ The type semiconductor regions 41 are aligned in the x and y directions and are disposed at equal intervals in the x and y directions.

[0079] In FIG. 13, each point in the x direction is defined as follows, for example: + The central portion of the x-direction of the square p-type semiconductor region 41 + The center point of the semiconductor region 41 is defined as a small region center P1 (an example of a small region center). - The end of the p-type semiconductor region 42 in the x direction, i.e., + type semiconductor region 41 and p - The boundary portion between the p-type semiconductor region 42 and the central region end P2 (an example of the central region end portion) is defined as the central region end P2 (an example of the central region end portion). + The center point between the end region semiconductor regions 41 is defined as an end region center position P3 (an example of the end region center position). A small region end position P4 is located adjacent to the end region center position P3.

[0080] 13 shows a cross-sectional view taken along line IV-IV in FIG. 4. As in FIG. 4 of the above embodiment, in each small region 40, p + The p-type semiconductor region 41 is continuously arranged in the radial direction. - A type semiconductor region 42 is formed. + The type semiconductor region (an example of a central region) 41 is a region that includes a small region central portion P1, which is also the central portion in the x direction of each small region 40. The end region 42a of the small region 40 is a region that includes an end region central position P3, and the end regions 42a of adjacent small regions 40 overlap each other. The end region central position P3 is also the central position in the x direction of the end region 42a.

[0081] The distance N between the end portions P2 of the central region adjacent to each other in the x direction across the center position P3 of the end portion + The distance K between the central portions P1 of the small regions in the semiconductor region 41 is + The distance M between the center positions P3 of the end regions between the semiconductor regions 41 is + The width W of the type semiconductor region 41 is as described in the above embodiment.

[0082] (4) Another aspect 4 of the inner peripheral pressure-resistant retaining region An inner peripheral voltage-resistant region 32a14 of another embodiment 4 will be described. Fig. 14 is a plan view of the inner peripheral voltage-resistant region of another embodiment 4. In the inner peripheral voltage-resistant region 32a14 of another embodiment 4, similarly to the inner peripheral voltage-resistant region 32a1 of the above embodiment, each small region 40 is p + A p-type semiconductor region (an example of a central region) 41 and - Similarly to the inner peripheral voltage-resistance maintaining region 32a1 of the above embodiment, the inner peripheral voltage-resistance maintaining region 32a14 of Alternative Mode 4 has a p + The p-type semiconductor region 41 is continuously formed and is a closed region. - The p-type semiconductor region 42 + The p-type semiconductor region 41 is arranged in a matrix shape. - The inner peripheral breakdown voltage holding region 32a14 of the fourth embodiment has a p - In the inner peripheral portion withstand voltage holding region 32a14 of the fourth embodiment, a plurality of p - The p-type semiconductor regions 42 are arranged such that one side of each regular hexagon is aligned along the y direction. - The type semiconductor regions 42 are arranged at equal intervals.

[0083] In FIG. 14, each point in the x direction is defined as follows, for example: - The central portion of the p-type semiconductor region 42, i.e., the regular hexagonal p - The center point of the end semiconductor region 42 is defined as the end region center position P3 (an example of the end region center position). - The end of the p-type semiconductor region 42 in the x direction, i.e., + type semiconductor region 41 and p - The boundary portion between the p-type semiconductor region 42 and the central region end P2 (an example of the central region end portion) is defined as the central region end P2 (an example of the central region end portion). -The center point between the type semiconductor regions 42 is defined as a small region center P1 (an example of a small region center). A small region end position P4 is located adjacent to the end region center position P3.

[0084] 14 shows a cross-sectional view taken along line IV-IV in FIG. 4. As in FIG. 4 of the above embodiment, in each small region 40, p + The p-type semiconductor region 41 is continuously arranged in the radial direction. - A type semiconductor region 42 is formed. + The type semiconductor region (an example of a central region) 41 is a region that includes a small region central portion P1, which is also the central portion in the x direction of each small region 40. The end region 42a of the small region 40 is a region that includes an end region central position P3, and the end regions 42a of adjacent small regions 40 overlap each other. The end region central position P3 is also the central position in the x direction of the end region 42a.

[0085] p - The distance N between the ends P2 of the central region adjacent to each other in the x direction with the type semiconductor region 42 in between is - The distance K between the central portions P1 of the small regions adjacent in the x direction with the type semiconductor region 42 in between, - The distance M between the center positions P3 of the end regions in the semiconductor region 42 is + The width W of the semiconductor region 41 (the adjacent - The width of the type semiconductor region 42 is as described in the above embodiment.

[0086] (5) Another aspect 5 of the inner peripheral pressure-resistant retaining region An inner peripheral voltage-resistant region 32a15 according to another embodiment 5 will be described. FIG. 15 is a plan view of the inner peripheral voltage-resistant region according to another embodiment 5. In the inner peripheral voltage-resistant region 32a15 according to the another embodiment 5, similarly to the inner peripheral voltage-resistant region 32a1 according to the above embodiment, each small region 40 is p + A p-type semiconductor region (an example of a central region) 41 and - Similarly to the inner peripheral voltage-resistance maintaining region 32a1 of the above embodiment, the inner peripheral voltage-resistance maintaining region 32a15 of Alternative Mode 5 has a p +The p-type semiconductor region 41 is continuously formed and is a closed region. - The p-type semiconductor region 42 + The p-type semiconductor region 41 is arranged in a matrix shape. - The inner peripheral breakdown voltage holding region 32a15 of the fifth embodiment has a p - In the inner peripheral portion withstand voltage holding region 32a15 of the fifth embodiment, a plurality of p - The type semiconductor regions 42 are aligned in the x and y directions and are disposed at equal intervals in the x and y directions.

[0087] In FIG. 15, for example, each point in the x direction is defined as follows: - The central portion of the square-shaped p-type semiconductor region 42 - The center point of the end semiconductor region 42 is defined as the end region center position P3 (an example of the end region center position). - The end of the p-type semiconductor region 42 in the x direction, i.e., + type semiconductor region 41 and p - The boundary portion between the p-type semiconductor region 42 and the central region end P2 (an example of the central region end portion) is defined as the central region end P2 (an example of the central region end portion). - The center point between the type semiconductor regions 42 is defined as a small region center P1 (an example of a small region center). A small region end position P4 is located adjacent to the end region center position P3.

[0088] 15 shows a cross-sectional view taken along line IV-IV in FIG. 4. As in FIG. 4 of the above embodiment, in each small region 40, p + The p-type semiconductor region 41 is continuously arranged in the radial direction. - A type semiconductor region 42 is formed. +The type semiconductor region (an example of a central region) 41 is a region that includes a small region central portion P1, which is also the central portion in the x direction of each small region 40. The end region 42a of the small region 40 is a region that includes an end region central position P3, and the end regions 42a of adjacent small regions 40 overlap each other. The end region central position P3 is also the central position in the x direction of the end region 42a.

[0089] p - The distance N between the ends P2 of the central region adjacent to each other in the x direction with the type semiconductor region 42 in between is - The distance K between the central portions P1 of the small regions adjacent in the x direction with the type semiconductor region 42 in between, - The distance M between the center positions P3 of the end regions in the semiconductor region 42 is + The width W of the semiconductor region 41 (the adjacent - The width of the type semiconductor region 42 is as described in the above embodiment.

[0090] (6) Another aspect of the inner peripheral pressure-resistant retaining region 6 An inner peripheral voltage-resistant region 32a16 according to another embodiment 6 will be described. FIG. 16 is a plan view of the inner peripheral voltage-resistant region according to another embodiment 6. In the inner peripheral voltage-resistant region 32a16 according to the another embodiment 6, similarly to the inner peripheral voltage-resistant region 32a1 according to the above embodiment, each small region 40 is p + A p-type semiconductor region (an example of a central region) 41 and - However, in the inner peripheral breakdown voltage holding region 32a1 of the above embodiment, a plurality of p - The p-type semiconductor region 42 + In contrast to the inner peripheral voltage-resistance holding region 32a11 of the sixth embodiment, the p + The p-type semiconductor region 41 - In the inner peripheral voltage-resistant region 32a16 of the sixth embodiment, the linear p + In the example of FIG. 16, the p-type semiconductor regions 41 are arranged at equal intervals in the x direction. + The p-type semiconductor region 41 -The electrodes may be arranged in a ring shape within the semiconductor region 42 .

[0091] In FIG. 16, as an example, each point in the x direction is defined as follows: + The central portion of the x-direction of the type semiconductor region 41, that is, the linear p + The center point of the type semiconductor region 41 in the x direction is defined as a small region center P1 (an example of a small region center). - The end of the p-type semiconductor region 42 in the x direction, i.e., + type semiconductor region 41 and p - The boundary portion between the p-type semiconductor region 42 and the central region end P2 (an example of the central region end portion) is defined as the central region end P2 (an example of the central region end portion). + The center point between the end region semiconductor regions 41 is defined as an end region center position P3 (an example of the end region center position). A small region end position P4 is located adjacent to the end region center position P3.

[0092] 16 shows a cross-sectional view taken along line IV-IV in FIG. 4. As in FIG. 4 of the above embodiment, in each small region 40, p + The p-type semiconductor region 41 is continuously arranged in the radial direction. - A type semiconductor region 42 is formed. + The type semiconductor region (an example of a central region) 41 is a region that includes a small region central portion P1, which is also the central portion in the x direction of each small region 40. The end region 42a of the small region 40 is a region that includes an end region central position P3, and the end regions 42a of adjacent small regions 40 overlap each other. The end region central position P3 is also the central position in the x direction of the end region 42a.

[0093] The distance N between the end portions P2 of the central region adjacent to each other in the x direction across the center position P3 of the end portion + The distance K between the central portions P1 of the small regions in the semiconductor region 41 is + The distance M between the center positions P3 of the end regions between the semiconductor regions 41 is + The width W of the type semiconductor region 41 is as described in the above embodiment.

[0094] (B) Impurities In the above embodiment, an n-type semiconductor region (an example of a first semiconductor region) 31 is formed on the back surface 30b of the substrate 30, and a p-type semiconductor region (an example of a second semiconductor region) 32 is formed on the front surface 30a. However, the p-type impurity region and the n-type impurity region may be interchanged. For example, a p-type semiconductor region (an example of a first semiconductor region) may be formed on the back surface 30b of the substrate 30, and an n-type semiconductor region (an example of a second semiconductor region) 32 may be formed on the front surface 30a. In this case, in the inner periphery withstand voltage holding region, - The p-type semiconductor region is the central region and the p-type semiconductor region radiates outwards. + Each small region is formed by a p + The end regions of the first and second semiconductor regions overlap each other to form a plurality of continuous small regions. In other respects, the second embodiment is the same as the first embodiment except that the p-type impurities and the n-type impurities are interchanged. [Explanation of symbols]

[0095] 10: Cathode electrode 20: Anode electrode 21: Contact 30: Substrate 30a: surface 30b: Back side 30c: Inner circumference 30d: Outer periphery 31: n-type semiconductor region 31a :n + Semiconductor area 31b :n - Semiconductor area 32: p-type semiconductor region 32a: Anode region 32a1, 32a11 to 32a16: inner peripheral pressure-resistant region 32b: Outer peripheral pressure-resistant region 33: Stopper area 40: Small area 40a~40e: 1st~5th small area 41 :p + Semiconductor area 42 :p- Semiconductor field 42a: End area 50: Equipotential electrode 60:Acidified film 70: Polyethylene film 80 :Masuku 81: Opening 90: Depletion layer 100:PINダイオード CV : Concentration curve P1, P1x, P1y: Central part of small area P2, P2x, P2y: End of the central area P3, P3x, P3y: Center position of end area P4, P4x, P4y: Small area terminal position

Claims

1. A substrate formed in a plate shape having a front surface and a back surface along a predetermined planar direction, the substrate having an outer periphery and an inner periphery surrounded by the outer periphery in a plan view; A first electrode formed on the back surface of the substrate; a second electrode formed on the inner peripheral portion of the surface of the substrate and having a polarity different from that of the first electrode; A planar PIN diode comprising: The substrate is a first semiconductor region of a first conductivity type having an outer surface formed as the back surface and having the first electrode disposed on the outer surface; a second semiconductor region of a second conductivity type formed inside the surface side of the first semiconductor region and connected to the second electrode at the inner periphery; an inner peripheral voltage-resistance holding region located in the inner peripheral portion of the second semiconductor region is formed in a state in which a plurality of small regions of the second conductivity type are aligned along the planar direction, In each small region, the second conductive type impurity concentration is highest in a small region central portion that is a central portion of the small region, and the second conductive type impurity concentration is lowest in an edge region that is a region at an edge of the small region among the outer regions with respect to a central region including the small region central portion, The end regions of adjacent small regions overlap each other, In a cross-sectional view, if the depth of the small region in a depth direction perpendicular to the planar direction is Xjp, The distance N between adjacent ends of the central regions is: 0.60×2×Xjp≦N≦0.95×2×Xjp That is, A planar type PIN diode.

2. 2. The planar PIN diode according to claim 1, wherein, when the width of the central region in the planar direction is W, a distance K between the central portions of adjacent small regions is W+N, or a distance M between center positions of the end regions, which are center positions of the end regions, is W+N.

3. 3. A planar PIN diode according to claim 2, wherein the width W is greater than or equal to 0.5*Xjp.

4. 4. The planar PIN diode of claim 3, wherein 3.0 x Xjp ≥ width W.

5. 3. The planar PIN diode according to claim 1, wherein, in a planar view, the central region is a closed region surrounded by the outer region, and the outer region is continuously formed in a state including a plurality of the central regions, or the outer region is a closed region surrounded by the central region, and the central region is continuously formed in a state including a plurality of the outer regions.

6. A substrate formed in a plate shape having a front surface and a back surface along a predetermined planar direction, the substrate having an outer periphery and an inner periphery surrounded by the outer periphery in a plan view; A first electrode formed on the back surface of the substrate; a second electrode formed on the inner peripheral portion of the surface of the substrate and having a polarity different from that of the first electrode; A method for manufacturing a planar PIN diode comprising: forming a first semiconductor region of a first conductivity type having an outer surface formed as the back surface and having the first electrode disposed on the outer surface; forming a second semiconductor region of a second conductivity type formed inside the surface side of the first semiconductor region and connected to the second electrode at the inner periphery; The step of forming the second semiconductor region includes: a step of depositing the second conductivity type impurity into the first semiconductor region through a plurality of openings using a mask having a plurality of openings in a portion located in the inner periphery, wherein a distance L between opening ends of adjacent openings is: 0.6×2×Xjp≦L≦0.95×2×Xjp and a process of forming an inner peripheral voltage-resistance holding region located in the inner peripheral portion of the second semiconductor region by diffusing the second conductivity type impurity deposited through the opening through a heat treatment, the inner peripheral portion being made up of a plurality of small regions of the second conductivity type aligned along the planar direction, wherein in each small region, the impurity concentration of the second conductivity type is highest in a small region central portion that is a central portion of the small region, and the impurity concentration of the second conductivity type is lowest in an end region that is a region at an end of the small region among outer regions in the planar direction relative to a central region including the small region central portion, The end regions of adjacent small regions overlap each other, the opening corresponds to the central region; a depth of the small region in a depth direction perpendicular to the plane direction in a cross-sectional view is Xjp.

Images