Macro model, circuit design simulation program including macro model, and circuit design simulator capable of running circuit design simulation program

Abstract

To provide a macro model capable of preventing convergence problems.SOLUTION: A macro model (X) is used in a nodal method-based circuit design simulator (210). The macro model (X) is configured to include a behavior model (7x) having functions thereof defined by one conditional branch (ifx1) including a plurality of conditional branches (ifx2, ifx3) as options.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a macro model, a circuit design simulation program including the macro model, and a circuit design simulator capable of executing the circuit design simulation program. [Background technology]

[0002] Generally, as a model for circuit design simulation, a macro model is known that combines a plurality of behavior models to simulate a circuit response by a nodal method (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-216187 A

[0004] [overview] The macro model used in the circuit design simulation using the nodal method as described above has room for further study regarding the problem of convergence of the calculation results.

[0005] The macro model disclosed in this specification is used in a circuit design simulator using a nodal method. This macro model is configured to include a behavior model whose function is defined by one conditional branch that includes multiple conditional branches as options. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing the internal configuration of a semiconductor integrated circuit device 2. [Diagram 2] FIG. 2 is a circuit diagram showing the configuration of the semiconductor integrated circuit device 2. As shown in FIG. [Diagram 3] FIG. 3 is a block diagram showing the configuration of the macro model Y. As shown in FIG. [Figure 4]FIG. 4 is a block diagram showing the configuration of the macro model X. As shown in FIG. [Diagram 5] FIG. 5 is a block diagram showing an example of the configuration of a circuit design simulator in which the above-mentioned macro model X is used. [Figure 6] FIG. 6 is a diagram showing an example of the configuration of the circuit design simulation program 300. As shown in FIG.

[0007] [Detailed Description] <Parts to be simulated> First, a semiconductor integrated circuit device 2 that is a simulation target of the macro model X of the present disclosure and the comparative macro model Y will be described. Here, an operational amplifier will be taken as an example of the semiconductor integrated circuit device 2.

[0008] Fig. 1 is a block diagram showing the internal configuration of a semiconductor integrated circuit device 2. As shown in Fig. 1, the semiconductor integrated circuit device 2 includes an input stage 3, a gain stage 4, an output stage 5, and a phase compensation capacitance 6.

[0009] The input stage 3 has an inverting input terminal (+) and a non-inverting input terminal (-). The gain stage 4 is connected between the input stage 3 and the output stage 5. A first terminal of the phase compensation capacitance 6 is connected to the input terminal of the gain stage 4. A second terminal of the phase compensation capacitance 6 is connected to the output terminal of the gain stage 4. The phase compensation capacitance 6 prevents the semiconductor integrated circuit device 2 from oscillating.

[0010] Fig. 2 is a circuit diagram showing the configuration of the semiconductor integrated circuit device 2. As shown in Fig. 2, the input stage 3 includes a PNP bipolar transistor having a base connected to the non-inverting input terminal (+) and a PNP bipolar transistor having a base connected to the inverting input terminal (-). The input stage 3 generates an internal signal by amplifying the difference voltage between the non-inverting input terminal (+) and the inverting input terminal (-), and inputs the internal signal to the gain stage 4.

[0011] The gain stage 4 receives the internal signal from the input stage 3 and generates a high-side signal and a low-side signal. The high-side signal is input to the base of a transistor t1, which will be described later. The low-side signal is input to the base of a transistor t2, which will be described later.

[0012] The output stage 5 includes transistors t1 and t2 and resistors r1 and r2. The transistor t1 is an NPN bipolar transistor. The transistor t2 is a PNP bipolar transistor. The collector of the transistor t1 is connected to a positive power supply VCC. The emitter of the transistor t1 is connected to a first terminal of the resistor r1. The emitter of the transistor t2 is connected to a first terminal of the resistor r2. The collector of the transistor t2 is connected to a negative power supply VEE. The second terminals of the resistors r1 and r2 are both connected to an output terminal of the output signal Vout.

[0013] The output stage 5 generates an output signal Vout according to the high-side signal and the low-side signal.

[0014] <About the macro model> Next, a detailed description will be given of a macro model for simulating the above-mentioned function of the semiconductor integrated circuit device 2 (more specifically, the output current Iout of the semiconductor integrated circuit device 2). First, a macro model Y will be described as a comparative example with the macro model X of the present disclosure (= a configuration to be compared with the embodiment of the present disclosure described later) with reference to FIG.

[0015] <Comparative example: Macro model Y> Macro model Y is a SPICE [Simulation Program with Integrated Circuit Emphasis] model based on the nodal method.

[0016] Fig. 3 is a block diagram showing a configuration of a macro model Y. As shown in Fig. 3, the macro model Y includes a behavior model a1, a Zo calculation unit 7y, a behavior model a2, and a behavior model a3. The behavior models a1 to a3 and the Zo calculation unit 7y (more specifically, a conditional branch model ify1, a conditional branch model ify2, a conditional branch model ify3, and behavior models a4 to a14, which will be described later) are connected to each other via nodes.

[0017] The behavior model a1 calculates the difference between the output current Iout and the input current Iin, and inputs the calculation result to the Zo calculation unit 7y and the behavior model a2. The output current Iout is fed back to the behavior model a1.

[0018] The Zo calculation unit 7y calculates the impedance Zo based on the output values ​​of I1, I2, I3, and I4, and inputs the calculation results to the behavior model a2 and the behavior model a3. The Zo calculation unit 7y will be described in detail later.

[0019] The behavior model a2 calculates the output current Iout based on the impedance Zo and the input current Iin. The behavior model a3 calculates the drive current Idout based on the output value of the behavior model a1 and the impedance Zo.

[0020] The Zo calculation unit 7y includes a conditional branch model ify1, a conditional branch model ify2, a conditional branch model ify3, and behavior models a4 to a14.

[0021] The conditional branch model ify1 has nodes L1, R1, T1, F1, and O1. The node L1 is connected to the ground terminal. In other words, a value of 0 is input to the node L1. The output terminal of the behavior model a1 is connected to the node R1. The node T1 is connected to the node O2 of the conditional branch model ify2. The node F1 is connected to the node O3 of the conditional branch model ify3. The node O1 is connected to the behavior models a2 and a3.

[0022] The conditional branch model ify2 includes a node L2, a node R2, a node T2, a node F2, and a node O2. The output terminal of the behavior model a4 is connected to the node L2. The output terminal of the behavior model a5 is connected to the node R2. The output terminal of the behavior model a6 is connected to the node T2. The output terminal of the behavior model a7 is connected to the node F2. The node O2 is connected to the node T1 of the conditional branch model ify1.

[0023] The conditional branch model ify3 includes a node L3, a node R3, a node T3, a node F3, and a node O3. The output terminal of the behavior model a10 is connected to the node L3. The output terminal of the behavior model a11 is connected to the node R3. The output terminal of the behavior model a12 is connected to the node T3. The output terminal of the behavior model a13 is connected to the node F3. The node O3 is connected to the node F1 of the conditional branch model ify1.

[0024] The conditional branch model ify1 outputs the input value input to node T1 (the output value of the conditional branch model ify2 in FIG. 3) when the input value input to node L1 (0 in FIG. 3) is greater than the input value input to node R1 (the output value of the behavior model a1 in FIG. 3). Conversely, the conditional branch model ify1 outputs the input value input to node F1 (the output value of the conditional branch model ify3 in FIG. 3) when the input value input to node L1 is equal to or less than the input value input to node R1.

[0025] The conditional branching model ify2 outputs the input value input to node T2 (the output value of behavior model a6 in FIG. 3) when the input value input to node L2 (the output value of behavior model a4 in FIG. 3) is greater than the input value input to node R2 (the output value of behavior model a5 in FIG. 3). Conversely, the conditional branching model ify2 outputs the input value input to node F2 (the output value of behavior model a7 in FIG. 3) when the input value input to node L2 is equal to or less than the input value input to node R2.

[0026] Behavior model a9 calculates the absolute value of the output value of behavior model a1 and inputs it to behavior model a4 and behavior model a10. Behavior model a4 outputs the calculation result obtained by dividing the output value of behavior model a9 by the output value of behavior model a7. Behavior model a7 outputs the calculation result obtained by multiplying the output value of behavior model a8 by a gain value (here, 100). Behavior model a8 calculates and outputs the absolute value of the output value of I1.

[0027] The behavior model a5 calculates and outputs the absolute value of I2. The behavior model a6 multiplies the output value of the behavior model a7 by maglimit (a predetermined parameter value) and outputs the calculation result.

[0028] The conditional branching model ify3 outputs the input value input to node T3 (the output value of behavior model a12 in FIG. 3) when the input value input to node L3 (the output value of behavior model a10 in FIG. 3) is greater than the input value input to node R3 (the output value of behavior model a11 in FIG. 3). Conversely, the conditional branching model ify3 outputs the input value input to node F3 (the output value of behavior model a13 in FIG. 3) when the input value input to node L3 is equal to or less than the input value input to node R3.

[0029] Behavior model a10 outputs the calculation result obtained by dividing the output value of behavior model a9 by the output value of behavior model a13. Behavior model a11 calculates and outputs the absolute value of the output value of I4. Behavior model a12 calculates and outputs a value obtained by multiplying the output result of behavior model a13 by maglimit.

[0030] The behavior model a13 multiplies the output of the behavior model a14 by a gain value (here, 100) and outputs the multiplication result. The behavior model a14 calculates and outputs the absolute value of the output value of I3.

[0031] <Convergence problem> However, in a simulation using a macro model as described above, convergence becomes an issue. A convergence issue is a problem in which the calculation result does not converge to a desired result even if a simulation is executed. Specifically, there is a risk that a simulation analysis error will occur, causing the calculation to not start or to stop midway, resulting in an unstable calculation result.

[0032] In particular, in macro models constructed based on the nodal method, convergence problems are likely to occur if the model contains feedback paths or has discontinuous nodes. Furthermore, the presence of discontinuous nodes can easily lead to logical inconsistencies, and the simulation results (calculation results) may not converge. An example of a discontinuous node is a node in a conditional branch. When so-called model-based development (MBD) is performed using a macro model that contains such discontinuous nodes, convergence problems are likely to occur.

[0033] The macro model Y described above is configured by connecting a plurality of behavior models to each other so as to comply with the nodal method. The behavior model a1 receives the output current Iout as a feedback input and configures a feedback path within the macro model Y. Furthermore, the output end of this behavior model a1 is directly connected to the discontinuous node L1. The output end of the behavior model a1 is also connected to the discontinuous node L2 via the behavior models a9 and a4. The output end of the behavior model a1 is also connected to the discontinuous node L3 via the behavior models a9 and a10. In this way, the Zo calculation unit 7y is configured to calculate the impedance Zo by repeatedly passing through any of the discontinuous nodes L1 to L3. Then, the above-mentioned convergence problem is likely to occur.

[0034] In contrast, the macro model X according to the present disclosure can suppress the occurrence of convergence problems. Hereinafter, the macro model X according to the embodiment of the present disclosure will be described in detail. Note that the macro model X according to the embodiment of the present disclosure includes configurations common to the macro model Y described above. For this reason, the common configurations are denoted by the same reference numerals and descriptions thereof will be omitted.

[0035] <About the macro model X according to the embodiment> Macro model X is a SPICE model that complies with the nodal method.

[0036] Fig. 4 is a block diagram showing the configuration of the macro model X. As shown in Fig. 4, the macro model X includes a Zo calculation unit 7x and behavior models a1 to a3. The Zo calculation unit 7x is a behavior model that simulates a function (more specifically, a function of calculating an impedance Zo) by one conditional branch (first conditional branch ifx1). The Zo calculation unit 7x is defined by the following formula (1).

[0037]

number

[0038] As shown in formula (1), the calculation formula of Zo calculation unit 7x is defined by one condition branch (in accordance with FIG. 4, the first condition branch ifx1) including multiple condition branches (in accordance with FIG. 4, two condition branches: the second condition branch Ifx2 and the third condition branch ifx3). Note that here, the condition branch defined at the highest level in formula (1) is defined as the first condition branch ifx1. Also, of the options of the first condition branch ifx1, the condition branch selected when the first condition branch ifx1 is true is defined as the second condition branch ifx2. Also, of the options of the first condition branch ifx1, the condition branch selected when the first condition branch ifx1 is false is defined as the third condition branch ifx3.

[0039] 4 and Equation (1), the first conditional branch ifx1 judges true or false based on the output Vo_Vin (first input) of the behavior model a1. As described above, the value of the output Vo_Vin is the difference between the output current Iout and the input current Iin.

[0040] The truth or falsity of the second condition branch ifx2 is determined based on the output Vo_Vi, I1 (second input), and I2 (third input). Of the options of the second condition branch ifx2, the formula (=I1×100×maglimit) selected when the second condition branch ifx2 is true is referred to as the first formula. Of the options of the second condition branch ifx2, the formula selected when the second condition branch ifx2 is false is referred to as the second formula (=I1×100).

[0041] The third condition branch ifx3 determines true or false based on the output Vo_Vi, I3 (fourth input), and I4 (fifth input). Of the options of the third condition branch ifx3, the formula (=I3×100×maglimit) selected when the third condition branch ifx3 is true is referred to as the third formula. Of the options of the third condition branch ifx3, the formula (=I3×100) selected when the third condition branch ifx3 is false is referred to as the fourth formula.

[0042] The first condition branch ifx1 will be specifically described. When the value of the output Vo_Vi is negative, the second condition branch ifx2 is selected from among the options of the first condition branch ifx1 (either the second condition branch ifx2 or the third condition branch ifx3). Here, when the output current Iout is greater than I2 (more specifically, when Vo_Vi / (I1×100) is greater than I2), the first formula is selected from among the options of the second condition branch ifx2 (either the first formula or the second formula). In this case, the impedance Zo is a value calculated by the absolute value of I1×100×maglimit.

[0043] When the value of the output Vo_Vi is negative and the output current Iout is equal to or less than I2 (more specifically, when Vo_Vi / (I1×100) is equal to or less than I2), the second formula is selected from the options of the second conditional branch ifx2. In this case, the impedance Zo is a value calculated by the absolute value of I1×100.

[0044] On the other hand, when the value of the output Vo_Vi is positive, the third conditional branch ifx3 is selected from among the options of the first conditional branch ifx1. Here, when the output current Iout is greater than I4 (more specifically, when Vo_Vi / (I3×100) is greater than I4), the third equation is selected from among the options of the third conditional branch ifx3 (either the third equation or the fourth equation). In this case, the impedance Zo is a value calculated by the absolute value of I3×100×maglimit.

[0045] When the value of the output Vo_Vi is positive and the output current Iout is equal to or less than I4 (more specifically, when Vo_Vi / (I3×100) is equal to or less than I4), the fourth formula is selected from among the options of the third conditional branch ifx3. In this case, the impedance Zo is a value calculated by the absolute value of I3×100.

[0046] As described above, the Zo calculation unit 7x is configured with one behavior model (first conditional branch ifx1). Therefore, the number of nodes in the Zo calculation unit 7x is relatively small, and convergence problems are unlikely to occur.

[0047] As described above, the Zo calculation unit 7x is configured with one behavior model (first condition branch ifx1) that includes multiple condition branches (second condition branch ifx2 and third condition branch ifx3) as options. This makes it difficult for convergence problems to occur.

[0048] Furthermore, the Zo calculation unit 7x selects one of four patterns (any of the first to fourth formulas) according to the output current Iout to calculate the impedance Zo. This allows for more accurate calculation of the impedance Zo according to the output current Iout. Therefore, the macro model X allows for more accurate simulation while suppressing the convergence problem as described above.

[0049] <Circuit design simulator> 5 is a block diagram showing an example of the configuration of a circuit design simulator that uses the above-mentioned macro model X. A circuit design simulator 210 of this example is a computer having a calculation unit 211, a storage unit 212, an operation unit 213, a display unit 214, and a communication unit 215, and is realized by causing the calculation unit 211 to execute a circuit design simulation program 300 stored in the storage unit 212.

[0050] The calculation unit 211 comprehensively controls the operation of the circuit design simulator 210. For example, the calculation unit 211 executes a circuit design simulation program 300 stored in the storage unit 212, performs various calculation processes for making a computer function as the circuit design simulator 210, and also performs recognition processing of user operations input from an operation unit 213 and display control of various screens on the display unit 214. As the calculation unit 211, for example, a CPU [central processing unit] can be used.

[0051] The storage unit 212 is used as a storage area for the OS (operation system) program and various software (including the circuit design simulation program 300), as well as a storage area for various data created by the user and a work area for various software. As the storage unit 212, a hard disk drive, a solid state drive, a USB (universal serial bus) memory, or the like can be used.

[0052] The operation unit 213 accepts various user operations (such as a circuit creation operation, a component reference operation, and a probe installation operation) and transmits them to the calculation unit 211. As the operation unit 213, a keyboard, a mouse, a trackball, a pen tablet, a touch panel, or the like can be used.

[0053] The display unit 214 displays various screens (such as a circuit creation field, a parts palette, and a waveform drawing window) based on instructions from the calculation unit 211. As the display unit 214, a liquid crystal display or the like can be used.

[0054] The communication unit 215 performs information communication via an electric communication line 220 (such as the Internet or a LAN [local area network]) based on an instruction from the calculation unit 211. For example, the communication unit 15 performs information communication with servers 230X to 230Z of vendors that manufacture and sell semiconductor integrated circuit devices via the electric communication line 220, and downloads macro model files (*.mod) and the like.

[0055] By using such a circuit design simulator 210, it becomes possible to perform simulation verification (characteristic evaluation, operation check, etc.) of an analog circuit before actually fabricating the analog circuit as a prototype.

[0056] <Circuit design simulation program> 6 is a diagram showing an example of the configuration of a circuit design simulation program 300. The circuit design simulation program 300 (for example, a SPICE-based circuit design simulation program) is software that is executed by a computer and causes the computer to function as a circuit design simulator 210 (see FIG. 5). The circuit design simulation program 300 of this example configuration includes a main program 310 and a model library 320. The circuit design simulation program 300 is transferred or distributed via physical media such as an optical disc (CD-ROM, DVD-ROM, etc.) or a semiconductor memory (USB memory, etc.), or via an electric communication line such as the Internet.

[0057] The main program 310 is the core part for causing the computer to function as the circuit design simulator 210, and is formed as a collection of various module programs (e.g., a circuit creation module 311, a component reference module 312, a probe placement module 313, a waveform drawing module 314, and a waveform analysis module 315).

[0058] The circuit creation module 311 is an element program for making the calculation unit 211 and the display unit 214 function to create a circuit on the circuit design simulator 210 based on an input from the operation unit 213. When a user uses the operation unit 213 to place component symbols (resistors, capacitors, transistors, diodes, operational amplifiers, voltage sources, current sources, wiring, etc.) displayed on the display unit 214 in the circuit creation field, the circuit creation module 311 creates text-based code according to the placement content. This allows the user to intuitively create any analog circuit without directly editing the text-based code.

[0059] The part reference module 312 is an element program for causing the calculation unit 211 and the display unit 214 to function so as to refer to the model library 320 based on an input from the operation unit 213. For example, when a user uses the operation unit 213 to select a symbol of an operational amplifier from a parts palette displayed on the display unit 214, the part reference module 312 refers to a macro model 323 (corresponding to the above-mentioned macro model X) of the operational amplifier included in the model library 320.

[0060] The probe installation module 313 is a component program for causing the calculation unit 211 and the display unit 214 to function so as to install a probe (a voltage or current measurement point) on the circuit diagram based on an input from the operation unit 213. For example, when a user uses the operation unit 213 to click with a mouse on a specific node on the circuit diagram displayed on the display unit 214, the probe installation module 313 installs a probe on the clicked node.

[0061] The waveform drawing module 314 is a component program for causing the calculation unit 211 and the display unit 214 to function so as to draw a waveform of a node at which a probe is placed, based on an input from the operation unit 213. For example, when a user places a probe on an output terminal of an operational amplifier displayed on the display unit 214 using the operation unit 213, the waveform drawing module 314 displays the output waveform (pseudo oscilloscope waveform) of the operational amplifier in a waveform drawing window.

[0062] The waveform analysis module 315 is a component program for causing the calculation unit 211 and the display unit 214 to function so as to perform waveform analysis of a node where a probe is installed based on an input from the operation unit 213. Examples of waveform analysis that can be performed by the waveform analysis module 315 include transient analysis, DC analysis, small signal AC analysis, and noise analysis.

[0063] The model library 320 includes various simulation models (such as a passive element model 321, an active element model 322, and a macro model 323) used in the circuit design simulator 210, and is referenced from the main program 310 (particularly the component reference module 312) as part of the circuit design simulation program 300. The passive element model 321 is a program that operates a computer to simulate the response of a passive element (such as a resistor and a capacitor) on the circuit design simulator 210. The active element model 322 is a program that operates a computer to simulate the response of an active element (such as a transistor and a diode) on the circuit design simulator 210. The operational amplifier macro model 323 (corresponding to the macro model X mentioned above) is a program that operates a computer to simulate the response of an operational amplifier on the circuit design simulator 210. Incidentally, some of the above simulation models (passive element model 321, active element model 322, macro model 323) can be downloaded free of charge via telecommunications line 220 from servers 230X-230Z of vendors that manufacture and sell semiconductor integrated circuit devices.

[0064] By using such a circuit design simulation program 300, it becomes possible to use a general-purpose computer (such as a personal computer or a workstation) as the circuit design simulator 210.

[0065] <Other Modifications> In addition to the above-mentioned embodiment, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-mentioned embodiment, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0066] For example, the above-mentioned first to fourth formulas may be formulas including conditional branching as options. In this way, it becomes possible to define various functions by one behavior model. Furthermore, it becomes possible to simulate relatively complicated functions to a high degree by using a macro model composed of a relatively small number of nodes while suppressing the above-mentioned convergence problem.

[0067] Moreover, the macro model X is a SPICE model conforming to the nodal point method, but it is not limited to the SPICE model and may be another simulation model as long as it is a simulation model based on a technique conforming to the nodal point method.

[0068] Furthermore, the Zo calculation unit 7x can be configured to include other behavior models in addition to the first condition branch ifx1. In this way, it is possible to provide a macro model X capable of executing a more advanced simulation.

[0069] Moreover, the electronic component to be simulated by the macro model X is not limited to the operational amplifier described above, but may be another semiconductor integrated circuit device.

[0070] <Additional Notes> The macro model (X) disclosed in the specification is a macro model (X) used in a circuit design simulator (210) using a nodal method, and is configured to include a behavior model (7x) whose function is defined by one conditional branch (ifx1) that includes multiple conditional branches (ifx2, ifx3) as options (first configuration).

[0071] In addition, in the macro model (X) according to the first configuration, the behavior model (7x) includes a first conditional branch (ifx1) that determines whether the result is true or false, a second conditional branch (ifx2) that is selected if the first conditional branch (ifx1) is true, and a third conditional branch (ifx3) that is selected if the first conditional branch (ifx1) is false, the second conditional branch (ifx2) is configured to include a first expression that is selected if the result is true and a second expression that is selected if the result is false, and the third conditional branch (ifx3) is configured to include a third expression that is selected if the result is true and a fourth expression that is selected if the result is false (second configuration).

[0072] Furthermore, the macro model (X) according to the second configuration may be configured such that the first condition branch (ifx1) is defined to determine true or false based on the first input (Vo_Vi), the second condition branch (ifx2) is defined to determine true or false based on the first input (Vo_Vi), the second input (I1), and the third input (I2), the third condition branch (ifx3) is defined to determine true or false based on the first input (Vo_Vi), the fourth input (I3), and the fifth input (I4), the first formula is a calculation formula based on the second input (I1) and a predetermined parameter value (maglimit), the second formula is a calculation formula based on the second input (I1), the third formula is a calculation formula based on the fourth input (I3) and the parameter value (maglimit), and the fourth formula is a calculation formula based on the fourth input (I3) (third configuration).

[0073] In addition, in the macro model (X) relating to any one of the first to third configurations, the behavior model (7x) may be configured to receive a feedback input corresponding to its output (Iout) (fourth configuration).

[0074] Moreover, the macro model (X) according to the fourth configuration may be configured to simulate the function of an operational amplifier (fifth configuration).

[0075] The circuit design simulation program (300) disclosed in the specification is executed by a computer having a calculation unit and causes the computer to function as a circuit design simulator (210), and includes a macro model (X) of any one of the first to fifth configurations, and is configured to operate the computer to simulate the response of a semiconductor integrated circuit device (2) on the circuit design simulator (210) (sixth configuration).

[0076] In addition, the circuit design simulator (210) disclosed in the specification is configured to be realized by causing a computer to execute a circuit design simulation program (300) of a sixth configuration (seventh configuration).

[0077] According to the macro model (X) of the first configuration, it is possible to define a macro model (X) that includes multiple conditional expressions among the options (ifx2, ifx3) of a conditional branch (ifx1). This makes it possible to define more complex calculation expressions while reducing the number of nodes. This makes it possible to configure a macro model (X) that can perform more advanced simulations while suppressing convergence problems.

[0078] Moreover, the macro model (X) of the second configuration makes it possible to execute a more advanced simulation while suppressing convergence problems.

[0079] Moreover, according to the macro model (X) of the third configuration, by defining a predetermined parameter value (maglimit), it is possible to configure the macro model (X) in accordance with various simulations.

[0080] Moreover, according to the macro model (X) of the fourth configuration, in the macro model (X) that simulates a control circuit including a feedback control system, it is possible to suppress the problem of convergence.

[0081] Moreover, according to the macro model (X) of the fifth configuration, it is possible to suppress the convergence problem in the macro model (X) that simulates the function of the operational amplifier.

[0082] Moreover, according to the circuit design simulation program (300) of the sixth configuration, it becomes possible to perform simulation verification of an analog circuit before actually fabricating the analog circuit as a prototype.

[0083] Moreover, according to the seventh configuration of the circuit design simulator (210), it becomes possible to use a general-purpose computer as the circuit design simulator (210). [Explanation of symbols]

[0084] 2. Semiconductor Devices 3 Input Stage 4 Gain Stages 5 Output Stage 6 Phase compensation capacitance 7x, 7y Zo calculation part 9 Behavioral Models 210 Circuit Design Simulator 211 Arithmetic section 212 Storage section 213 Operation section 214 Display section 215 Communications Department 220 Telecommunications Lines 230X~230Z Servers 300 Circuit design simulation program 310 Main Program 311 Circuit Creation Module 312 Part Reference Module 313 Probe Installation Module 314 Waveform Drawing Module 315 Waveform Analysis Module 320 Model Library 321 Passive Element Model 322 Active element model 323 Macro Model F1~F3 nodes Idout Drive current Iin Input current Iout Output current L1~L3 nodes O1~O3 nodes r1, r2 resistance R1~R3 ​​nodes t1, t2 transistors T1~T3 nodes VCC positive power supply VEE negative power supply Vout Output signal X, Y Macro Model a1~a14 Behavior models ifx1 First conditional branch ifx2 Second conditional branch ifx3 Third conditional branch ify1~ify3 Conditional branching model

Claims

1. A macro model used in a circuit design simulator using a nodal method, The macro model is configured to include a behavior model whose function is defined by one conditional branch that includes a plurality of conditional branches as options.

2. the behavior model includes a first conditional branch that determines whether the condition is true or false, a second conditional branch that is selected when the first conditional branch is true, and a third conditional branch that is selected when the first conditional branch is false; the second conditional branch is configured to include a first expression that is selected if true and a second expression that is selected if false; 2. The macro model of claim 1, wherein the third conditional branch is configured to include a third expression that is selected if true and a fourth expression that is selected if false.

3. The first conditional branch is defined to determine true or false based on a first input; the second conditional branch is defined to determine true or false based on the first input, the second input, and the third input; the third conditional branch is defined to determine true or false based on the first input, the fourth input, and the fifth input; the first formula is a calculation formula based on the second input and a predetermined parameter value; the second formula is a calculation formula based on the second input, the third formula is a calculation formula based on the fourth input and the parameter value, The macro model according to claim 2 , wherein the fourth equation is a calculation equation based on the fourth input.

4. 2. The macro model of claim 1, wherein the behavior model is configured to receive a feedback input responsive to its output.

5. 5. The macromodel of claim 4 configured to simulate the function of an operational amplifier.

6. A circuit design simulation program that is executed by a computer having a calculation unit and causes the computer to function as the circuit design simulator, 6. A circuit design simulation program comprising the macro model according to claim 1, for operating said computer so as to simulate a response of a semiconductor integrated circuit device on said circuit design simulator.

7. A circuit design simulator that is realized by causing the computer to execute the circuit design simulation program according to claim 6.

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