Input excitation completeness detection method, system and device and storage medium

Abstract

The embodiment of the invention discloses an input excitation completeness detection method, system and device and a storage medium, relates to the technical field of semiconductor verification, and aims to improve the efficiency of port signal excitation completeness verification. The method comprises the following steps: analyzing a signal attribute of an input port in a tested design file; based on the signal attributes, generating a function coverage rate file covering all input signals, the function coverage rate file including value coverage logic detection assertions corresponding to different signal attributes and function coverage rates; and monitoring and detecting the function coverage state of the current input excitation signal according to the function coverage file. The method is suitable for verification scenes of semiconductors such as chips and the like.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor verification technology, and in particular to an input stimulus integrity detection method, system, device and storage medium. Background Art

[0002] With the development of very large-scale integrated circuits, the design of large chips and very large chips has become increasingly complex. Vulnerabilities in the design can easily cause the chip to malfunction. Once it needs to be re-striped, it will not only cost a lot of money but also delay the chip's time to market. The high risk of chips highlights the importance of verification, and the requirements for the completeness of verification are getting higher and higher.

[0003] To verify more functions, related technologies combine targeted verification with random verification. In random verification platforms, functional coverage methods are often used. This involves manually adding corresponding functional coverage files for all function points in the test plan, loading the files into the verification environment (testbench), and analyzing the functional coverage reports. However, this method often relies on manual operation, is inefficient, and prone to omissions. Furthermore, some basic input ports, because they are not considered as functional points, can also result in omissions in the completeness verification of port signal excitation. Summary of the Invention

[0004] In view of this, embodiments of the present application provide an input stimulus integrity detection method, system, device, and storage medium to facilitate improving the efficiency of port signal stimulus integrity verification.

[0005] In a first aspect, an embodiment of the present application provides an input stimulus completeness detection method, comprising: parsing the signal attributes of the input port in the design under test (DUT); generating a functional coverage file covering all input signals based on the signal attributes, wherein the functional coverage file contains value coverage logic detection assertions and functional coverage corresponding to different signal attributes; and testing the functional coverage file to detect the functional coverage status of the current input stimulus signal.

[0006] According to a specific implementation method of an embodiment of the present application, after monitoring and detecting the functional coverage status of the current input stimulus according to the functional coverage file, the method also includes: if there is an input stimulus signal that is not functionally covered, dynamically adjusting the current input stimulus according to the characteristic parameters of the input stimulus signal that is not functionally covered until the preset functional coverage of the input stimulus signal is reached.

[0007] According to a specific implementation method of an embodiment of the present application, the generating of a functional coverage file covering all input signals based on the signal attributes includes: for a signal having a numerical value range, generating a boundary value functional coverage including a maximum value and a minimum value of the bit width; wherein, the signal attribute at least indicates that the type of the input signal is a signal having a numerical value range.

[0008] According to a specific implementation method of an embodiment of the present application, the boundary value function coverage including the maximum and minimum values of the bit width is generated for a signal with a numerical value range, including: for a signal within the minimum value and the bit width threshold range, all values are traversed; for a signal within the bit width threshold and the maximum value range, it is divided into multiple value range segments, and the boundary values and each segmented interval are covered.

[0009] According to a specific implementation method of an embodiment of the present application, the generation of a functional coverage file covering all input signals based on the signal attributes includes: for signals with fixed timing requirements, determining trigger conditions based on the edge characteristics of the clock signal, and setting disable conditions to define the scope of the assertion; the signal attributes at least indicate that the type of the input signal is a signal with fixed timing requirements; defining attributes according to preset timing intervals and signal state change rules, and generating a functional coverage logic detection assertion for detecting whether the clock signal timing sequence meets the design requirements; wherein the preset timing intervals and signal state change rules are determined according to the design specifications of the signal with fixed timing requirements.

[0010] According to a specific implementation method of an embodiment of the present application, the parsing of the signal properties of the input ports in the design file under test includes: parsing the top-level module description file of the design under test, and extracting the signal properties of all input ports; the top-level module description file includes indicating the input port and the signal properties of the corresponding input port.

[0011] According to a specific implementation method of an embodiment of the present application, the function coverage file is generated based on a script; after generating the function coverage file, the method further includes: compiling the function coverage file into a design verification environment under test, and configuring the design verification environment under test so as to call the function coverage file during verification to detect the coverage status of the design function under test.

[0012] In the second aspect, an embodiment of the present application provides an input stimulus completeness detection system, including: a parsing unit for parsing the signal properties of the input port in the design file under test; a generation unit for generating a functional coverage file covering all input signals based on the signal properties, wherein the functional coverage file contains value coverage logic detection assertions and functional coverage corresponding to different signal properties; a monitoring and detection unit for testing the functional coverage file to detect the functional coverage status of the current input stimulus signal.

[0013] According to a specific implementation method of an embodiment of the present application, the system also includes: an adjustment unit, which is used to dynamically adjust the current input excitation according to the characteristic parameters of the input excitation signal that is not covered by the function if there is an input excitation signal with no function coverage, until the functional coverage of the preset input excitation signal is reached.

[0014] According to a specific implementation method of an embodiment of the present application, the generation unit includes: a first generation module, which is used to generate a boundary value function coverage including a maximum value and a minimum value of a bit width for a signal having a numerical value range; wherein the signal attribute at least indicates that the type of the input signal is a signal having a numerical value range.

[0015] According to a specific implementation method of an embodiment of the present application, the generation module includes: a traversal sub-module, which is used to traverse all values for signals within the minimum value and bit width threshold range; a division sub-module, which is used to divide the signal within the bit width threshold and maximum value range into multiple value range segments, and cover the boundary values and each segmented interval.

[0016] According to a specific implementation method of an embodiment of the present application, the generation unit includes: a determination module, which is used to determine the trigger condition for a signal with fixed timing requirements based on the edge characteristics of the clock signal, and set a disable condition to define the scope of the assertion; the signal attribute at least indicates that the type of the input signal is a signal with fixed timing requirements; a second generation module, which defines the attribute according to the preset timing interval and signal state change rules, and generates a functional coverage logic detection assertion for detecting whether the clock signal timing sequence meets the design requirements; wherein the preset timing interval and signal state change rules are determined according to the design specifications of the signal with fixed timing requirements.

[0017] According to a specific implementation method of an embodiment of the present application, the parsing unit includes: a parsing module for parsing the top-level module description file of the design under test, wherein the top-level module description file includes an indication of an input port and a signal attribute of the corresponding input port; an extraction module for extracting the signal attributes of all input ports.

[0018] According to a specific implementation method of an embodiment of the present application, the function coverage file is generated based on a script. After the function coverage file is generated, the system also includes: a compilation unit, which is used to compile the function coverage file into the design verification environment under test, and configure the design verification environment under test to call the function coverage file during verification to detect the coverage status of the design function under test.

[0019] In a third aspect, an embodiment of the present invention provides an electronic device, characterized in that the electronic device includes: a memory and a processor, wherein the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, thereby implementing any input stimulus completeness detection method described in the first aspect.

[0020] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores one or more computer programs. When the one or more computer programs are executed by one or more processors, the input stimulus completeness detection method described in any one of the first aspects is implemented.

[0021] The input stimulus completeness detection method, system, device, and storage medium provided in the embodiments of the present application no longer manually add functional coverage files through function points in the test plan. Instead, the method analyzes the signal attributes of the input ports in the design file under test; generates a functional coverage file covering all input signals based on the signal attributes; the functional coverage file contains value coverage logic detection assertions and functional coverage corresponding to different signal attributes; and monitors and detects the functional coverage status of the current input stimulus signal based on the functional coverage file. In this way, since the DUT input ports are analyzed to generate a functional coverage file covering all input signals, and the functional coverage file contains value coverage logic detection assertions corresponding to different signal attributes, it ensures that all input ports are covered and all possible values of each input port are tested, which helps avoid the potential problem of missing basic input ports. As a result, port signal excitation can be more comprehensively covered, thereby facilitating the improvement of the efficiency of port signal excitation completeness verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1This is a flow chart of an embodiment of a method for detecting completeness of input incentives in this application; Figure 2 This is a timing relationship diagram of the fixed timing requirement signals in this application; Figure 3 Schematic diagram of the input signal stimulus integrity check process in this application; Figure 4 This is a schematic diagram of the basic structure of the verification environment in this application; Figure 5 This is a schematic block diagram of the architecture of an embodiment of an input stimulus integrity detection system in this application; Figure 6 This is a schematic structural diagram of an embodiment of the electronic device of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0026] In a first aspect, an embodiment of the present invention provides an input stimulus completeness detection method, which is applicable to integrated circuit design verification scenarios including chips, and can more comprehensively cover port signal stimulus and improve the completeness of the verification of the design under test.

[0027] like Figure 1 As shown, the input stimulus integrity detection method provided by the embodiment of the present invention includes: S11, parsing the signal attributes of the input port in the design file under test; Parsing the input signal properties of the Design Under Test (DUT) file is a key step in setting up the verification environment. In some cases, manual parsing of the design file is sufficient. However, as the design complexity increases, systematic parsing of the input signal properties can be implemented to support rapid verification environment setup and accurate signal property extraction.

[0028] Extracting input port signal properties is accomplished by parsing hardware description language files. In some examples, the hardware description language file can be at least one of Verilog, VHDL, or SystemVerilog. The signal extraction process begins by importing the DUT file into the verification platform, reading the DUT file, extracting the input port declarations within the DUT file, parsing the input port signal names, and determining the unique identifier for each input port. The input port signal direction is then determined, confirming that the signal direction is input.

[0029] S12. Generate a function coverage file covering all input signals based on the signal attributes, wherein the function coverage file includes value coverage logic detection assertions and function coverage corresponding to different signal attributes; In functional coverage files, assertions and functional coverage work together. Assertions are used to perform real-time checks on the specific functions and behaviors of the design during verification, ensuring design correctness; functional coverage, on the other hand, provides a quantitative assessment of the overall comprehensiveness of verification. In some embodiments, functional coverage files can be generated manually or based on input port signal attributes to ensure coverage of all input signal attribute value combinations, thereby improving verification completeness and efficiency.

[0030] Based on input port signal attributes, such as signal name, direction, width, type, attributes, comments, initial value, timing requirements, and electrical characteristics, the value range and value combinations of each signal can be determined. Based on the signal value range and value combinations, a functional coverage model is configured and generated, with coverpoints and covergroups defined. Value coverage logic assertions are generated for each coverpoint to ensure that all possible signal attribute value combinations are covered, thus forming a functional coverage file. In some examples, the functional coverage file can be formatted in SystemVerilog functional coverage syntax, XML, or JSON.

[0031] S13: Test the function coverage file to detect the function coverage status of the current input excitation signal.

[0032] After generating the functional coverage file, load the functional coverage file. In one embodiment, the functional coverage file is parsed and run by a simulation tool to complete the test of the coverage file, and the coverage is collected to generate a report. The simulation tool can be VCS or Verilator. Test the functional coverage file and monitor the value changes of the input stimulus signal in real time. According to the coverage points, coverage groups and value coverage logic detection assertions in the functional coverage file, detect the functional coverage status of the current input stimulus signal and determine whether the current input stimulus signal covers the target value combination. Based on the recorded functional coverage status, generate real-time coverage data to check whether all target function points are fully covered.

[0033] The input stimulus completeness testing method provided in the embodiments of the present application no longer manually adds a functional coverage file through the function points in the test plan. Instead, it analyzes the signal attributes of the input ports in the design file under test; generates a functional coverage file covering all input signals based on the signal attributes; the functional coverage file contains value coverage logic detection assertions and functional coverage corresponding to different signal attributes; and monitors and detects the functional coverage status of the current input stimulus signal based on the functional coverage file. In this way, because the DUT input ports are analyzed to generate a functional coverage file covering all input signals, and the functional coverage file contains value coverage logic detection assertions corresponding to different signal attributes, all input ports are ensured to be covered, and all possible values of each input port are tested, which helps to avoid the potential problem of missing basic input ports. As a result, port signal stimulus can be more comprehensively covered, thereby facilitating the improvement of the efficiency of port signal stimulus completeness verification.

[0034] In some embodiments, after monitoring and detecting the functional coverage status of the current input stimulus according to the functional coverage file, the method further includes: if there is an input stimulus signal that is not functionally covered, dynamically adjusting the current input stimulus according to the characteristic parameters of the input stimulus signal that is not functionally covered until the functional coverage of the preset input stimulus signal is reached.

[0035] During the simulation process, the functional coverage status of the input stimulus signal is monitored in real time. This monitoring is implemented through an interface provided by the simulation tool. In some examples, the interface provided by the simulation tool may be a Verilog Procedural Interface (VPI) or a Direct Programming Interface (DPI). Based on the functional coverage status, a check is performed to determine whether there are any input stimulus signals that are not functionally covered. If there are any input stimulus signals that are not functionally covered, characteristic parameters of the uncovered signals are extracted, the current input stimulus is dynamically adjusted, and the functional coverage status of the input stimulus signal is continuously monitored in real time. The above steps are repeated until the preset functional coverage rate of the input stimulus signal is reached.

[0036] When dynamically adjusting the current input stimulus, targeted supplemental test cases are generated based on the characteristic parameters of uncovered signals. Constrained random testing weights are adjusted to prioritize uncovered value combinations, increasing simulation time or resource allocation to ensure that uncovered combinations are fully tested. After adjusting the input stimulus, the functional coverage status of the input stimulus signal is re-monitored and the coverage data is updated.

[0037] In some embodiments, when parsing the signal attributes of the input port in the design under test file, extracting the input port declaration portion in the DUT file further includes: obtaining the input port signal width for a signal type with a numerical value range, extracting the signal bit width information, and defaulting to 1 bit if not specified; parsing the input port signal type to determine the signal data type, and defaulting to a wire type if not specified. The wire type is a basic data type used to represent a connection in a hardware description language, and is generally a signal type with a numerical value range.

[0038] In some embodiments, generating a functional coverage file covering all input signals based on the signal attributes includes: for a signal having a numerical value range, generating a boundary value functional coverage including a maximum value and a minimum value of the bit width; wherein the signal attribute at least indicates that the type of the input signal is a signal having a numerical value range.

[0039] Based on the attribute information of the signal in the DUT, the signal attribute at least indicates that the type of the input signal is a signal with a numerical value range, such as the signal name, width, and value range information, the boundary value of the signal is calculated, including the minimum value, maximum value and optional other boundary values, and then the boundary value functional coverage including the maximum and minimum values of the bit width is generated. In some examples, the functional coverage syntax can be used to generate and define coverage points to detect whether the signal value covers the boundary value.

[0040] In some embodiments, the signal having a numerical value range generates a boundary value function coverage including the maximum and minimum values of the bit width, including: for signals within the minimum value and the bit width threshold range, traversing all values; for signals within the bit width threshold and the maximum value range, dividing into multiple value range segments, and covering the boundary values and each segmented interval.

[0041] For example, using the Coverpoint definition in a SystemVerilog functional coverage model as a reference, monitor the value of the signal signal_exmp and collect coverage data during simulation. If the bit width of signal_exmp is no more than 5 bits, and all values are iterated over, taking a bit width of 5 as an example, the functional code for achieving functional coverage can be: cp_signal_exmp : coverpoint signal_exmp iff(resetn ==1){ bins b_signal_exmp[] = {[0:31]};} This coverpoint is used to monitor the value of the signal signal_exmp and count whether its value covers the range of 0 to 31. This function coverpoint is monitored only when n is reset to 1. Bins b_signal_exmp divides the value of signal_exmp into intervals of 0 to 31. During simulation, the system counts whether the value of signal_exmp covers all possible values of 0 to 31.

[0042] Extract the signal attributes from the top-level module description file of the design under test to obtain information such as signal name, width, and value range. Determine the bit width threshold based on the signal width and verification requirements. For example, for an 8-bit signal, the bit width threshold can be set to 16. Traverse all signal values within the minimum value and bit width threshold range to generate coverage logic detection assertions. For signals within the bit width threshold and maximum value range, they can be divided into multiple value range segments, and the boundary values and boundary values of each segmented interval are covered. This allows for flexible generation of functional coverage based on the characteristics of the signal value range, thereby improving verification efficiency and accuracy.

[0043] For example, using a Coverpoint definition in a SystemVerilog functional coverage model as a reference, monitor the value of the signal signal_exmp and collect coverage data during simulation. If the signal signal_exmp bit width is greater than 5 bits, divide the range into several segments, covering the boundary values and these ranges. For example, if the bit width is 10: {cp_signal_exmp : coverpoint signal_exmp iff(resetn ==1){ bins b_signal_exmp = {0, 1023, [1:255], [256:511], [511:766], [767:1022]}; } This coverpoint is used to monitor the value of signal signal_exmp and count whether its value covers the following ranges: specific values are 0 and 1023; interval values are [1:255], [256:511], [511:766] and [767:1022]. This coverpoint is monitored only when n is reset to 1. The values of signal_exmp are divided into multiple intervals and specific values as shown in the examples above. During the simulation verification process, the verification platform will count whether the values of signal_exmp cover all defined intervals and specific values.

[0044] Of course, there are also some signal types with fixed timing requirements. For such signals, in some embodiments, the generating of a functional coverage file covering all input signals based on the signal attributes includes: for signals with fixed timing requirements, determining trigger conditions based on the edge characteristics of the clock signal, and setting disable conditions to define the scope of the assertion; the signal attributes at least indicate that the type of input signal is a signal with fixed timing requirements; defining attributes according to preset timing intervals and signal state change rules, and generating a functional coverage logic detection assertion for detecting whether the clock signal timing sequence meets the design requirements; wherein the preset timing intervals and signal state change rules are determined according to the design specifications of the signal with fixed timing requirements.

[0045] In chip verification, timing requirements are a key factor in ensuring the functional correctness of a design. For signals with fixed timing requirements, determining trigger conditions based on the edge characteristics of the clock signal and setting disable conditions to limit the scope of assertion validity can effectively verify the design's behavior under specific timing conditions.

[0046] Extract signal attribute information from the DUT top-level module description file. The signal attributes at least indicate that the input signal type is a signal with fixed timing requirements, including signal name, timing requirements, clock signal, etc. Determine the trigger condition based on the edge characteristics of the clock signal, such as the rising edge or falling edge. Set the disable condition based on the timing requirements to define the scope within which the detection assertion is effective. Define the timing interval and signal state change rules based on the design requirements. In some embodiments, the timing interval can be the number of clock cycles, and the signal state change rule is the change of the signal from a low level to a high level. The definition of the timing interval and signal state change rules is based on the design specifications for signals with fixed timing requirements. In some examples, they can be determined by the number of clock cycles and signal state change rules in the design specifications.

[0047] According to the timing interval and signal state change rules, SystemVerilog assertions are used to generate functional coverage logic detection assertions for detecting whether the clock signal timing sequence meets the design requirements.

[0048] For example, a SystemVerilog concurrency check assertion describes a timing sequence property. The purpose of this property is to check whether the state changes of a series of signals meet the expected timing rules under a specific clock edge (negedge CLK). In this example, the state changes of the VDD_ALWAYSON, VDD_SOC, PWROK, and RESET signals meet expectations. The specific assertion implementation function code is as follows: {property signal_sequence; @(negedge CLK) disable iff(POWER_ENABLE==0) ((VDD_ALWAYSON==1'b1)|=>|=>##[1:20](VDD_SOC==1) |=>##[1:20] (PWROK) |=>##[1:20](RESET); Endproperty} From @(negedge CLK), we can see that the trigger condition of the assertion is the falling edge of the clock signal CLK. From disable iff(POWER_ENABLE == 0), we can know that the disable condition of the assertion is when POWER_ENABLE is 0, the assertion fails and is no longer checked.

[0049] Figure 2 The timing relationship diagram of the signal with fixed timing requirements, such as Figure 2 As shown in the figure, this assertion describes the logic of a timing sequence: When VDD_ALWAYSON is high, the subsequent conditions are checked. VDD_SOC must go high within 1 to 20 cycles. PWROK must go high within 1 to 20 cycles after VDD_SOC goes high. RESET must go high within 1 to 20 cycles after PWROK goes high. If any of these conditions are not met, the assertion fails and an error is reported.

[0050] Of course, the above is only an illustrative description of the specific contents of several assertions. For different signal types, different assertions can be configured according to the design verification specification to achieve the completeness of the verification of the design under test.

[0051] In some embodiments, parsing the signal properties of the input ports in the design under test file includes: parsing the top-level module description file of the design under test to extract the signal properties of all input ports; the top-level module description file includes indicating the input ports and the signal properties of the corresponding input ports.

[0052] In chip verification, the top-level module of the DUT is the highest-level module of the entire design. It contains the instantiations of all submodules and the definitions of input and output ports. The top-level module is the interface between the verification environment and the design. The verification platform applies stimulus through the input ports of the top-level module and monitors the design's response through the output ports.

[0053] When parsing the signal properties of the input ports in the design file under test, use a file reading tool to load the top-level module description file, which includes the definition of the input ports and their signal properties. Convert the file contents into a string or data structure to facilitate subsequent parsing. Extract the module declaration, module name, and port list, use regular expressions to match the input and output port declarations, and extract the signal name, direction, width, type, and other information of each port. Also, extract the sub-module instantiation using regular expressions to match the sub-module instantiation part and the sub-module name and its port connection relationship. Finally, store the extracted signal properties and sub-module information as structured data, such as JSON, XML, or a database, which can be used to build a verification environment.

[0054] See Figure 3 In some embodiments, the functional coverage file is generated based on a script; after generating the functional coverage file, the method further includes: compiling the functional coverage file into a design under test verification environment, and configuring the design under test verification environment so as to call the functional coverage file during verification to detect the coverage status of the input stimulus signal on the design under test function.

[0055] In this embodiment, since the RTL code is parsed by the script to generate a functional coverage file containing all port signals, in some examples, other programming languages can also be used to generate a functional coverage file containing all port signals. From the underlying technical level of the design under test, it is ensured that the functional verification of all port signals will be covered, avoiding the problem of manually adding missing functional coverage.

[0056] Figure 4 For the basic structure of a typical verification environment, such as Figure 4 As shown in the figure, it mainly includes two parts: stimulus generator and comparator (checker). In the existing function verification method of the design under test, the stimulus generator part mainly drives the code to work according to the functional points of the test plan, and the comparator monitors the output signal and reports the verification results to check whether the function of the DUT is correct.

[0057] The verification scheme optimized according to the present application is as follows: the stimulus generator part mainly drives the code to generate comprehensive stimulus signals based on the input port signal properties parsed from the design file under test, such as bit width, value range, timing requirements, etc., and is not limited to the functional points in the test plan, so as to avoid missing basic input port functional tests. The comparator calls the functional coverage file to monitor the input stimulus signal, outputs a signal of the coverage status of the design function under test, collects coverage data, and reports the verification results to check whether the function of the DUT is correct. Therefore, in the design under test verification scheme of the present application, the completeness of the verification is guaranteed from the port signal level, and all port signals can be stimulated and covered to all functions, generating input stimulus values that are beneficial to functional testing, which is convenient for improving the reliability of the verification results and is suitable for various integrated circuit IP (Intellectual Property) verification scenarios.

[0058] In a second aspect, an embodiment of the present invention provides an input stimulus completeness detection system, which is applicable to integrated circuit design verification scenarios including chips, and can more comprehensively cover port signal stimulus and improve the completeness of the verification of the design under test.

[0059] like Figure 5 As shown, an embodiment of the present invention further provides an input stimulus integrity detection system, comprising: The parsing unit 31 is used to parse the signal attributes of the input port in the design file under test; A generating unit 32 is configured to generate a functional coverage file covering all input signals based on the signal attributes; the functional coverage file includes value coverage logic detection assertions corresponding to different signal attributes; The monitoring and detecting unit 33 is used to test the function coverage file and detect the function coverage status of the current input excitation signal.

[0060] The input stimulus completeness testing system provided by the embodiments of the present application no longer manually adds functional coverage files based on function points in the test plan. Instead, it analyzes the signal attributes of the input ports in the design file under test; generates a functional coverage file covering all input signals based on the signal attributes; the functional coverage file contains value coverage logic detection assertions and functional coverage corresponding to different signal attributes; and monitors and detects the functional coverage status of the current input stimulus signal based on the functional coverage file. In this way, because the DUT input ports are analyzed to generate a functional coverage file covering all input signals, and the functional coverage file contains value coverage logic detection assertions corresponding to different signal attributes, all input ports are ensured to be covered, and all possible values of each input port are tested, which helps avoid the potential problem of missing basic input ports. As a result, port signal stimulus can be more comprehensively covered, thereby improving the efficiency and comprehensiveness of port signal stimulus completeness verification.

[0061] In some embodiments, the system further includes: an adjustment unit for dynamically adjusting the current input excitation according to characteristic parameters of the input excitation signal that is not covered by the function, if there is an input excitation signal that is not covered by the function, until the function coverage of the preset input excitation signal is reached.

[0062] In some embodiments, the generation unit includes: a first generation module, used to generate a boundary value function coverage including a maximum value and a minimum value of a bit width for a signal having a numerical value range; wherein the signal attribute at least indicates that the type of the input signal is a signal having a numerical value range.

[0063] In some embodiments, the generation module includes: a traversal submodule, which is used to traverse all values for signals within the range of the minimum value and the bit width threshold; a division submodule, which is used to divide the signals within the range of the bit width threshold and the maximum value into multiple value range segments, and cover the boundary values and each segmented interval.

[0064] In some embodiments, the generation unit includes: a determination module, which is used to determine the trigger conditions for signals with fixed timing requirements based on the edge characteristics of the clock signal, and set the disable conditions to define the scope of the assertion; the signal attributes at least indicate that the type of the input signal is a signal with fixed timing requirements; a second generation module, which defines the attributes according to the preset timing interval and signal state change rules, and generates a functional coverage logic detection assertion for detecting whether the clock signal timing sequence meets the design requirements; wherein the preset timing interval and signal state change rules are determined according to the design specifications of the signal with fixed timing requirements.

[0065] In some embodiments, the parsing unit includes: a parsing module for parsing the top-level module description file of the design under test, wherein the top-level module description file includes an indication of an input port and a signal attribute of the corresponding input port; and an extraction module for extracting the signal attributes of all input ports.

[0066] In some embodiments, the functional coverage file is generated based on a script. After generating the functional coverage file, the system also includes: a compilation unit, used to compile the functional coverage file into the design under test verification environment, and configure the design under test verification environment to call the functional coverage file during verification to detect the coverage status of the design under test function.

[0067] On the third aspect, an embodiment of the present invention further provides an electronic device suitable for integrated circuit design verification scenarios including chips, which can more comprehensively cover port signal excitation and improve the completeness of the verification of the design under test.

[0068] like Figure 6 As shown, the electronic device provided by an embodiment of the present invention may include: a memory 41 and a processor 42, wherein the memory 41 is used to store executable program code; the processor 42 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 41, and is used to execute the input stimulus integrity detection verification method provided by any embodiment of the present invention.

[0069] The specific execution process of the above steps by the processor 42 and the steps further executed by the processor 42 by running the executable program code can be found in the description of the first embodiment of the input stimulus integrity detection method of the present invention, which will not be repeated here.

[0070] In the fourth aspect, an embodiment of the present invention also provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement any input stimulus completeness detection method provided by the aforementioned embodiments, thereby also achieving the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0071] It should be noted that, in this document, except for the first and second priority qualifiers such as first and second priority, which represent the queue priorities, the remaining relational terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0072] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0073] For the convenience of description, the above device is described as being divided into various units / modules based on their functions. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0074] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can also be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0075] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for detecting the completeness of an input stimulus, characterized in that: include: Parse the signal properties of the input ports in the design file under test; Generate a functional coverage file covering all input signals based on the signal attributes, wherein the functional coverage file includes value coverage logic detection assertions and functional coverage corresponding to different signal attributes; The function coverage file is tested to detect the function coverage status of the current input stimulus signal.

2. The input stimulus integrity detection method according to claim 1, characterized in that: After monitoring and detecting the functional coverage status of the current input stimulus according to the functional coverage file, the method further includes: if there is an input stimulus signal that is not functionally covered, dynamically adjusting the current input stimulus according to the characteristic parameters of the input stimulus signal that is not functionally covered until the functional coverage of the preset input stimulus signal is reached.

3. The input stimulus integrity detection method according to claim 1, characterized in that: Generating a function coverage file covering all input signals based on the signal attributes includes: For a signal with a numerical value range, a boundary value function coverage including a maximum value and a minimum value of a bit width is generated; wherein the signal attribute at least indicates that the type of the input signal is a signal with a numerical value range.

4. The input stimulus integrity detection method according to claim 3, characterized in that: The generating, for a signal having a range of numerical values, a boundary value function coverage including a maximum value and a minimum value of a bit width comprises: for a signal within a range of a minimum value and a bit width threshold, traversing all values; For signals within the range of the bit width threshold and the maximum value, they are divided into multiple value range segments, covering the boundary values and each segment interval.

5. The input stimulus integrity detection method according to claim 1, characterized in that: Generating a functional coverage file covering all input signals based on the signal attributes includes: for signals with fixed timing requirements, determining a trigger condition based on edge characteristics of a clock signal, and setting a disable condition to define a scope in which the assertion is effective; The signal attribute further indicates at least that the type of the input signal is a signal with fixed timing requirements; Define attributes according to preset timing intervals and signal state change rules to generate functional coverage logic detection assertions for detecting whether the clock signal timing sequence meets design requirements; wherein the preset timing intervals and signal state change rules are determined according to the design specifications of the signal with fixed timing requirements.

6. The input stimulus integrity detection method according to claim 1, characterized in that: The analyzing the signal attributes of the input port in the design file under test includes: The top-level module description file of the design under test is parsed to extract signal properties of all input ports, wherein the top-level module description file includes the signal properties of the indicated input ports and the corresponding input ports.

7. The input stimulus integrity detection method according to claim 1, 2 or 5, characterized in that: The function coverage file is generated based on a script; after generating the function coverage file, the method further includes: The function coverage file is compiled into the design under test verification environment, and the design under test verification environment is configured so that the function coverage file is called during verification to detect the coverage status of the design under test function.

8. An input stimulus integrity detection system, characterized in that: include: A parsing unit, used for parsing the signal attributes of the input port in the design file under test; A generating unit, configured to generate a functional coverage file covering all input signals based on the signal attributes, wherein the functional coverage file includes value coverage logic detection assertions and functional coverage corresponding to different signal attributes; The monitoring and detection unit is used to test the functional coverage file and detect the functional coverage status of the current input excitation signal.

9. The input stimulus integrity detection system according to claim 8, characterized in that: The system further comprises: The adjustment unit is used to dynamically adjust the current input stimulus according to the characteristic parameters of the input stimulus signal that is not covered by the function if there is an input stimulus signal that is not covered by the function, until the function coverage of the preset input stimulus signal is reached.

10. The input stimulus integrity detection system according to claim 8, characterized in that: The generation unit includes: a first generation module, which is used to generate a boundary value function coverage including a maximum value and a minimum value of a bit width for a signal with a numerical value range; wherein the signal attribute at least indicates that the type of the input signal is a signal with a numerical value range.

11. The input stimulus integrity detection system according to claim 10, characterized in that: The generation module includes: The traversal submodule is used to traverse all values of the signal within the minimum value and bit width threshold range; The division submodule is used to divide the signal within the range of the bit width threshold and the maximum value into multiple value range segments, and cover the boundary values and each segment interval.

12. The input stimulus integrity detection system according to claim 8, characterized in that: The generating unit comprises: a determination module, configured to determine a trigger condition for a signal with fixed timing requirements based on an edge characteristic of a clock signal, and to set a disable condition to define a scope within which the assertion is effective; wherein the signal attribute further indicates at least that the type of the input signal is a signal with fixed timing requirements; The second generation module defines attributes according to preset timing intervals and signal state change rules, and generates functional coverage logic detection assertions for detecting whether the clock signal timing sequence meets the design requirements; wherein the preset timing intervals and signal state change rules are determined according to the design specifications of the signal with fixed timing requirements.

13. The input stimulus integrity detection system according to claim 8, characterized in that: The parsing unit includes: A parsing module, configured to parse a top-level module description file of the design under test, wherein the top-level module description file includes an indication input port and a signal attribute corresponding to the input port; The extraction module is used to extract the signal properties of all input ports.

14. The input stimulus integrity detection system according to claim 8, 9 or 12, characterized in that: The function coverage file is generated based on a script. After the function coverage file is generated, the system further includes: The compiling unit is used to compile the function coverage file into the design under test verification environment, and configure the design under test verification environment so as to call the function coverage file to detect the coverage status of the design under test function during verification.

15. An electronic device, characterized in that: The electronic device includes: a memory and a processor; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute the input stimulus integrity detection method described in any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that The computer-readable storage medium stores one or more computer programs, and when the one or more computer programs are executed by one or more processors, the input stimulus integrity detection method according to any one of claims 1 to 7 is implemented.

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